xref: /titanic_44/usr/src/uts/common/io/e1000api/e1000_i210.h (revision 5539384561c0efe744226d5e5d331f5546e500e4)
1 /******************************************************************************
2 
3   Copyright (c) 2001-2013, Intel Corporation
4   All rights reserved.
5 
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
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10       this list of conditions and the following disclaimer.
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12    2. Redistributions in binary form must reproduce the above copyright
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14       documentation and/or other materials provided with the distribution.
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16    3. Neither the name of the Intel Corporation nor the names of its
17       contributors may be used to endorse or promote products derived from
18       this software without specific prior written permission.
19 
20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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31 
32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _E1000_I210_H_
36 #define _E1000_I210_H_
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
42 s32 e1000_update_flash_i210(struct e1000_hw *hw);
43 s32 e1000_update_nvm_checksum_i210(struct e1000_hw *hw);
44 s32 e1000_validate_nvm_checksum_i210(struct e1000_hw *hw);
45 s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,
46 			      u16 words, u16 *data);
47 s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
48 			     u16 words, u16 *data);
49 s32 e1000_read_invm_i211(struct e1000_hw *hw, u8 address, u16 *data);
50 s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
51 void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
52 s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
53 			 u16 *data);
54 s32 e1000_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
55 			  u16 data);
56 
57 #define E1000_STM_OPCODE		0xDB00
58 #define E1000_EEPROM_FLASH_SIZE_WORD	0x11
59 
60 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
61 	(u8)((invm_dword) & 0x7)
62 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
63 	(u8)(((invm_dword) & 0x0000FE00) >> 9)
64 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \
65 	(u16)(((invm_dword) & 0xFFFF0000) >> 16)
66 
67 enum E1000_INVM_STRUCTURE_TYPE {
68 	E1000_INVM_UNINITIALIZED_STRUCTURE		= 0x00,
69 	E1000_INVM_WORD_AUTOLOAD_STRUCTURE		= 0x01,
70 	E1000_INVM_CSR_AUTOLOAD_STRUCTURE		= 0x02,
71 	E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE	= 0x03,
72 	E1000_INVM_RSA_KEY_SHA256_STRUCTURE		= 0x04,
73 	E1000_INVM_INVALIDATED_STRUCTURE		= 0x0F,
74 };
75 
76 #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS	8
77 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS	1
78 #define E1000_INVM_ULT_BYTES_SIZE	8
79 #define E1000_INVM_RECORD_SIZE_IN_BYTES	4
80 #define E1000_INVM_VER_FIELD_ONE	0x1FF8
81 #define E1000_INVM_VER_FIELD_TWO	0x7FE000
82 #define E1000_INVM_IMGTYPE_FIELD	0x1F800000
83 
84 #define E1000_INVM_MAJOR_MASK	0x3F0
85 #define E1000_INVM_MINOR_MASK	0xF
86 #define E1000_INVM_MAJOR_SHIFT	4
87 
88 #define ID_LED_DEFAULT_I210		((ID_LED_OFF1_ON2  << 8) | \
89 					 (ID_LED_DEF1_DEF2 <<  4) | \
90 					 (ID_LED_OFF1_OFF2))
91 #define ID_LED_DEFAULT_I210_SERDES	((ID_LED_DEF1_DEF2 << 8) | \
92 					 (ID_LED_DEF1_DEF2 <<  4) | \
93 					 (ID_LED_DEF1_DEF2))
94 
95 /* NVM offset defaults for I211 devices */
96 #define NVM_INIT_CTRL_2_DEFAULT_I211	0X7243
97 #define NVM_INIT_CTRL_4_DEFAULT_I211	0x00C1
98 #define NVM_LED_1_CFG_DEFAULT_I211	0x0184
99 #define NVM_LED_0_2_CFG_DEFAULT_I211	0x200C
100 
101 #ifdef __cplusplus
102 }
103 #endif
104 
105 #endif /* _E1000_I210_H_ */
106