1 /****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD$*/ 34 35 #ifndef _E1000_HW_H_ 36 #define _E1000_HW_H_ 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 #include "e1000_osdep.h" 43 #include "e1000_regs.h" 44 #include "e1000_defines.h" 45 46 struct e1000_hw; 47 48 #define E1000_DEV_ID_82542 0x1000 49 #define E1000_DEV_ID_82543GC_FIBER 0x1001 50 #define E1000_DEV_ID_82543GC_COPPER 0x1004 51 #define E1000_DEV_ID_82544EI_COPPER 0x1008 52 #define E1000_DEV_ID_82544EI_FIBER 0x1009 53 #define E1000_DEV_ID_82544GC_COPPER 0x100C 54 #define E1000_DEV_ID_82544GC_LOM 0x100D 55 #define E1000_DEV_ID_82540EM 0x100E 56 #define E1000_DEV_ID_82540EM_LOM 0x1015 57 #define E1000_DEV_ID_82540EP_LOM 0x1016 58 #define E1000_DEV_ID_82540EP 0x1017 59 #define E1000_DEV_ID_82540EP_LP 0x101E 60 #define E1000_DEV_ID_82545EM_COPPER 0x100F 61 #define E1000_DEV_ID_82545EM_FIBER 0x1011 62 #define E1000_DEV_ID_82545GM_COPPER 0x1026 63 #define E1000_DEV_ID_82545GM_FIBER 0x1027 64 #define E1000_DEV_ID_82545GM_SERDES 0x1028 65 #define E1000_DEV_ID_82546EB_COPPER 0x1010 66 #define E1000_DEV_ID_82546EB_FIBER 0x1012 67 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 68 #define E1000_DEV_ID_82546GB_COPPER 0x1079 69 #define E1000_DEV_ID_82546GB_FIBER 0x107A 70 #define E1000_DEV_ID_82546GB_SERDES 0x107B 71 #define E1000_DEV_ID_82546GB_PCIE 0x108A 72 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 73 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 74 #define E1000_DEV_ID_82541EI 0x1013 75 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 76 #define E1000_DEV_ID_82541ER_LOM 0x1014 77 #define E1000_DEV_ID_82541ER 0x1078 78 #define E1000_DEV_ID_82541GI 0x1076 79 #define E1000_DEV_ID_82541GI_LF 0x107C 80 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 81 #define E1000_DEV_ID_82547EI 0x1019 82 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 83 #define E1000_DEV_ID_82547GI 0x1075 84 #define E1000_DEV_ID_82571EB_COPPER 0x105E 85 #define E1000_DEV_ID_82571EB_FIBER 0x105F 86 #define E1000_DEV_ID_82571EB_SERDES 0x1060 87 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 88 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 89 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 90 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 91 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 92 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 93 #define E1000_DEV_ID_82572EI_COPPER 0x107D 94 #define E1000_DEV_ID_82572EI_FIBER 0x107E 95 #define E1000_DEV_ID_82572EI_SERDES 0x107F 96 #define E1000_DEV_ID_82572EI 0x10B9 97 #define E1000_DEV_ID_82573E 0x108B 98 #define E1000_DEV_ID_82573E_IAMT 0x108C 99 #define E1000_DEV_ID_82573L 0x109A 100 #define E1000_DEV_ID_82574L 0x10D3 101 #define E1000_DEV_ID_82574LA 0x10F6 102 #define E1000_DEV_ID_82583V 0x150C 103 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 104 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 105 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 106 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 107 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 108 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 109 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 110 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 111 #define E1000_DEV_ID_ICH8_IFE 0x104C 112 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 113 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 114 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 115 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 116 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 117 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 118 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 119 #define E1000_DEV_ID_ICH9_BM 0x10E5 120 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 121 #define E1000_DEV_ID_ICH9_IFE 0x10C0 122 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 123 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 124 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 125 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 126 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 127 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 128 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 129 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 130 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 131 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 132 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 133 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 134 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 135 #define E1000_DEV_ID_PCH2_LV_V 0x1503 136 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 137 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 138 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 139 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 140 #define E1000_DEV_ID_82576 0x10C9 141 #define E1000_DEV_ID_82576_FIBER 0x10E6 142 #define E1000_DEV_ID_82576_SERDES 0x10E7 143 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 144 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 145 #define E1000_DEV_ID_82576_NS 0x150A 146 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 147 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 148 #define E1000_DEV_ID_82576_VF 0x10CA 149 #define E1000_DEV_ID_82576_VF_HV 0x152D 150 #define E1000_DEV_ID_I350_VF 0x1520 151 #define E1000_DEV_ID_I350_VF_HV 0x152F 152 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 153 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 154 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 155 #define E1000_DEV_ID_82580_COPPER 0x150E 156 #define E1000_DEV_ID_82580_FIBER 0x150F 157 #define E1000_DEV_ID_82580_SERDES 0x1510 158 #define E1000_DEV_ID_82580_SGMII 0x1511 159 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 160 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 161 #define E1000_DEV_ID_I350_COPPER 0x1521 162 #define E1000_DEV_ID_I350_FIBER 0x1522 163 #define E1000_DEV_ID_I350_SERDES 0x1523 164 #define E1000_DEV_ID_I350_SGMII 0x1524 165 #define E1000_DEV_ID_I350_DA4 0x1546 166 #define E1000_DEV_ID_I210_COPPER 0x1533 167 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 168 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 169 #define E1000_DEV_ID_I210_FIBER 0x1536 170 #define E1000_DEV_ID_I210_SERDES 0x1537 171 #define E1000_DEV_ID_I210_SGMII 0x1538 172 #define E1000_DEV_ID_I211_COPPER 0x1539 173 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 174 #define E1000_DEV_ID_I354_SGMII 0x1F41 175 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 176 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 177 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 178 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 179 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 180 181 #define E1000_REVISION_0 0 182 #define E1000_REVISION_1 1 183 #define E1000_REVISION_2 2 184 #define E1000_REVISION_3 3 185 #define E1000_REVISION_4 4 186 187 #define E1000_FUNC_0 0 188 #define E1000_FUNC_1 1 189 #define E1000_FUNC_2 2 190 #define E1000_FUNC_3 3 191 192 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 193 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 194 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 195 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 196 197 enum e1000_mac_type { 198 e1000_undefined = 0, 199 e1000_82542, 200 e1000_82543, 201 e1000_82544, 202 e1000_82540, 203 e1000_82545, 204 e1000_82545_rev_3, 205 e1000_82546, 206 e1000_82546_rev_3, 207 e1000_82541, 208 e1000_82541_rev_2, 209 e1000_82547, 210 e1000_82547_rev_2, 211 e1000_82571, 212 e1000_82572, 213 e1000_82573, 214 e1000_82574, 215 e1000_82583, 216 e1000_80003es2lan, 217 e1000_ich8lan, 218 e1000_ich9lan, 219 e1000_ich10lan, 220 e1000_pchlan, 221 e1000_pch2lan, 222 e1000_pch_lpt, 223 e1000_82575, 224 e1000_82576, 225 e1000_82580, 226 e1000_i350, 227 e1000_i354, 228 e1000_i210, 229 e1000_i211, 230 e1000_vfadapt, 231 e1000_vfadapt_i350, 232 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 233 }; 234 235 enum e1000_media_type { 236 e1000_media_type_unknown = 0, 237 e1000_media_type_copper = 1, 238 e1000_media_type_fiber = 2, 239 e1000_media_type_internal_serdes = 3, 240 e1000_num_media_types 241 }; 242 243 enum e1000_nvm_type { 244 e1000_nvm_unknown = 0, 245 e1000_nvm_none, 246 e1000_nvm_eeprom_spi, 247 e1000_nvm_eeprom_microwire, 248 e1000_nvm_flash_hw, 249 e1000_nvm_flash_sw 250 }; 251 252 enum e1000_nvm_override { 253 e1000_nvm_override_none = 0, 254 e1000_nvm_override_spi_small, 255 e1000_nvm_override_spi_large, 256 e1000_nvm_override_microwire_small, 257 e1000_nvm_override_microwire_large 258 }; 259 260 enum e1000_phy_type { 261 e1000_phy_unknown = 0, 262 e1000_phy_none, 263 e1000_phy_m88, 264 e1000_phy_igp, 265 e1000_phy_igp_2, 266 e1000_phy_gg82563, 267 e1000_phy_igp_3, 268 e1000_phy_ife, 269 e1000_phy_bm, 270 e1000_phy_82578, 271 e1000_phy_82577, 272 e1000_phy_82579, 273 e1000_phy_i217, 274 e1000_phy_82580, 275 e1000_phy_vf, 276 e1000_phy_i210, 277 }; 278 279 enum e1000_bus_type { 280 e1000_bus_type_unknown = 0, 281 e1000_bus_type_pci, 282 e1000_bus_type_pcix, 283 e1000_bus_type_pci_express, 284 e1000_bus_type_reserved 285 }; 286 287 enum e1000_bus_speed { 288 e1000_bus_speed_unknown = 0, 289 e1000_bus_speed_33, 290 e1000_bus_speed_66, 291 e1000_bus_speed_100, 292 e1000_bus_speed_120, 293 e1000_bus_speed_133, 294 e1000_bus_speed_2500, 295 e1000_bus_speed_5000, 296 e1000_bus_speed_reserved 297 }; 298 299 enum e1000_bus_width { 300 e1000_bus_width_unknown = 0, 301 e1000_bus_width_pcie_x1, 302 e1000_bus_width_pcie_x2, 303 e1000_bus_width_pcie_x4 = 4, 304 e1000_bus_width_pcie_x8 = 8, 305 e1000_bus_width_32, 306 e1000_bus_width_64, 307 e1000_bus_width_reserved 308 }; 309 310 enum e1000_1000t_rx_status { 311 e1000_1000t_rx_status_not_ok = 0, 312 e1000_1000t_rx_status_ok, 313 e1000_1000t_rx_status_undefined = 0xFF 314 }; 315 316 enum e1000_rev_polarity { 317 e1000_rev_polarity_normal = 0, 318 e1000_rev_polarity_reversed, 319 e1000_rev_polarity_undefined = 0xFF 320 }; 321 322 enum e1000_fc_mode { 323 e1000_fc_none = 0, 324 e1000_fc_rx_pause, 325 e1000_fc_tx_pause, 326 e1000_fc_full, 327 e1000_fc_default = 0xFF 328 }; 329 330 enum e1000_ffe_config { 331 e1000_ffe_config_enabled = 0, 332 e1000_ffe_config_active, 333 e1000_ffe_config_blocked 334 }; 335 336 enum e1000_dsp_config { 337 e1000_dsp_config_disabled = 0, 338 e1000_dsp_config_enabled, 339 e1000_dsp_config_activated, 340 e1000_dsp_config_undefined = 0xFF 341 }; 342 343 enum e1000_ms_type { 344 e1000_ms_hw_default = 0, 345 e1000_ms_force_master, 346 e1000_ms_force_slave, 347 e1000_ms_auto 348 }; 349 350 enum e1000_smart_speed { 351 e1000_smart_speed_default = 0, 352 e1000_smart_speed_on, 353 e1000_smart_speed_off 354 }; 355 356 enum e1000_serdes_link_state { 357 e1000_serdes_link_down = 0, 358 e1000_serdes_link_autoneg_progress, 359 e1000_serdes_link_autoneg_complete, 360 e1000_serdes_link_forced_up 361 }; 362 363 /* Receive Descriptor */ 364 struct e1000_rx_desc { 365 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 366 __le16 length; /* Length of data DMAed into data buffer */ 367 __le16 csum; /* Packet checksum */ 368 u8 status; /* Descriptor status */ 369 u8 errors; /* Descriptor Errors */ 370 __le16 special; 371 }; 372 373 /* Receive Descriptor - Extended */ 374 union e1000_rx_desc_extended { 375 struct { 376 __le64 buffer_addr; 377 __le64 reserved; 378 } read; 379 struct { 380 struct { 381 __le32 mrq; /* Multiple Rx Queues */ 382 union { 383 __le32 rss; /* RSS Hash */ 384 struct { 385 __le16 ip_id; /* IP id */ 386 __le16 csum; /* Packet Checksum */ 387 } csum_ip; 388 } hi_dword; 389 } lower; 390 struct { 391 __le32 status_error; /* ext status/error */ 392 __le16 length; 393 __le16 vlan; /* VLAN tag */ 394 } upper; 395 } wb; /* writeback */ 396 }; 397 398 #define MAX_PS_BUFFERS 4 399 /* Receive Descriptor - Packet Split */ 400 union e1000_rx_desc_packet_split { 401 struct { 402 /* one buffer for protocol header(s), three data buffers */ 403 __le64 buffer_addr[MAX_PS_BUFFERS]; 404 } read; 405 struct { 406 struct { 407 __le32 mrq; /* Multiple Rx Queues */ 408 union { 409 __le32 rss; /* RSS Hash */ 410 struct { 411 __le16 ip_id; /* IP id */ 412 __le16 csum; /* Packet Checksum */ 413 } csum_ip; 414 } hi_dword; 415 } lower; 416 struct { 417 __le32 status_error; /* ext status/error */ 418 __le16 length0; /* length of buffer 0 */ 419 __le16 vlan; /* VLAN tag */ 420 } middle; 421 struct { 422 __le16 header_status; 423 __le16 length[3]; /* length of buffers 1-3 */ 424 } upper; 425 __le64 reserved; 426 } wb; /* writeback */ 427 }; 428 429 /* Transmit Descriptor */ 430 struct e1000_tx_desc { 431 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 432 union { 433 __le32 data; 434 struct { 435 __le16 length; /* Data buffer length */ 436 u8 cso; /* Checksum offset */ 437 u8 cmd; /* Descriptor control */ 438 } flags; 439 } lower; 440 union { 441 __le32 data; 442 struct { 443 u8 status; /* Descriptor status */ 444 u8 css; /* Checksum start */ 445 __le16 special; 446 } fields; 447 } upper; 448 }; 449 450 /* Offload Context Descriptor */ 451 struct e1000_context_desc { 452 union { 453 __le32 ip_config; 454 struct { 455 u8 ipcss; /* IP checksum start */ 456 u8 ipcso; /* IP checksum offset */ 457 __le16 ipcse; /* IP checksum end */ 458 } ip_fields; 459 } lower_setup; 460 union { 461 __le32 tcp_config; 462 struct { 463 u8 tucss; /* TCP checksum start */ 464 u8 tucso; /* TCP checksum offset */ 465 __le16 tucse; /* TCP checksum end */ 466 } tcp_fields; 467 } upper_setup; 468 __le32 cmd_and_length; 469 union { 470 __le32 data; 471 struct { 472 u8 status; /* Descriptor status */ 473 u8 hdr_len; /* Header length */ 474 __le16 mss; /* Maximum segment size */ 475 } fields; 476 } tcp_seg_setup; 477 }; 478 479 /* Offload data descriptor */ 480 struct e1000_data_desc { 481 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 482 union { 483 __le32 data; 484 struct { 485 __le16 length; /* Data buffer length */ 486 u8 typ_len_ext; 487 u8 cmd; 488 } flags; 489 } lower; 490 union { 491 __le32 data; 492 struct { 493 u8 status; /* Descriptor status */ 494 u8 popts; /* Packet Options */ 495 __le16 special; 496 } fields; 497 } upper; 498 }; 499 500 /* Statistics counters collected by the MAC */ 501 struct e1000_hw_stats { 502 u64 crcerrs; 503 u64 algnerrc; 504 u64 symerrs; 505 u64 rxerrc; 506 u64 mpc; 507 u64 scc; 508 u64 ecol; 509 u64 mcc; 510 u64 latecol; 511 u64 colc; 512 u64 dc; 513 u64 tncrs; 514 u64 sec; 515 u64 cexterr; 516 u64 rlec; 517 u64 xonrxc; 518 u64 xontxc; 519 u64 xoffrxc; 520 u64 xofftxc; 521 u64 fcruc; 522 u64 prc64; 523 u64 prc127; 524 u64 prc255; 525 u64 prc511; 526 u64 prc1023; 527 u64 prc1522; 528 u64 gprc; 529 u64 bprc; 530 u64 mprc; 531 u64 gptc; 532 u64 gorc; 533 u64 gotc; 534 u64 rnbc; 535 u64 ruc; 536 u64 rfc; 537 u64 roc; 538 u64 rjc; 539 u64 mgprc; 540 u64 mgpdc; 541 u64 mgptc; 542 u64 tor; 543 u64 tot; 544 u64 tpr; 545 u64 tpt; 546 u64 ptc64; 547 u64 ptc127; 548 u64 ptc255; 549 u64 ptc511; 550 u64 ptc1023; 551 u64 ptc1522; 552 u64 mptc; 553 u64 bptc; 554 u64 tsctc; 555 u64 tsctfc; 556 u64 iac; 557 u64 icrxptc; 558 u64 icrxatc; 559 u64 ictxptc; 560 u64 ictxatc; 561 u64 ictxqec; 562 u64 ictxqmtc; 563 u64 icrxdmtc; 564 u64 icrxoc; 565 u64 cbtmpc; 566 u64 htdpmc; 567 u64 cbrdpc; 568 u64 cbrmpc; 569 u64 rpthc; 570 u64 hgptc; 571 u64 htcbdpc; 572 u64 hgorc; 573 u64 hgotc; 574 u64 lenerrs; 575 u64 scvpc; 576 u64 hrmpc; 577 u64 doosync; 578 u64 o2bgptc; 579 u64 o2bspc; 580 u64 b2ospc; 581 u64 b2ogprc; 582 }; 583 584 struct e1000_vf_stats { 585 u64 base_gprc; 586 u64 base_gptc; 587 u64 base_gorc; 588 u64 base_gotc; 589 u64 base_mprc; 590 u64 base_gotlbc; 591 u64 base_gptlbc; 592 u64 base_gorlbc; 593 u64 base_gprlbc; 594 595 u32 last_gprc; 596 u32 last_gptc; 597 u32 last_gorc; 598 u32 last_gotc; 599 u32 last_mprc; 600 u32 last_gotlbc; 601 u32 last_gptlbc; 602 u32 last_gorlbc; 603 u32 last_gprlbc; 604 605 u64 gprc; 606 u64 gptc; 607 u64 gorc; 608 u64 gotc; 609 u64 mprc; 610 u64 gotlbc; 611 u64 gptlbc; 612 u64 gorlbc; 613 u64 gprlbc; 614 }; 615 616 struct e1000_phy_stats { 617 u32 idle_errors; 618 u32 receive_errors; 619 }; 620 621 struct e1000_host_mng_dhcp_cookie { 622 u32 signature; 623 u8 status; 624 u8 reserved0; 625 u16 vlan_id; 626 u32 reserved1; 627 u16 reserved2; 628 u8 reserved3; 629 u8 checksum; 630 }; 631 632 /* Host Interface "Rev 1" */ 633 struct e1000_host_command_header { 634 u8 command_id; 635 u8 command_length; 636 u8 command_options; 637 u8 checksum; 638 }; 639 640 #define E1000_HI_MAX_DATA_LENGTH 252 641 struct e1000_host_command_info { 642 struct e1000_host_command_header command_header; 643 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 644 }; 645 646 /* Host Interface "Rev 2" */ 647 struct e1000_host_mng_command_header { 648 u8 command_id; 649 u8 checksum; 650 u16 reserved1; 651 u16 reserved2; 652 u16 command_length; 653 }; 654 655 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 656 struct e1000_host_mng_command_info { 657 struct e1000_host_mng_command_header command_header; 658 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 659 }; 660 661 #include "e1000_mac.h" 662 #include "e1000_phy.h" 663 #include "e1000_nvm.h" 664 #include "e1000_manage.h" 665 #include "e1000_mbx.h" 666 667 /* Function pointers for the MAC. */ 668 struct e1000_mac_operations { 669 s32 (*init_params)(struct e1000_hw *); 670 s32 (*id_led_init)(struct e1000_hw *); 671 s32 (*blink_led)(struct e1000_hw *); 672 bool (*check_mng_mode)(struct e1000_hw *); 673 s32 (*check_for_link)(struct e1000_hw *); 674 s32 (*cleanup_led)(struct e1000_hw *); 675 void (*clear_hw_cntrs)(struct e1000_hw *); 676 void (*clear_vfta)(struct e1000_hw *); 677 s32 (*get_bus_info)(struct e1000_hw *); 678 void (*set_lan_id)(struct e1000_hw *); 679 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 680 s32 (*led_on)(struct e1000_hw *); 681 s32 (*led_off)(struct e1000_hw *); 682 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 683 s32 (*reset_hw)(struct e1000_hw *); 684 s32 (*init_hw)(struct e1000_hw *); 685 void (*shutdown_serdes)(struct e1000_hw *); 686 void (*power_up_serdes)(struct e1000_hw *); 687 s32 (*setup_link)(struct e1000_hw *); 688 s32 (*setup_physical_interface)(struct e1000_hw *); 689 s32 (*setup_led)(struct e1000_hw *); 690 void (*write_vfta)(struct e1000_hw *, u32, u32); 691 void (*config_collision_dist)(struct e1000_hw *); 692 void (*rar_set)(struct e1000_hw *, u8*, u32); 693 s32 (*read_mac_addr)(struct e1000_hw *); 694 s32 (*validate_mdi_setting)(struct e1000_hw *); 695 s32 (*set_obff_timer)(struct e1000_hw *, u32); 696 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 697 void (*release_swfw_sync)(struct e1000_hw *, u16); 698 }; 699 700 /* When to use various PHY register access functions: 701 * 702 * Func Caller 703 * Function Does Does When to use 704 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 705 * X_reg L,P,A n/a for simple PHY reg accesses 706 * X_reg_locked P,A L for multiple accesses of different regs 707 * on different pages 708 * X_reg_page A L,P for multiple accesses of different regs 709 * on the same page 710 * 711 * Where X=[read|write], L=locking, P=sets page, A=register access 712 * 713 */ 714 struct e1000_phy_operations { 715 s32 (*init_params)(struct e1000_hw *); 716 s32 (*acquire)(struct e1000_hw *); 717 s32 (*cfg_on_link_up)(struct e1000_hw *); 718 s32 (*check_polarity)(struct e1000_hw *); 719 s32 (*check_reset_block)(struct e1000_hw *); 720 s32 (*commit)(struct e1000_hw *); 721 s32 (*force_speed_duplex)(struct e1000_hw *); 722 s32 (*get_cfg_done)(struct e1000_hw *hw); 723 s32 (*get_cable_length)(struct e1000_hw *); 724 s32 (*get_info)(struct e1000_hw *); 725 s32 (*set_page)(struct e1000_hw *, u16); 726 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 727 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 728 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 729 void (*release)(struct e1000_hw *); 730 s32 (*reset)(struct e1000_hw *); 731 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 732 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 733 s32 (*write_reg)(struct e1000_hw *, u32, u16); 734 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 735 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 736 void (*power_up)(struct e1000_hw *); 737 void (*power_down)(struct e1000_hw *); 738 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 739 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 740 }; 741 742 /* Function pointers for the NVM. */ 743 struct e1000_nvm_operations { 744 s32 (*init_params)(struct e1000_hw *); 745 s32 (*acquire)(struct e1000_hw *); 746 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 747 void (*release)(struct e1000_hw *); 748 void (*reload)(struct e1000_hw *); 749 s32 (*update)(struct e1000_hw *); 750 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 751 s32 (*validate)(struct e1000_hw *); 752 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 753 }; 754 755 struct e1000_mac_info { 756 struct e1000_mac_operations ops; 757 u8 addr[ETH_ADDR_LEN]; 758 u8 perm_addr[ETH_ADDR_LEN]; 759 760 enum e1000_mac_type type; 761 762 u32 collision_delta; 763 u32 ledctl_default; 764 u32 ledctl_mode1; 765 u32 ledctl_mode2; 766 u32 mc_filter_type; 767 u32 tx_packet_delta; 768 u32 txcw; 769 770 u16 current_ifs_val; 771 u16 ifs_max_val; 772 u16 ifs_min_val; 773 u16 ifs_ratio; 774 u16 ifs_step_size; 775 u16 mta_reg_count; 776 u16 uta_reg_count; 777 778 /* Maximum size of the MTA register table in all supported adapters */ 779 #define MAX_MTA_REG 128 780 u32 mta_shadow[MAX_MTA_REG]; 781 u16 rar_entry_count; 782 783 u8 forced_speed_duplex; 784 785 bool adaptive_ifs; 786 bool has_fwsm; 787 bool arc_subsystem_valid; 788 bool asf_firmware_present; 789 bool autoneg; 790 bool autoneg_failed; 791 bool get_link_status; 792 bool in_ifs_mode; 793 bool report_tx_early; 794 enum e1000_serdes_link_state serdes_link_state; 795 bool serdes_has_link; 796 bool tx_pkt_filtering; 797 u32 max_frame_size; 798 }; 799 800 struct e1000_phy_info { 801 struct e1000_phy_operations ops; 802 enum e1000_phy_type type; 803 804 enum e1000_1000t_rx_status local_rx; 805 enum e1000_1000t_rx_status remote_rx; 806 enum e1000_ms_type ms_type; 807 enum e1000_ms_type original_ms_type; 808 enum e1000_rev_polarity cable_polarity; 809 enum e1000_smart_speed smart_speed; 810 811 u32 addr; 812 u32 id; 813 u32 reset_delay_us; /* in usec */ 814 u32 revision; 815 816 enum e1000_media_type media_type; 817 818 u16 autoneg_advertised; 819 u16 autoneg_mask; 820 u16 cable_length; 821 u16 max_cable_length; 822 u16 min_cable_length; 823 824 u8 mdix; 825 826 bool disable_polarity_correction; 827 bool is_mdix; 828 bool polarity_correction; 829 bool speed_downgraded; 830 bool autoneg_wait_to_complete; 831 }; 832 833 struct e1000_nvm_info { 834 struct e1000_nvm_operations ops; 835 enum e1000_nvm_type type; 836 enum e1000_nvm_override override; 837 838 u32 flash_bank_size; 839 u32 flash_base_addr; 840 841 u16 word_size; 842 u16 delay_usec; 843 u16 address_bits; 844 u16 opcode_bits; 845 u16 page_size; 846 }; 847 848 struct e1000_bus_info { 849 enum e1000_bus_type type; 850 enum e1000_bus_speed speed; 851 enum e1000_bus_width width; 852 853 u16 func; 854 u16 pci_cmd_word; 855 }; 856 857 struct e1000_fc_info { 858 u32 high_water; /* Flow control high-water mark */ 859 u32 low_water; /* Flow control low-water mark */ 860 u16 pause_time; /* Flow control pause timer */ 861 u16 refresh_time; /* Flow control refresh timer */ 862 bool send_xon; /* Flow control send XON */ 863 bool strict_ieee; /* Strict IEEE mode */ 864 enum e1000_fc_mode current_mode; /* FC mode in effect */ 865 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 866 }; 867 868 struct e1000_mbx_operations { 869 s32 (*init_params)(struct e1000_hw *hw); 870 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 871 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 872 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 873 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 874 s32 (*check_for_msg)(struct e1000_hw *, u16); 875 s32 (*check_for_ack)(struct e1000_hw *, u16); 876 s32 (*check_for_rst)(struct e1000_hw *, u16); 877 }; 878 879 struct e1000_mbx_stats { 880 u32 msgs_tx; 881 u32 msgs_rx; 882 883 u32 acks; 884 u32 reqs; 885 u32 rsts; 886 }; 887 888 struct e1000_mbx_info { 889 struct e1000_mbx_operations ops; 890 struct e1000_mbx_stats stats; 891 u32 timeout; 892 u32 usec_delay; 893 u16 size; 894 }; 895 896 struct e1000_dev_spec_82541 { 897 enum e1000_dsp_config dsp_config; 898 enum e1000_ffe_config ffe_config; 899 u32 tx_fifo_head; 900 u32 tx_fifo_start; 901 u32 tx_fifo_size; 902 u16 dsp_reset_counter; 903 u16 spd_default; 904 bool phy_init_script; 905 bool ttl_workaround; 906 }; 907 908 struct e1000_dev_spec_82542 { 909 bool dma_fairness; 910 }; 911 912 struct e1000_dev_spec_82543 { 913 u32 tbi_compatibility; 914 bool dma_fairness; 915 bool init_phy_disabled; 916 }; 917 918 struct e1000_dev_spec_82571 { 919 bool laa_is_present; 920 u32 smb_counter; 921 E1000_MUTEX swflag_mutex; 922 }; 923 924 struct e1000_dev_spec_80003es2lan { 925 bool mdic_wa_enable; 926 }; 927 928 struct e1000_shadow_ram { 929 u16 value; 930 bool modified; 931 }; 932 933 #define E1000_SHADOW_RAM_WORDS 2048 934 935 struct e1000_dev_spec_ich8lan { 936 bool kmrn_lock_loss_workaround_enabled; 937 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 938 E1000_MUTEX nvm_mutex; 939 E1000_MUTEX swflag_mutex; 940 bool nvm_k1_enabled; 941 bool eee_disable; 942 u16 eee_lp_ability; 943 }; 944 945 struct e1000_dev_spec_82575 { 946 bool sgmii_active; 947 bool global_device_reset; 948 bool eee_disable; 949 bool module_plugged; 950 bool clear_semaphore_once; 951 u32 mtu; 952 struct sfp_e1000_flags eth_flags; 953 }; 954 955 struct e1000_dev_spec_vf { 956 u32 vf_number; 957 u32 v2p_mailbox; 958 }; 959 960 struct e1000_hw { 961 void *back; 962 963 u8 *hw_addr; 964 u8 *flash_address; 965 unsigned long io_base; 966 967 struct e1000_mac_info mac; 968 struct e1000_fc_info fc; 969 struct e1000_phy_info phy; 970 struct e1000_nvm_info nvm; 971 struct e1000_bus_info bus; 972 struct e1000_mbx_info mbx; 973 struct e1000_host_mng_dhcp_cookie mng_cookie; 974 975 union { 976 struct e1000_dev_spec_82541 _82541; 977 struct e1000_dev_spec_82542 _82542; 978 struct e1000_dev_spec_82543 _82543; 979 struct e1000_dev_spec_82571 _82571; 980 struct e1000_dev_spec_80003es2lan _80003es2lan; 981 struct e1000_dev_spec_ich8lan ich8lan; 982 struct e1000_dev_spec_82575 _82575; 983 struct e1000_dev_spec_vf vf; 984 } dev_spec; 985 986 u16 device_id; 987 u16 subsystem_vendor_id; 988 u16 subsystem_device_id; 989 u16 vendor_id; 990 991 u8 revision_id; 992 }; 993 994 #include "e1000_82541.h" 995 #include "e1000_82543.h" 996 #include "e1000_82571.h" 997 #include "e1000_80003es2lan.h" 998 #include "e1000_ich8lan.h" 999 #include "e1000_82575.h" 1000 #include "e1000_i210.h" 1001 1002 /* These functions must be implemented by drivers */ 1003 void e1000_pci_clear_mwi(struct e1000_hw *hw); 1004 void e1000_pci_set_mwi(struct e1000_hw *hw); 1005 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1006 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1007 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1008 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1009 1010 #ifdef __cplusplus 1011 } 1012 #endif 1013 1014 #endif /* _E1000_HW_H_ */ 1015