1 /* BEGIN CSTYLED */ 2 3 /** 4 * \file drm.h 5 * Header for the Direct Rendering Manager 6 * 7 * \author Rickard E. (Rik) Faith <faith@valinux.com> 8 * 9 * \par Acknowledgments: 10 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. 11 */ 12 13 /* 14 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 15 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 16 * All rights reserved. 17 * 18 * Permission is hereby granted, free of charge, to any person obtaining a 19 * copy of this software and associated documentation files (the "Software"), 20 * to deal in the Software without restriction, including without limitation 21 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 22 * and/or sell copies of the Software, and to permit persons to whom the 23 * Software is furnished to do so, subject to the following conditions: 24 * 25 * The above copyright notice and this permission notice (including the next 26 * paragraph) shall be included in all copies or substantial portions of the 27 * Software. 28 * 29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 30 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 31 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 32 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 33 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 34 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 35 * OTHER DEALINGS IN THE SOFTWARE. 36 */ 37 38 /** 39 * \mainpage 40 * 41 * The Direct Rendering Manager (DRM) is a device-independent kernel-level 42 * device driver that provides support for the XFree86 Direct Rendering 43 * Infrastructure (DRI). 44 * 45 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major 46 * ways: 47 * -# The DRM provides synchronized access to the graphics hardware via 48 * the use of an optimized two-tiered lock. 49 * -# The DRM enforces the DRI security policy for access to the graphics 50 * hardware by only allowing authenticated X11 clients access to 51 * restricted regions of memory. 52 * -# The DRM provides a generic DMA engine, complete with multiple 53 * queues and the ability to detect the need for an OpenGL context 54 * switch. 55 * -# The DRM is extensible via the use of small device-specific modules 56 * that rely extensively on the API exported by the DRM module. 57 * 58 */ 59 60 /* 61 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 62 * Use is subject to license terms. 63 */ 64 65 #ifndef _DRM_H_ 66 #define _DRM_H_ 67 68 #pragma ident "%Z%%M% %I% %E% SMI" 69 70 #include <sys/types32.h> 71 72 #ifndef __user 73 #define __user 74 #endif 75 76 #ifdef __GNUC__ 77 # define DEPRECATED __attribute__ ((deprecated)) 78 #else 79 # define DEPRECATED 80 # define __volatile__ volatile 81 #endif 82 83 #if defined(__linux__) 84 #include <asm/ioctl.h> /* For _IO* macros */ 85 #define DRM_IOCTL_NR(n) _IOC_NR(n) 86 #define DRM_IOC_VOID _IOC_NONE 87 #define DRM_IOC_READ _IOC_READ 88 #define DRM_IOC_WRITE _IOC_WRITE 89 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE 90 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 91 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) 92 #if (defined(__FreeBSD__) || defined(__FreeBSD_kernel__)) && defined(IN_MODULE) 93 /* Prevent name collision when including sys/ioccom.h */ 94 #undef ioctl 95 #include <sys/ioccom.h> 96 #define ioctl(a,b,c) xf86ioctl(a,b,c) 97 #else 98 #include <sys/ioccom.h> 99 #endif /* __FreeBSD__ && xf86ioctl */ 100 #define DRM_IOCTL_NR(n) ((n) & 0xff) 101 #define DRM_IOC_VOID IOC_VOID 102 #define DRM_IOC_READ IOC_OUT 103 #define DRM_IOC_WRITE IOC_IN 104 #define DRM_IOC_READWRITE IOC_INOUT 105 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 106 #endif 107 108 /* Solaris-specific. */ 109 #if defined(__SOLARIS__) || defined(sun) 110 #define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) 111 112 #define _IOC_NRBITS 8 113 #define _IOC_TYPEBITS 8 114 #define _IOC_SIZEBITS 14 115 #define _IOC_DIRBITS 2 116 117 #define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) 118 #define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) 119 #define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) 120 #define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) 121 122 #define _IOC_NRSHIFT 0 123 #define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) 124 #define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) 125 #define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) 126 127 #define _IOC_NONE 0U 128 #define _IOC_WRITE 1U 129 #define _IOC_READ 2U 130 131 #define _IOC(dir, type, nr, size) \ 132 (((dir) << _IOC_DIRSHIFT) | \ 133 ((type) << _IOC_TYPESHIFT) | \ 134 ((nr) << _IOC_NRSHIFT) | \ 135 ((size) << _IOC_SIZESHIFT)) 136 137 /* used for X server compile */ 138 #if !defined(_KERNEL) 139 #define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0) 140 #define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof (size)) 141 #define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof (size)) 142 #define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, \ 143 (type), (nr), sizeof (size)) 144 145 #define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) 146 #define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) 147 #define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) 148 #define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) 149 150 #define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) 151 #define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) 152 #define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) 153 #define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) 154 #define IOCSIZE_SHIFT (_IOC_SIZESHIFT) 155 #endif /* _KERNEL */ 156 157 #define DRM_IOCTL_NR(n) _IOC_NR(n) 158 #define DRM_IOC_VOID IOC_VOID 159 #define DRM_IOC_READ IOC_OUT 160 #define DRM_IOC_WRITE IOC_IN 161 #define DRM_IOC_READWRITE IOC_INOUT 162 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 163 164 #endif /* __Solaris__ or sun */ 165 #define XFREE86_VERSION(major,minor,patch,snap) \ 166 ((major << 16) | (minor << 8) | patch) 167 168 #ifndef CONFIG_XFREE86_VERSION 169 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0) 170 #endif 171 172 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0) 173 #define DRM_PROC_DEVICES "/proc/devices" 174 #define DRM_PROC_MISC "/proc/misc" 175 #define DRM_PROC_DRM "/proc/drm" 176 #define DRM_DEV_DRM "/dev/drm" 177 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) 178 #define DRM_DEV_UID 0 179 #define DRM_DEV_GID 0 180 #endif 181 182 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0) 183 #ifdef __OpenBSD__ 184 #define DRM_MAJOR 81 185 #endif 186 #if defined(__linux__) || defined(__NetBSD__) 187 #define DRM_MAJOR 226 188 #endif 189 #define DRM_MAX_MINOR 15 190 #endif 191 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ 192 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ 193 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ 194 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ 195 196 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 197 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 198 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) 199 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) 200 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) 201 202 #if defined(__linux__) 203 #if defined(__KERNEL__) 204 typedef __u64 drm_u64_t; 205 #else 206 typedef unsigned long long drm_u64_t; 207 #endif 208 209 typedef unsigned int drm_handle_t; 210 #else 211 #include <sys/types.h> 212 typedef uint64_t drm_u64_t; 213 typedef unsigned long long drm_handle_t; /**< To mapped regions */ 214 #endif 215 typedef unsigned int drm_context_t; /**< GLXContext handle */ 216 typedef unsigned int drm_drawable_t; 217 typedef unsigned int drm_magic_t; /**< Magic for authentication */ 218 219 /** 220 * Cliprect. 221 * 222 * \warning If you change this structure, make sure you change 223 * XF86DRIClipRectRec in the server as well 224 * 225 * \note KW: Actually it's illegal to change either for 226 * backwards-compatibility reasons. 227 */ 228 typedef struct drm_clip_rect { 229 unsigned short x1; 230 unsigned short y1; 231 unsigned short x2; 232 unsigned short y2; 233 } drm_clip_rect_t; 234 235 /** 236 * Drawable information. 237 */ 238 typedef struct drm_drawable_info { 239 unsigned int num_rects; 240 drm_clip_rect_t *rects; 241 } drm_drawable_info_t; 242 243 /** 244 * Texture region, 245 */ 246 typedef struct drm_tex_region { 247 unsigned char next; 248 unsigned char prev; 249 unsigned char in_use; 250 unsigned char padding; 251 unsigned int age; 252 } drm_tex_region_t; 253 254 /** 255 * Hardware lock. 256 * 257 * The lock structure is a simple cache-line aligned integer. To avoid 258 * processor bus contention on a multiprocessor system, there should not be any 259 * other data stored in the same cache line. 260 */ 261 typedef struct drm_hw_lock { 262 __volatile__ unsigned int lock; /**< lock variable */ 263 char padding[60]; /**< Pad to cache line */ 264 } drm_hw_lock_t; 265 266 /* This is beyond ugly, and only works on GCC. However, it allows me to use 267 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real 268 * fix is to use uint32_t instead of size_t, but that fix will break existing 269 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will* 270 * eventually happen, though. I chose 'unsigned long' to be the fallback type 271 * because that works on all the platforms I know about. Hopefully, the 272 * real fix will happen before that bites us. 273 */ 274 275 #ifdef __SIZE_TYPE__ 276 # define DRM_SIZE_T __SIZE_TYPE__ 277 #else 278 #if !defined(__SOLARIS__) && !defined(sun) 279 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!" 280 #endif 281 # define DRM_SIZE_T unsigned long 282 #endif 283 284 /** 285 * DRM_IOCTL_VERSION ioctl argument type. 286 * 287 * \sa drmGetVersion(). 288 */ 289 typedef struct drm_version { 290 int version_major; /**< Major version */ 291 int version_minor; /**< Minor version */ 292 int version_patchlevel; /**< Patch level */ 293 DRM_SIZE_T name_len; /**< Length of name buffer */ 294 char __user *name; /**< Name of driver */ 295 DRM_SIZE_T date_len; /**< Length of date buffer */ 296 char __user *date; /**< User-space buffer to hold date */ 297 DRM_SIZE_T desc_len; /**< Length of desc buffer */ 298 char __user *desc; /**< User-space buffer to hold desc */ 299 } drm_version_t; 300 301 /** 302 * DRM_IOCTL_GET_UNIQUE ioctl argument type. 303 * 304 * \sa drmGetBusid() and drmSetBusId(). 305 */ 306 typedef struct drm_unique { 307 DRM_SIZE_T unique_len; /**< Length of unique */ 308 char __user *unique; /**< Unique name for driver instantiation */ 309 } drm_unique_t; 310 311 #undef DRM_SIZE_T 312 313 typedef struct drm_list { 314 int count; /**< Length of user-space structures */ 315 drm_version_t __user *version; 316 } drm_list_t; 317 318 typedef struct drm_block { 319 int unused; 320 } drm_block_t; 321 322 /** 323 * DRM_IOCTL_CONTROL ioctl argument type. 324 * 325 * \sa drmCtlInstHandler() and drmCtlUninstHandler(). 326 */ 327 typedef struct drm_control { 328 enum { 329 DRM_ADD_COMMAND, 330 DRM_RM_COMMAND, 331 DRM_INST_HANDLER, 332 DRM_UNINST_HANDLER 333 } func; 334 int irq; 335 } drm_control_t; 336 337 /** 338 * Type of memory to map. 339 */ 340 typedef enum drm_map_type { 341 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ 342 _DRM_REGISTERS = 1, /**< no caching, no core dump */ 343 _DRM_SHM = 2, /**< shared, cached */ 344 _DRM_AGP = 3, /**< AGP/GART */ 345 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ 346 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ 347 _DRM_TTM = 6 348 } drm_map_type_t; 349 350 /** 351 * Memory mapping flags. 352 */ 353 typedef enum drm_map_flags { 354 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ 355 _DRM_READ_ONLY = 0x02, 356 _DRM_LOCKED = 0x04, /**< shared, cached, locked */ 357 _DRM_KERNEL = 0x08, /**< kernel requires access */ 358 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ 359 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ 360 _DRM_REMOVABLE = 0x40 /**< Removable mapping */ 361 } drm_map_flags_t; 362 363 typedef struct drm_ctx_priv_map { 364 unsigned int ctx_id; /**< Context requesting private mapping */ 365 void *handle; /**< Handle of map */ 366 } drm_ctx_priv_map_t; 367 368 /** 369 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls 370 * argument type. 371 * 372 * \sa drmAddMap(). 373 */ 374 typedef struct drm_map { 375 unsigned long long offset; /**< Requested physical address (0 for SAREA)*/ 376 unsigned long long handle; 377 /**< User-space: "Handle" to pass to mmap() */ 378 /**< Kernel-space: kernel-virtual address */ 379 unsigned long size; /**< Requested physical size (bytes) */ 380 drm_map_type_t type; /**< Type of memory to map */ 381 drm_map_flags_t flags; /**< Flags */ 382 int mtrr; /**< MTRR slot used */ 383 /* Private data */ 384 } drm_map_t; 385 386 /** 387 * DRM_IOCTL_GET_CLIENT ioctl argument type. 388 */ 389 typedef struct drm_client { 390 int idx; /**< Which client desired? */ 391 int auth; /**< Is client authenticated? */ 392 unsigned long pid; /**< Process ID */ 393 unsigned long uid; /**< User ID */ 394 unsigned long magic; /**< Magic */ 395 unsigned long iocs; /**< Ioctl count */ 396 } drm_client_t; 397 398 typedef enum { 399 _DRM_STAT_LOCK, 400 _DRM_STAT_OPENS, 401 _DRM_STAT_CLOSES, 402 _DRM_STAT_IOCTLS, 403 _DRM_STAT_LOCKS, 404 _DRM_STAT_UNLOCKS, 405 _DRM_STAT_VALUE, /**< Generic value */ 406 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ 407 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ 408 409 _DRM_STAT_IRQ, /**< IRQ */ 410 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ 411 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ 412 _DRM_STAT_DMA, /**< DMA */ 413 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ 414 _DRM_STAT_MISSED /**< Missed DMA opportunity */ 415 /* Add to the *END* of the list */ 416 } drm_stat_type_t; 417 418 /** 419 * DRM_IOCTL_GET_STATS ioctl argument type. 420 */ 421 typedef struct drm_stats { 422 unsigned long count; 423 struct { 424 unsigned long value; 425 drm_stat_type_t type; 426 } data[15]; 427 } drm_stats_t; 428 429 /** 430 * Hardware locking flags. 431 */ 432 typedef enum drm_lock_flags { 433 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 434 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 435 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 436 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 437 /* These *HALT* flags aren't supported yet 438 -- they will be used to support the 439 full-screen DGA-like mode. */ 440 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 441 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 442 } drm_lock_flags_t; 443 444 /** 445 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. 446 * 447 * \sa drmGetLock() and drmUnlock(). 448 */ 449 typedef struct drm_lock { 450 int context; 451 drm_lock_flags_t flags; 452 } drm_lock_t; 453 454 /** 455 * DMA flags 456 * 457 * \warning 458 * These values \e must match xf86drm.h. 459 * 460 * \sa drm_dma. 461 */ 462 typedef enum drm_dma_flags { 463 /* Flags for DMA buffer dispatch */ 464 _DRM_DMA_BLOCK = 0x01, /**< 465 * Block until buffer dispatched. 466 * 467 * \note The buffer may not yet have 468 * been processed by the hardware -- 469 * getting a hardware lock with the 470 * hardware quiescent will ensure 471 * that the buffer has been 472 * processed. 473 */ 474 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 475 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 476 477 /* Flags for DMA buffer request */ 478 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 479 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 480 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 481 } drm_dma_flags_t; 482 483 /** 484 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. 485 * 486 * \sa drmAddBufs(). 487 */ 488 typedef enum { 489 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ 490 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ 491 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ 492 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ 493 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ 494 } drm_buf_flag; 495 typedef struct drm_buf_desc { 496 int count; /**< Number of buffers of this size */ 497 int size; /**< Size in bytes */ 498 int low_mark; /**< Low water mark */ 499 int high_mark; /**< High water mark */ 500 drm_buf_flag flags; 501 unsigned long agp_start; /**< 502 * Start address of where the AGP buffers are 503 * in the AGP aperture 504 */ 505 } drm_buf_desc_t; 506 507 /** 508 * DRM_IOCTL_INFO_BUFS ioctl argument type. 509 */ 510 typedef struct drm_buf_info { 511 int count; /**< Number of buffers described in list */ 512 drm_buf_desc_t __user *list; /**< List of buffer descriptions */ 513 } drm_buf_info_t; 514 515 /** 516 * DRM_IOCTL_FREE_BUFS ioctl argument type. 517 */ 518 typedef struct drm_buf_free { 519 int count; 520 int __user *list; 521 } drm_buf_free_t; 522 523 /** 524 * Buffer information 525 * 526 * \sa drm_buf_map. 527 */ 528 typedef struct drm_buf_pub { 529 int idx; /**< Index into the master buffer list */ 530 int total; /**< Buffer size */ 531 int used; /**< Amount of buffer in use (for DMA) */ 532 void __user *address; /**< Address of buffer */ 533 } drm_buf_pub_t; 534 535 /** 536 * DRM_IOCTL_MAP_BUFS ioctl argument type. 537 */ 538 typedef struct drm_buf_map { 539 int count; /**< Length of the buffer list */ 540 #if defined(__cplusplus) 541 void __user *c_virtual; 542 #else 543 void __user *virtual; /**< Mmap'd area in user-virtual */ 544 #endif 545 drm_buf_pub_t __user *list; /**< Buffer information */ 546 int fd; 547 } drm_buf_map_t; 548 549 /** 550 * DRM_IOCTL_DMA ioctl argument type. 551 * 552 * Indices here refer to the offset into the buffer list in drm_buf_get. 553 * 554 * \sa drmDMA(). 555 */ 556 typedef struct drm_dma { 557 int context; /**< Context handle */ 558 int send_count; /**< Number of buffers to send */ 559 int __user *send_indices; /**< List of handles to buffers */ 560 int __user *send_sizes; /**< Lengths of data to send */ 561 drm_dma_flags_t flags; /**< Flags */ 562 int request_count; /**< Number of buffers requested */ 563 int request_size; /**< Desired size for buffers */ 564 int __user *request_indices; /**< Buffer information */ 565 int __user *request_sizes; 566 int granted_count; /**< Number of buffers granted */ 567 } drm_dma_t; 568 569 typedef enum { 570 _DRM_CONTEXT_PRESERVED = 0x01, 571 _DRM_CONTEXT_2DONLY = 0x02 572 } drm_ctx_flags_t; 573 574 /** 575 * DRM_IOCTL_ADD_CTX ioctl argument type. 576 * 577 * \sa drmCreateContext() and drmDestroyContext(). 578 */ 579 typedef struct drm_ctx { 580 drm_context_t handle; 581 drm_ctx_flags_t flags; 582 } drm_ctx_t; 583 584 /** 585 * DRM_IOCTL_RES_CTX ioctl argument type. 586 */ 587 typedef struct drm_ctx_res { 588 int count; 589 drm_ctx_t __user *contexts; 590 } drm_ctx_res_t; 591 592 593 /** 594 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. 595 */ 596 typedef struct drm_draw { 597 drm_drawable_t handle; 598 } drm_draw_t; 599 600 /** 601 * DRM_IOCTL_UPDATE_DRAW ioctl argument type. 602 */ 603 typedef enum { 604 DRM_DRAWABLE_CLIPRECTS, 605 } drm_drawable_info_type_t; 606 607 typedef struct drm_update_draw { 608 drm_drawable_t handle; 609 unsigned int type; 610 unsigned int num; 611 unsigned long long data; 612 } drm_update_draw_t; 613 614 /** 615 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. 616 */ 617 typedef struct drm_auth { 618 drm_magic_t magic; 619 } drm_auth_t; 620 621 /** 622 * DRM_IOCTL_IRQ_BUSID ioctl argument type. 623 * 624 * \sa drmGetInterruptFromBusID(). 625 */ 626 typedef struct drm_irq_busid { 627 int irq; /**< IRQ number */ 628 int busnum; /**< bus number */ 629 int devnum; /**< device number */ 630 int funcnum; /**< function number */ 631 } drm_irq_busid_t; 632 633 typedef enum { 634 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 635 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 636 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 637 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 638 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */ 639 } drm_vblank_seq_type_t; 640 641 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) 642 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \ 643 _DRM_VBLANK_NEXTONMISS) 644 645 struct drm_wait_vblank_request { 646 drm_vblank_seq_type_t type; 647 unsigned int sequence; 648 unsigned long signal; 649 }; 650 651 struct drm_wait_vblank_reply { 652 drm_vblank_seq_type_t type; 653 unsigned int sequence; 654 long tval_sec; 655 long tval_usec; 656 }; 657 658 /** 659 * DRM_IOCTL_WAIT_VBLANK ioctl argument type. 660 * 661 * \sa drmWaitVBlank(). 662 */ 663 typedef union drm_wait_vblank { 664 struct drm_wait_vblank_request request; 665 struct drm_wait_vblank_reply reply; 666 } drm_wait_vblank_t; 667 668 /** 669 * DRM_IOCTL_AGP_ENABLE ioctl argument type. 670 * 671 * \sa drmAgpEnable(). 672 */ 673 typedef struct drm_agp_mode { 674 unsigned long mode; /**< AGP mode */ 675 } drm_agp_mode_t; 676 677 /** 678 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. 679 * 680 * \sa drmAgpAlloc() and drmAgpFree(). 681 */ 682 typedef struct drm_agp_buffer { 683 unsigned long size; /**< In bytes -- will round to page boundary */ 684 unsigned long handle; /**< Used for binding / unbinding */ 685 unsigned long type; /**< Type of memory to allocate */ 686 unsigned long physical; /**< Physical used by i810 */ 687 } drm_agp_buffer_t; 688 689 /** 690 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. 691 * 692 * \sa drmAgpBind() and drmAgpUnbind(). 693 */ 694 typedef struct drm_agp_binding { 695 unsigned long handle; /**< From drm_agp_buffer */ 696 unsigned long offset; /**< In bytes -- will round to page boundary */ 697 } drm_agp_binding_t; 698 699 /** 700 * DRM_IOCTL_AGP_INFO ioctl argument type. 701 * 702 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), 703 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), 704 * drmAgpVendorId() and drmAgpDeviceId(). 705 */ 706 typedef struct drm_agp_info { 707 int agp_version_major; 708 int agp_version_minor; 709 unsigned long mode; 710 unsigned long aperture_base; /**< physical address */ 711 unsigned long aperture_size; /**< bytes */ 712 unsigned long memory_allowed; /**< bytes */ 713 unsigned long memory_used; 714 715 /** \name PCI information */ 716 /*@{ */ 717 unsigned short id_vendor; 718 unsigned short id_device; 719 /*@} */ 720 } drm_agp_info_t; 721 722 /** 723 * DRM_IOCTL_SG_ALLOC ioctl argument type. 724 */ 725 typedef struct drm_scatter_gather { 726 unsigned long size; /**< In bytes -- will round to page boundary */ 727 unsigned long handle; /**< Used for mapping / unmapping */ 728 } drm_scatter_gather_t; 729 730 /** 731 * DRM_IOCTL_SET_VERSION ioctl argument type. 732 */ 733 typedef struct drm_set_version { 734 int drm_di_major; 735 int drm_di_minor; 736 int drm_dd_major; 737 int drm_dd_minor; 738 } drm_set_version_t; 739 740 /** 741 * \name Ioctls Definitions 742 */ 743 /*@{*/ 744 745 #define DRM_IOCTL_BASE 'd' 746 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) 747 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) 748 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) 749 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) 750 751 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t) 752 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t) 753 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t) 754 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t) 755 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t) 756 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t) 757 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t) 758 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t) 759 760 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t) 761 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t) 762 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t) 763 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t) 764 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t) 765 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t) 766 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t) 767 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t) 768 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t) 769 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t) 770 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t) 771 772 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t) 773 774 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t) 775 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t) 776 777 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t) 778 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t) 779 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t) 780 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t) 781 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t) 782 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t) 783 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t) 784 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t) 785 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t) 786 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t) 787 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t) 788 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t) 789 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t) 790 791 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) 792 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) 793 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t) 794 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t) 795 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t) 796 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t) 797 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t) 798 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t) 799 800 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t) 801 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t) 802 803 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t) 804 805 /*@}*/ 806 807 /** 808 * Device specific ioctls should only be in their respective headers 809 * The device specific ioctl range is from 0x40 to 0x99. 810 * Generic IOCTLS restart at 0xA0. 811 * 812 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and 813 * drmCommandReadWrite(). 814 */ 815 #define DRM_COMMAND_BASE 0x40 816 #define DRM_COMMAND_END 0xA0 817 818 #endif /* _DRM_H_ */ 819