1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 /* 30 * Bit test macros, returning boolean_t values 31 */ 32 #define BIS(w, b) (((w) & (b)) ? B_TRUE : B_FALSE) 33 #define BIC(w, b) (((w) & (b)) ? B_FALSE : B_TRUE) 34 #define UPORDOWN(x) ((x) ? "up" : "down") 35 36 /* 37 * ========== Copper (PHY) support ========== 38 */ 39 40 #define BGE_DBG BGE_DBG_PHY /* debug flag for this code */ 41 42 /* 43 * #defines: 44 * BGE_COPPER_WIRESPEED controls whether the Broadcom WireSpeed(tm) 45 * feature is enabled. We need to recheck whether this can be 46 * enabled; at one time it seemed to interact unpleasantly with the 47 * loopback modes. 48 * 49 * BGE_COPPER_IDLEOFF controls whether the (copper) PHY power is 50 * turned off when the PHY is idled i.e. during driver suspend(). 51 * For now this is disabled because the chip doesn't seem to 52 * resume cleanly if the PHY power is turned off. 53 */ 54 #define BGE_COPPER_WIRESPEED B_TRUE 55 #define BGE_COPPER_IDLEOFF B_FALSE 56 57 /* 58 * The arrays below can be indexed by the MODE bits from the Auxiliary 59 * Status register to determine the current speed/duplex settings. 60 */ 61 static const int16_t bge_copper_link_speed[] = { 62 0, /* MII_AUX_STATUS_MODE_NONE */ 63 10, /* MII_AUX_STATUS_MODE_10_H */ 64 10, /* MII_AUX_STATUS_MODE_10_F */ 65 100, /* MII_AUX_STATUS_MODE_100_H */ 66 0, /* MII_AUX_STATUS_MODE_100_4 */ 67 100, /* MII_AUX_STATUS_MODE_100_F */ 68 1000, /* MII_AUX_STATUS_MODE_1000_H */ 69 1000 /* MII_AUX_STATUS_MODE_1000_F */ 70 }; 71 72 static const int8_t bge_copper_link_duplex[] = { 73 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */ 74 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */ 75 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */ 76 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */ 77 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */ 78 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */ 79 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_1000_H */ 80 LINK_DUPLEX_FULL /* MII_AUX_STATUS_MODE_1000_F */ 81 }; 82 83 static const int16_t bge_copper_link_speed_5906[] = { 84 0, /* MII_AUX_STATUS_MODE_NONE */ 85 10, /* MII_AUX_STATUS_MODE_10_H */ 86 10, /* MII_AUX_STATUS_MODE_10_F */ 87 100, /* MII_AUX_STATUS_MODE_100_H */ 88 0, /* MII_AUX_STATUS_MODE_100_4 */ 89 100, /* MII_AUX_STATUS_MODE_100_F */ 90 0, /* MII_AUX_STATUS_MODE_1000_H */ 91 0 /* MII_AUX_STATUS_MODE_1000_F */ 92 }; 93 94 static const int8_t bge_copper_link_duplex_5906[] = { 95 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_NONE */ 96 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_10_H */ 97 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_10_F */ 98 LINK_DUPLEX_HALF, /* MII_AUX_STATUS_MODE_100_H */ 99 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_100_4 */ 100 LINK_DUPLEX_FULL, /* MII_AUX_STATUS_MODE_100_F */ 101 LINK_DUPLEX_UNKNOWN, /* MII_AUX_STATUS_MODE_1000_H */ 102 LINK_DUPLEX_UNKNOWN /* MII_AUX_STATUS_MODE_1000_F */ 103 }; 104 105 #if BGE_DEBUGGING 106 107 static void 108 bge_phydump(bge_t *bgep, uint16_t mii_status, uint16_t aux) 109 { 110 uint16_t regs[32]; 111 int i; 112 113 ASSERT(mutex_owned(bgep->genlock)); 114 115 for (i = 0; i < 32; ++i) 116 switch (i) { 117 default: 118 regs[i] = bge_mii_get16(bgep, i); 119 break; 120 121 case MII_STATUS: 122 regs[i] = mii_status; 123 break; 124 125 case MII_AUX_STATUS: 126 regs[i] = aux; 127 break; 128 129 case 0x0b: case 0x0c: case 0x0d: case 0x0e: 130 case 0x15: case 0x16: case 0x17: 131 case 0x1c: 132 case 0x1f: 133 /* reserved registers -- don't read these */ 134 regs[i] = 0; 135 break; 136 } 137 138 for (i = 0; i < 32; i += 8) 139 BGE_DEBUG(("bge_phydump: " 140 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 141 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 142 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 143 } 144 145 #endif /* BGE_DEBUGGING */ 146 147 /* 148 * Basic low-level function to probe for a PHY 149 * 150 * Returns TRUE if the PHY responds with valid data, FALSE otherwise 151 */ 152 static boolean_t 153 bge_phy_probe(bge_t *bgep) 154 { 155 uint16_t miicfg; 156 uint32_t nicsig, niccfg; 157 158 BGE_TRACE(("bge_phy_probe($%p)", (void *)bgep)); 159 160 ASSERT(mutex_owned(bgep->genlock)); 161 162 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 163 if (nicsig == BGE_NIC_DATA_SIG) { 164 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 165 switch (niccfg & BGE_NIC_CFG_PHY_TYPE_MASK) { 166 default: 167 case BGE_NIC_CFG_PHY_TYPE_COPPER: 168 return (B_TRUE); 169 case BGE_NIC_CFG_PHY_TYPE_FIBER: 170 return (B_FALSE); 171 } 172 } else { 173 /* 174 * Read the MII_STATUS register twice, in 175 * order to clear any sticky bits (but they should 176 * have been cleared by the RESET, I think). 177 */ 178 miicfg = bge_mii_get16(bgep, MII_STATUS); 179 miicfg = bge_mii_get16(bgep, MII_STATUS); 180 BGE_DEBUG(("bge_phy_probe: status 0x%x", miicfg)); 181 182 /* 183 * Now check the value read; it should have at least one bit set 184 * (for the device capabilities) and at least one clear (one of 185 * the error bits). So if we see all 0s or all 1s, there's a 186 * problem. In particular, bge_mii_get16() returns all 1s if 187 * communications fails ... 188 */ 189 switch (miicfg) { 190 case 0x0000: 191 case 0xffff: 192 return (B_FALSE); 193 194 default : 195 return (B_TRUE); 196 } 197 } 198 } 199 200 /* 201 * Basic low-level function to reset the PHY. 202 * Doesn't incorporate any special-case workarounds. 203 * 204 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 205 */ 206 static boolean_t 207 bge_phy_reset(bge_t *bgep) 208 { 209 uint16_t control; 210 uint_t count; 211 212 BGE_TRACE(("bge_phy_reset($%p)", (void *)bgep)); 213 214 ASSERT(mutex_owned(bgep->genlock)); 215 216 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 217 drv_usecwait(40); 218 /* put PHY into ready state */ 219 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 220 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 221 drv_usecwait(40); 222 } 223 224 /* 225 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 226 */ 227 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_RESET); 228 for (count = 0; ++count < 1000; ) { 229 drv_usecwait(5); 230 control = bge_mii_get16(bgep, MII_CONTROL); 231 if (BIC(control, MII_CONTROL_RESET)) 232 return (B_TRUE); 233 } 234 235 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 236 (void) bge_adj_volt_5906(bgep); 237 238 BGE_DEBUG(("bge_phy_reset: FAILED, control now 0x%x", control)); 239 240 return (B_FALSE); 241 } 242 243 /* 244 * Basic low-level function to powerdown the PHY, if supported 245 * If powerdown support is compiled out, this function does nothing. 246 */ 247 static void 248 bge_phy_powerdown(bge_t *bgep) 249 { 250 BGE_TRACE(("bge_phy_powerdown")); 251 #if BGE_COPPER_IDLEOFF 252 bge_mii_put16(bgep, MII_CONTROL, MII_CONTROL_PWRDN); 253 #endif /* BGE_COPPER_IDLEOFF */ 254 } 255 256 /* 257 * The following functions are based on sample code provided by 258 * Broadcom (20-June-2003), and implement workarounds said to be 259 * required on the early revisions of the BCM5703/4C. 260 * 261 * The registers and values used are mostly UNDOCUMENTED, and 262 * therefore don't have symbolic names ;-( 263 * 264 * Many of the comments are straight out of the Broadcom code: 265 * even where the code has been restructured, the original 266 * comments have been preserved in order to explain what these 267 * undocumented registers & values are all about ... 268 */ 269 270 static void 271 bge_phy_macro_wait(bge_t *bgep) 272 { 273 uint_t count; 274 275 for (count = 100; --count; ) 276 if ((bge_mii_get16(bgep, 0x16) & 0x1000) == 0) 277 break; 278 } 279 280 /* 281 * PHY test data pattern: 282 * 283 * For 5703/04, each DFE TAP has 21-bits (low word 15, hi word 6) 284 * For 5705, each DFE TAP has 19-bits (low word 15, hi word 4) 285 * For simplicity, we check only 19-bits, so we don't have to 286 * distinguish which chip it is. 287 * the LO word contains 15 bits, make sure pattern data is < 0x7fff 288 * the HI word contains 6 bits, make sure pattern data is < 0x003f 289 */ 290 #define N_CHANNELS 4 291 #define N_TAPS 3 292 293 static struct { 294 uint16_t lo; 295 uint16_t hi; 296 } tap_data[N_CHANNELS][N_TAPS] = { 297 { 298 { 0x5555, 0x0005 }, /* ch0, TAP 0, LO/HI pattern */ 299 { 0x2aaa, 0x000a }, /* ch0, TAP 1, LO/HI pattern */ 300 { 0x3456, 0x0003 } /* ch0, TAP 2, LO/HI pattern */ 301 }, 302 { 303 { 0x2aaa, 0x000a }, /* ch1, TAP 0, LO/HI pattern */ 304 { 0x3333, 0x0003 }, /* ch1, TAP 1, LO/HI pattern */ 305 { 0x789a, 0x0005 } /* ch1, TAP 2, LO/HI pattern */ 306 }, 307 { 308 { 0x5a5a, 0x0005 }, /* ch2, TAP 0, LO/HI pattern */ 309 { 0x2a6a, 0x000a }, /* ch2, TAP 1, LO/HI pattern */ 310 { 0x1bcd, 0x0003 } /* ch2, TAP 2, LO/HI pattern */ 311 }, 312 { 313 { 0x2a5a, 0x000a }, /* ch3, TAP 0, LO/HI pattern */ 314 { 0x33c3, 0x0003 }, /* ch3, TAP 1, LO/HI pattern */ 315 { 0x2ef1, 0x0005 } /* ch3, TAP 2, LO/HI pattern */ 316 } 317 }; 318 319 /* 320 * Check whether the PHY has locked up after a RESET. 321 * 322 * Returns TRUE if it did, FALSE is it's OK ;-) 323 */ 324 static boolean_t 325 bge_phy_locked_up(bge_t *bgep) 326 { 327 uint16_t dataLo; 328 uint16_t dataHi; 329 uint_t chan; 330 uint_t tap; 331 332 /* 333 * Check TAPs for all 4 channels, as soon as we see a lockup 334 * we'll stop checking. 335 */ 336 for (chan = 0; chan < N_CHANNELS; ++chan) { 337 /* Select channel and set TAP index to 0 */ 338 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 339 /* Freeze filter again just to be safe */ 340 bge_mii_put16(bgep, 0x16, 0x0002); 341 342 /* 343 * Write fixed pattern to the RAM, 3 TAPs for 344 * each channel, each TAP have 2 WORDs (LO/HI) 345 */ 346 for (tap = 0; tap < N_TAPS; ++tap) { 347 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].lo); 348 bge_mii_put16(bgep, 0x15, tap_data[chan][tap].hi); 349 } 350 351 /* 352 * Active PHY's Macro operation to write DFE 353 * TAP from RAM, and wait for Macro to complete. 354 */ 355 bge_mii_put16(bgep, 0x16, 0x0202); 356 bge_phy_macro_wait(bgep); 357 358 /* 359 * Done with write phase, now begin read phase. 360 */ 361 362 /* Select channel and set TAP index to 0 */ 363 bge_mii_put16(bgep, 0x17, (chan << 13) | 0x0200); 364 365 /* 366 * Active PHY's Macro operation to load DFE 367 * TAP to RAM, and wait for Macro to complete 368 */ 369 bge_mii_put16(bgep, 0x16, 0x0082); 370 bge_phy_macro_wait(bgep); 371 372 /* Enable "pre-fetch" */ 373 bge_mii_put16(bgep, 0x16, 0x0802); 374 bge_phy_macro_wait(bgep); 375 376 /* 377 * Read back the TAP values. 3 TAPs for each 378 * channel, each TAP have 2 WORDs (LO/HI) 379 */ 380 for (tap = 0; tap < N_TAPS; ++tap) { 381 /* 382 * Read Lo/Hi then wait for 'done' is faster. 383 * For DFE TAP, the HI word contains 6 bits, 384 * LO word contains 15 bits 385 */ 386 dataLo = bge_mii_get16(bgep, 0x15) & 0x7fff; 387 dataHi = bge_mii_get16(bgep, 0x15) & 0x003f; 388 bge_phy_macro_wait(bgep); 389 390 /* 391 * Check if what we wrote is what we read back. 392 * If failed, then the PHY is locked up, we need 393 * to do PHY reset again 394 */ 395 if (dataLo != tap_data[chan][tap].lo) 396 return (B_TRUE); /* wedged! */ 397 398 if (dataHi != tap_data[chan][tap].hi) 399 return (B_TRUE); /* wedged! */ 400 } 401 } 402 403 /* 404 * The PHY isn't locked up ;-) 405 */ 406 return (B_FALSE); 407 } 408 409 /* 410 * Special-case code to reset the PHY on the 5702/5703/5704C/5705/5782. 411 * Tries up to 5 times to recover from failure to reset or PHY lockup. 412 * 413 * Returns TRUE on success, FALSE if there's an unrecoverable problem 414 */ 415 static boolean_t 416 bge_phy_reset_and_check(bge_t *bgep) 417 { 418 boolean_t reset_success; 419 boolean_t phy_locked; 420 uint16_t extctrl; 421 uint_t retries; 422 423 for (retries = 0; retries < 5; ++retries) { 424 /* Issue a phy reset, and wait for reset to complete */ 425 /* Assuming reset is successful first */ 426 reset_success = bge_phy_reset(bgep); 427 428 /* 429 * Now go check the DFE TAPs to see if locked up, but 430 * first, we need to set up PHY so we can read DFE 431 * TAPs. 432 */ 433 434 /* 435 * Disable Transmitter and Interrupt, while we play 436 * with the PHY registers, so the link partner won't 437 * see any strange data and the Driver won't see any 438 * interrupts. 439 */ 440 extctrl = bge_mii_get16(bgep, 0x10); 441 bge_mii_put16(bgep, 0x10, extctrl | 0x3000); 442 443 /* Setup Full-Duplex, 1000 mbps */ 444 bge_mii_put16(bgep, 0x0, 0x0140); 445 446 /* Set to Master mode */ 447 bge_mii_put16(bgep, 0x9, 0x1800); 448 449 /* Enable SM_DSP_CLOCK & 6dB */ 450 bge_mii_put16(bgep, 0x18, 0x0c00); /* "the ADC fix" */ 451 452 /* Work-arounds */ 453 bge_mii_put16(bgep, 0x17, 0x201f); 454 bge_mii_put16(bgep, 0x15, 0x2aaa); 455 456 /* More workarounds */ 457 bge_mii_put16(bgep, 0x17, 0x000a); 458 bge_mii_put16(bgep, 0x15, 0x0323); /* "the Gamma fix" */ 459 460 /* Blocks the PHY control access */ 461 bge_mii_put16(bgep, 0x17, 0x8005); 462 bge_mii_put16(bgep, 0x15, 0x0800); 463 464 /* Test whether PHY locked up ;-( */ 465 phy_locked = bge_phy_locked_up(bgep); 466 if (reset_success && !phy_locked) 467 break; 468 469 /* 470 * Some problem here ... log it & retry 471 */ 472 if (!reset_success) 473 BGE_REPORT((bgep, "PHY didn't reset!")); 474 if (phy_locked) 475 BGE_REPORT((bgep, "PHY locked up!")); 476 } 477 478 /* Remove block phy control */ 479 bge_mii_put16(bgep, 0x17, 0x8005); 480 bge_mii_put16(bgep, 0x15, 0x0000); 481 482 /* Unfreeze DFE TAP filter for all channels */ 483 bge_mii_put16(bgep, 0x17, 0x8200); 484 bge_mii_put16(bgep, 0x16, 0x0000); 485 486 /* Restore PHY back to operating state */ 487 bge_mii_put16(bgep, 0x18, 0x0400); 488 489 /* Enable transmitter and interrupt */ 490 extctrl = bge_mii_get16(bgep, 0x10); 491 bge_mii_put16(bgep, 0x10, extctrl & ~0x3000); 492 493 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 494 (void) bge_adj_volt_5906(bgep); 495 496 if (!reset_success) 497 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 498 else if (phy_locked) 499 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 500 return (reset_success && !phy_locked); 501 } 502 503 static void 504 bge_phy_tweak_gmii(bge_t *bgep) 505 { 506 /* Tweak GMII timing */ 507 bge_mii_put16(bgep, 0x1c, 0x8d68); 508 bge_mii_put16(bgep, 0x1c, 0x8d68); 509 } 510 511 /* Bit Error Rate reduction fix */ 512 static void 513 bge_phy_bit_err_fix(bge_t *bgep) 514 { 515 bge_mii_put16(bgep, 0x18, 0x0c00); 516 bge_mii_put16(bgep, 0x17, 0x000a); 517 bge_mii_put16(bgep, 0x15, 0x310b); 518 bge_mii_put16(bgep, 0x17, 0x201f); 519 bge_mii_put16(bgep, 0x15, 0x9506); 520 bge_mii_put16(bgep, 0x17, 0x401f); 521 bge_mii_put16(bgep, 0x15, 0x14e2); 522 bge_mii_put16(bgep, 0x18, 0x0400); 523 } 524 525 /* 526 * End of Broadcom-derived workaround code * 527 */ 528 529 static int 530 bge_restart_copper(bge_t *bgep, boolean_t powerdown) 531 { 532 uint16_t phy_status; 533 boolean_t reset_ok; 534 535 BGE_TRACE(("bge_restart_copper($%p, %d)", (void *)bgep, powerdown)); 536 537 ASSERT(mutex_owned(bgep->genlock)); 538 539 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 540 default: 541 /* 542 * Shouldn't happen; it means we don't recognise this chip. 543 * It's probably a new one, so we'll try our best anyway ... 544 */ 545 case MHCR_CHIP_ASIC_REV_5703: 546 case MHCR_CHIP_ASIC_REV_5704: 547 case MHCR_CHIP_ASIC_REV_5705: 548 case MHCR_CHIP_ASIC_REV_5721_5751: 549 case MHCR_CHIP_ASIC_REV_5752: 550 case MHCR_CHIP_ASIC_REV_5714: 551 case MHCR_CHIP_ASIC_REV_5715: 552 reset_ok = bge_phy_reset_and_check(bgep); 553 break; 554 555 case MHCR_CHIP_ASIC_REV_5906: 556 case MHCR_CHIP_ASIC_REV_5700: 557 case MHCR_CHIP_ASIC_REV_5701: 558 /* 559 * Just a plain reset; the "check" code breaks these chips 560 */ 561 reset_ok = bge_phy_reset(bgep); 562 if (!reset_ok) 563 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 564 break; 565 } 566 if (!reset_ok) { 567 BGE_REPORT((bgep, "PHY failed to reset correctly")); 568 return (DDI_FAILURE); 569 } 570 571 /* 572 * Step 5: disable WOL (not required after RESET) 573 * 574 * Step 6: refer to errata 575 */ 576 switch (bgep->chipid.asic_rev) { 577 default: 578 break; 579 580 case MHCR_CHIP_REV_5704_A0: 581 bge_phy_tweak_gmii(bgep); 582 break; 583 } 584 585 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 586 case MHCR_CHIP_ASIC_REV_5705: 587 case MHCR_CHIP_ASIC_REV_5721_5751: 588 bge_phy_bit_err_fix(bgep); 589 break; 590 } 591 592 /* 593 * Step 7: read the MII_INTR_STATUS register twice, 594 * in order to clear any sticky bits (but they should 595 * have been cleared by the RESET, I think), and we're 596 * not using PHY interrupts anyway. 597 * 598 * Step 8: enable the PHY to interrupt on link status 599 * change (not required) 600 * 601 * Step 9: configure PHY LED Mode - not applicable? 602 * 603 * Step 10: read the MII_STATUS register twice, in 604 * order to clear any sticky bits (but they should 605 * have been cleared by the RESET, I think). 606 */ 607 phy_status = bge_mii_get16(bgep, MII_STATUS); 608 phy_status = bge_mii_get16(bgep, MII_STATUS); 609 BGE_DEBUG(("bge_restart_copper: status 0x%x", phy_status)); 610 611 /* 612 * Finally, shut down the PHY, if required 613 */ 614 if (powerdown) 615 bge_phy_powerdown(bgep); 616 return (DDI_SUCCESS); 617 } 618 619 /* 620 * Synchronise the (copper) PHY's speed/duplex/autonegotiation capabilities 621 * and advertisements with the required settings as specified by the various 622 * param_* variables that can be poked via the NDD interface. 623 * 624 * We always reset the PHY and reprogram *all* the relevant registers, 625 * not just those changed. This should cause the link to go down, and then 626 * back up again once the link is stable and autonegotiation (if enabled) 627 * is complete. We should get a link state change interrupt somewhere along 628 * the way ... 629 * 630 * NOTE: <genlock> must already be held by the caller 631 */ 632 static int 633 bge_update_copper(bge_t *bgep) 634 { 635 boolean_t adv_autoneg; 636 boolean_t adv_pause; 637 boolean_t adv_asym_pause; 638 boolean_t adv_1000fdx; 639 boolean_t adv_1000hdx; 640 boolean_t adv_100fdx; 641 boolean_t adv_100hdx; 642 boolean_t adv_10fdx; 643 boolean_t adv_10hdx; 644 645 uint16_t control; 646 uint16_t gigctrl; 647 uint16_t auxctrl; 648 uint16_t anar; 649 650 BGE_TRACE(("bge_update_copper($%p)", (void *)bgep)); 651 652 ASSERT(mutex_owned(bgep->genlock)); 653 654 BGE_DEBUG(("bge_update_copper: autoneg %d " 655 "pause %d asym_pause %d " 656 "1000fdx %d 1000hdx %d " 657 "100fdx %d 100hdx %d " 658 "10fdx %d 10hdx %d ", 659 bgep->param_adv_autoneg, 660 bgep->param_adv_pause, bgep->param_adv_asym_pause, 661 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 662 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 663 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 664 665 control = gigctrl = auxctrl = anar = 0; 666 667 /* 668 * PHY settings are normally based on the param_* variables, 669 * but if any loopback mode is in effect, that takes precedence. 670 * 671 * BGE supports MAC-internal loopback, PHY-internal loopback, 672 * and External loopback at a variety of speeds (with a special 673 * cable). In all cases, autoneg is turned OFF, full-duplex 674 * is turned ON, and the speed/mastership is forced. 675 */ 676 switch (bgep->param_loop_mode) { 677 case BGE_LOOP_NONE: 678 default: 679 adv_autoneg = bgep->param_adv_autoneg; 680 adv_pause = bgep->param_adv_pause; 681 adv_asym_pause = bgep->param_adv_asym_pause; 682 adv_1000fdx = bgep->param_adv_1000fdx; 683 adv_1000hdx = bgep->param_adv_1000hdx; 684 adv_100fdx = bgep->param_adv_100fdx; 685 adv_100hdx = bgep->param_adv_100hdx; 686 adv_10fdx = bgep->param_adv_10fdx; 687 adv_10hdx = bgep->param_adv_10hdx; 688 break; 689 690 case BGE_LOOP_EXTERNAL_1000: 691 case BGE_LOOP_EXTERNAL_100: 692 case BGE_LOOP_EXTERNAL_10: 693 case BGE_LOOP_INTERNAL_PHY: 694 case BGE_LOOP_INTERNAL_MAC: 695 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 696 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 697 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 698 bgep->param_link_duplex = LINK_DUPLEX_FULL; 699 700 switch (bgep->param_loop_mode) { 701 case BGE_LOOP_EXTERNAL_1000: 702 bgep->param_link_speed = 1000; 703 adv_1000fdx = B_TRUE; 704 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 705 gigctrl |= MII_1000BT_CTL_MASTER_CFG; 706 gigctrl |= MII_1000BT_CTL_MASTER_SEL; 707 break; 708 709 case BGE_LOOP_EXTERNAL_100: 710 bgep->param_link_speed = 100; 711 adv_100fdx = B_TRUE; 712 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 713 break; 714 715 case BGE_LOOP_EXTERNAL_10: 716 bgep->param_link_speed = 10; 717 adv_10fdx = B_TRUE; 718 auxctrl = MII_AUX_CTRL_NORM_EXT_LOOPBACK; 719 break; 720 721 case BGE_LOOP_INTERNAL_PHY: 722 bgep->param_link_speed = 1000; 723 adv_1000fdx = B_TRUE; 724 control = MII_CONTROL_LOOPBACK; 725 break; 726 727 case BGE_LOOP_INTERNAL_MAC: 728 bgep->param_link_speed = 1000; 729 adv_1000fdx = B_TRUE; 730 break; 731 } 732 } 733 734 BGE_DEBUG(("bge_update_copper: autoneg %d " 735 "pause %d asym_pause %d " 736 "1000fdx %d 1000hdx %d " 737 "100fdx %d 100hdx %d " 738 "10fdx %d 10hdx %d ", 739 adv_autoneg, 740 adv_pause, adv_asym_pause, 741 adv_1000fdx, adv_1000hdx, 742 adv_100fdx, adv_100hdx, 743 adv_10fdx, adv_10hdx)); 744 745 /* 746 * We should have at least one technology capability set; 747 * if not, we select a default of 1000Mb/s full-duplex 748 */ 749 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 750 !adv_1000hdx && !adv_100hdx && !adv_10hdx) 751 adv_1000fdx = B_TRUE; 752 753 /* 754 * Now transform the adv_* variables into the proper settings 755 * of the PHY registers ... 756 * 757 * If autonegotiation is (now) enabled, we want to trigger 758 * a new autonegotiation cycle once the PHY has been 759 * programmed with the capabilities to be advertised. 760 */ 761 if (adv_autoneg) 762 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 763 764 if (adv_1000fdx) 765 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 766 else if (adv_1000hdx) 767 control |= MII_CONTROL_1000MB; 768 else if (adv_100fdx) 769 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 770 else if (adv_100hdx) 771 control |= MII_CONTROL_100MB; 772 else if (adv_10fdx) 773 control |= MII_CONTROL_FDUPLEX; 774 else if (adv_10hdx) 775 control |= 0; 776 else 777 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 778 779 if (adv_1000fdx) 780 gigctrl |= MII_1000BT_CTL_ADV_FDX; 781 if (adv_1000hdx) 782 gigctrl |= MII_1000BT_CTL_ADV_HDX; 783 784 if (adv_100fdx) 785 anar |= MII_ABILITY_100BASE_TX_FD; 786 if (adv_100hdx) 787 anar |= MII_ABILITY_100BASE_TX; 788 if (adv_10fdx) 789 anar |= MII_ABILITY_10BASE_T_FD; 790 if (adv_10hdx) 791 anar |= MII_ABILITY_10BASE_T; 792 793 if (adv_pause) 794 anar |= MII_ABILITY_PAUSE; 795 if (adv_asym_pause) 796 anar |= MII_ABILITY_ASYM_PAUSE; 797 798 /* 799 * Munge in any other fixed bits we require ... 800 */ 801 anar |= MII_AN_SELECTOR_8023; 802 auxctrl |= MII_AUX_CTRL_NORM_TX_MODE; 803 auxctrl |= MII_AUX_CTRL_NORMAL; 804 805 /* 806 * Restart the PHY and write the new values. Note the 807 * time, so that we can say whether subsequent link state 808 * changes can be attributed to our reprogramming the PHY 809 */ 810 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) == DDI_FAILURE) 811 return (DDI_FAILURE); 812 bge_mii_put16(bgep, MII_AN_ADVERT, anar); 813 bge_mii_put16(bgep, MII_CONTROL, control); 814 bge_mii_put16(bgep, MII_AUX_CONTROL, auxctrl); 815 bge_mii_put16(bgep, MII_1000BASE_T_CONTROL, gigctrl); 816 817 BGE_DEBUG(("bge_update_copper: anar <- 0x%x", anar)); 818 BGE_DEBUG(("bge_update_copper: control <- 0x%x", control)); 819 BGE_DEBUG(("bge_update_copper: auxctrl <- 0x%x", auxctrl)); 820 BGE_DEBUG(("bge_update_copper: gigctrl <- 0x%x", gigctrl)); 821 822 #if BGE_COPPER_WIRESPEED 823 /* 824 * Enable the 'wire-speed' feature, if the chip supports it 825 * and we haven't got (any) loopback mode selected. 826 */ 827 switch (bgep->chipid.device) { 828 case DEVICE_ID_5700: 829 case DEVICE_ID_5700x: 830 case DEVICE_ID_5705C: 831 case DEVICE_ID_5782: 832 /* 833 * These chips are known or assumed not to support it 834 */ 835 break; 836 837 default: 838 /* 839 * All other Broadcom chips are expected to support it. 840 */ 841 if (bgep->param_loop_mode == BGE_LOOP_NONE) 842 bge_mii_put16(bgep, MII_AUX_CONTROL, 843 MII_AUX_CTRL_MISC_WRITE_ENABLE | 844 MII_AUX_CTRL_MISC_WIRE_SPEED | 845 MII_AUX_CTRL_MISC); 846 break; 847 } 848 #endif /* BGE_COPPER_WIRESPEED */ 849 return (DDI_SUCCESS); 850 } 851 852 static boolean_t 853 bge_check_copper(bge_t *bgep, boolean_t recheck) 854 { 855 uint32_t emac_status; 856 uint16_t mii_status; 857 uint16_t aux; 858 uint_t mode; 859 boolean_t linkup; 860 861 /* 862 * Step 10: read the status from the PHY (which is self-clearing 863 * on read!); also read & clear the main (Ethernet) MAC status 864 * (the relevant bits of this are write-one-to-clear). 865 */ 866 mii_status = bge_mii_get16(bgep, MII_STATUS); 867 emac_status = bge_reg_get32(bgep, ETHERNET_MAC_STATUS_REG); 868 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, emac_status); 869 870 BGE_DEBUG(("bge_check_copper: link %d/%s, MII status 0x%x " 871 "(was 0x%x), Ethernet MAC status 0x%x", 872 bgep->link_state, UPORDOWN(bgep->param_link_up), mii_status, 873 bgep->phy_gen_status, emac_status)); 874 875 /* 876 * If the PHY status hasn't changed since last we looked, and 877 * we not forcing a recheck (i.e. the link state was already 878 * known), there's nothing to do. 879 */ 880 if (mii_status == bgep->phy_gen_status && !recheck) 881 return (B_FALSE); 882 883 do { 884 /* 885 * Step 11: read AUX STATUS register to find speed/duplex 886 */ 887 aux = bge_mii_get16(bgep, MII_AUX_STATUS); 888 BGE_CDB(bge_phydump, (bgep, mii_status, aux)); 889 890 /* 891 * We will only consider the link UP if all the readings 892 * are consistent and give meaningful results ... 893 */ 894 mode = aux & MII_AUX_STATUS_MODE_MASK; 895 mode >>= MII_AUX_STATUS_MODE_SHIFT; 896 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 897 linkup = BIS(aux, MII_AUX_STATUS_LINKUP); 898 linkup &= BIS(mii_status, MII_STATUS_LINKUP); 899 } else { 900 linkup = bge_copper_link_speed[mode] > 0; 901 linkup &= bge_copper_link_duplex[mode] != 902 LINK_DUPLEX_UNKNOWN; 903 linkup &= BIS(aux, MII_AUX_STATUS_LINKUP); 904 linkup &= BIS(mii_status, MII_STATUS_LINKUP); 905 } 906 907 BGE_DEBUG(("bge_check_copper: MII status 0x%x aux 0x%x " 908 "=> mode %d (%s)", 909 mii_status, aux, 910 mode, UPORDOWN(linkup))); 911 912 /* 913 * Record current register values, then reread status 914 * register & loop until it stabilises ... 915 */ 916 bgep->phy_aux_status = aux; 917 bgep->phy_gen_status = mii_status; 918 mii_status = bge_mii_get16(bgep, MII_STATUS); 919 } while (mii_status != bgep->phy_gen_status); 920 921 /* 922 * Assume very little ... 923 */ 924 bgep->param_lp_autoneg = B_FALSE; 925 bgep->param_lp_1000fdx = B_FALSE; 926 bgep->param_lp_1000hdx = B_FALSE; 927 bgep->param_lp_100fdx = B_FALSE; 928 bgep->param_lp_100hdx = B_FALSE; 929 bgep->param_lp_10fdx = B_FALSE; 930 bgep->param_lp_10hdx = B_FALSE; 931 bgep->param_lp_pause = B_FALSE; 932 bgep->param_lp_asym_pause = B_FALSE; 933 bgep->param_link_autoneg = B_FALSE; 934 bgep->param_link_tx_pause = B_FALSE; 935 if (bgep->param_adv_autoneg) 936 bgep->param_link_rx_pause = B_FALSE; 937 else 938 bgep->param_link_rx_pause = bgep->param_adv_pause; 939 940 /* 941 * Discover all the link partner's abilities. 942 * These are scattered through various registers ... 943 */ 944 if (BIS(aux, MII_AUX_STATUS_LP_ANEG_ABLE)) { 945 bgep->param_lp_autoneg = B_TRUE; 946 bgep->param_link_autoneg = B_TRUE; 947 bgep->param_link_tx_pause = BIS(aux, MII_AUX_STATUS_TX_PAUSE); 948 bgep->param_link_rx_pause = BIS(aux, MII_AUX_STATUS_RX_PAUSE); 949 950 aux = bge_mii_get16(bgep, MII_1000BASE_T_STATUS); 951 bgep->param_lp_1000fdx = BIS(aux, MII_1000BT_STAT_LP_FDX_CAP); 952 bgep->param_lp_1000hdx = BIS(aux, MII_1000BT_STAT_LP_HDX_CAP); 953 954 aux = bge_mii_get16(bgep, MII_AN_LPABLE); 955 bgep->param_lp_100fdx = BIS(aux, MII_ABILITY_100BASE_TX_FD); 956 bgep->param_lp_100hdx = BIS(aux, MII_ABILITY_100BASE_TX); 957 bgep->param_lp_10fdx = BIS(aux, MII_ABILITY_10BASE_T_FD); 958 bgep->param_lp_10hdx = BIS(aux, MII_ABILITY_10BASE_T); 959 bgep->param_lp_pause = BIS(aux, MII_ABILITY_PAUSE); 960 bgep->param_lp_asym_pause = BIS(aux, MII_ABILITY_ASYM_PAUSE); 961 } 962 963 /* 964 * Step 12: update ndd-visible state parameters, BUT! 965 * we don't transfer the new state to <link_state> just yet; 966 * instead we mark the <link_state> as UNKNOWN, and our caller 967 * will resolve it once the status has stopped changing and 968 * been stable for several seconds. 969 */ 970 BGE_DEBUG(("bge_check_copper: link was %s speed %d duplex %d", 971 UPORDOWN(bgep->param_link_up), 972 bgep->param_link_speed, 973 bgep->param_link_duplex)); 974 975 if (!linkup) 976 mode = MII_AUX_STATUS_MODE_NONE; 977 bgep->param_link_up = linkup; 978 bgep->link_state = LINK_STATE_UNKNOWN; 979 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 980 if (bgep->phy_aux_status & MII_AUX_STATUS_NEG_ENABLED_5906) { 981 bgep->param_link_speed = 982 bge_copper_link_speed_5906[mode]; 983 bgep->param_link_duplex = 984 bge_copper_link_duplex_5906[mode]; 985 } else { 986 bgep->param_link_speed = (bgep->phy_aux_status & 987 MII_AUX_STATUS_SPEED_IND_5906) ? 100 : 10; 988 bgep->param_link_duplex = (bgep->phy_aux_status & 989 MII_AUX_STATUS_DUPLEX_IND_5906) ? LINK_DUPLEX_FULL : 990 LINK_DUPLEX_HALF; 991 } 992 } else { 993 bgep->param_link_speed = bge_copper_link_speed[mode]; 994 bgep->param_link_duplex = bge_copper_link_duplex[mode]; 995 } 996 997 BGE_DEBUG(("bge_check_copper: link now %s speed %d duplex %d", 998 UPORDOWN(bgep->param_link_up), 999 bgep->param_link_speed, 1000 bgep->param_link_duplex)); 1001 1002 return (B_TRUE); 1003 } 1004 1005 static const phys_ops_t copper_ops = { 1006 bge_restart_copper, 1007 bge_update_copper, 1008 bge_check_copper 1009 }; 1010 1011 1012 /* 1013 * ========== SerDes support ========== 1014 */ 1015 1016 #undef BGE_DBG 1017 #define BGE_DBG BGE_DBG_SERDES /* debug flag for this code */ 1018 1019 /* 1020 * Reinitialise the SerDes interface. Note that it normally powers 1021 * up in the disabled state, so we need to explicitly activate it. 1022 */ 1023 static int 1024 bge_restart_serdes(bge_t *bgep, boolean_t powerdown) 1025 { 1026 uint32_t macmode; 1027 1028 BGE_TRACE(("bge_restart_serdes($%p, %d)", (void *)bgep, powerdown)); 1029 1030 ASSERT(mutex_owned(bgep->genlock)); 1031 1032 /* 1033 * Ensure that the main Ethernet MAC mode register is programmed 1034 * appropriately for the SerDes interface ... 1035 */ 1036 macmode = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 1037 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1038 macmode |= ETHERNET_MODE_LINK_POLARITY; 1039 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 1040 macmode |= ETHERNET_MODE_PORTMODE_GMII; 1041 } else { 1042 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 1043 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 1044 macmode |= ETHERNET_MODE_PORTMODE_TBI; 1045 } 1046 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 1047 1048 /* 1049 * Ensure that loopback is OFF and comma detection is enabled. Then 1050 * disable the SerDes output (the first time through, it may/will 1051 * already be disabled). If we're shutting down, leave it disabled. 1052 */ 1053 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TBI_LOOPBACK); 1054 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_COMMA_DETECT); 1055 bge_reg_set32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 1056 if (powerdown) 1057 return (DDI_SUCCESS); 1058 1059 /* 1060 * Otherwise, pause, (re-)enable the SerDes output, and send 1061 * all-zero config words in order to force autoneg restart. 1062 * Invalidate the saved "link partners received configs", as 1063 * we're starting over ... 1064 */ 1065 drv_usecwait(10000); 1066 bge_reg_clr32(bgep, SERDES_CONTROL_REG, SERDES_CONTROL_TX_DISABLE); 1067 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 0); 1068 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1069 drv_usecwait(10); 1070 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, ETHERNET_MODE_SEND_CFGS); 1071 bgep->serdes_lpadv = AUTONEG_CODE_FAULT_ANEG_ERR; 1072 bgep->serdes_status = ~0U; 1073 return (DDI_SUCCESS); 1074 } 1075 1076 /* 1077 * Synchronise the SerDes speed/duplex/autonegotiation capabilities and 1078 * advertisements with the required settings as specified by the various 1079 * param_* variables that can be poked via the NDD interface. 1080 * 1081 * We always reinitalise the SerDes; this should cause the link to go down, 1082 * and then back up again once the link is stable and autonegotiation 1083 * (if enabled) is complete. We should get a link state change interrupt 1084 * somewhere along the way ... 1085 * 1086 * NOTE: SerDes only supports 1000FDX/HDX (with or without pause) so the 1087 * param_* variables relating to lower speeds are ignored. 1088 * 1089 * NOTE: <genlock> must already be held by the caller 1090 */ 1091 static int 1092 bge_update_serdes(bge_t *bgep) 1093 { 1094 boolean_t adv_autoneg; 1095 boolean_t adv_pause; 1096 boolean_t adv_asym_pause; 1097 boolean_t adv_1000fdx; 1098 boolean_t adv_1000hdx; 1099 1100 uint32_t serdes; 1101 uint32_t advert; 1102 1103 BGE_TRACE(("bge_update_serdes($%p)", (void *)bgep)); 1104 1105 ASSERT(mutex_owned(bgep->genlock)); 1106 1107 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1108 "pause %d asym_pause %d " 1109 "1000fdx %d 1000hdx %d " 1110 "100fdx %d 100hdx %d " 1111 "10fdx %d 10hdx %d ", 1112 bgep->param_adv_autoneg, 1113 bgep->param_adv_pause, bgep->param_adv_asym_pause, 1114 bgep->param_adv_1000fdx, bgep->param_adv_1000hdx, 1115 bgep->param_adv_100fdx, bgep->param_adv_100hdx, 1116 bgep->param_adv_10fdx, bgep->param_adv_10hdx)); 1117 1118 serdes = advert = 0; 1119 1120 /* 1121 * SerDes settings are normally based on the param_* variables, 1122 * but if any loopback mode is in effect, that takes precedence. 1123 * 1124 * BGE supports MAC-internal loopback, PHY-internal loopback, 1125 * and External loopback at a variety of speeds (with a special 1126 * cable). In all cases, autoneg is turned OFF, full-duplex 1127 * is turned ON, and the speed/mastership is forced. 1128 * 1129 * Note: for the SerDes interface, "PHY" internal loopback is 1130 * interpreted as SerDes internal loopback, and all external 1131 * loopback modes are treated equivalently, as 1Gb/external. 1132 */ 1133 switch (bgep->param_loop_mode) { 1134 case BGE_LOOP_NONE: 1135 default: 1136 adv_autoneg = bgep->param_adv_autoneg; 1137 adv_pause = bgep->param_adv_pause; 1138 adv_asym_pause = bgep->param_adv_asym_pause; 1139 adv_1000fdx = bgep->param_adv_1000fdx; 1140 adv_1000hdx = bgep->param_adv_1000hdx; 1141 break; 1142 1143 case BGE_LOOP_INTERNAL_PHY: 1144 serdes |= SERDES_CONTROL_TBI_LOOPBACK; 1145 /* FALLTHRU */ 1146 case BGE_LOOP_INTERNAL_MAC: 1147 case BGE_LOOP_EXTERNAL_1000: 1148 case BGE_LOOP_EXTERNAL_100: 1149 case BGE_LOOP_EXTERNAL_10: 1150 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 1151 adv_1000fdx = B_TRUE; 1152 adv_1000hdx = B_FALSE; 1153 break; 1154 } 1155 1156 BGE_DEBUG(("bge_update_serdes: autoneg %d " 1157 "pause %d asym_pause %d " 1158 "1000fdx %d 1000hdx %d ", 1159 adv_autoneg, 1160 adv_pause, adv_asym_pause, 1161 adv_1000fdx, adv_1000hdx)); 1162 1163 /* 1164 * We should have at least one gigabit technology capability 1165 * set; if not, we select a default of 1000Mb/s full-duplex 1166 */ 1167 if (!adv_1000fdx && !adv_1000hdx) 1168 adv_1000fdx = B_TRUE; 1169 1170 /* 1171 * Now transform the adv_* variables into the proper settings 1172 * of the SerDes registers ... 1173 * 1174 * If autonegotiation is (now) not enabled, pretend it's been 1175 * done and failed ... 1176 */ 1177 if (!adv_autoneg) 1178 advert |= AUTONEG_CODE_FAULT_ANEG_ERR; 1179 1180 if (adv_1000fdx) { 1181 advert |= AUTONEG_CODE_FULL_DUPLEX; 1182 bgep->param_adv_1000fdx = adv_1000fdx; 1183 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1184 bgep->param_link_speed = 1000; 1185 } 1186 if (adv_1000hdx) { 1187 advert |= AUTONEG_CODE_HALF_DUPLEX; 1188 bgep->param_adv_1000hdx = adv_1000hdx; 1189 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1190 bgep->param_link_speed = 1000; 1191 } 1192 1193 if (adv_pause) 1194 advert |= AUTONEG_CODE_PAUSE; 1195 if (adv_asym_pause) 1196 advert |= AUTONEG_CODE_ASYM_PAUSE; 1197 1198 /* 1199 * Restart the SerDes and write the new values. Note the 1200 * time, so that we can say whether subsequent link state 1201 * changes can be attributed to our reprogramming the SerDes 1202 */ 1203 bgep->serdes_advert = advert; 1204 (void) bge_restart_serdes(bgep, B_FALSE); 1205 bge_reg_set32(bgep, SERDES_CONTROL_REG, serdes); 1206 1207 BGE_DEBUG(("bge_update_serdes: serdes |= 0x%x, advert 0x%x", 1208 serdes, advert)); 1209 return (DDI_SUCCESS); 1210 } 1211 1212 /* 1213 * Bare-minimum autoneg protocol 1214 * 1215 * This code is only called when the link is up and we're receiving config 1216 * words, which implies that the link partner wants to autonegotiate 1217 * (otherwise, we wouldn't see configs and wouldn't reach this code). 1218 */ 1219 static void 1220 bge_autoneg_serdes(bge_t *bgep) 1221 { 1222 boolean_t ack; 1223 1224 bgep->serdes_lpadv = bge_reg_get32(bgep, RX_1000BASEX_AUTONEG_REG); 1225 ack = BIS(bgep->serdes_lpadv, AUTONEG_CODE_ACKNOWLEDGE); 1226 1227 if (!ack) { 1228 /* 1229 * Phase 1: after SerDes reset, we send a few zero configs 1230 * but then stop. Here the partner is sending configs, but 1231 * not ACKing ours; we assume that's 'cos we're not sending 1232 * any. So here we send ours, with ACK already set. 1233 */ 1234 bge_reg_put32(bgep, TX_1000BASEX_AUTONEG_REG, 1235 bgep->serdes_advert | AUTONEG_CODE_ACKNOWLEDGE); 1236 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 1237 ETHERNET_MODE_SEND_CFGS); 1238 } else { 1239 /* 1240 * Phase 2: partner has ACKed our configs, so now we can 1241 * stop sending; once our partner also stops sending, we 1242 * can resolve the Tx/Rx configs. 1243 */ 1244 bge_reg_clr32(bgep, ETHERNET_MAC_MODE_REG, 1245 ETHERNET_MODE_SEND_CFGS); 1246 } 1247 1248 BGE_DEBUG(("bge_autoneg_serdes: Rx 0x%x %s Tx 0x%x", 1249 bgep->serdes_lpadv, 1250 ack ? "stop" : "send", 1251 bgep->serdes_advert)); 1252 } 1253 1254 static boolean_t 1255 bge_check_serdes(bge_t *bgep, boolean_t recheck) 1256 { 1257 uint32_t emac_status; 1258 uint32_t lpadv; 1259 boolean_t linkup; 1260 boolean_t linkup_old = bgep->param_link_up; 1261 1262 for (;;) { 1263 /* 1264 * Step 10: BCM5714S, BCM5715S only 1265 * Don't call function bge_autoneg_serdes() as 1266 * RX_1000BASEX_AUTONEG_REG (0x0448) is not applicable 1267 * to BCM5705, BCM5788, BCM5721, BCM5751, BCM5752, 1268 * BCM5714, and BCM5715 devices. 1269 */ 1270 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1271 emac_status = bge_reg_get32(bgep, MI_STATUS_REG); 1272 linkup = BIS(emac_status, MI_STATUS_LINK); 1273 bgep->serdes_status = emac_status; 1274 if ((linkup && linkup_old) || 1275 (!linkup && !linkup_old)) { 1276 emac_status &= ~ETHERNET_STATUS_LINK_CHANGED; 1277 emac_status &= ~ETHERNET_STATUS_RECEIVING_CFG; 1278 break; 1279 } 1280 emac_status |= ETHERNET_STATUS_LINK_CHANGED; 1281 emac_status |= ETHERNET_STATUS_RECEIVING_CFG; 1282 if (linkup) 1283 linkup_old = B_TRUE; 1284 else 1285 linkup_old = B_FALSE; 1286 recheck = B_TRUE; 1287 } else { 1288 /* 1289 * Step 10: others 1290 * read & clear the main (Ethernet) MAC status 1291 * (the relevant bits of this are write-one-to-clear). 1292 */ 1293 emac_status = bge_reg_get32(bgep, 1294 ETHERNET_MAC_STATUS_REG); 1295 bge_reg_put32(bgep, 1296 ETHERNET_MAC_STATUS_REG, emac_status); 1297 1298 BGE_DEBUG(("bge_check_serdes: link %d/%s, " 1299 "MAC status 0x%x (was 0x%x)", 1300 bgep->link_state, UPORDOWN(bgep->param_link_up), 1301 emac_status, bgep->serdes_status)); 1302 1303 /* 1304 * We will only consider the link UP if all the readings 1305 * are consistent and give meaningful results ... 1306 */ 1307 bgep->serdes_status = emac_status; 1308 linkup = BIS(emac_status, 1309 ETHERNET_STATUS_SIGNAL_DETECT); 1310 linkup &= BIS(emac_status, ETHERNET_STATUS_PCS_SYNCHED); 1311 1312 /* 1313 * Now some fiddling with the interpretation: 1314 * if there's been an error at the PCS level, treat 1315 * it as a link change (the h/w doesn't do this) 1316 * 1317 * if there's been a change, but it's only a PCS 1318 * sync change (not a config change), AND the link 1319 * already was & is still UP, then ignore the 1320 * change 1321 */ 1322 if (BIS(emac_status, ETHERNET_STATUS_PCS_ERROR)) 1323 emac_status |= ETHERNET_STATUS_LINK_CHANGED; 1324 else if (BIC(emac_status, ETHERNET_STATUS_CFG_CHANGED)) 1325 if (bgep->param_link_up && linkup) 1326 emac_status &= 1327 ~ETHERNET_STATUS_LINK_CHANGED; 1328 1329 BGE_DEBUG(("bge_check_serdes: status 0x%x => 0x%x %s", 1330 bgep->serdes_status, emac_status, 1331 UPORDOWN(linkup))); 1332 1333 /* 1334 * If we're receiving configs, run the autoneg protocol 1335 */ 1336 if (linkup && BIS(emac_status, 1337 ETHERNET_STATUS_RECEIVING_CFG)) 1338 bge_autoneg_serdes(bgep); 1339 1340 /* 1341 * If the SerDes status hasn't changed, we're done ... 1342 */ 1343 if (BIC(emac_status, ETHERNET_STATUS_LINK_CHANGED)) 1344 break; 1345 1346 /* 1347 * Go round again until we no longer see a change ... 1348 */ 1349 recheck = B_TRUE; 1350 } 1351 } 1352 1353 /* 1354 * If we're not forcing a recheck (i.e. the link state was already 1355 * known), and we didn't see the hardware flag a change, there's 1356 * no more to do (and we tell the caller nothing happened). 1357 */ 1358 if (!recheck) 1359 return (B_FALSE); 1360 1361 /* 1362 * Don't resolve autoneg until we're no longer receiving configs 1363 */ 1364 if (linkup && BIS(emac_status, ETHERNET_STATUS_RECEIVING_CFG)) 1365 return (B_FALSE); 1366 1367 /* 1368 * Assume very little ... 1369 */ 1370 bgep->param_lp_autoneg = B_FALSE; 1371 bgep->param_lp_1000fdx = B_FALSE; 1372 bgep->param_lp_1000hdx = B_FALSE; 1373 bgep->param_lp_100fdx = B_FALSE; 1374 bgep->param_lp_100hdx = B_FALSE; 1375 bgep->param_lp_10fdx = B_FALSE; 1376 bgep->param_lp_10hdx = B_FALSE; 1377 bgep->param_lp_pause = B_FALSE; 1378 bgep->param_lp_asym_pause = B_FALSE; 1379 bgep->param_link_autoneg = B_FALSE; 1380 bgep->param_link_tx_pause = B_FALSE; 1381 if (bgep->param_adv_autoneg) 1382 bgep->param_link_rx_pause = B_FALSE; 1383 else 1384 bgep->param_link_rx_pause = bgep->param_adv_pause; 1385 1386 /* 1387 * Discover all the link partner's abilities. 1388 */ 1389 lpadv = bgep->serdes_lpadv; 1390 if (lpadv != 0 && BIC(lpadv, AUTONEG_CODE_FAULT_MASK)) { 1391 /* 1392 * No fault, so derive partner's capabilities 1393 */ 1394 bgep->param_lp_autoneg = B_TRUE; 1395 bgep->param_lp_1000fdx = BIS(lpadv, AUTONEG_CODE_FULL_DUPLEX); 1396 bgep->param_lp_1000hdx = BIS(lpadv, AUTONEG_CODE_HALF_DUPLEX); 1397 bgep->param_lp_pause = BIS(lpadv, AUTONEG_CODE_PAUSE); 1398 bgep->param_lp_asym_pause = BIS(lpadv, AUTONEG_CODE_ASYM_PAUSE); 1399 1400 /* 1401 * Pause direction resolution 1402 */ 1403 bgep->param_link_autoneg = B_TRUE; 1404 if (bgep->param_adv_pause && 1405 bgep->param_lp_pause) { 1406 bgep->param_link_tx_pause = B_TRUE; 1407 bgep->param_link_rx_pause = B_TRUE; 1408 } 1409 if (bgep->param_adv_asym_pause && 1410 bgep->param_lp_asym_pause) { 1411 if (bgep->param_adv_pause) 1412 bgep->param_link_rx_pause = B_TRUE; 1413 if (bgep->param_lp_pause) 1414 bgep->param_link_tx_pause = B_TRUE; 1415 } 1416 } 1417 1418 /* 1419 * Step 12: update ndd-visible state parameters, BUT! 1420 * we don't transfer the new state to <link_state> just yet; 1421 * instead we mark the <link_state> as UNKNOWN, and our caller 1422 * will resolve it once the status has stopped changing and 1423 * been stable for several seconds. 1424 */ 1425 BGE_DEBUG(("bge_check_serdes: link was %s speed %d duplex %d", 1426 UPORDOWN(bgep->param_link_up), 1427 bgep->param_link_speed, 1428 bgep->param_link_duplex)); 1429 1430 if (linkup) { 1431 bgep->param_link_up = B_TRUE; 1432 bgep->param_link_speed = 1000; 1433 if (bgep->param_adv_1000fdx) 1434 bgep->param_link_duplex = LINK_DUPLEX_FULL; 1435 else 1436 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1437 if (bgep->param_lp_autoneg && !bgep->param_lp_1000fdx) 1438 bgep->param_link_duplex = LINK_DUPLEX_HALF; 1439 } else { 1440 bgep->param_link_up = B_FALSE; 1441 bgep->param_link_speed = 0; 1442 bgep->param_link_duplex = LINK_DUPLEX_UNKNOWN; 1443 } 1444 bgep->link_state = LINK_STATE_UNKNOWN; 1445 1446 BGE_DEBUG(("bge_check_serdes: link now %s speed %d duplex %d", 1447 UPORDOWN(bgep->param_link_up), 1448 bgep->param_link_speed, 1449 bgep->param_link_duplex)); 1450 1451 return (B_TRUE); 1452 } 1453 1454 static const phys_ops_t serdes_ops = { 1455 bge_restart_serdes, 1456 bge_update_serdes, 1457 bge_check_serdes 1458 }; 1459 1460 /* 1461 * ========== Exported physical layer control routines ========== 1462 */ 1463 1464 #undef BGE_DBG 1465 #define BGE_DBG BGE_DBG_PHYS /* debug flag for this code */ 1466 1467 /* 1468 * Here we have to determine which media we're using (copper or serdes). 1469 * Once that's done, we can initialise the physical layer appropriately. 1470 */ 1471 int 1472 bge_phys_init(bge_t *bgep) 1473 { 1474 BGE_TRACE(("bge_phys_init($%p)", (void *)bgep)); 1475 1476 mutex_enter(bgep->genlock); 1477 1478 /* 1479 * Probe for the (internal) PHY. If it's not there, we'll assume 1480 * that this is a 5703/4S, with a SerDes interface rather than 1481 * a PHY. BCM5714S/BCM5715S are not supported.It are based on 1482 * BCM800x PHY. 1483 */ 1484 bgep->phy_mii_addr = 1; 1485 if (bge_phy_probe(bgep)) { 1486 bgep->chipid.flags &= ~CHIP_FLAG_SERDES; 1487 bgep->physops = &copper_ops; 1488 } else { 1489 bgep->chipid.flags |= CHIP_FLAG_SERDES; 1490 bgep->physops = &serdes_ops; 1491 } 1492 1493 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) { 1494 mutex_exit(bgep->genlock); 1495 return (EIO); 1496 } 1497 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 1498 mutex_exit(bgep->genlock); 1499 return (EIO); 1500 } 1501 mutex_exit(bgep->genlock); 1502 return (0); 1503 } 1504 1505 /* 1506 * Reset the physical layer 1507 */ 1508 void 1509 bge_phys_reset(bge_t *bgep) 1510 { 1511 BGE_TRACE(("bge_phys_reset($%p)", (void *)bgep)); 1512 1513 mutex_enter(bgep->genlock); 1514 if ((*bgep->physops->phys_restart)(bgep, B_FALSE) != DDI_SUCCESS) 1515 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1516 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 1517 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 1518 mutex_exit(bgep->genlock); 1519 } 1520 1521 /* 1522 * Reset and power off the physical layer. 1523 * 1524 * Another RESET should get it back to working, but it may take a few 1525 * seconds it may take a few moments to return to normal operation ... 1526 */ 1527 int 1528 bge_phys_idle(bge_t *bgep) 1529 { 1530 BGE_TRACE(("bge_phys_idle($%p)", (void *)bgep)); 1531 1532 ASSERT(mutex_owned(bgep->genlock)); 1533 return ((*bgep->physops->phys_restart)(bgep, B_TRUE)); 1534 } 1535 1536 /* 1537 * Synchronise the PHYSICAL layer's speed/duplex/autonegotiation capabilities 1538 * and advertisements with the required settings as specified by the various 1539 * param_* variables that can be poked via the NDD interface. 1540 * 1541 * We always reset the PHYSICAL layer and reprogram *all* relevant registers. 1542 * This is expected to cause the link to go down, and then back up again once 1543 * the link is stable and autonegotiation (if enabled) is complete. We should 1544 * get a link state change interrupt somewhere along the way ... 1545 * 1546 * NOTE: <genlock> must already be held by the caller 1547 */ 1548 int 1549 bge_phys_update(bge_t *bgep) 1550 { 1551 BGE_TRACE(("bge_phys_update($%p)", (void *)bgep)); 1552 1553 ASSERT(mutex_owned(bgep->genlock)); 1554 return ((*bgep->physops->phys_update)(bgep)); 1555 } 1556 1557 #undef BGE_DBG 1558 #define BGE_DBG BGE_DBG_LINK /* debug flag for this code */ 1559 1560 /* 1561 * Read the link status and determine whether anything's changed ... 1562 * 1563 * This routine should be called whenever the chip flags a change 1564 * in the hardware link state. 1565 * 1566 * This routine returns B_FALSE if the link state has not changed, 1567 * returns B_TRUE when the change to the new state should be accepted. 1568 * In such a case, the param_* variables give the new hardware state, 1569 * which the caller should use to update link_state etc. 1570 * 1571 * The caller must already hold <genlock> 1572 */ 1573 boolean_t 1574 bge_phys_check(bge_t *bgep) 1575 { 1576 int32_t orig_state; 1577 boolean_t recheck; 1578 1579 BGE_TRACE(("bge_phys_check($%p)", (void *)bgep)); 1580 1581 ASSERT(mutex_owned(bgep->genlock)); 1582 1583 orig_state = bgep->link_state; 1584 recheck = orig_state == LINK_STATE_UNKNOWN; 1585 recheck = (*bgep->physops->phys_check)(bgep, recheck); 1586 if (!recheck) 1587 return (B_FALSE); 1588 1589 return (B_TRUE); 1590 } 1591