1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 #include <sys/sdt.h> 31 32 /* 33 * This is the string displayed by modinfo, etc. 34 * Make sure you keep the version ID up to date! 35 */ 36 static char bge_ident[] = "Broadcom Gb Ethernet v0.53"; 37 38 /* 39 * Property names 40 */ 41 static char debug_propname[] = "bge-debug-flags"; 42 static char clsize_propname[] = "cache-line-size"; 43 static char latency_propname[] = "latency-timer"; 44 static char localmac_boolname[] = "local-mac-address?"; 45 static char localmac_propname[] = "local-mac-address"; 46 static char macaddr_propname[] = "mac-address"; 47 static char subdev_propname[] = "subsystem-id"; 48 static char subven_propname[] = "subsystem-vendor-id"; 49 static char rxrings_propname[] = "bge-rx-rings"; 50 static char txrings_propname[] = "bge-tx-rings"; 51 static char fm_cap[] = "fm-capable"; 52 static char default_mtu[] = "default_mtu"; 53 54 static int bge_add_intrs(bge_t *, int); 55 static void bge_rem_intrs(bge_t *); 56 57 /* 58 * Describes the chip's DMA engine 59 */ 60 static ddi_dma_attr_t dma_attr = { 61 DMA_ATTR_V0, /* dma_attr version */ 62 0x0000000000000000ull, /* dma_attr_addr_lo */ 63 0xFFFFFFFFFFFFFFFFull, /* dma_attr_addr_hi */ 64 0x00000000FFFFFFFFull, /* dma_attr_count_max */ 65 0x0000000000000001ull, /* dma_attr_align */ 66 0x00000FFF, /* dma_attr_burstsizes */ 67 0x00000001, /* dma_attr_minxfer */ 68 0x000000000000FFFFull, /* dma_attr_maxxfer */ 69 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */ 70 1, /* dma_attr_sgllen */ 71 0x00000001, /* dma_attr_granular */ 72 DDI_DMA_FLAGERR /* dma_attr_flags */ 73 }; 74 75 /* 76 * PIO access attributes for registers 77 */ 78 static ddi_device_acc_attr_t bge_reg_accattr = { 79 DDI_DEVICE_ATTR_V0, 80 DDI_NEVERSWAP_ACC, 81 DDI_STRICTORDER_ACC, 82 DDI_FLAGERR_ACC 83 }; 84 85 /* 86 * DMA access attributes for descriptors: NOT to be byte swapped. 87 */ 88 static ddi_device_acc_attr_t bge_desc_accattr = { 89 DDI_DEVICE_ATTR_V0, 90 DDI_NEVERSWAP_ACC, 91 DDI_STRICTORDER_ACC, 92 DDI_FLAGERR_ACC 93 }; 94 95 /* 96 * DMA access attributes for data: NOT to be byte swapped. 97 */ 98 static ddi_device_acc_attr_t bge_data_accattr = { 99 DDI_DEVICE_ATTR_V0, 100 DDI_NEVERSWAP_ACC, 101 DDI_STRICTORDER_ACC 102 }; 103 104 /* 105 * Versions of the O/S up to Solaris 8 didn't support network booting 106 * from any network interface except the first (NET0). Patching this 107 * flag to a non-zero value will tell the driver to work around this 108 * limitation by creating an extra (internal) pathname node. To do 109 * this, just add a line like the following to the CLIENT'S etc/system 110 * file ON THE ROOT FILESYSTEM SERVER before booting the client: 111 * 112 * set bge:bge_net1_boot_support = 1; 113 */ 114 static uint32_t bge_net1_boot_support = 1; 115 116 static int bge_m_start(void *); 117 static void bge_m_stop(void *); 118 static int bge_m_promisc(void *, boolean_t); 119 static int bge_m_multicst(void *, boolean_t, const uint8_t *); 120 static int bge_m_unicst(void *, const uint8_t *); 121 static void bge_m_resources(void *); 122 static void bge_m_ioctl(void *, queue_t *, mblk_t *); 123 static boolean_t bge_m_getcapab(void *, mac_capab_t, void *); 124 static int bge_unicst_set(void *, const uint8_t *, 125 mac_addr_slot_t); 126 static int bge_m_unicst_add(void *, mac_multi_addr_t *); 127 static int bge_m_unicst_remove(void *, mac_addr_slot_t); 128 static int bge_m_unicst_modify(void *, mac_multi_addr_t *); 129 static int bge_m_unicst_get(void *, mac_multi_addr_t *); 130 131 #define BGE_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 132 133 static mac_callbacks_t bge_m_callbacks = { 134 BGE_M_CALLBACK_FLAGS, 135 bge_m_stat, 136 bge_m_start, 137 bge_m_stop, 138 bge_m_promisc, 139 bge_m_multicst, 140 bge_m_unicst, 141 bge_m_tx, 142 bge_m_resources, 143 bge_m_ioctl, 144 bge_m_getcapab 145 }; 146 147 /* 148 * ========== Transmit and receive ring reinitialisation ========== 149 */ 150 151 /* 152 * These <reinit> routines each reset the specified ring to an initial 153 * state, assuming that the corresponding <init> routine has already 154 * been called exactly once. 155 */ 156 157 static void 158 bge_reinit_send_ring(send_ring_t *srp) 159 { 160 bge_queue_t *txbuf_queue; 161 bge_queue_item_t *txbuf_head; 162 sw_txbuf_t *txbuf; 163 sw_sbd_t *ssbdp; 164 uint32_t slot; 165 166 /* 167 * Reinitialise control variables ... 168 */ 169 srp->tx_flow = 0; 170 srp->tx_next = 0; 171 srp->txfill_next = 0; 172 srp->tx_free = srp->desc.nslots; 173 ASSERT(mutex_owned(srp->tc_lock)); 174 srp->tc_next = 0; 175 srp->txpkt_next = 0; 176 srp->tx_block = 0; 177 srp->tx_nobd = 0; 178 srp->tx_nobuf = 0; 179 180 /* 181 * Initialize the tx buffer push queue 182 */ 183 mutex_enter(srp->freetxbuf_lock); 184 mutex_enter(srp->txbuf_lock); 185 txbuf_queue = &srp->freetxbuf_queue; 186 txbuf_queue->head = NULL; 187 txbuf_queue->count = 0; 188 txbuf_queue->lock = srp->freetxbuf_lock; 189 srp->txbuf_push_queue = txbuf_queue; 190 191 /* 192 * Initialize the tx buffer pop queue 193 */ 194 txbuf_queue = &srp->txbuf_queue; 195 txbuf_queue->head = NULL; 196 txbuf_queue->count = 0; 197 txbuf_queue->lock = srp->txbuf_lock; 198 srp->txbuf_pop_queue = txbuf_queue; 199 txbuf_head = srp->txbuf_head; 200 txbuf = srp->txbuf; 201 for (slot = 0; slot < srp->tx_buffers; ++slot) { 202 txbuf_head->item = txbuf; 203 txbuf_head->next = txbuf_queue->head; 204 txbuf_queue->head = txbuf_head; 205 txbuf_queue->count++; 206 txbuf++; 207 txbuf_head++; 208 } 209 mutex_exit(srp->txbuf_lock); 210 mutex_exit(srp->freetxbuf_lock); 211 212 /* 213 * Zero and sync all the h/w Send Buffer Descriptors 214 */ 215 DMA_ZERO(srp->desc); 216 DMA_SYNC(srp->desc, DDI_DMA_SYNC_FORDEV); 217 bzero(srp->pktp, BGE_SEND_BUF_MAX * sizeof (*srp->pktp)); 218 ssbdp = srp->sw_sbds; 219 for (slot = 0; slot < srp->desc.nslots; ++ssbdp, ++slot) 220 ssbdp->pbuf = NULL; 221 } 222 223 static void 224 bge_reinit_recv_ring(recv_ring_t *rrp) 225 { 226 /* 227 * Reinitialise control variables ... 228 */ 229 rrp->rx_next = 0; 230 } 231 232 static void 233 bge_reinit_buff_ring(buff_ring_t *brp, uint32_t ring) 234 { 235 bge_rbd_t *hw_rbd_p; 236 sw_rbd_t *srbdp; 237 uint32_t bufsize; 238 uint32_t nslots; 239 uint32_t slot; 240 241 static uint16_t ring_type_flag[BGE_BUFF_RINGS_MAX] = { 242 RBD_FLAG_STD_RING, 243 RBD_FLAG_JUMBO_RING, 244 RBD_FLAG_MINI_RING 245 }; 246 247 /* 248 * Zero, initialise and sync all the h/w Receive Buffer Descriptors 249 * Note: all the remaining fields (<type>, <flags>, <ip_cksum>, 250 * <tcp_udp_cksum>, <error_flag>, <vlan_tag>, and <reserved>) 251 * should be zeroed, and so don't need to be set up specifically 252 * once the whole area has been cleared. 253 */ 254 DMA_ZERO(brp->desc); 255 256 hw_rbd_p = DMA_VPTR(brp->desc); 257 nslots = brp->desc.nslots; 258 ASSERT(brp->buf[0].nslots == nslots/BGE_SPLIT); 259 bufsize = brp->buf[0].size; 260 srbdp = brp->sw_rbds; 261 for (slot = 0; slot < nslots; ++hw_rbd_p, ++srbdp, ++slot) { 262 hw_rbd_p->host_buf_addr = srbdp->pbuf.cookie.dmac_laddress; 263 hw_rbd_p->index = slot; 264 hw_rbd_p->len = bufsize; 265 hw_rbd_p->opaque = srbdp->pbuf.token; 266 hw_rbd_p->flags |= ring_type_flag[ring]; 267 } 268 269 DMA_SYNC(brp->desc, DDI_DMA_SYNC_FORDEV); 270 271 /* 272 * Finally, reinitialise the ring control variables ... 273 */ 274 brp->rf_next = (nslots != 0) ? (nslots-1) : 0; 275 } 276 277 /* 278 * Reinitialize all rings 279 */ 280 static void 281 bge_reinit_rings(bge_t *bgep) 282 { 283 uint32_t ring; 284 285 ASSERT(mutex_owned(bgep->genlock)); 286 287 /* 288 * Send Rings ... 289 */ 290 for (ring = 0; ring < bgep->chipid.tx_rings; ++ring) 291 bge_reinit_send_ring(&bgep->send[ring]); 292 293 /* 294 * Receive Return Rings ... 295 */ 296 for (ring = 0; ring < bgep->chipid.rx_rings; ++ring) 297 bge_reinit_recv_ring(&bgep->recv[ring]); 298 299 /* 300 * Receive Producer Rings ... 301 */ 302 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 303 bge_reinit_buff_ring(&bgep->buff[ring], ring); 304 } 305 306 /* 307 * ========== Internal state management entry points ========== 308 */ 309 310 #undef BGE_DBG 311 #define BGE_DBG BGE_DBG_NEMO /* debug flag for this code */ 312 313 /* 314 * These routines provide all the functionality required by the 315 * corresponding GLD entry points, but don't update the GLD state 316 * so they can be called internally without disturbing our record 317 * of what GLD thinks we should be doing ... 318 */ 319 320 /* 321 * bge_reset() -- reset h/w & rings to initial state 322 */ 323 static int 324 #ifdef BGE_IPMI_ASF 325 bge_reset(bge_t *bgep, uint_t asf_mode) 326 #else 327 bge_reset(bge_t *bgep) 328 #endif 329 { 330 uint32_t ring; 331 int retval; 332 333 BGE_TRACE(("bge_reset($%p)", (void *)bgep)); 334 335 ASSERT(mutex_owned(bgep->genlock)); 336 337 /* 338 * Grab all the other mutexes in the world (this should 339 * ensure no other threads are manipulating driver state) 340 */ 341 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring) 342 mutex_enter(bgep->recv[ring].rx_lock); 343 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring) 344 mutex_enter(bgep->buff[ring].rf_lock); 345 rw_enter(bgep->errlock, RW_WRITER); 346 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 347 mutex_enter(bgep->send[ring].tx_lock); 348 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 349 mutex_enter(bgep->send[ring].tc_lock); 350 351 #ifdef BGE_IPMI_ASF 352 retval = bge_chip_reset(bgep, B_TRUE, asf_mode); 353 #else 354 retval = bge_chip_reset(bgep, B_TRUE); 355 #endif 356 bge_reinit_rings(bgep); 357 358 /* 359 * Free the world ... 360 */ 361 for (ring = BGE_SEND_RINGS_MAX; ring-- > 0; ) 362 mutex_exit(bgep->send[ring].tc_lock); 363 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 364 mutex_exit(bgep->send[ring].tx_lock); 365 rw_exit(bgep->errlock); 366 for (ring = BGE_BUFF_RINGS_MAX; ring-- > 0; ) 367 mutex_exit(bgep->buff[ring].rf_lock); 368 for (ring = BGE_RECV_RINGS_MAX; ring-- > 0; ) 369 mutex_exit(bgep->recv[ring].rx_lock); 370 371 BGE_DEBUG(("bge_reset($%p) done", (void *)bgep)); 372 return (retval); 373 } 374 375 /* 376 * bge_stop() -- stop processing, don't reset h/w or rings 377 */ 378 static void 379 bge_stop(bge_t *bgep) 380 { 381 BGE_TRACE(("bge_stop($%p)", (void *)bgep)); 382 383 ASSERT(mutex_owned(bgep->genlock)); 384 385 #ifdef BGE_IPMI_ASF 386 if (bgep->asf_enabled) { 387 bgep->asf_pseudostop = B_TRUE; 388 } else { 389 #endif 390 bge_chip_stop(bgep, B_FALSE); 391 #ifdef BGE_IPMI_ASF 392 } 393 #endif 394 395 BGE_DEBUG(("bge_stop($%p) done", (void *)bgep)); 396 } 397 398 /* 399 * bge_start() -- start transmitting/receiving 400 */ 401 static int 402 bge_start(bge_t *bgep, boolean_t reset_phys) 403 { 404 int retval; 405 406 BGE_TRACE(("bge_start($%p, %d)", (void *)bgep, reset_phys)); 407 408 ASSERT(mutex_owned(bgep->genlock)); 409 410 /* 411 * Start chip processing, including enabling interrupts 412 */ 413 retval = bge_chip_start(bgep, reset_phys); 414 415 BGE_DEBUG(("bge_start($%p, %d) done", (void *)bgep, reset_phys)); 416 return (retval); 417 } 418 419 /* 420 * bge_restart - restart transmitting/receiving after error or suspend 421 */ 422 int 423 bge_restart(bge_t *bgep, boolean_t reset_phys) 424 { 425 int retval = DDI_SUCCESS; 426 ASSERT(mutex_owned(bgep->genlock)); 427 428 #ifdef BGE_IPMI_ASF 429 if (bgep->asf_enabled) { 430 if (bge_reset(bgep, ASF_MODE_POST_INIT) != DDI_SUCCESS) 431 retval = DDI_FAILURE; 432 } else 433 if (bge_reset(bgep, ASF_MODE_NONE) != DDI_SUCCESS) 434 retval = DDI_FAILURE; 435 #else 436 if (bge_reset(bgep) != DDI_SUCCESS) 437 retval = DDI_FAILURE; 438 #endif 439 if (bgep->bge_mac_state == BGE_MAC_STARTED && 440 retval == DDI_SUCCESS) { 441 if (bge_start(bgep, reset_phys) != DDI_SUCCESS) 442 retval = DDI_FAILURE; 443 bgep->watchdog = 0; 444 ddi_trigger_softintr(bgep->drain_id); 445 } 446 447 BGE_DEBUG(("bge_restart($%p, %d) done", (void *)bgep, reset_phys)); 448 return (retval); 449 } 450 451 452 /* 453 * ========== Nemo-required management entry points ========== 454 */ 455 456 #undef BGE_DBG 457 #define BGE_DBG BGE_DBG_NEMO /* debug flag for this code */ 458 459 /* 460 * bge_m_stop() -- stop transmitting/receiving 461 */ 462 static void 463 bge_m_stop(void *arg) 464 { 465 bge_t *bgep = arg; /* private device info */ 466 send_ring_t *srp; 467 uint32_t ring; 468 469 BGE_TRACE(("bge_m_stop($%p)", arg)); 470 471 /* 472 * Just stop processing, then record new GLD state 473 */ 474 mutex_enter(bgep->genlock); 475 if (!(bgep->progress & PROGRESS_INTR)) { 476 /* can happen during autorecovery */ 477 mutex_exit(bgep->genlock); 478 return; 479 } 480 bgep->link_up_msg = bgep->link_down_msg = " (stopped)"; 481 bge_stop(bgep); 482 /* 483 * Free the possible tx buffers allocated in tx process. 484 */ 485 #ifdef BGE_IPMI_ASF 486 if (!bgep->asf_pseudostop) 487 #endif 488 { 489 rw_enter(bgep->errlock, RW_WRITER); 490 for (ring = 0; ring < bgep->chipid.tx_rings; ++ring) { 491 srp = &bgep->send[ring]; 492 mutex_enter(srp->tx_lock); 493 if (srp->tx_array > 1) 494 bge_free_txbuf_arrays(srp); 495 mutex_exit(srp->tx_lock); 496 } 497 rw_exit(bgep->errlock); 498 } 499 bgep->bge_mac_state = BGE_MAC_STOPPED; 500 BGE_DEBUG(("bge_m_stop($%p) done", arg)); 501 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 502 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 503 mutex_exit(bgep->genlock); 504 } 505 506 /* 507 * bge_m_start() -- start transmitting/receiving 508 */ 509 static int 510 bge_m_start(void *arg) 511 { 512 bge_t *bgep = arg; /* private device info */ 513 514 BGE_TRACE(("bge_m_start($%p)", arg)); 515 516 /* 517 * Start processing and record new GLD state 518 */ 519 mutex_enter(bgep->genlock); 520 if (!(bgep->progress & PROGRESS_INTR)) { 521 /* can happen during autorecovery */ 522 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 523 mutex_exit(bgep->genlock); 524 return (EIO); 525 } 526 #ifdef BGE_IPMI_ASF 527 if (bgep->asf_enabled) { 528 if ((bgep->asf_status == ASF_STAT_RUN) && 529 (bgep->asf_pseudostop)) { 530 531 bgep->link_up_msg = bgep->link_down_msg 532 = " (initialized)"; 533 bgep->bge_mac_state = BGE_MAC_STARTED; 534 mutex_exit(bgep->genlock); 535 return (0); 536 } 537 } 538 if (bge_reset(bgep, ASF_MODE_INIT) != DDI_SUCCESS) { 539 #else 540 if (bge_reset(bgep) != DDI_SUCCESS) { 541 #endif 542 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 543 (void) bge_check_acc_handle(bgep, bgep->io_handle); 544 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 545 mutex_exit(bgep->genlock); 546 return (EIO); 547 } 548 bgep->link_up_msg = bgep->link_down_msg = " (initialized)"; 549 if (bge_start(bgep, B_TRUE) != DDI_SUCCESS) { 550 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 551 (void) bge_check_acc_handle(bgep, bgep->io_handle); 552 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 553 mutex_exit(bgep->genlock); 554 return (EIO); 555 } 556 bgep->bge_mac_state = BGE_MAC_STARTED; 557 BGE_DEBUG(("bge_m_start($%p) done", arg)); 558 559 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 560 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 561 mutex_exit(bgep->genlock); 562 return (EIO); 563 } 564 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 565 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 566 mutex_exit(bgep->genlock); 567 return (EIO); 568 } 569 #ifdef BGE_IPMI_ASF 570 if (bgep->asf_enabled) { 571 if (bgep->asf_status != ASF_STAT_RUN) { 572 /* start ASF heart beat */ 573 bgep->asf_timeout_id = timeout(bge_asf_heartbeat, 574 (void *)bgep, 575 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 576 bgep->asf_status = ASF_STAT_RUN; 577 } 578 } 579 #endif 580 mutex_exit(bgep->genlock); 581 582 return (0); 583 } 584 585 /* 586 * bge_m_unicst() -- set the physical network address 587 */ 588 static int 589 bge_m_unicst(void *arg, const uint8_t *macaddr) 590 { 591 /* 592 * Request to set address in 593 * address slot 0, i.e., default address 594 */ 595 return (bge_unicst_set(arg, macaddr, 0)); 596 } 597 598 /* 599 * bge_unicst_set() -- set the physical network address 600 */ 601 static int 602 bge_unicst_set(void *arg, const uint8_t *macaddr, mac_addr_slot_t slot) 603 { 604 bge_t *bgep = arg; /* private device info */ 605 606 BGE_TRACE(("bge_m_unicst_set($%p, %s)", arg, 607 ether_sprintf((void *)macaddr))); 608 /* 609 * Remember the new current address in the driver state 610 * Sync the chip's idea of the address too ... 611 */ 612 mutex_enter(bgep->genlock); 613 if (!(bgep->progress & PROGRESS_INTR)) { 614 /* can happen during autorecovery */ 615 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 616 mutex_exit(bgep->genlock); 617 return (EIO); 618 } 619 ethaddr_copy(macaddr, bgep->curr_addr[slot].addr); 620 #ifdef BGE_IPMI_ASF 621 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) { 622 #else 623 if (bge_chip_sync(bgep) == DDI_FAILURE) { 624 #endif 625 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 626 (void) bge_check_acc_handle(bgep, bgep->io_handle); 627 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 628 mutex_exit(bgep->genlock); 629 return (EIO); 630 } 631 #ifdef BGE_IPMI_ASF 632 if (bgep->asf_enabled) { 633 /* 634 * The above bge_chip_sync() function wrote the ethernet MAC 635 * addresses registers which destroyed the IPMI/ASF sideband. 636 * Here, we have to reset chip to make IPMI/ASF sideband work. 637 */ 638 if (bgep->asf_status == ASF_STAT_RUN) { 639 /* 640 * We must stop ASF heart beat before bge_chip_stop(), 641 * otherwise some computers (ex. IBM HS20 blade server) 642 * may crash. 643 */ 644 bge_asf_update_status(bgep); 645 bge_asf_stop_timer(bgep); 646 bgep->asf_status = ASF_STAT_STOP; 647 648 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 649 } 650 bge_chip_stop(bgep, B_FALSE); 651 652 if (bge_restart(bgep, B_FALSE) == DDI_FAILURE) { 653 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 654 (void) bge_check_acc_handle(bgep, bgep->io_handle); 655 ddi_fm_service_impact(bgep->devinfo, 656 DDI_SERVICE_DEGRADED); 657 mutex_exit(bgep->genlock); 658 return (EIO); 659 } 660 661 /* 662 * Start our ASF heartbeat counter as soon as possible. 663 */ 664 if (bgep->asf_status != ASF_STAT_RUN) { 665 /* start ASF heart beat */ 666 bgep->asf_timeout_id = timeout(bge_asf_heartbeat, 667 (void *)bgep, 668 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 669 bgep->asf_status = ASF_STAT_RUN; 670 } 671 } 672 #endif 673 BGE_DEBUG(("bge_m_unicst_set($%p) done", arg)); 674 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 675 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 676 mutex_exit(bgep->genlock); 677 return (EIO); 678 } 679 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 680 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 681 mutex_exit(bgep->genlock); 682 return (EIO); 683 } 684 mutex_exit(bgep->genlock); 685 686 return (0); 687 } 688 689 /* 690 * The following four routines are used as callbacks for multiple MAC 691 * address support: 692 * - bge_m_unicst_add(void *, mac_multi_addr_t *); 693 * - bge_m_unicst_remove(void *, mac_addr_slot_t); 694 * - bge_m_unicst_modify(void *, mac_multi_addr_t *); 695 * - bge_m_unicst_get(void *, mac_multi_addr_t *); 696 */ 697 698 /* 699 * bge_m_unicst_add() - will find an unused address slot, set the 700 * address value to the one specified, reserve that slot and enable 701 * the NIC to start filtering on the new MAC address. 702 * address slot. Returns 0 on success. 703 */ 704 static int 705 bge_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 706 { 707 bge_t *bgep = arg; /* private device info */ 708 mac_addr_slot_t slot; 709 int err; 710 711 if (mac_unicst_verify(bgep->mh, 712 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 713 return (EINVAL); 714 715 mutex_enter(bgep->genlock); 716 if (bgep->unicst_addr_avail == 0) { 717 /* no slots available */ 718 mutex_exit(bgep->genlock); 719 return (ENOSPC); 720 } 721 722 /* 723 * Primary/default address is in slot 0. The next three 724 * addresses are the multiple MAC addresses. So multiple 725 * MAC address 0 is in slot 1, 1 in slot 2, and so on. 726 * So the first multiple MAC address resides in slot 1. 727 */ 728 for (slot = 1; slot < bgep->unicst_addr_total; slot++) { 729 if (bgep->curr_addr[slot].set == B_FALSE) { 730 bgep->curr_addr[slot].set = B_TRUE; 731 break; 732 } 733 } 734 735 ASSERT(slot < bgep->unicst_addr_total); 736 bgep->unicst_addr_avail--; 737 mutex_exit(bgep->genlock); 738 maddr->mma_slot = slot; 739 740 if ((err = bge_unicst_set(bgep, maddr->mma_addr, slot)) != 0) { 741 mutex_enter(bgep->genlock); 742 bgep->curr_addr[slot].set = B_FALSE; 743 bgep->unicst_addr_avail++; 744 mutex_exit(bgep->genlock); 745 } 746 return (err); 747 } 748 749 /* 750 * bge_m_unicst_remove() - removes a MAC address that was added by a 751 * call to bge_m_unicst_add(). The slot number that was returned in 752 * add() is passed in the call to remove the address. 753 * Returns 0 on success. 754 */ 755 static int 756 bge_m_unicst_remove(void *arg, mac_addr_slot_t slot) 757 { 758 bge_t *bgep = arg; /* private device info */ 759 760 if (slot <= 0 || slot >= bgep->unicst_addr_total) 761 return (EINVAL); 762 763 mutex_enter(bgep->genlock); 764 if (bgep->curr_addr[slot].set == B_TRUE) { 765 bgep->curr_addr[slot].set = B_FALSE; 766 bgep->unicst_addr_avail++; 767 mutex_exit(bgep->genlock); 768 /* 769 * Copy the default address to the passed slot 770 */ 771 return (bge_unicst_set(bgep, bgep->curr_addr[0].addr, slot)); 772 } 773 mutex_exit(bgep->genlock); 774 return (EINVAL); 775 } 776 777 /* 778 * bge_m_unicst_modify() - modifies the value of an address that 779 * has been added by bge_m_unicst_add(). The new address, address 780 * length and the slot number that was returned in the call to add 781 * should be passed to bge_m_unicst_modify(). mma_flags should be 782 * set to 0. Returns 0 on success. 783 */ 784 static int 785 bge_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 786 { 787 bge_t *bgep = arg; /* private device info */ 788 mac_addr_slot_t slot; 789 790 if (mac_unicst_verify(bgep->mh, 791 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 792 return (EINVAL); 793 794 slot = maddr->mma_slot; 795 796 if (slot <= 0 || slot >= bgep->unicst_addr_total) 797 return (EINVAL); 798 799 mutex_enter(bgep->genlock); 800 if (bgep->curr_addr[slot].set == B_TRUE) { 801 mutex_exit(bgep->genlock); 802 return (bge_unicst_set(bgep, maddr->mma_addr, slot)); 803 } 804 mutex_exit(bgep->genlock); 805 806 return (EINVAL); 807 } 808 809 /* 810 * bge_m_unicst_get() - will get the MAC address and all other 811 * information related to the address slot passed in mac_multi_addr_t. 812 * mma_flags should be set to 0 in the call. 813 * On return, mma_flags can take the following values: 814 * 1) MMAC_SLOT_UNUSED 815 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 816 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 817 * 4) MMAC_SLOT_USED 818 */ 819 static int 820 bge_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 821 { 822 bge_t *bgep = arg; /* private device info */ 823 mac_addr_slot_t slot; 824 825 slot = maddr->mma_slot; 826 827 if (slot <= 0 || slot >= bgep->unicst_addr_total) 828 return (EINVAL); 829 830 mutex_enter(bgep->genlock); 831 if (bgep->curr_addr[slot].set == B_TRUE) { 832 ethaddr_copy(bgep->curr_addr[slot].addr, 833 maddr->mma_addr); 834 maddr->mma_flags = MMAC_SLOT_USED; 835 } else { 836 maddr->mma_flags = MMAC_SLOT_UNUSED; 837 } 838 mutex_exit(bgep->genlock); 839 840 return (0); 841 } 842 843 /* 844 * Compute the index of the required bit in the multicast hash map. 845 * This must mirror the way the hardware actually does it! 846 * See Broadcom document 570X-PG102-R page 125. 847 */ 848 static uint32_t 849 bge_hash_index(const uint8_t *mca) 850 { 851 uint32_t hash; 852 853 CRC32(hash, mca, ETHERADDRL, -1U, crc32_table); 854 855 return (hash); 856 } 857 858 /* 859 * bge_m_multicst_add() -- enable/disable a multicast address 860 */ 861 static int 862 bge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 863 { 864 bge_t *bgep = arg; /* private device info */ 865 uint32_t hash; 866 uint32_t index; 867 uint32_t word; 868 uint32_t bit; 869 uint8_t *refp; 870 871 BGE_TRACE(("bge_m_multicst($%p, %s, %s)", arg, 872 (add) ? "add" : "remove", ether_sprintf((void *)mca))); 873 874 /* 875 * Precalculate all required masks, pointers etc ... 876 */ 877 hash = bge_hash_index(mca); 878 index = hash % BGE_HASH_TABLE_SIZE; 879 word = index/32u; 880 bit = 1 << (index % 32u); 881 refp = &bgep->mcast_refs[index]; 882 883 BGE_DEBUG(("bge_m_multicst: hash 0x%x index %d (%d:0x%x) = %d", 884 hash, index, word, bit, *refp)); 885 886 /* 887 * We must set the appropriate bit in the hash map (and the 888 * corresponding h/w register) when the refcount goes from 0 889 * to >0, and clear it when the last ref goes away (refcount 890 * goes from >0 back to 0). If we change the hash map, we 891 * must also update the chip's hardware map registers. 892 */ 893 mutex_enter(bgep->genlock); 894 if (!(bgep->progress & PROGRESS_INTR)) { 895 /* can happen during autorecovery */ 896 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 897 mutex_exit(bgep->genlock); 898 return (EIO); 899 } 900 if (add) { 901 if ((*refp)++ == 0) { 902 bgep->mcast_hash[word] |= bit; 903 #ifdef BGE_IPMI_ASF 904 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 905 #else 906 if (bge_chip_sync(bgep) == DDI_FAILURE) { 907 #endif 908 (void) bge_check_acc_handle(bgep, 909 bgep->cfg_handle); 910 (void) bge_check_acc_handle(bgep, 911 bgep->io_handle); 912 ddi_fm_service_impact(bgep->devinfo, 913 DDI_SERVICE_DEGRADED); 914 mutex_exit(bgep->genlock); 915 return (EIO); 916 } 917 } 918 } else { 919 if (--(*refp) == 0) { 920 bgep->mcast_hash[word] &= ~bit; 921 #ifdef BGE_IPMI_ASF 922 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 923 #else 924 if (bge_chip_sync(bgep) == DDI_FAILURE) { 925 #endif 926 (void) bge_check_acc_handle(bgep, 927 bgep->cfg_handle); 928 (void) bge_check_acc_handle(bgep, 929 bgep->io_handle); 930 ddi_fm_service_impact(bgep->devinfo, 931 DDI_SERVICE_DEGRADED); 932 mutex_exit(bgep->genlock); 933 return (EIO); 934 } 935 } 936 } 937 BGE_DEBUG(("bge_m_multicst($%p) done", arg)); 938 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 939 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 940 mutex_exit(bgep->genlock); 941 return (EIO); 942 } 943 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 944 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 945 mutex_exit(bgep->genlock); 946 return (EIO); 947 } 948 mutex_exit(bgep->genlock); 949 950 return (0); 951 } 952 953 /* 954 * bge_m_promisc() -- set or reset promiscuous mode on the board 955 * 956 * Program the hardware to enable/disable promiscuous and/or 957 * receive-all-multicast modes. 958 */ 959 static int 960 bge_m_promisc(void *arg, boolean_t on) 961 { 962 bge_t *bgep = arg; 963 964 BGE_TRACE(("bge_m_promisc_set($%p, %d)", arg, on)); 965 966 /* 967 * Store MAC layer specified mode and pass to chip layer to update h/w 968 */ 969 mutex_enter(bgep->genlock); 970 if (!(bgep->progress & PROGRESS_INTR)) { 971 /* can happen during autorecovery */ 972 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 973 mutex_exit(bgep->genlock); 974 return (EIO); 975 } 976 bgep->promisc = on; 977 #ifdef BGE_IPMI_ASF 978 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 979 #else 980 if (bge_chip_sync(bgep) == DDI_FAILURE) { 981 #endif 982 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 983 (void) bge_check_acc_handle(bgep, bgep->io_handle); 984 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 985 mutex_exit(bgep->genlock); 986 return (EIO); 987 } 988 BGE_DEBUG(("bge_m_promisc_set($%p) done", arg)); 989 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 990 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 991 mutex_exit(bgep->genlock); 992 return (EIO); 993 } 994 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 995 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 996 mutex_exit(bgep->genlock); 997 return (EIO); 998 } 999 mutex_exit(bgep->genlock); 1000 return (0); 1001 } 1002 1003 /*ARGSUSED*/ 1004 static boolean_t 1005 bge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 1006 { 1007 bge_t *bgep = arg; 1008 1009 switch (cap) { 1010 case MAC_CAPAB_HCKSUM: { 1011 uint32_t *txflags = cap_data; 1012 1013 *txflags = HCKSUM_INET_FULL_V4 | HCKSUM_IPHDRCKSUM; 1014 break; 1015 } 1016 1017 case MAC_CAPAB_POLL: 1018 /* 1019 * There's nothing for us to fill in, simply returning 1020 * B_TRUE stating that we support polling is sufficient. 1021 */ 1022 break; 1023 1024 case MAC_CAPAB_MULTIADDRESS: { 1025 multiaddress_capab_t *mmacp = cap_data; 1026 1027 mutex_enter(bgep->genlock); 1028 /* 1029 * The number of MAC addresses made available by 1030 * this capability is one less than the total as 1031 * the primary address in slot 0 is counted in 1032 * the total. 1033 */ 1034 mmacp->maddr_naddr = bgep->unicst_addr_total - 1; 1035 mmacp->maddr_naddrfree = bgep->unicst_addr_avail; 1036 /* No multiple factory addresses, set mma_flag to 0 */ 1037 mmacp->maddr_flag = 0; 1038 mmacp->maddr_handle = bgep; 1039 mmacp->maddr_add = bge_m_unicst_add; 1040 mmacp->maddr_remove = bge_m_unicst_remove; 1041 mmacp->maddr_modify = bge_m_unicst_modify; 1042 mmacp->maddr_get = bge_m_unicst_get; 1043 mmacp->maddr_reserve = NULL; 1044 mutex_exit(bgep->genlock); 1045 break; 1046 } 1047 1048 default: 1049 return (B_FALSE); 1050 } 1051 return (B_TRUE); 1052 } 1053 1054 /* 1055 * Loopback ioctl code 1056 */ 1057 1058 static lb_property_t loopmodes[] = { 1059 { normal, "normal", BGE_LOOP_NONE }, 1060 { external, "1000Mbps", BGE_LOOP_EXTERNAL_1000 }, 1061 { external, "100Mbps", BGE_LOOP_EXTERNAL_100 }, 1062 { external, "10Mbps", BGE_LOOP_EXTERNAL_10 }, 1063 { internal, "PHY", BGE_LOOP_INTERNAL_PHY }, 1064 { internal, "MAC", BGE_LOOP_INTERNAL_MAC } 1065 }; 1066 1067 static enum ioc_reply 1068 bge_set_loop_mode(bge_t *bgep, uint32_t mode) 1069 { 1070 const char *msg; 1071 1072 /* 1073 * If the mode isn't being changed, there's nothing to do ... 1074 */ 1075 if (mode == bgep->param_loop_mode) 1076 return (IOC_ACK); 1077 1078 /* 1079 * Validate the requested mode and prepare a suitable message 1080 * to explain the link down/up cycle that the change will 1081 * probably induce ... 1082 */ 1083 switch (mode) { 1084 default: 1085 return (IOC_INVAL); 1086 1087 case BGE_LOOP_NONE: 1088 msg = " (loopback disabled)"; 1089 break; 1090 1091 case BGE_LOOP_EXTERNAL_1000: 1092 case BGE_LOOP_EXTERNAL_100: 1093 case BGE_LOOP_EXTERNAL_10: 1094 msg = " (external loopback selected)"; 1095 break; 1096 1097 case BGE_LOOP_INTERNAL_PHY: 1098 msg = " (PHY internal loopback selected)"; 1099 break; 1100 1101 case BGE_LOOP_INTERNAL_MAC: 1102 msg = " (MAC internal loopback selected)"; 1103 break; 1104 } 1105 1106 /* 1107 * All OK; tell the caller to reprogram 1108 * the PHY and/or MAC for the new mode ... 1109 */ 1110 bgep->link_down_msg = bgep->link_up_msg = msg; 1111 bgep->param_loop_mode = mode; 1112 return (IOC_RESTART_ACK); 1113 } 1114 1115 static enum ioc_reply 1116 bge_loop_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 1117 { 1118 lb_info_sz_t *lbsp; 1119 lb_property_t *lbpp; 1120 uint32_t *lbmp; 1121 int cmd; 1122 1123 _NOTE(ARGUNUSED(wq)) 1124 1125 /* 1126 * Validate format of ioctl 1127 */ 1128 if (mp->b_cont == NULL) 1129 return (IOC_INVAL); 1130 1131 cmd = iocp->ioc_cmd; 1132 switch (cmd) { 1133 default: 1134 /* NOTREACHED */ 1135 bge_error(bgep, "bge_loop_ioctl: invalid cmd 0x%x", cmd); 1136 return (IOC_INVAL); 1137 1138 case LB_GET_INFO_SIZE: 1139 if (iocp->ioc_count != sizeof (lb_info_sz_t)) 1140 return (IOC_INVAL); 1141 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 1142 *lbsp = sizeof (loopmodes); 1143 return (IOC_REPLY); 1144 1145 case LB_GET_INFO: 1146 if (iocp->ioc_count != sizeof (loopmodes)) 1147 return (IOC_INVAL); 1148 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 1149 bcopy(loopmodes, lbpp, sizeof (loopmodes)); 1150 return (IOC_REPLY); 1151 1152 case LB_GET_MODE: 1153 if (iocp->ioc_count != sizeof (uint32_t)) 1154 return (IOC_INVAL); 1155 lbmp = (uint32_t *)mp->b_cont->b_rptr; 1156 *lbmp = bgep->param_loop_mode; 1157 return (IOC_REPLY); 1158 1159 case LB_SET_MODE: 1160 if (iocp->ioc_count != sizeof (uint32_t)) 1161 return (IOC_INVAL); 1162 lbmp = (uint32_t *)mp->b_cont->b_rptr; 1163 return (bge_set_loop_mode(bgep, *lbmp)); 1164 } 1165 } 1166 1167 /* 1168 * Specific bge IOCTLs, the gld module handles the generic ones. 1169 */ 1170 static void 1171 bge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 1172 { 1173 bge_t *bgep = arg; 1174 struct iocblk *iocp; 1175 enum ioc_reply status; 1176 boolean_t need_privilege; 1177 int err; 1178 int cmd; 1179 1180 /* 1181 * Validate the command before bothering with the mutex ... 1182 */ 1183 iocp = (struct iocblk *)mp->b_rptr; 1184 iocp->ioc_error = 0; 1185 need_privilege = B_TRUE; 1186 cmd = iocp->ioc_cmd; 1187 switch (cmd) { 1188 default: 1189 miocnak(wq, mp, 0, EINVAL); 1190 return; 1191 1192 case BGE_MII_READ: 1193 case BGE_MII_WRITE: 1194 case BGE_SEE_READ: 1195 case BGE_SEE_WRITE: 1196 case BGE_FLASH_READ: 1197 case BGE_FLASH_WRITE: 1198 case BGE_DIAG: 1199 case BGE_PEEK: 1200 case BGE_POKE: 1201 case BGE_PHY_RESET: 1202 case BGE_SOFT_RESET: 1203 case BGE_HARD_RESET: 1204 break; 1205 1206 case LB_GET_INFO_SIZE: 1207 case LB_GET_INFO: 1208 case LB_GET_MODE: 1209 need_privilege = B_FALSE; 1210 /* FALLTHRU */ 1211 case LB_SET_MODE: 1212 break; 1213 1214 case ND_GET: 1215 need_privilege = B_FALSE; 1216 /* FALLTHRU */ 1217 case ND_SET: 1218 break; 1219 } 1220 1221 if (need_privilege) { 1222 /* 1223 * Check for specific net_config privilege on Solaris 10+. 1224 */ 1225 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 1226 if (err != 0) { 1227 miocnak(wq, mp, 0, err); 1228 return; 1229 } 1230 } 1231 1232 mutex_enter(bgep->genlock); 1233 if (!(bgep->progress & PROGRESS_INTR)) { 1234 /* can happen during autorecovery */ 1235 mutex_exit(bgep->genlock); 1236 miocnak(wq, mp, 0, EIO); 1237 return; 1238 } 1239 1240 switch (cmd) { 1241 default: 1242 _NOTE(NOTREACHED) 1243 status = IOC_INVAL; 1244 break; 1245 1246 case BGE_MII_READ: 1247 case BGE_MII_WRITE: 1248 case BGE_SEE_READ: 1249 case BGE_SEE_WRITE: 1250 case BGE_FLASH_READ: 1251 case BGE_FLASH_WRITE: 1252 case BGE_DIAG: 1253 case BGE_PEEK: 1254 case BGE_POKE: 1255 case BGE_PHY_RESET: 1256 case BGE_SOFT_RESET: 1257 case BGE_HARD_RESET: 1258 status = bge_chip_ioctl(bgep, wq, mp, iocp); 1259 break; 1260 1261 case LB_GET_INFO_SIZE: 1262 case LB_GET_INFO: 1263 case LB_GET_MODE: 1264 case LB_SET_MODE: 1265 status = bge_loop_ioctl(bgep, wq, mp, iocp); 1266 break; 1267 1268 case ND_GET: 1269 case ND_SET: 1270 status = bge_nd_ioctl(bgep, wq, mp, iocp); 1271 break; 1272 } 1273 1274 /* 1275 * Do we need to reprogram the PHY and/or the MAC? 1276 * Do it now, while we still have the mutex. 1277 * 1278 * Note: update the PHY first, 'cos it controls the 1279 * speed/duplex parameters that the MAC code uses. 1280 */ 1281 switch (status) { 1282 case IOC_RESTART_REPLY: 1283 case IOC_RESTART_ACK: 1284 if (bge_phys_update(bgep) != DDI_SUCCESS) { 1285 ddi_fm_service_impact(bgep->devinfo, 1286 DDI_SERVICE_DEGRADED); 1287 status = IOC_INVAL; 1288 } 1289 #ifdef BGE_IPMI_ASF 1290 if (bge_chip_sync(bgep, B_TRUE) == DDI_FAILURE) { 1291 #else 1292 if (bge_chip_sync(bgep) == DDI_FAILURE) { 1293 #endif 1294 ddi_fm_service_impact(bgep->devinfo, 1295 DDI_SERVICE_DEGRADED); 1296 status = IOC_INVAL; 1297 } 1298 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 1299 bge_chip_msi_trig(bgep); 1300 break; 1301 } 1302 1303 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 1304 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 1305 status = IOC_INVAL; 1306 } 1307 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 1308 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 1309 status = IOC_INVAL; 1310 } 1311 mutex_exit(bgep->genlock); 1312 1313 /* 1314 * Finally, decide how to reply 1315 */ 1316 switch (status) { 1317 default: 1318 case IOC_INVAL: 1319 /* 1320 * Error, reply with a NAK and EINVAL or the specified error 1321 */ 1322 miocnak(wq, mp, 0, iocp->ioc_error == 0 ? 1323 EINVAL : iocp->ioc_error); 1324 break; 1325 1326 case IOC_DONE: 1327 /* 1328 * OK, reply already sent 1329 */ 1330 break; 1331 1332 case IOC_RESTART_ACK: 1333 case IOC_ACK: 1334 /* 1335 * OK, reply with an ACK 1336 */ 1337 miocack(wq, mp, 0, 0); 1338 break; 1339 1340 case IOC_RESTART_REPLY: 1341 case IOC_REPLY: 1342 /* 1343 * OK, send prepared reply as ACK or NAK 1344 */ 1345 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1346 M_IOCACK : M_IOCNAK; 1347 qreply(wq, mp); 1348 break; 1349 } 1350 } 1351 1352 static void 1353 bge_m_resources(void *arg) 1354 { 1355 bge_t *bgep = arg; 1356 recv_ring_t *rrp; 1357 mac_rx_fifo_t mrf; 1358 int ring; 1359 1360 mutex_enter(bgep->genlock); 1361 1362 /* 1363 * Register Rx rings as resources and save mac 1364 * resource id for future reference 1365 */ 1366 mrf.mrf_type = MAC_RX_FIFO; 1367 mrf.mrf_blank = bge_chip_blank; 1368 mrf.mrf_arg = (void *)bgep; 1369 mrf.mrf_normal_blank_time = bge_rx_ticks_norm; 1370 mrf.mrf_normal_pkt_count = bge_rx_count_norm; 1371 1372 for (ring = 0; ring < bgep->chipid.rx_rings; ring++) { 1373 rrp = &bgep->recv[ring]; 1374 rrp->handle = mac_resource_add(bgep->mh, 1375 (mac_resource_t *)&mrf); 1376 } 1377 1378 mutex_exit(bgep->genlock); 1379 } 1380 1381 /* 1382 * ========== Per-instance setup/teardown code ========== 1383 */ 1384 1385 #undef BGE_DBG 1386 #define BGE_DBG BGE_DBG_INIT /* debug flag for this code */ 1387 /* 1388 * Allocate an area of memory and a DMA handle for accessing it 1389 */ 1390 static int 1391 bge_alloc_dma_mem(bge_t *bgep, size_t memsize, ddi_device_acc_attr_t *attr_p, 1392 uint_t dma_flags, dma_area_t *dma_p) 1393 { 1394 caddr_t va; 1395 int err; 1396 1397 BGE_TRACE(("bge_alloc_dma_mem($%p, %ld, $%p, 0x%x, $%p)", 1398 (void *)bgep, memsize, attr_p, dma_flags, dma_p)); 1399 1400 /* 1401 * Allocate handle 1402 */ 1403 err = ddi_dma_alloc_handle(bgep->devinfo, &dma_attr, 1404 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_hdl); 1405 if (err != DDI_SUCCESS) 1406 return (DDI_FAILURE); 1407 1408 /* 1409 * Allocate memory 1410 */ 1411 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 1412 dma_flags, DDI_DMA_DONTWAIT, NULL, &va, &dma_p->alength, 1413 &dma_p->acc_hdl); 1414 if (err != DDI_SUCCESS) 1415 return (DDI_FAILURE); 1416 1417 /* 1418 * Bind the two together 1419 */ 1420 dma_p->mem_va = va; 1421 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 1422 va, dma_p->alength, dma_flags, DDI_DMA_DONTWAIT, NULL, 1423 &dma_p->cookie, &dma_p->ncookies); 1424 1425 BGE_DEBUG(("bge_alloc_dma_mem(): bind %d bytes; err %d, %d cookies", 1426 dma_p->alength, err, dma_p->ncookies)); 1427 1428 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) 1429 return (DDI_FAILURE); 1430 1431 dma_p->nslots = ~0U; 1432 dma_p->size = ~0U; 1433 dma_p->token = ~0U; 1434 dma_p->offset = 0; 1435 return (DDI_SUCCESS); 1436 } 1437 1438 /* 1439 * Free one allocated area of DMAable memory 1440 */ 1441 static void 1442 bge_free_dma_mem(dma_area_t *dma_p) 1443 { 1444 if (dma_p->dma_hdl != NULL) { 1445 if (dma_p->ncookies) { 1446 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 1447 dma_p->ncookies = 0; 1448 } 1449 ddi_dma_free_handle(&dma_p->dma_hdl); 1450 dma_p->dma_hdl = NULL; 1451 } 1452 1453 if (dma_p->acc_hdl != NULL) { 1454 ddi_dma_mem_free(&dma_p->acc_hdl); 1455 dma_p->acc_hdl = NULL; 1456 } 1457 } 1458 /* 1459 * Utility routine to carve a slice off a chunk of allocated memory, 1460 * updating the chunk descriptor accordingly. The size of the slice 1461 * is given by the product of the <qty> and <size> parameters. 1462 */ 1463 static void 1464 bge_slice_chunk(dma_area_t *slice, dma_area_t *chunk, 1465 uint32_t qty, uint32_t size) 1466 { 1467 static uint32_t sequence = 0xbcd5704a; 1468 size_t totsize; 1469 1470 totsize = qty*size; 1471 ASSERT(size >= 0); 1472 ASSERT(totsize <= chunk->alength); 1473 1474 *slice = *chunk; 1475 slice->nslots = qty; 1476 slice->size = size; 1477 slice->alength = totsize; 1478 slice->token = ++sequence; 1479 1480 chunk->mem_va = (caddr_t)chunk->mem_va + totsize; 1481 chunk->alength -= totsize; 1482 chunk->offset += totsize; 1483 chunk->cookie.dmac_laddress += totsize; 1484 chunk->cookie.dmac_size -= totsize; 1485 } 1486 1487 /* 1488 * Initialise the specified Receive Producer (Buffer) Ring, using 1489 * the information in the <dma_area> descriptors that it contains 1490 * to set up all the other fields. This routine should be called 1491 * only once for each ring. 1492 */ 1493 static void 1494 bge_init_buff_ring(bge_t *bgep, uint64_t ring) 1495 { 1496 buff_ring_t *brp; 1497 bge_status_t *bsp; 1498 sw_rbd_t *srbdp; 1499 dma_area_t pbuf; 1500 uint32_t bufsize; 1501 uint32_t nslots; 1502 uint32_t slot; 1503 uint32_t split; 1504 1505 static bge_regno_t nic_ring_addrs[BGE_BUFF_RINGS_MAX] = { 1506 NIC_MEM_SHADOW_BUFF_STD, 1507 NIC_MEM_SHADOW_BUFF_JUMBO, 1508 NIC_MEM_SHADOW_BUFF_MINI 1509 }; 1510 static bge_regno_t mailbox_regs[BGE_BUFF_RINGS_MAX] = { 1511 RECV_STD_PROD_INDEX_REG, 1512 RECV_JUMBO_PROD_INDEX_REG, 1513 RECV_MINI_PROD_INDEX_REG 1514 }; 1515 static bge_regno_t buff_cons_xref[BGE_BUFF_RINGS_MAX] = { 1516 STATUS_STD_BUFF_CONS_INDEX, 1517 STATUS_JUMBO_BUFF_CONS_INDEX, 1518 STATUS_MINI_BUFF_CONS_INDEX 1519 }; 1520 1521 BGE_TRACE(("bge_init_buff_ring($%p, %d)", 1522 (void *)bgep, ring)); 1523 1524 brp = &bgep->buff[ring]; 1525 nslots = brp->desc.nslots; 1526 ASSERT(brp->buf[0].nslots == nslots/BGE_SPLIT); 1527 bufsize = brp->buf[0].size; 1528 1529 /* 1530 * Set up the copy of the h/w RCB 1531 * 1532 * Note: unlike Send & Receive Return Rings, (where the max_len 1533 * field holds the number of slots), in a Receive Buffer Ring 1534 * this field indicates the size of each buffer in the ring. 1535 */ 1536 brp->hw_rcb.host_ring_addr = brp->desc.cookie.dmac_laddress; 1537 brp->hw_rcb.max_len = bufsize; 1538 brp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED; 1539 brp->hw_rcb.nic_ring_addr = nic_ring_addrs[ring]; 1540 1541 /* 1542 * Other one-off initialisation of per-ring data 1543 */ 1544 brp->bgep = bgep; 1545 bsp = DMA_VPTR(bgep->status_block); 1546 brp->cons_index_p = &bsp->buff_cons_index[buff_cons_xref[ring]]; 1547 brp->chip_mbx_reg = mailbox_regs[ring]; 1548 mutex_init(brp->rf_lock, NULL, MUTEX_DRIVER, 1549 DDI_INTR_PRI(bgep->intr_pri)); 1550 1551 /* 1552 * Allocate the array of s/w Receive Buffer Descriptors 1553 */ 1554 srbdp = kmem_zalloc(nslots*sizeof (*srbdp), KM_SLEEP); 1555 brp->sw_rbds = srbdp; 1556 1557 /* 1558 * Now initialise each array element once and for all 1559 */ 1560 for (split = 0; split < BGE_SPLIT; ++split) { 1561 pbuf = brp->buf[split]; 1562 for (slot = 0; slot < nslots/BGE_SPLIT; ++srbdp, ++slot) 1563 bge_slice_chunk(&srbdp->pbuf, &pbuf, 1, bufsize); 1564 ASSERT(pbuf.alength == 0); 1565 } 1566 } 1567 1568 /* 1569 * Clean up initialisation done above before the memory is freed 1570 */ 1571 static void 1572 bge_fini_buff_ring(bge_t *bgep, uint64_t ring) 1573 { 1574 buff_ring_t *brp; 1575 sw_rbd_t *srbdp; 1576 1577 BGE_TRACE(("bge_fini_buff_ring($%p, %d)", 1578 (void *)bgep, ring)); 1579 1580 brp = &bgep->buff[ring]; 1581 srbdp = brp->sw_rbds; 1582 kmem_free(srbdp, brp->desc.nslots*sizeof (*srbdp)); 1583 1584 mutex_destroy(brp->rf_lock); 1585 } 1586 1587 /* 1588 * Initialise the specified Receive (Return) Ring, using the 1589 * information in the <dma_area> descriptors that it contains 1590 * to set up all the other fields. This routine should be called 1591 * only once for each ring. 1592 */ 1593 static void 1594 bge_init_recv_ring(bge_t *bgep, uint64_t ring) 1595 { 1596 recv_ring_t *rrp; 1597 bge_status_t *bsp; 1598 uint32_t nslots; 1599 1600 BGE_TRACE(("bge_init_recv_ring($%p, %d)", 1601 (void *)bgep, ring)); 1602 1603 /* 1604 * The chip architecture requires that receive return rings have 1605 * 512 or 1024 or 2048 elements per ring. See 570X-PG108-R page 103. 1606 */ 1607 rrp = &bgep->recv[ring]; 1608 nslots = rrp->desc.nslots; 1609 ASSERT(nslots == 0 || nslots == 512 || 1610 nslots == 1024 || nslots == 2048); 1611 1612 /* 1613 * Set up the copy of the h/w RCB 1614 */ 1615 rrp->hw_rcb.host_ring_addr = rrp->desc.cookie.dmac_laddress; 1616 rrp->hw_rcb.max_len = nslots; 1617 rrp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED; 1618 rrp->hw_rcb.nic_ring_addr = 0; 1619 1620 /* 1621 * Other one-off initialisation of per-ring data 1622 */ 1623 rrp->bgep = bgep; 1624 bsp = DMA_VPTR(bgep->status_block); 1625 rrp->prod_index_p = RECV_INDEX_P(bsp, ring); 1626 rrp->chip_mbx_reg = RECV_RING_CONS_INDEX_REG(ring); 1627 mutex_init(rrp->rx_lock, NULL, MUTEX_DRIVER, 1628 DDI_INTR_PRI(bgep->intr_pri)); 1629 } 1630 1631 1632 /* 1633 * Clean up initialisation done above before the memory is freed 1634 */ 1635 static void 1636 bge_fini_recv_ring(bge_t *bgep, uint64_t ring) 1637 { 1638 recv_ring_t *rrp; 1639 1640 BGE_TRACE(("bge_fini_recv_ring($%p, %d)", 1641 (void *)bgep, ring)); 1642 1643 rrp = &bgep->recv[ring]; 1644 if (rrp->rx_softint) 1645 ddi_remove_softintr(rrp->rx_softint); 1646 mutex_destroy(rrp->rx_lock); 1647 } 1648 1649 /* 1650 * Initialise the specified Send Ring, using the information in the 1651 * <dma_area> descriptors that it contains to set up all the other 1652 * fields. This routine should be called only once for each ring. 1653 */ 1654 static void 1655 bge_init_send_ring(bge_t *bgep, uint64_t ring) 1656 { 1657 send_ring_t *srp; 1658 bge_status_t *bsp; 1659 sw_sbd_t *ssbdp; 1660 dma_area_t desc; 1661 dma_area_t pbuf; 1662 uint32_t nslots; 1663 uint32_t slot; 1664 uint32_t split; 1665 sw_txbuf_t *txbuf; 1666 1667 BGE_TRACE(("bge_init_send_ring($%p, %d)", 1668 (void *)bgep, ring)); 1669 1670 /* 1671 * The chip architecture requires that host-based send rings 1672 * have 512 elements per ring. See 570X-PG102-R page 56. 1673 */ 1674 srp = &bgep->send[ring]; 1675 nslots = srp->desc.nslots; 1676 ASSERT(nslots == 0 || nslots == 512); 1677 1678 /* 1679 * Set up the copy of the h/w RCB 1680 */ 1681 srp->hw_rcb.host_ring_addr = srp->desc.cookie.dmac_laddress; 1682 srp->hw_rcb.max_len = nslots; 1683 srp->hw_rcb.flags = nslots > 0 ? 0 : RCB_FLAG_RING_DISABLED; 1684 srp->hw_rcb.nic_ring_addr = NIC_MEM_SHADOW_SEND_RING(ring, nslots); 1685 1686 /* 1687 * Other one-off initialisation of per-ring data 1688 */ 1689 srp->bgep = bgep; 1690 bsp = DMA_VPTR(bgep->status_block); 1691 srp->cons_index_p = SEND_INDEX_P(bsp, ring); 1692 srp->chip_mbx_reg = SEND_RING_HOST_INDEX_REG(ring); 1693 mutex_init(srp->tx_lock, NULL, MUTEX_DRIVER, 1694 DDI_INTR_PRI(bgep->intr_pri)); 1695 mutex_init(srp->txbuf_lock, NULL, MUTEX_DRIVER, 1696 DDI_INTR_PRI(bgep->intr_pri)); 1697 mutex_init(srp->freetxbuf_lock, NULL, MUTEX_DRIVER, 1698 DDI_INTR_PRI(bgep->intr_pri)); 1699 mutex_init(srp->tc_lock, NULL, MUTEX_DRIVER, 1700 DDI_INTR_PRI(bgep->intr_pri)); 1701 if (nslots == 0) 1702 return; 1703 1704 /* 1705 * Allocate the array of s/w Send Buffer Descriptors 1706 */ 1707 ssbdp = kmem_zalloc(nslots*sizeof (*ssbdp), KM_SLEEP); 1708 txbuf = kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (*txbuf), KM_SLEEP); 1709 srp->txbuf_head = 1710 kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (bge_queue_item_t), KM_SLEEP); 1711 srp->pktp = kmem_zalloc(BGE_SEND_BUF_MAX*sizeof (send_pkt_t), KM_SLEEP); 1712 srp->sw_sbds = ssbdp; 1713 srp->txbuf = txbuf; 1714 srp->tx_buffers = BGE_SEND_BUF_NUM; 1715 srp->tx_buffers_low = srp->tx_buffers / 4; 1716 if (bgep->chipid.snd_buff_size > BGE_SEND_BUFF_SIZE_DEFAULT) 1717 srp->tx_array_max = BGE_SEND_BUF_ARRAY_JUMBO; 1718 else 1719 srp->tx_array_max = BGE_SEND_BUF_ARRAY; 1720 srp->tx_array = 1; 1721 1722 /* 1723 * Chunk tx desc area 1724 */ 1725 desc = srp->desc; 1726 for (slot = 0; slot < nslots; ++ssbdp, ++slot) { 1727 bge_slice_chunk(&ssbdp->desc, &desc, 1, 1728 sizeof (bge_sbd_t)); 1729 } 1730 ASSERT(desc.alength == 0); 1731 1732 /* 1733 * Chunk tx buffer area 1734 */ 1735 for (split = 0; split < BGE_SPLIT; ++split) { 1736 pbuf = srp->buf[0][split]; 1737 for (slot = 0; slot < BGE_SEND_BUF_NUM/BGE_SPLIT; ++slot) { 1738 bge_slice_chunk(&txbuf->buf, &pbuf, 1, 1739 bgep->chipid.snd_buff_size); 1740 txbuf++; 1741 } 1742 ASSERT(pbuf.alength == 0); 1743 } 1744 } 1745 1746 /* 1747 * Clean up initialisation done above before the memory is freed 1748 */ 1749 static void 1750 bge_fini_send_ring(bge_t *bgep, uint64_t ring) 1751 { 1752 send_ring_t *srp; 1753 uint32_t array; 1754 uint32_t split; 1755 uint32_t nslots; 1756 1757 BGE_TRACE(("bge_fini_send_ring($%p, %d)", 1758 (void *)bgep, ring)); 1759 1760 srp = &bgep->send[ring]; 1761 mutex_destroy(srp->tc_lock); 1762 mutex_destroy(srp->freetxbuf_lock); 1763 mutex_destroy(srp->txbuf_lock); 1764 mutex_destroy(srp->tx_lock); 1765 nslots = srp->desc.nslots; 1766 if (nslots == 0) 1767 return; 1768 1769 for (array = 1; array < srp->tx_array; ++array) 1770 for (split = 0; split < BGE_SPLIT; ++split) 1771 bge_free_dma_mem(&srp->buf[array][split]); 1772 kmem_free(srp->sw_sbds, nslots*sizeof (*srp->sw_sbds)); 1773 kmem_free(srp->txbuf_head, BGE_SEND_BUF_MAX*sizeof (*srp->txbuf_head)); 1774 kmem_free(srp->txbuf, BGE_SEND_BUF_MAX*sizeof (*srp->txbuf)); 1775 kmem_free(srp->pktp, BGE_SEND_BUF_MAX*sizeof (*srp->pktp)); 1776 srp->sw_sbds = NULL; 1777 srp->txbuf_head = NULL; 1778 srp->txbuf = NULL; 1779 srp->pktp = NULL; 1780 } 1781 1782 /* 1783 * Initialise all transmit, receive, and buffer rings. 1784 */ 1785 void 1786 bge_init_rings(bge_t *bgep) 1787 { 1788 uint32_t ring; 1789 1790 BGE_TRACE(("bge_init_rings($%p)", (void *)bgep)); 1791 1792 /* 1793 * Perform one-off initialisation of each ring ... 1794 */ 1795 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 1796 bge_init_send_ring(bgep, ring); 1797 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring) 1798 bge_init_recv_ring(bgep, ring); 1799 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring) 1800 bge_init_buff_ring(bgep, ring); 1801 } 1802 1803 /* 1804 * Undo the work of bge_init_rings() above before the memory is freed 1805 */ 1806 void 1807 bge_fini_rings(bge_t *bgep) 1808 { 1809 uint32_t ring; 1810 1811 BGE_TRACE(("bge_fini_rings($%p)", (void *)bgep)); 1812 1813 for (ring = 0; ring < BGE_BUFF_RINGS_MAX; ++ring) 1814 bge_fini_buff_ring(bgep, ring); 1815 for (ring = 0; ring < BGE_RECV_RINGS_MAX; ++ring) 1816 bge_fini_recv_ring(bgep, ring); 1817 for (ring = 0; ring < BGE_SEND_RINGS_MAX; ++ring) 1818 bge_fini_send_ring(bgep, ring); 1819 } 1820 1821 /* 1822 * Called from the bge_m_stop() to free the tx buffers which are 1823 * allocated from the tx process. 1824 */ 1825 void 1826 bge_free_txbuf_arrays(send_ring_t *srp) 1827 { 1828 uint32_t array; 1829 uint32_t split; 1830 1831 ASSERT(mutex_owned(srp->tx_lock)); 1832 1833 /* 1834 * Free the extra tx buffer DMA area 1835 */ 1836 for (array = 1; array < srp->tx_array; ++array) 1837 for (split = 0; split < BGE_SPLIT; ++split) 1838 bge_free_dma_mem(&srp->buf[array][split]); 1839 1840 /* 1841 * Restore initial tx buffer numbers 1842 */ 1843 srp->tx_array = 1; 1844 srp->tx_buffers = BGE_SEND_BUF_NUM; 1845 srp->tx_buffers_low = srp->tx_buffers / 4; 1846 srp->tx_flow = 0; 1847 bzero(srp->pktp, BGE_SEND_BUF_MAX * sizeof (*srp->pktp)); 1848 } 1849 1850 /* 1851 * Called from tx process to allocate more tx buffers 1852 */ 1853 bge_queue_item_t * 1854 bge_alloc_txbuf_array(bge_t *bgep, send_ring_t *srp) 1855 { 1856 bge_queue_t *txbuf_queue; 1857 bge_queue_item_t *txbuf_item_last; 1858 bge_queue_item_t *txbuf_item; 1859 bge_queue_item_t *txbuf_item_rtn; 1860 sw_txbuf_t *txbuf; 1861 dma_area_t area; 1862 size_t txbuffsize; 1863 uint32_t slot; 1864 uint32_t array; 1865 uint32_t split; 1866 uint32_t err; 1867 1868 ASSERT(mutex_owned(srp->tx_lock)); 1869 1870 array = srp->tx_array; 1871 if (array >= srp->tx_array_max) 1872 return (NULL); 1873 1874 /* 1875 * Allocate memory & handles for TX buffers 1876 */ 1877 txbuffsize = BGE_SEND_BUF_NUM*bgep->chipid.snd_buff_size; 1878 ASSERT((txbuffsize % BGE_SPLIT) == 0); 1879 for (split = 0; split < BGE_SPLIT; ++split) { 1880 err = bge_alloc_dma_mem(bgep, txbuffsize/BGE_SPLIT, 1881 &bge_data_accattr, DDI_DMA_WRITE | BGE_DMA_MODE, 1882 &srp->buf[array][split]); 1883 if (err != DDI_SUCCESS) { 1884 /* Free the last already allocated OK chunks */ 1885 for (slot = 0; slot <= split; ++slot) 1886 bge_free_dma_mem(&srp->buf[array][slot]); 1887 srp->tx_alloc_fail++; 1888 return (NULL); 1889 } 1890 } 1891 1892 /* 1893 * Chunk tx buffer area 1894 */ 1895 txbuf = srp->txbuf + array*BGE_SEND_BUF_NUM; 1896 for (split = 0; split < BGE_SPLIT; ++split) { 1897 area = srp->buf[array][split]; 1898 for (slot = 0; slot < BGE_SEND_BUF_NUM/BGE_SPLIT; ++slot) { 1899 bge_slice_chunk(&txbuf->buf, &area, 1, 1900 bgep->chipid.snd_buff_size); 1901 txbuf++; 1902 } 1903 } 1904 1905 /* 1906 * Add above buffers to the tx buffer pop queue 1907 */ 1908 txbuf_item = srp->txbuf_head + array*BGE_SEND_BUF_NUM; 1909 txbuf = srp->txbuf + array*BGE_SEND_BUF_NUM; 1910 txbuf_item_last = NULL; 1911 for (slot = 0; slot < BGE_SEND_BUF_NUM; ++slot) { 1912 txbuf_item->item = txbuf; 1913 txbuf_item->next = txbuf_item_last; 1914 txbuf_item_last = txbuf_item; 1915 txbuf++; 1916 txbuf_item++; 1917 } 1918 txbuf_item = srp->txbuf_head + array*BGE_SEND_BUF_NUM; 1919 txbuf_item_rtn = txbuf_item; 1920 txbuf_item++; 1921 txbuf_queue = srp->txbuf_pop_queue; 1922 mutex_enter(txbuf_queue->lock); 1923 txbuf_item->next = txbuf_queue->head; 1924 txbuf_queue->head = txbuf_item_last; 1925 txbuf_queue->count += BGE_SEND_BUF_NUM - 1; 1926 mutex_exit(txbuf_queue->lock); 1927 1928 srp->tx_array++; 1929 srp->tx_buffers += BGE_SEND_BUF_NUM; 1930 srp->tx_buffers_low = srp->tx_buffers / 4; 1931 1932 return (txbuf_item_rtn); 1933 } 1934 1935 /* 1936 * This function allocates all the transmit and receive buffers 1937 * and descriptors, in four chunks. 1938 */ 1939 int 1940 bge_alloc_bufs(bge_t *bgep) 1941 { 1942 dma_area_t area; 1943 size_t rxbuffsize; 1944 size_t txbuffsize; 1945 size_t rxbuffdescsize; 1946 size_t rxdescsize; 1947 size_t txdescsize; 1948 uint32_t ring; 1949 uint32_t rx_rings = bgep->chipid.rx_rings; 1950 uint32_t tx_rings = bgep->chipid.tx_rings; 1951 int split; 1952 int err; 1953 1954 BGE_TRACE(("bge_alloc_bufs($%p)", 1955 (void *)bgep)); 1956 1957 rxbuffsize = BGE_STD_SLOTS_USED*bgep->chipid.std_buf_size; 1958 rxbuffsize += bgep->chipid.jumbo_slots*bgep->chipid.recv_jumbo_size; 1959 rxbuffsize += BGE_MINI_SLOTS_USED*BGE_MINI_BUFF_SIZE; 1960 1961 txbuffsize = BGE_SEND_BUF_NUM*bgep->chipid.snd_buff_size; 1962 txbuffsize *= tx_rings; 1963 1964 rxdescsize = rx_rings*bgep->chipid.recv_slots; 1965 rxdescsize *= sizeof (bge_rbd_t); 1966 1967 rxbuffdescsize = BGE_STD_SLOTS_USED; 1968 rxbuffdescsize += bgep->chipid.jumbo_slots; 1969 rxbuffdescsize += BGE_MINI_SLOTS_USED; 1970 rxbuffdescsize *= sizeof (bge_rbd_t); 1971 1972 txdescsize = tx_rings*BGE_SEND_SLOTS_USED; 1973 txdescsize *= sizeof (bge_sbd_t); 1974 txdescsize += sizeof (bge_statistics_t); 1975 txdescsize += sizeof (bge_status_t); 1976 txdescsize += BGE_STATUS_PADDING; 1977 1978 /* 1979 * Allocate memory & handles for RX buffers 1980 */ 1981 ASSERT((rxbuffsize % BGE_SPLIT) == 0); 1982 for (split = 0; split < BGE_SPLIT; ++split) { 1983 err = bge_alloc_dma_mem(bgep, rxbuffsize/BGE_SPLIT, 1984 &bge_data_accattr, DDI_DMA_READ | BGE_DMA_MODE, 1985 &bgep->rx_buff[split]); 1986 if (err != DDI_SUCCESS) 1987 return (DDI_FAILURE); 1988 } 1989 1990 /* 1991 * Allocate memory & handles for TX buffers 1992 */ 1993 ASSERT((txbuffsize % BGE_SPLIT) == 0); 1994 for (split = 0; split < BGE_SPLIT; ++split) { 1995 err = bge_alloc_dma_mem(bgep, txbuffsize/BGE_SPLIT, 1996 &bge_data_accattr, DDI_DMA_WRITE | BGE_DMA_MODE, 1997 &bgep->tx_buff[split]); 1998 if (err != DDI_SUCCESS) 1999 return (DDI_FAILURE); 2000 } 2001 2002 /* 2003 * Allocate memory & handles for receive return rings 2004 */ 2005 ASSERT((rxdescsize % rx_rings) == 0); 2006 for (split = 0; split < rx_rings; ++split) { 2007 err = bge_alloc_dma_mem(bgep, rxdescsize/rx_rings, 2008 &bge_desc_accattr, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2009 &bgep->rx_desc[split]); 2010 if (err != DDI_SUCCESS) 2011 return (DDI_FAILURE); 2012 } 2013 2014 /* 2015 * Allocate memory & handles for buffer (producer) descriptor rings 2016 */ 2017 err = bge_alloc_dma_mem(bgep, rxbuffdescsize, &bge_desc_accattr, 2018 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &bgep->rx_desc[split]); 2019 if (err != DDI_SUCCESS) 2020 return (DDI_FAILURE); 2021 2022 /* 2023 * Allocate memory & handles for TX descriptor rings, 2024 * status block, and statistics area 2025 */ 2026 err = bge_alloc_dma_mem(bgep, txdescsize, &bge_desc_accattr, 2027 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, &bgep->tx_desc); 2028 if (err != DDI_SUCCESS) 2029 return (DDI_FAILURE); 2030 2031 /* 2032 * Now carve up each of the allocated areas ... 2033 */ 2034 for (split = 0; split < BGE_SPLIT; ++split) { 2035 area = bgep->rx_buff[split]; 2036 bge_slice_chunk(&bgep->buff[BGE_STD_BUFF_RING].buf[split], 2037 &area, BGE_STD_SLOTS_USED/BGE_SPLIT, 2038 bgep->chipid.std_buf_size); 2039 bge_slice_chunk(&bgep->buff[BGE_JUMBO_BUFF_RING].buf[split], 2040 &area, bgep->chipid.jumbo_slots/BGE_SPLIT, 2041 bgep->chipid.recv_jumbo_size); 2042 bge_slice_chunk(&bgep->buff[BGE_MINI_BUFF_RING].buf[split], 2043 &area, BGE_MINI_SLOTS_USED/BGE_SPLIT, 2044 BGE_MINI_BUFF_SIZE); 2045 ASSERT(area.alength >= 0); 2046 } 2047 2048 for (split = 0; split < BGE_SPLIT; ++split) { 2049 area = bgep->tx_buff[split]; 2050 for (ring = 0; ring < tx_rings; ++ring) 2051 bge_slice_chunk(&bgep->send[ring].buf[0][split], 2052 &area, BGE_SEND_BUF_NUM/BGE_SPLIT, 2053 bgep->chipid.snd_buff_size); 2054 for (; ring < BGE_SEND_RINGS_MAX; ++ring) 2055 bge_slice_chunk(&bgep->send[ring].buf[0][split], 2056 &area, 0, bgep->chipid.snd_buff_size); 2057 ASSERT(area.alength >= 0); 2058 } 2059 2060 for (ring = 0; ring < rx_rings; ++ring) 2061 bge_slice_chunk(&bgep->recv[ring].desc, &bgep->rx_desc[ring], 2062 bgep->chipid.recv_slots, sizeof (bge_rbd_t)); 2063 2064 area = bgep->rx_desc[rx_rings]; 2065 for (; ring < BGE_RECV_RINGS_MAX; ++ring) 2066 bge_slice_chunk(&bgep->recv[ring].desc, &area, 2067 0, sizeof (bge_rbd_t)); 2068 bge_slice_chunk(&bgep->buff[BGE_STD_BUFF_RING].desc, &area, 2069 BGE_STD_SLOTS_USED, sizeof (bge_rbd_t)); 2070 bge_slice_chunk(&bgep->buff[BGE_JUMBO_BUFF_RING].desc, &area, 2071 bgep->chipid.jumbo_slots, sizeof (bge_rbd_t)); 2072 bge_slice_chunk(&bgep->buff[BGE_MINI_BUFF_RING].desc, &area, 2073 BGE_MINI_SLOTS_USED, sizeof (bge_rbd_t)); 2074 ASSERT(area.alength == 0); 2075 2076 area = bgep->tx_desc; 2077 for (ring = 0; ring < tx_rings; ++ring) 2078 bge_slice_chunk(&bgep->send[ring].desc, &area, 2079 BGE_SEND_SLOTS_USED, sizeof (bge_sbd_t)); 2080 for (; ring < BGE_SEND_RINGS_MAX; ++ring) 2081 bge_slice_chunk(&bgep->send[ring].desc, &area, 2082 0, sizeof (bge_sbd_t)); 2083 bge_slice_chunk(&bgep->statistics, &area, 1, sizeof (bge_statistics_t)); 2084 bge_slice_chunk(&bgep->status_block, &area, 1, sizeof (bge_status_t)); 2085 ASSERT(area.alength == BGE_STATUS_PADDING); 2086 DMA_ZERO(bgep->status_block); 2087 2088 return (DDI_SUCCESS); 2089 } 2090 2091 /* 2092 * This routine frees the transmit and receive buffers and descriptors. 2093 * Make sure the chip is stopped before calling it! 2094 */ 2095 void 2096 bge_free_bufs(bge_t *bgep) 2097 { 2098 int split; 2099 2100 BGE_TRACE(("bge_free_bufs($%p)", 2101 (void *)bgep)); 2102 2103 bge_free_dma_mem(&bgep->tx_desc); 2104 for (split = 0; split < BGE_RECV_RINGS_SPLIT; ++split) 2105 bge_free_dma_mem(&bgep->rx_desc[split]); 2106 for (split = 0; split < BGE_SPLIT; ++split) 2107 bge_free_dma_mem(&bgep->tx_buff[split]); 2108 for (split = 0; split < BGE_SPLIT; ++split) 2109 bge_free_dma_mem(&bgep->rx_buff[split]); 2110 } 2111 2112 /* 2113 * Determine (initial) MAC address ("BIA") to use for this interface 2114 */ 2115 2116 static void 2117 bge_find_mac_address(bge_t *bgep, chip_id_t *cidp) 2118 { 2119 struct ether_addr sysaddr; 2120 char propbuf[8]; /* "true" or "false", plus NUL */ 2121 uchar_t *bytes; 2122 int *ints; 2123 uint_t nelts; 2124 int err; 2125 2126 BGE_TRACE(("bge_find_mac_address($%p)", 2127 (void *)bgep)); 2128 2129 BGE_DEBUG(("bge_find_mac_address: hw_mac_addr %012llx, => %s (%sset)", 2130 cidp->hw_mac_addr, 2131 ether_sprintf((void *)cidp->vendor_addr.addr), 2132 cidp->vendor_addr.set ? "" : "not ")); 2133 2134 /* 2135 * The "vendor's factory-set address" may already have 2136 * been extracted from the chip, but if the property 2137 * "local-mac-address" is set we use that instead. It 2138 * will normally be set by OBP, but it could also be 2139 * specified in a .conf file(!) 2140 * 2141 * There doesn't seem to be a way to define byte-array 2142 * properties in a .conf, so we check whether it looks 2143 * like an array of 6 ints instead. 2144 * 2145 * Then, we check whether it looks like an array of 6 2146 * bytes (which it should, if OBP set it). If we can't 2147 * make sense of it either way, we'll ignore it. 2148 */ 2149 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2150 DDI_PROP_DONTPASS, localmac_propname, &ints, &nelts); 2151 if (err == DDI_PROP_SUCCESS) { 2152 if (nelts == ETHERADDRL) { 2153 while (nelts--) 2154 cidp->vendor_addr.addr[nelts] = ints[nelts]; 2155 cidp->vendor_addr.set = B_TRUE; 2156 } 2157 ddi_prop_free(ints); 2158 } 2159 2160 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, bgep->devinfo, 2161 DDI_PROP_DONTPASS, localmac_propname, &bytes, &nelts); 2162 if (err == DDI_PROP_SUCCESS) { 2163 if (nelts == ETHERADDRL) { 2164 while (nelts--) 2165 cidp->vendor_addr.addr[nelts] = bytes[nelts]; 2166 cidp->vendor_addr.set = B_TRUE; 2167 } 2168 ddi_prop_free(bytes); 2169 } 2170 2171 BGE_DEBUG(("bge_find_mac_address: +local %s (%sset)", 2172 ether_sprintf((void *)cidp->vendor_addr.addr), 2173 cidp->vendor_addr.set ? "" : "not ")); 2174 2175 /* 2176 * Look up the OBP property "local-mac-address?". Note that even 2177 * though its value is a string (which should be "true" or "false"), 2178 * it can't be decoded by ddi_prop_lookup_string(9F). So, we zero 2179 * the buffer first and then fetch the property as an untyped array; 2180 * this may or may not include a final NUL, but since there will 2181 * always be one left at the end of the buffer we can now treat it 2182 * as a string anyway. 2183 */ 2184 nelts = sizeof (propbuf); 2185 bzero(propbuf, nelts--); 2186 err = ddi_getlongprop_buf(DDI_DEV_T_ANY, bgep->devinfo, 2187 DDI_PROP_CANSLEEP, localmac_boolname, propbuf, (int *)&nelts); 2188 2189 /* 2190 * Now, if the address still isn't set from the hardware (SEEPROM) 2191 * or the OBP or .conf property, OR if the user has foolishly set 2192 * 'local-mac-address? = false', use "the system address" instead 2193 * (but only if it's non-null i.e. has been set from the IDPROM). 2194 */ 2195 if (cidp->vendor_addr.set == B_FALSE || strcmp(propbuf, "false") == 0) 2196 if (localetheraddr(NULL, &sysaddr) != 0) { 2197 ethaddr_copy(&sysaddr, cidp->vendor_addr.addr); 2198 cidp->vendor_addr.set = B_TRUE; 2199 } 2200 2201 BGE_DEBUG(("bge_find_mac_address: +system %s (%sset)", 2202 ether_sprintf((void *)cidp->vendor_addr.addr), 2203 cidp->vendor_addr.set ? "" : "not ")); 2204 2205 /* 2206 * Finally(!), if there's a valid "mac-address" property (created 2207 * if we netbooted from this interface), we must use this instead 2208 * of any of the above to ensure that the NFS/install server doesn't 2209 * get confused by the address changing as Solaris takes over! 2210 */ 2211 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, bgep->devinfo, 2212 DDI_PROP_DONTPASS, macaddr_propname, &bytes, &nelts); 2213 if (err == DDI_PROP_SUCCESS) { 2214 if (nelts == ETHERADDRL) { 2215 while (nelts--) 2216 cidp->vendor_addr.addr[nelts] = bytes[nelts]; 2217 cidp->vendor_addr.set = B_TRUE; 2218 } 2219 ddi_prop_free(bytes); 2220 } 2221 2222 BGE_DEBUG(("bge_find_mac_address: =final %s (%sset)", 2223 ether_sprintf((void *)cidp->vendor_addr.addr), 2224 cidp->vendor_addr.set ? "" : "not ")); 2225 } 2226 2227 2228 /*ARGSUSED*/ 2229 int 2230 bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle) 2231 { 2232 ddi_fm_error_t de; 2233 2234 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 2235 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 2236 return (de.fme_status); 2237 } 2238 2239 /*ARGSUSED*/ 2240 int 2241 bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle) 2242 { 2243 ddi_fm_error_t de; 2244 2245 ASSERT(bgep->progress & PROGRESS_BUFS); 2246 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 2247 return (de.fme_status); 2248 } 2249 2250 /* 2251 * The IO fault service error handling callback function 2252 */ 2253 /*ARGSUSED*/ 2254 static int 2255 bge_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 2256 { 2257 /* 2258 * as the driver can always deal with an error in any dma or 2259 * access handle, we can just return the fme_status value. 2260 */ 2261 pci_ereport_post(dip, err, NULL); 2262 return (err->fme_status); 2263 } 2264 2265 static void 2266 bge_fm_init(bge_t *bgep) 2267 { 2268 ddi_iblock_cookie_t iblk; 2269 2270 /* Only register with IO Fault Services if we have some capability */ 2271 if (bgep->fm_capabilities) { 2272 bge_reg_accattr.devacc_attr_access = DDI_FLAGERR_ACC; 2273 bge_desc_accattr.devacc_attr_access = DDI_FLAGERR_ACC; 2274 dma_attr.dma_attr_flags = DDI_DMA_FLAGERR; 2275 2276 /* Register capabilities with IO Fault Services */ 2277 ddi_fm_init(bgep->devinfo, &bgep->fm_capabilities, &iblk); 2278 2279 /* 2280 * Initialize pci ereport capabilities if ereport capable 2281 */ 2282 if (DDI_FM_EREPORT_CAP(bgep->fm_capabilities) || 2283 DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2284 pci_ereport_setup(bgep->devinfo); 2285 2286 /* 2287 * Register error callback if error callback capable 2288 */ 2289 if (DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2290 ddi_fm_handler_register(bgep->devinfo, 2291 bge_fm_error_cb, (void*) bgep); 2292 } else { 2293 /* 2294 * These fields have to be cleared of FMA if there are no 2295 * FMA capabilities at runtime. 2296 */ 2297 bge_reg_accattr.devacc_attr_access = DDI_DEFAULT_ACC; 2298 bge_desc_accattr.devacc_attr_access = DDI_DEFAULT_ACC; 2299 dma_attr.dma_attr_flags = 0; 2300 } 2301 } 2302 2303 static void 2304 bge_fm_fini(bge_t *bgep) 2305 { 2306 /* Only unregister FMA capabilities if we registered some */ 2307 if (bgep->fm_capabilities) { 2308 2309 /* 2310 * Release any resources allocated by pci_ereport_setup() 2311 */ 2312 if (DDI_FM_EREPORT_CAP(bgep->fm_capabilities) || 2313 DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2314 pci_ereport_teardown(bgep->devinfo); 2315 2316 /* 2317 * Un-register error callback if error callback capable 2318 */ 2319 if (DDI_FM_ERRCB_CAP(bgep->fm_capabilities)) 2320 ddi_fm_handler_unregister(bgep->devinfo); 2321 2322 /* Unregister from IO Fault Services */ 2323 ddi_fm_fini(bgep->devinfo); 2324 } 2325 } 2326 2327 static void 2328 #ifdef BGE_IPMI_ASF 2329 bge_unattach(bge_t *bgep, uint_t asf_mode) 2330 #else 2331 bge_unattach(bge_t *bgep) 2332 #endif 2333 { 2334 BGE_TRACE(("bge_unattach($%p)", 2335 (void *)bgep)); 2336 2337 /* 2338 * Flag that no more activity may be initiated 2339 */ 2340 bgep->progress &= ~PROGRESS_READY; 2341 2342 /* 2343 * Quiesce the PHY and MAC (leave it reset but still powered). 2344 * Clean up and free all BGE data structures 2345 */ 2346 if (bgep->cyclic_id) { 2347 mutex_enter(&cpu_lock); 2348 cyclic_remove(bgep->cyclic_id); 2349 mutex_exit(&cpu_lock); 2350 } 2351 if (bgep->progress & PROGRESS_KSTATS) 2352 bge_fini_kstats(bgep); 2353 if (bgep->progress & PROGRESS_NDD) 2354 bge_nd_cleanup(bgep); 2355 if (bgep->progress & PROGRESS_PHY) 2356 bge_phys_reset(bgep); 2357 if (bgep->progress & PROGRESS_HWINT) { 2358 mutex_enter(bgep->genlock); 2359 #ifdef BGE_IPMI_ASF 2360 if (bge_chip_reset(bgep, B_FALSE, asf_mode) != DDI_SUCCESS) 2361 #else 2362 if (bge_chip_reset(bgep, B_FALSE) != DDI_SUCCESS) 2363 #endif 2364 ddi_fm_service_impact(bgep->devinfo, 2365 DDI_SERVICE_UNAFFECTED); 2366 #ifdef BGE_IPMI_ASF 2367 if (bgep->asf_enabled) { 2368 /* 2369 * This register has been overlaid. We restore its 2370 * initial value here. 2371 */ 2372 bge_nic_put32(bgep, BGE_NIC_DATA_SIG_ADDR, 2373 BGE_NIC_DATA_SIG); 2374 } 2375 #endif 2376 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 2377 ddi_fm_service_impact(bgep->devinfo, 2378 DDI_SERVICE_UNAFFECTED); 2379 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2380 ddi_fm_service_impact(bgep->devinfo, 2381 DDI_SERVICE_UNAFFECTED); 2382 mutex_exit(bgep->genlock); 2383 } 2384 if (bgep->progress & PROGRESS_INTR) { 2385 bge_intr_disable(bgep); 2386 bge_fini_rings(bgep); 2387 } 2388 if (bgep->progress & PROGRESS_HWINT) { 2389 bge_rem_intrs(bgep); 2390 rw_destroy(bgep->errlock); 2391 mutex_destroy(bgep->softintrlock); 2392 mutex_destroy(bgep->genlock); 2393 } 2394 if (bgep->progress & PROGRESS_FACTOTUM) 2395 ddi_remove_softintr(bgep->factotum_id); 2396 if (bgep->progress & PROGRESS_RESCHED) 2397 ddi_remove_softintr(bgep->drain_id); 2398 if (bgep->progress & PROGRESS_BUFS) 2399 bge_free_bufs(bgep); 2400 if (bgep->progress & PROGRESS_REGS) 2401 ddi_regs_map_free(&bgep->io_handle); 2402 if (bgep->progress & PROGRESS_CFG) 2403 pci_config_teardown(&bgep->cfg_handle); 2404 2405 bge_fm_fini(bgep); 2406 2407 ddi_remove_minor_node(bgep->devinfo, NULL); 2408 kmem_free(bgep->pstats, sizeof (bge_statistics_reg_t)); 2409 kmem_free(bgep->nd_params, PARAM_COUNT * sizeof (nd_param_t)); 2410 kmem_free(bgep, sizeof (*bgep)); 2411 } 2412 2413 static int 2414 bge_resume(dev_info_t *devinfo) 2415 { 2416 bge_t *bgep; /* Our private data */ 2417 chip_id_t *cidp; 2418 chip_id_t chipid; 2419 2420 bgep = ddi_get_driver_private(devinfo); 2421 if (bgep == NULL) 2422 return (DDI_FAILURE); 2423 2424 /* 2425 * Refuse to resume if the data structures aren't consistent 2426 */ 2427 if (bgep->devinfo != devinfo) 2428 return (DDI_FAILURE); 2429 2430 #ifdef BGE_IPMI_ASF 2431 /* 2432 * Power management hasn't been supported in BGE now. If you 2433 * want to implement it, please add the ASF/IPMI related 2434 * code here. 2435 */ 2436 2437 #endif 2438 2439 /* 2440 * Read chip ID & set up config space command register(s) 2441 * Refuse to resume if the chip has changed its identity! 2442 */ 2443 cidp = &bgep->chipid; 2444 mutex_enter(bgep->genlock); 2445 bge_chip_cfg_init(bgep, &chipid, B_FALSE); 2446 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2447 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2448 mutex_exit(bgep->genlock); 2449 return (DDI_FAILURE); 2450 } 2451 mutex_exit(bgep->genlock); 2452 if (chipid.vendor != cidp->vendor) 2453 return (DDI_FAILURE); 2454 if (chipid.device != cidp->device) 2455 return (DDI_FAILURE); 2456 if (chipid.revision != cidp->revision) 2457 return (DDI_FAILURE); 2458 if (chipid.asic_rev != cidp->asic_rev) 2459 return (DDI_FAILURE); 2460 2461 /* 2462 * All OK, reinitialise h/w & kick off GLD scheduling 2463 */ 2464 mutex_enter(bgep->genlock); 2465 if (bge_restart(bgep, B_TRUE) != DDI_SUCCESS) { 2466 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 2467 (void) bge_check_acc_handle(bgep, bgep->io_handle); 2468 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2469 mutex_exit(bgep->genlock); 2470 return (DDI_FAILURE); 2471 } 2472 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2473 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2474 mutex_exit(bgep->genlock); 2475 return (DDI_FAILURE); 2476 } 2477 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 2478 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2479 mutex_exit(bgep->genlock); 2480 return (DDI_FAILURE); 2481 } 2482 mutex_exit(bgep->genlock); 2483 return (DDI_SUCCESS); 2484 } 2485 2486 /* 2487 * attach(9E) -- Attach a device to the system 2488 * 2489 * Called once for each board successfully probed. 2490 */ 2491 static int 2492 bge_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2493 { 2494 bge_t *bgep; /* Our private data */ 2495 mac_register_t *macp; 2496 chip_id_t *cidp; 2497 cyc_handler_t cychand; 2498 cyc_time_t cyctime; 2499 caddr_t regs; 2500 int instance; 2501 int err; 2502 int intr_types; 2503 #ifdef BGE_IPMI_ASF 2504 uint32_t mhcrValue; 2505 #endif 2506 2507 instance = ddi_get_instance(devinfo); 2508 2509 BGE_GTRACE(("bge_attach($%p, %d) instance %d", 2510 (void *)devinfo, cmd, instance)); 2511 BGE_BRKPT(NULL, "bge_attach"); 2512 2513 switch (cmd) { 2514 default: 2515 return (DDI_FAILURE); 2516 2517 case DDI_RESUME: 2518 return (bge_resume(devinfo)); 2519 2520 case DDI_ATTACH: 2521 break; 2522 } 2523 2524 bgep = kmem_zalloc(sizeof (*bgep), KM_SLEEP); 2525 bgep->pstats = kmem_zalloc(sizeof (bge_statistics_reg_t), KM_SLEEP); 2526 bgep->nd_params = 2527 kmem_zalloc(PARAM_COUNT * sizeof (nd_param_t), KM_SLEEP); 2528 ddi_set_driver_private(devinfo, bgep); 2529 bgep->bge_guard = BGE_GUARD; 2530 bgep->devinfo = devinfo; 2531 2532 /* 2533 * Initialize more fields in BGE private data 2534 */ 2535 bgep->debug = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2536 DDI_PROP_DONTPASS, debug_propname, bge_debug); 2537 (void) snprintf(bgep->ifname, sizeof (bgep->ifname), "%s%d", 2538 BGE_DRIVER_NAME, instance); 2539 2540 /* 2541 * Initialize for fma support 2542 */ 2543 bgep->fm_capabilities = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2544 DDI_PROP_DONTPASS, fm_cap, 2545 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 2546 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 2547 BGE_DEBUG(("bgep->fm_capabilities = %d", bgep->fm_capabilities)); 2548 bge_fm_init(bgep); 2549 2550 /* 2551 * Look up the IOMMU's page size for DVMA mappings (must be 2552 * a power of 2) and convert to a mask. This can be used to 2553 * determine whether a message buffer crosses a page boundary. 2554 * Note: in 2s complement binary notation, if X is a power of 2555 * 2, then -X has the representation "11...1100...00". 2556 */ 2557 bgep->pagemask = dvma_pagesize(devinfo); 2558 ASSERT(ddi_ffs(bgep->pagemask) == ddi_fls(bgep->pagemask)); 2559 bgep->pagemask = -bgep->pagemask; 2560 2561 /* 2562 * Map config space registers 2563 * Read chip ID & set up config space command register(s) 2564 * 2565 * Note: this leaves the chip accessible by Memory Space 2566 * accesses, but with interrupts and Bus Mastering off. 2567 * This should ensure that nothing untoward will happen 2568 * if it has been left active by the (net-)bootloader. 2569 * We'll re-enable Bus Mastering once we've reset the chip, 2570 * and allow interrupts only when everything else is set up. 2571 */ 2572 err = pci_config_setup(devinfo, &bgep->cfg_handle); 2573 #ifdef BGE_IPMI_ASF 2574 mhcrValue = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MHCR); 2575 if (mhcrValue & MHCR_ENABLE_ENDIAN_WORD_SWAP) { 2576 bgep->asf_wordswapped = B_TRUE; 2577 } else { 2578 bgep->asf_wordswapped = B_FALSE; 2579 } 2580 bge_asf_get_config(bgep); 2581 #endif 2582 if (err != DDI_SUCCESS) { 2583 bge_problem(bgep, "pci_config_setup() failed"); 2584 goto attach_fail; 2585 } 2586 bgep->progress |= PROGRESS_CFG; 2587 cidp = &bgep->chipid; 2588 bzero(cidp, sizeof (*cidp)); 2589 bge_chip_cfg_init(bgep, cidp, B_FALSE); 2590 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2591 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2592 goto attach_fail; 2593 } 2594 2595 #ifdef BGE_IPMI_ASF 2596 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 2597 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2598 bgep->asf_newhandshake = B_TRUE; 2599 } else { 2600 bgep->asf_newhandshake = B_FALSE; 2601 } 2602 #endif 2603 2604 /* 2605 * Update those parts of the chip ID derived from volatile 2606 * registers with the values seen by OBP (in case the chip 2607 * has been reset externally and therefore lost them). 2608 */ 2609 cidp->subven = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2610 DDI_PROP_DONTPASS, subven_propname, cidp->subven); 2611 cidp->subdev = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2612 DDI_PROP_DONTPASS, subdev_propname, cidp->subdev); 2613 cidp->clsize = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2614 DDI_PROP_DONTPASS, clsize_propname, cidp->clsize); 2615 cidp->latency = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2616 DDI_PROP_DONTPASS, latency_propname, cidp->latency); 2617 cidp->rx_rings = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2618 DDI_PROP_DONTPASS, rxrings_propname, cidp->rx_rings); 2619 cidp->tx_rings = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2620 DDI_PROP_DONTPASS, txrings_propname, cidp->tx_rings); 2621 2622 if (bge_jumbo_enable == B_TRUE) { 2623 cidp->default_mtu = ddi_prop_get_int(DDI_DEV_T_ANY, devinfo, 2624 DDI_PROP_DONTPASS, default_mtu, BGE_DEFAULT_MTU); 2625 if ((cidp->default_mtu < BGE_DEFAULT_MTU)|| 2626 (cidp->default_mtu > BGE_MAXIMUM_MTU)) { 2627 cidp->default_mtu = BGE_DEFAULT_MTU; 2628 } 2629 } 2630 /* 2631 * Map operating registers 2632 */ 2633 err = ddi_regs_map_setup(devinfo, BGE_PCI_OPREGS_RNUMBER, 2634 ®s, 0, 0, &bge_reg_accattr, &bgep->io_handle); 2635 if (err != DDI_SUCCESS) { 2636 bge_problem(bgep, "ddi_regs_map_setup() failed"); 2637 goto attach_fail; 2638 } 2639 bgep->io_regs = regs; 2640 bgep->progress |= PROGRESS_REGS; 2641 2642 /* 2643 * Characterise the device, so we know its requirements. 2644 * Then allocate the appropriate TX and RX descriptors & buffers. 2645 */ 2646 if (bge_chip_id_init(bgep) == EIO) { 2647 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2648 goto attach_fail; 2649 } 2650 err = bge_alloc_bufs(bgep); 2651 if (err != DDI_SUCCESS) { 2652 bge_problem(bgep, "DMA buffer allocation failed"); 2653 goto attach_fail; 2654 } 2655 bgep->progress |= PROGRESS_BUFS; 2656 2657 /* 2658 * Add the softint handlers: 2659 * 2660 * Both of these handlers are used to avoid restrictions on the 2661 * context and/or mutexes required for some operations. In 2662 * particular, the hardware interrupt handler and its subfunctions 2663 * can detect a number of conditions that we don't want to handle 2664 * in that context or with that set of mutexes held. So, these 2665 * softints are triggered instead: 2666 * 2667 * the <resched> softint is triggered if we have previously 2668 * had to refuse to send a packet because of resource shortage 2669 * (we've run out of transmit buffers), but the send completion 2670 * interrupt handler has now detected that more buffers have 2671 * become available. 2672 * 2673 * the <factotum> is triggered if the h/w interrupt handler 2674 * sees the <link state changed> or <error> bits in the status 2675 * block. It's also triggered periodically to poll the link 2676 * state, just in case we aren't getting link status change 2677 * interrupts ... 2678 */ 2679 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &bgep->drain_id, 2680 NULL, NULL, bge_send_drain, (caddr_t)bgep); 2681 if (err != DDI_SUCCESS) { 2682 bge_problem(bgep, "ddi_add_softintr() failed"); 2683 goto attach_fail; 2684 } 2685 bgep->progress |= PROGRESS_RESCHED; 2686 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, &bgep->factotum_id, 2687 NULL, NULL, bge_chip_factotum, (caddr_t)bgep); 2688 if (err != DDI_SUCCESS) { 2689 bge_problem(bgep, "ddi_add_softintr() failed"); 2690 goto attach_fail; 2691 } 2692 bgep->progress |= PROGRESS_FACTOTUM; 2693 2694 /* Get supported interrupt types */ 2695 if (ddi_intr_get_supported_types(devinfo, &intr_types) != DDI_SUCCESS) { 2696 bge_error(bgep, "ddi_intr_get_supported_types failed\n"); 2697 2698 goto attach_fail; 2699 } 2700 2701 BGE_DEBUG(("%s: ddi_intr_get_supported_types() returned: %x", 2702 bgep->ifname, intr_types)); 2703 2704 if ((intr_types & DDI_INTR_TYPE_MSI) && bgep->chipid.msi_enabled) { 2705 if (bge_add_intrs(bgep, DDI_INTR_TYPE_MSI) != DDI_SUCCESS) { 2706 bge_error(bgep, "MSI registration failed, " 2707 "trying FIXED interrupt type\n"); 2708 } else { 2709 BGE_DEBUG(("%s: Using MSI interrupt type", 2710 bgep->ifname)); 2711 bgep->intr_type = DDI_INTR_TYPE_MSI; 2712 bgep->progress |= PROGRESS_HWINT; 2713 } 2714 } 2715 2716 if (!(bgep->progress & PROGRESS_HWINT) && 2717 (intr_types & DDI_INTR_TYPE_FIXED)) { 2718 if (bge_add_intrs(bgep, DDI_INTR_TYPE_FIXED) != DDI_SUCCESS) { 2719 bge_error(bgep, "FIXED interrupt " 2720 "registration failed\n"); 2721 goto attach_fail; 2722 } 2723 2724 BGE_DEBUG(("%s: Using FIXED interrupt type", bgep->ifname)); 2725 2726 bgep->intr_type = DDI_INTR_TYPE_FIXED; 2727 bgep->progress |= PROGRESS_HWINT; 2728 } 2729 2730 if (!(bgep->progress & PROGRESS_HWINT)) { 2731 bge_error(bgep, "No interrupts registered\n"); 2732 goto attach_fail; 2733 } 2734 2735 /* 2736 * Note that interrupts are not enabled yet as 2737 * mutex locks are not initialized. Initialize mutex locks. 2738 */ 2739 mutex_init(bgep->genlock, NULL, MUTEX_DRIVER, 2740 DDI_INTR_PRI(bgep->intr_pri)); 2741 mutex_init(bgep->softintrlock, NULL, MUTEX_DRIVER, 2742 DDI_INTR_PRI(bgep->intr_pri)); 2743 rw_init(bgep->errlock, NULL, RW_DRIVER, 2744 DDI_INTR_PRI(bgep->intr_pri)); 2745 2746 /* 2747 * Initialize rings. 2748 */ 2749 bge_init_rings(bgep); 2750 2751 /* 2752 * Now that mutex locks are initialized, enable interrupts. 2753 */ 2754 bge_intr_enable(bgep); 2755 bgep->progress |= PROGRESS_INTR; 2756 2757 /* 2758 * Initialise link state variables 2759 * Stop, reset & reinitialise the chip. 2760 * Initialise the (internal) PHY. 2761 */ 2762 bgep->link_state = LINK_STATE_UNKNOWN; 2763 bgep->link_up_msg = bgep->link_down_msg = " (initialized)"; 2764 2765 mutex_enter(bgep->genlock); 2766 2767 /* 2768 * Reset chip & rings to initial state; also reset address 2769 * filtering, promiscuity, loopback mode. 2770 */ 2771 #ifdef BGE_IPMI_ASF 2772 if (bge_reset(bgep, ASF_MODE_SHUTDOWN) != DDI_SUCCESS) { 2773 #else 2774 if (bge_reset(bgep) != DDI_SUCCESS) { 2775 #endif 2776 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 2777 (void) bge_check_acc_handle(bgep, bgep->io_handle); 2778 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2779 mutex_exit(bgep->genlock); 2780 goto attach_fail; 2781 } 2782 2783 #ifdef BGE_IPMI_ASF 2784 if (bgep->asf_enabled) { 2785 bgep->asf_status = ASF_STAT_RUN_INIT; 2786 } 2787 #endif 2788 2789 bzero(bgep->mcast_hash, sizeof (bgep->mcast_hash)); 2790 bzero(bgep->mcast_refs, sizeof (bgep->mcast_refs)); 2791 bgep->promisc = B_FALSE; 2792 bgep->param_loop_mode = BGE_LOOP_NONE; 2793 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) { 2794 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2795 mutex_exit(bgep->genlock); 2796 goto attach_fail; 2797 } 2798 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 2799 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2800 mutex_exit(bgep->genlock); 2801 goto attach_fail; 2802 } 2803 2804 mutex_exit(bgep->genlock); 2805 2806 if (bge_phys_init(bgep) == EIO) { 2807 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2808 goto attach_fail; 2809 } 2810 bgep->progress |= PROGRESS_PHY; 2811 2812 /* 2813 * Register NDD-tweakable parameters 2814 */ 2815 if (bge_nd_init(bgep)) { 2816 bge_problem(bgep, "bge_nd_init() failed"); 2817 goto attach_fail; 2818 } 2819 bgep->progress |= PROGRESS_NDD; 2820 2821 /* 2822 * Create & initialise named kstats 2823 */ 2824 bge_init_kstats(bgep, instance); 2825 bgep->progress |= PROGRESS_KSTATS; 2826 2827 /* 2828 * Determine whether to override the chip's own MAC address 2829 */ 2830 bge_find_mac_address(bgep, cidp); 2831 ethaddr_copy(cidp->vendor_addr.addr, bgep->curr_addr[0].addr); 2832 bgep->curr_addr[0].set = B_TRUE; 2833 2834 bgep->unicst_addr_total = MAC_ADDRESS_REGS_MAX; 2835 /* 2836 * Address available is one less than MAX 2837 * as primary address is not advertised 2838 * as a multiple MAC address. 2839 */ 2840 bgep->unicst_addr_avail = MAC_ADDRESS_REGS_MAX - 1; 2841 2842 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 2843 goto attach_fail; 2844 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 2845 macp->m_driver = bgep; 2846 macp->m_dip = devinfo; 2847 macp->m_src_addr = bgep->curr_addr[0].addr; 2848 macp->m_callbacks = &bge_m_callbacks; 2849 macp->m_min_sdu = 0; 2850 macp->m_max_sdu = cidp->ethmax_size - sizeof (struct ether_header); 2851 /* 2852 * Finally, we're ready to register ourselves with the MAC layer 2853 * interface; if this succeeds, we're all ready to start() 2854 */ 2855 err = mac_register(macp, &bgep->mh); 2856 mac_free(macp); 2857 if (err != 0) 2858 goto attach_fail; 2859 2860 cychand.cyh_func = bge_chip_cyclic; 2861 cychand.cyh_arg = bgep; 2862 cychand.cyh_level = CY_LOCK_LEVEL; 2863 cyctime.cyt_when = 0; 2864 cyctime.cyt_interval = BGE_CYCLIC_PERIOD; 2865 mutex_enter(&cpu_lock); 2866 bgep->cyclic_id = cyclic_add(&cychand, &cyctime); 2867 mutex_exit(&cpu_lock); 2868 2869 bgep->progress |= PROGRESS_READY; 2870 ASSERT(bgep->bge_guard == BGE_GUARD); 2871 return (DDI_SUCCESS); 2872 2873 attach_fail: 2874 #ifdef BGE_IPMI_ASF 2875 bge_unattach(bgep, ASF_MODE_SHUTDOWN); 2876 #else 2877 bge_unattach(bgep); 2878 #endif 2879 return (DDI_FAILURE); 2880 } 2881 2882 /* 2883 * bge_suspend() -- suspend transmit/receive for powerdown 2884 */ 2885 static int 2886 bge_suspend(bge_t *bgep) 2887 { 2888 /* 2889 * Stop processing and idle (powerdown) the PHY ... 2890 */ 2891 mutex_enter(bgep->genlock); 2892 #ifdef BGE_IPMI_ASF 2893 /* 2894 * Power management hasn't been supported in BGE now. If you 2895 * want to implement it, please add the ASF/IPMI related 2896 * code here. 2897 */ 2898 #endif 2899 bge_stop(bgep); 2900 if (bge_phys_idle(bgep) != DDI_SUCCESS) { 2901 (void) bge_check_acc_handle(bgep, bgep->io_handle); 2902 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 2903 mutex_exit(bgep->genlock); 2904 return (DDI_FAILURE); 2905 } 2906 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) { 2907 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 2908 mutex_exit(bgep->genlock); 2909 return (DDI_FAILURE); 2910 } 2911 mutex_exit(bgep->genlock); 2912 2913 return (DDI_SUCCESS); 2914 } 2915 2916 /* 2917 * detach(9E) -- Detach a device from the system 2918 */ 2919 static int 2920 bge_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2921 { 2922 bge_t *bgep; 2923 #ifdef BGE_IPMI_ASF 2924 uint_t asf_mode; 2925 asf_mode = ASF_MODE_NONE; 2926 #endif 2927 2928 BGE_GTRACE(("bge_detach($%p, %d)", (void *)devinfo, cmd)); 2929 2930 bgep = ddi_get_driver_private(devinfo); 2931 2932 switch (cmd) { 2933 default: 2934 return (DDI_FAILURE); 2935 2936 case DDI_SUSPEND: 2937 return (bge_suspend(bgep)); 2938 2939 case DDI_DETACH: 2940 break; 2941 } 2942 2943 #ifdef BGE_IPMI_ASF 2944 mutex_enter(bgep->genlock); 2945 if (bgep->asf_enabled && ((bgep->asf_status == ASF_STAT_RUN) || 2946 (bgep->asf_status == ASF_STAT_RUN_INIT))) { 2947 2948 bge_asf_update_status(bgep); 2949 if (bgep->asf_status == ASF_STAT_RUN) { 2950 bge_asf_stop_timer(bgep); 2951 } 2952 bgep->asf_status = ASF_STAT_STOP; 2953 2954 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 2955 2956 if (bgep->asf_pseudostop) { 2957 bgep->link_up_msg = bgep->link_down_msg = " (stopped)"; 2958 bge_chip_stop(bgep, B_FALSE); 2959 bgep->bge_mac_state = BGE_MAC_STOPPED; 2960 bgep->asf_pseudostop = B_FALSE; 2961 } 2962 2963 asf_mode = ASF_MODE_POST_SHUTDOWN; 2964 2965 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 2966 ddi_fm_service_impact(bgep->devinfo, 2967 DDI_SERVICE_UNAFFECTED); 2968 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2969 ddi_fm_service_impact(bgep->devinfo, 2970 DDI_SERVICE_UNAFFECTED); 2971 } 2972 mutex_exit(bgep->genlock); 2973 #endif 2974 2975 /* 2976 * Unregister from the GLD subsystem. This can fail, in 2977 * particular if there are DLPI style-2 streams still open - 2978 * in which case we just return failure without shutting 2979 * down chip operations. 2980 */ 2981 if (mac_unregister(bgep->mh) != 0) 2982 return (DDI_FAILURE); 2983 2984 /* 2985 * All activity stopped, so we can clean up & exit 2986 */ 2987 #ifdef BGE_IPMI_ASF 2988 bge_unattach(bgep, asf_mode); 2989 #else 2990 bge_unattach(bgep); 2991 #endif 2992 return (DDI_SUCCESS); 2993 } 2994 2995 2996 /* 2997 * ========== Module Loading Data & Entry Points ========== 2998 */ 2999 3000 #undef BGE_DBG 3001 #define BGE_DBG BGE_DBG_INIT /* debug flag for this code */ 3002 3003 DDI_DEFINE_STREAM_OPS(bge_dev_ops, nulldev, nulldev, bge_attach, bge_detach, 3004 nodev, NULL, D_MP, NULL); 3005 3006 static struct modldrv bge_modldrv = { 3007 &mod_driverops, /* Type of module. This one is a driver */ 3008 bge_ident, /* short description */ 3009 &bge_dev_ops /* driver specific ops */ 3010 }; 3011 3012 static struct modlinkage modlinkage = { 3013 MODREV_1, (void *)&bge_modldrv, NULL 3014 }; 3015 3016 3017 int 3018 _info(struct modinfo *modinfop) 3019 { 3020 return (mod_info(&modlinkage, modinfop)); 3021 } 3022 3023 int 3024 _init(void) 3025 { 3026 int status; 3027 3028 mac_init_ops(&bge_dev_ops, "bge"); 3029 status = mod_install(&modlinkage); 3030 if (status == DDI_SUCCESS) 3031 mutex_init(bge_log_mutex, NULL, MUTEX_DRIVER, NULL); 3032 else 3033 mac_fini_ops(&bge_dev_ops); 3034 return (status); 3035 } 3036 3037 int 3038 _fini(void) 3039 { 3040 int status; 3041 3042 status = mod_remove(&modlinkage); 3043 if (status == DDI_SUCCESS) { 3044 mac_fini_ops(&bge_dev_ops); 3045 mutex_destroy(bge_log_mutex); 3046 } 3047 return (status); 3048 } 3049 3050 3051 /* 3052 * bge_add_intrs: 3053 * 3054 * Register FIXED or MSI interrupts. 3055 */ 3056 static int 3057 bge_add_intrs(bge_t *bgep, int intr_type) 3058 { 3059 dev_info_t *dip = bgep->devinfo; 3060 int avail, actual, intr_size, count = 0; 3061 int i, flag, ret; 3062 3063 BGE_DEBUG(("bge_add_intrs($%p, 0x%x)", (void *)bgep, intr_type)); 3064 3065 /* Get number of interrupts */ 3066 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 3067 if ((ret != DDI_SUCCESS) || (count == 0)) { 3068 bge_error(bgep, "ddi_intr_get_nintrs() failure, ret: %d, " 3069 "count: %d", ret, count); 3070 3071 return (DDI_FAILURE); 3072 } 3073 3074 /* Get number of available interrupts */ 3075 ret = ddi_intr_get_navail(dip, intr_type, &avail); 3076 if ((ret != DDI_SUCCESS) || (avail == 0)) { 3077 bge_error(bgep, "ddi_intr_get_navail() failure, " 3078 "ret: %d, avail: %d\n", ret, avail); 3079 3080 return (DDI_FAILURE); 3081 } 3082 3083 if (avail < count) { 3084 BGE_DEBUG(("%s: nintrs() returned %d, navail returned %d", 3085 bgep->ifname, count, avail)); 3086 } 3087 3088 /* 3089 * BGE hardware generates only single MSI even though it claims 3090 * to support multiple MSIs. So, hard code MSI count value to 1. 3091 */ 3092 if (intr_type == DDI_INTR_TYPE_MSI) { 3093 count = 1; 3094 flag = DDI_INTR_ALLOC_STRICT; 3095 } else { 3096 flag = DDI_INTR_ALLOC_NORMAL; 3097 } 3098 3099 /* Allocate an array of interrupt handles */ 3100 intr_size = count * sizeof (ddi_intr_handle_t); 3101 bgep->htable = kmem_alloc(intr_size, KM_SLEEP); 3102 3103 /* Call ddi_intr_alloc() */ 3104 ret = ddi_intr_alloc(dip, bgep->htable, intr_type, 0, 3105 count, &actual, flag); 3106 3107 if ((ret != DDI_SUCCESS) || (actual == 0)) { 3108 bge_error(bgep, "ddi_intr_alloc() failed %d\n", ret); 3109 3110 kmem_free(bgep->htable, intr_size); 3111 return (DDI_FAILURE); 3112 } 3113 3114 if (actual < count) { 3115 BGE_DEBUG(("%s: Requested: %d, Received: %d", 3116 bgep->ifname, count, actual)); 3117 } 3118 3119 bgep->intr_cnt = actual; 3120 3121 /* 3122 * Get priority for first msi, assume remaining are all the same 3123 */ 3124 if ((ret = ddi_intr_get_pri(bgep->htable[0], &bgep->intr_pri)) != 3125 DDI_SUCCESS) { 3126 bge_error(bgep, "ddi_intr_get_pri() failed %d\n", ret); 3127 3128 /* Free already allocated intr */ 3129 for (i = 0; i < actual; i++) { 3130 (void) ddi_intr_free(bgep->htable[i]); 3131 } 3132 3133 kmem_free(bgep->htable, intr_size); 3134 return (DDI_FAILURE); 3135 } 3136 3137 /* Call ddi_intr_add_handler() */ 3138 for (i = 0; i < actual; i++) { 3139 if ((ret = ddi_intr_add_handler(bgep->htable[i], bge_intr, 3140 (caddr_t)bgep, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 3141 bge_error(bgep, "ddi_intr_add_handler() " 3142 "failed %d\n", ret); 3143 3144 /* Free already allocated intr */ 3145 for (i = 0; i < actual; i++) { 3146 (void) ddi_intr_free(bgep->htable[i]); 3147 } 3148 3149 kmem_free(bgep->htable, intr_size); 3150 return (DDI_FAILURE); 3151 } 3152 } 3153 3154 if ((ret = ddi_intr_get_cap(bgep->htable[0], &bgep->intr_cap)) 3155 != DDI_SUCCESS) { 3156 bge_error(bgep, "ddi_intr_get_cap() failed %d\n", ret); 3157 3158 for (i = 0; i < actual; i++) { 3159 (void) ddi_intr_remove_handler(bgep->htable[i]); 3160 (void) ddi_intr_free(bgep->htable[i]); 3161 } 3162 3163 kmem_free(bgep->htable, intr_size); 3164 return (DDI_FAILURE); 3165 } 3166 3167 return (DDI_SUCCESS); 3168 } 3169 3170 /* 3171 * bge_rem_intrs: 3172 * 3173 * Unregister FIXED or MSI interrupts 3174 */ 3175 static void 3176 bge_rem_intrs(bge_t *bgep) 3177 { 3178 int i; 3179 3180 BGE_DEBUG(("bge_rem_intrs($%p)", (void *)bgep)); 3181 3182 /* Call ddi_intr_remove_handler() */ 3183 for (i = 0; i < bgep->intr_cnt; i++) { 3184 (void) ddi_intr_remove_handler(bgep->htable[i]); 3185 (void) ddi_intr_free(bgep->htable[i]); 3186 } 3187 3188 kmem_free(bgep->htable, bgep->intr_cnt * sizeof (ddi_intr_handle_t)); 3189 } 3190 3191 3192 void 3193 bge_intr_enable(bge_t *bgep) 3194 { 3195 int i; 3196 3197 if (bgep->intr_cap & DDI_INTR_FLAG_BLOCK) { 3198 /* Call ddi_intr_block_enable() for MSI interrupts */ 3199 (void) ddi_intr_block_enable(bgep->htable, bgep->intr_cnt); 3200 } else { 3201 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 3202 for (i = 0; i < bgep->intr_cnt; i++) { 3203 (void) ddi_intr_enable(bgep->htable[i]); 3204 } 3205 } 3206 } 3207 3208 3209 void 3210 bge_intr_disable(bge_t *bgep) 3211 { 3212 int i; 3213 3214 if (bgep->intr_cap & DDI_INTR_FLAG_BLOCK) { 3215 /* Call ddi_intr_block_disable() */ 3216 (void) ddi_intr_block_disable(bgep->htable, bgep->intr_cnt); 3217 } else { 3218 for (i = 0; i < bgep->intr_cnt; i++) { 3219 (void) ddi_intr_disable(bgep->htable[i]); 3220 } 3221 } 3222 } 3223