1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_BGE_IMPL_H 28 #define _SYS_BGE_IMPL_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/stream.h> 38 #include <sys/strsun.h> 39 #include <sys/strsubr.h> 40 #include <sys/stat.h> 41 #include <sys/pci.h> 42 #include <sys/note.h> 43 #include <sys/modctl.h> 44 #include <sys/crc32.h> 45 #ifdef __sparcv9 46 #include <v9/sys/membar.h> 47 #endif /* __sparcv9 */ 48 #include <sys/kstat.h> 49 #include <sys/ethernet.h> 50 #include <sys/vlan.h> 51 #include <sys/errno.h> 52 #include <sys/dlpi.h> 53 #include <sys/devops.h> 54 #include <sys/debug.h> 55 #include <sys/cyclic.h> 56 #include <sys/conf.h> 57 58 #include <netinet/ip6.h> 59 60 #include <inet/common.h> 61 #include <inet/ip.h> 62 #include <inet/mi.h> 63 #include <inet/nd.h> 64 #include <sys/pattr.h> 65 66 #include <sys/dditypes.h> 67 #include <sys/ddi.h> 68 #include <sys/sunddi.h> 69 70 #include <sys/ddifm.h> 71 #include <sys/fm/protocol.h> 72 #include <sys/fm/util.h> 73 #include <sys/fm/io/ddi.h> 74 75 #include <sys/mac.h> 76 #include <sys/mac_ether.h> 77 78 #ifdef __amd64 79 #include <sys/x86_archext.h> 80 #endif 81 82 /* 83 * <sys/ethernet.h> *may* already have provided the typedef ether_addr_t; 84 * but of course C doesn't provide a way to check this directly. So here 85 * we rely on the fact that the symbol ETHERTYPE_AT was added to the 86 * header file (as a #define, which we *can* test for) at the same time 87 * as the typedef for ether_addr_t ;-! 88 */ 89 #ifndef ETHERTYPE_AT 90 typedef uchar_t ether_addr_t[ETHERADDRL]; 91 #endif /* ETHERTYPE_AT */ 92 93 /* 94 * Reconfiguring the network devices requires the net_config privilege 95 * in Solaris 10+. Prior to this, root privilege is required. In order 96 * that the driver binary can run on both S10+ and earlier versions, we 97 * make the decision as to which to use at runtime. These declarations 98 * allow for either (or both) to exist ... 99 */ 100 extern int secpolicy_net_config(const cred_t *, boolean_t); 101 extern int drv_priv(cred_t *); 102 #pragma weak secpolicy_net_config 103 #pragma weak drv_priv 104 105 #include <sys/netlb.h> /* originally from cassini */ 106 #include <sys/miiregs.h> /* by fjlite out of intel */ 107 108 #include "bge.h" 109 #include "bge_hw.h" 110 111 /* 112 * Compile-time feature switches ... 113 */ 114 #define BGE_DO_PPIO 0 /* peek/poke ioctls */ 115 #define BGE_RX_SOFTINT 0 /* softint per receive ring */ 116 #define BGE_CHOOSE_SEND_METHOD 0 /* send by copying only */ 117 118 /* 119 * NOTES: 120 * 121 * #defines: 122 * 123 * BGE_PCI_CONFIG_RNUMBER and BGE_PCI_OPREGS_RNUMBER are the 124 * register-set numbers to use for the config space registers 125 * and the operating registers respectively. On an OBP-based 126 * machine, regset 0 refers to CONFIG space, and regset 1 will 127 * be the operating registers in MEMORY space. If an expansion 128 * ROM is fitted, it may appear as a further register set. 129 * 130 * BGE_DMA_MODE defines the mode (STREAMING/CONSISTENT) used 131 * for the data buffers. The descriptors are always set up 132 * in CONSISTENT mode. 133 * 134 * BGE_HEADROOM defines how much space we'll leave in allocated 135 * mblks before the first valid data byte. This should be chosen 136 * to be 2 modulo 4, so that once the ethernet header (14 bytes) 137 * has been stripped off, the packet data will be 4-byte aligned. 138 * The remaining space can be used by upstream modules to prepend 139 * any headers required. 140 */ 141 142 #define BGE_PCI_CONFIG_RNUMBER 0 143 #define BGE_PCI_OPREGS_RNUMBER 1 144 #define BGE_DMA_MODE DDI_DMA_STREAMING 145 #define BGE_HEADROOM 34 146 147 /* 148 * BGE_HALFTICK is half the period of the cyclic callback (in 149 * nanoseconds), chosen so that 0.5s <= cyclic period <= 1s. 150 * Other time values are derived as odd multiples of this value 151 * so that there's little chance of ambiguity w.r.t. which tick 152 * a timeout expires on. 153 * 154 * BGE_PHY_STABLE_TIME is the period for which the contents of the 155 * PHY's status register must remain unchanging before we accept 156 * that the link has come up. [Sometimes the link comes up, only 157 * to go down again within a short time as the autonegotiation 158 * process cycles through various options before finding the best 159 * compatible mode. We don't want to report repeated link up/down 160 * cycles, so we wait until we think it's stable.] 161 * 162 * BGE_SERDES_STABLE_TIME is the analogous value for the SerDes 163 * interface. It's much shorter, 'cos the SerDes doesn't show 164 * these effects as much as the copper PHY. 165 * 166 * BGE_LINK_SETTLE_TIME is the period during which we regard link 167 * up/down cycles as an normal event after resetting/reprogramming 168 * the PHY. During this time, link up/down messages are sent to 169 * the log only, not the console. At any other time, link change 170 * events are regarded as unexpected and sent to both console & log. 171 * 172 * These latter two values have no theoretical justification, but 173 * are derived from observations and heuristics - the values below 174 * just seem to work quite well. 175 */ 176 177 #define BGE_HALFTICK 268435456LL /* 2**28 ns! */ 178 #define BGE_CYCLIC_PERIOD (2*BGE_HALFTICK) /* ~0.5s */ 179 #define BGE_SERDES_STABLE_TIME (3*BGE_HALFTICK) /* ~0.8s */ 180 #define BGE_PHY_STABLE_TIME (11*BGE_HALFTICK) /* ~3.0s */ 181 #define BGE_LINK_SETTLE_TIME (111*BGE_HALFTICK) /* ~30.0s */ 182 183 /* 184 * Indices used to identify the different buffer rings internally 185 */ 186 #define BGE_STD_BUFF_RING 0 187 #define BGE_JUMBO_BUFF_RING 1 188 #define BGE_MINI_BUFF_RING 2 189 190 /* 191 * Current implementation limits 192 */ 193 #define BGE_BUFF_RINGS_USED 2 /* std & jumbo ring */ 194 /* for now */ 195 #define BGE_RECV_RINGS_USED 16 /* up to 16 rtn rings */ 196 /* for now */ 197 #define BGE_SEND_RINGS_USED 4 /* up to 4 tx rings */ 198 /* for now */ 199 #define BGE_HASH_TABLE_SIZE 128 /* may be 256 later */ 200 201 /* 202 * Ring/buffer size parameters 203 * 204 * All of the (up to) 16 TX rings & and the corresponding buffers are the 205 * same size. 206 * 207 * Each of the (up to) 3 receive producer (aka buffer) rings is a different 208 * size and has different sized buffers associated with it too. 209 * 210 * The (up to) 16 receive return rings have no buffers associated with them. 211 * The number of slots per receive return ring must be 2048 if the mini 212 * ring is enabled, otherwise it may be 1024. See Broadcom document 213 * 570X-PG102-R page 56. 214 * 215 * Note: only the 5700 supported external memory (and therefore the mini 216 * ring); the 5702/3/4 don't. This driver doesn't support the original 217 * 5700, so we won't ever use the mini ring capability. 218 */ 219 220 #define BGE_SEND_RINGS_DEFAULT 1 221 #define BGE_RECV_RINGS_DEFAULT 1 222 223 #define BGE_SEND_BUFF_SIZE_DEFAULT 1536 224 #define BGE_SEND_BUFF_SIZE_JUMBO 9022 225 #define BGE_SEND_SLOTS_USED 512 226 227 #define BGE_STD_BUFF_SIZE 1536 /* 0x600 */ 228 #define BGE_STD_SLOTS_USED 512 229 230 #define BGE_JUMBO_BUFF_SIZE 9022 /* 9k */ 231 #define BGE_JUMBO_SLOTS_USED 256 232 233 #define BGE_MINI_BUFF_SIZE 128 /* 64? 256? */ 234 #define BGE_MINI_SLOTS_USED 0 /* must be 0; see above */ 235 236 #define BGE_RECV_BUFF_SIZE 0 237 #if BGE_MINI_SLOTS_USED > 0 238 #define BGE_RECV_SLOTS_USED 2048 /* required */ 239 #else 240 #define BGE_RECV_SLOTS_USED 1024 /* could be 2048 anyway */ 241 #endif 242 243 /* 244 * PCI type. PCI-Express or PCI/PCIX 245 */ 246 #define BGE_PCI 0 247 #define BGE_PCI_E 1 248 #define BGE_PCI_X 2 249 250 /* 251 * Statistic type. There are two type of statistic: 252 * statistic block and statistic registers 253 */ 254 #define BGE_STAT_BLK 1 255 #define BGE_STAT_REG 2 256 257 /* 258 * MTU.for all chipsets ,the default is 1500 ,and some chipsets 259 * support 9k jumbo frames size 260 */ 261 #define BGE_DEFAULT_MTU 1500 262 #define BGE_MAXIMUM_MTU 9000 263 264 /* 265 * Pad the h/w defined status block (which can be up to 80 bytes long) 266 * to a power-of-two boundary 267 */ 268 #define BGE_STATUS_PADDING (128 - sizeof (bge_status_t)) 269 270 /* 271 * On platforms which support DVMA, we can simply allocate one big piece 272 * of memory for all the Tx buffers and another for the Rx buffers, and 273 * then carve them up as required. It doesn't matter if they aren't just 274 * one physically contiguous piece each, because both the CPU *and* the 275 * I/O device can see them *as though they were*. 276 * 277 * However, if only physically-addressed DMA is possible, this doesn't 278 * work; we can't expect to get enough contiguously-addressed memory for 279 * all the buffers of each type, so in this case we request a number of 280 * smaller pieces, each still large enough for several buffers but small 281 * enough to fit within "an I/O page" (e.g. 64K). 282 * 283 * The #define below specifies how many pieces of memory are to be used; 284 * 16 has been shown to work on an i86pc architecture but this could be 285 * different on other non-DVMA platforms ... 286 */ 287 #ifdef _DMA_USES_VIRTADDR 288 #define BGE_SPLIT 1 /* no split required */ 289 #else 290 #if ((BGE_BUFF_RINGS_USED > 1) || (BGE_SEND_RINGS_USED > 1) || \ 291 (BGE_RECV_RINGS_USED > 1)) 292 #define BGE_SPLIT 128 /* split 128 ways */ 293 #else 294 #define BGE_SPLIT 16 /* split 16 ways */ 295 #endif 296 #endif /* _DMA_USES_VIRTADDR */ 297 298 #define BGE_RECV_RINGS_SPLIT (BGE_RECV_RINGS_MAX + 1) 299 300 /* 301 * MONOLITHIC allocation is a hardware debugging aid, so that a logic 302 * analyser can more easily be programmed with the (single) range of 303 * memory addresses that the chip will then use for DMA. 304 * 305 * It's incompatible with non-DVMA architectures that require BGE_SPLIT 306 * to be set greater than 1. Here, it overrides BGE_SPLIT, so the code 307 * will compile correctly but will *probably* fail at runtime because it 308 * simply won't be able to allocate a big enough piece of memory ... 309 */ 310 #define BGE_MONOLITHIC 0 311 #if BGE_MONOLITHIC 312 #undef BGE_SPLIT 313 #define BGE_SPLIT 1 /* must be 1 if MONOLITHIC */ 314 #endif /* BGE_MONOLITHIC */ 315 316 /* 317 * STREAMS parameters 318 */ 319 #define BGE_IDNUM 0 /* zero seems to work */ 320 #define BGE_LOWAT (256) 321 #define BGE_HIWAT (256*1024) 322 323 324 /* 325 * Basic data types, for clarity in distinguishing 'numbers' 326 * used for different purposes ... 327 * 328 * A <bge_regno_t> is a register 'address' (offset) in any one of 329 * various address spaces (PCI config space, PCI memory-mapped I/O 330 * register space, MII registers, etc). None of these exceeds 64K, 331 * so we could use a 16-bit representation but pointer-sized objects 332 * are more "natural" in most architectures; they seem to be handled 333 * more efficiently on SPARC and no worse on x86. 334 * 335 * BGE_REGNO_NONE represents the non-existent value in this space. 336 */ 337 typedef uintptr_t bge_regno_t; /* register # (offset) */ 338 #define BGE_REGNO_NONE (~(uintptr_t)0u) 339 340 /* 341 * Describes one chunk of allocated DMA-able memory 342 * 343 * In some cases, this is a single chunk as allocated from the system; 344 * but we also use this structure to represent slices carved off such 345 * a chunk. Even when we don't really need all the information, we 346 * use this structure as a convenient way of correlating the various 347 * ways of looking at a piece of memory (kernel VA, IO space DVMA, 348 * handle+offset, etc). 349 */ 350 typedef struct { 351 ddi_acc_handle_t acc_hdl; /* handle for memory */ 352 void *mem_va; /* CPU VA of memory */ 353 uint32_t nslots; /* number of slots */ 354 uint32_t size; /* size per slot */ 355 size_t alength; /* allocated size */ 356 /* >= product of above */ 357 358 ddi_dma_handle_t dma_hdl; /* DMA handle */ 359 offset_t offset; /* relative to handle */ 360 ddi_dma_cookie_t cookie; /* associated cookie */ 361 uint32_t ncookies; /* must be 1 */ 362 uint32_t token; /* arbitrary identifier */ 363 } dma_area_t; /* 0x50 (80) bytes */ 364 365 /* 366 * Software version of the Receive Buffer Descriptor 367 * There's one of these for each receive buffer (up to 256/512/1024 per ring). 368 */ 369 typedef struct sw_rbd { 370 dma_area_t pbuf; /* (const) related */ 371 /* buffer area */ 372 } sw_rbd_t; /* 0x50 (80) bytes */ 373 374 /* 375 * Software Receive Buffer (Producer) Ring Control Block 376 * There's one of these for each receiver producer ring (up to 3), 377 * but each holds buffers of a different size. 378 */ 379 typedef struct buff_ring { 380 dma_area_t desc; /* (const) related h/w */ 381 /* descriptor area */ 382 dma_area_t buf[BGE_SPLIT]; /* (const) related */ 383 /* buffer area(s) */ 384 bge_rcb_t hw_rcb; /* (const) image of h/w */ 385 /* RCB, and used to */ 386 struct bge *bgep; /* (const) containing */ 387 /* driver soft state */ 388 /* initialise same */ 389 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 390 /* "consumer index" */ 391 /* (in status block) */ 392 393 /* 394 * The rf_lock must be held when updating the h/w producer index 395 * mailbox register (*chip_mbox_reg), or the s/w producer index 396 * (rf_next). 397 */ 398 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 399 /* index mailbox offset */ 400 kmutex_t rf_lock[1]; /* serialize refill */ 401 uint64_t rf_next; /* next slot to refill */ 402 /* ("producer index") */ 403 404 sw_rbd_t *sw_rbds; /* software descriptors */ 405 void *spare[4]; /* padding */ 406 } buff_ring_t; /* 0x100 (256) bytes */ 407 408 /* 409 * Software Receive (Return) Ring Control Block 410 * There's one of these for each receiver return ring (up to 16). 411 */ 412 typedef struct recv_ring { 413 /* 414 * The elements flagged (const) in the comments below are 415 * set up once during initialiation and thereafter unchanged. 416 */ 417 dma_area_t desc; /* (const) related h/w */ 418 /* descriptor area */ 419 bge_rcb_t hw_rcb; /* (const) image of h/w */ 420 /* RCB, and used to */ 421 /* initialise same */ 422 struct bge *bgep; /* (const) containing */ 423 /* driver soft state */ 424 ddi_softintr_t rx_softint; /* (const) per-ring */ 425 /* receive callback */ 426 volatile uint16_t *prod_index_p; /* (const) ptr to h/w */ 427 /* "producer index" */ 428 /* (in status block) */ 429 430 /* 431 * The rx_lock must be held when updating the h/w consumer index 432 * mailbox register (*chip_mbox_reg), or the s/w consumer index 433 * (rx_next). 434 */ 435 bge_regno_t chip_mbx_reg; /* (const) h/w consumer */ 436 /* index mailbox offset */ 437 kmutex_t rx_lock[1]; /* serialize receive */ 438 uint64_t rx_next; /* next slot to examine */ 439 mac_resource_handle_t handle; /* per ring cookie */ 440 /* ("producer index") */ 441 } recv_ring_t; /* 0x90 (144) bytes */ 442 443 /* 444 * Software version of the Send Buffer Descriptor 445 * There's one of these for each send buffer (up to 512 per ring) 446 */ 447 typedef struct sw_sbd { 448 dma_area_t desc; /* (const) related h/w */ 449 /* descriptor area */ 450 dma_area_t pbuf; /* (const) related */ 451 /* buffer area */ 452 453 void (*recycle)(struct sw_sbd *); 454 uint64_t flags; 455 456 mblk_t *mp; /* related mblk, if any */ 457 ddi_dma_handle_t mblk_hdl; /* handle for same */ 458 } sw_sbd_t; /* 0xc0 (192) bytes */ 459 460 #define SW_SBD_FLAG_BUSY 0x0000000000000001 461 #define SW_SBD_FLAG_PBUF 0x0000000000000002 462 #define SW_SBD_FLAG_BIND 0x0000000000000004 463 464 /* 465 * Software Send Ring Control Block 466 * There's one of these for each of (up to) 16 send rings 467 */ 468 typedef struct send_ring { 469 /* 470 * The elements flagged (const) in the comments below are 471 * set up once during initialiation and thereafter unchanged. 472 */ 473 dma_area_t desc; /* (const) related h/w */ 474 /* descriptor area */ 475 dma_area_t buf[BGE_SPLIT]; /* (const) related */ 476 /* buffer area(s) */ 477 bge_rcb_t hw_rcb; /* (const) image of h/w */ 478 /* RCB, and used to */ 479 /* initialise same */ 480 struct bge *bgep; /* (const) containing */ 481 /* driver soft state */ 482 volatile uint16_t *cons_index_p; /* (const) ptr to h/w */ 483 /* "consumer index" */ 484 /* (in status block) */ 485 486 bge_regno_t chip_mbx_reg; /* (const) h/w producer */ 487 /* index mailbox offset */ 488 kmutex_t tx_lock[1]; /* serialize h/w update */ 489 /* ("producer index") */ 490 uint64_t tx_next; /* next slot to use */ 491 uint64_t tx_flow; /* # concurrent sends */ 492 493 /* 494 * These counters/indexes are manipulated in the transmit 495 * path using atomics rather than mutexes for speed 496 */ 497 uint64_t tx_free; /* # of slots available */ 498 499 /* 500 * The tc_lock must be held while manipulating the s/w consumer 501 * index (tc_next). 502 */ 503 kmutex_t tc_lock[1]; /* serialize recycle */ 504 uint64_t tc_next; /* next slot to recycle */ 505 /* ("consumer index") */ 506 507 sw_sbd_t *sw_sbds; /* software descriptors */ 508 uint64_t mac_resid; /* special per resource id */ 509 } send_ring_t; /* 0x100 (256) bytes */ 510 511 typedef struct { 512 ether_addr_t addr; /* in canonical form */ 513 uint8_t spare; 514 boolean_t set; /* B_TRUE => valid */ 515 } bge_mac_addr_t; 516 517 /* 518 * The original 5700/01 supported only SEEPROMs. Later chips (5702+) 519 * support both SEEPROMs (using the same 2-wire CLK/DATA interface for 520 * the hardware and a backwards-compatible software access method), and 521 * buffered or unbuffered FLASH devices connected to the 4-wire SPI bus 522 * and using a new software access method. 523 * 524 * The access methods for SEEPROM and Flash are generally similar, with 525 * the chip handling the serialisation/deserialisation and handshaking, 526 * but the registers used are different, as are a few details of the 527 * protocol, and the timing, so we have to determine which (if any) is 528 * fitted. 529 * 530 * The value UNKNOWN means just that; we haven't yet tried to determine 531 * the device type. 532 * 533 * The value NONE can indicate either that a real and definite absence of 534 * any NVmem has been detected, or that there may be NVmem but we can't 535 * determine its type, perhaps because the NVconfig pins on the chip have 536 * been wired up incorrectly. In either case, access to the NVmem (if any) 537 * is not supported. 538 */ 539 enum bge_nvmem_type { 540 BGE_NVTYPE_NONE = -1, /* (or indeterminable) */ 541 BGE_NVTYPE_UNKNOWN, /* not yet checked */ 542 BGE_NVTYPE_SEEPROM, /* BCM5700/5701 only */ 543 BGE_NVTYPE_LEGACY_SEEPROM, /* 5702+ */ 544 BGE_NVTYPE_UNBUFFERED_FLASH, /* 5702+ */ 545 BGE_NVTYPE_BUFFERED_FLASH /* 5702+ */ 546 }; 547 548 /* 549 * Describes the characteristics of a specific chip 550 * 551 * Note: elements from <businfo> to <latency> are filled in by during 552 * the first phase of chip initialisation (see bge_chip_cfg_init()). 553 * The remaining ones are determined just after the first RESET, in 554 * bge_poll_firmware(). Thereafter, the entire structure is readonly. 555 */ 556 typedef struct { 557 uint32_t asic_rev; /* masked from MHCR */ 558 uint32_t businfo; /* from private reg */ 559 uint16_t command; /* saved during attach */ 560 561 uint16_t vendor; /* vendor-id */ 562 uint16_t device; /* device-id */ 563 uint16_t subven; /* subsystem-vendor-id */ 564 uint16_t subdev; /* subsystem-id */ 565 uint8_t revision; /* revision-id */ 566 uint8_t clsize; /* cache-line-size */ 567 uint8_t latency; /* latency-timer */ 568 569 uint8_t flags; 570 uint16_t chip_label; /* numeric part only */ 571 /* (e.g. 5703/5794/etc) */ 572 uint32_t mbuf_base; /* Mbuf pool parameters */ 573 uint32_t mbuf_length; /* depend on chiptype */ 574 uint32_t pci_type; 575 uint32_t statistic_type; 576 uint32_t bge_dma_rwctrl; 577 uint32_t bge_mlcr_default; 578 uint32_t recv_slots; /* receive ring size */ 579 enum bge_nvmem_type nvtype; /* SEEPROM or Flash */ 580 581 uint16_t jumbo_slots; 582 uint16_t ethmax_size; 583 uint16_t snd_buff_size; 584 uint16_t recv_jumbo_size; 585 uint16_t std_buf_size; 586 uint32_t mbuf_hi_water; 587 uint32_t mbuf_lo_water_rmac; 588 uint32_t mbuf_lo_water_rdma; 589 590 uint64_t rx_rings; /* from bge.conf */ 591 uint64_t tx_rings; /* from bge.conf */ 592 uint64_t default_mtu; /* from bge.conf */ 593 594 uint64_t hw_mac_addr; /* from chip register */ 595 bge_mac_addr_t vendor_addr; /* transform of same */ 596 boolean_t msi_enabled; /* default to true */ 597 } chip_id_t; 598 599 #define CHIP_FLAG_SUPPORTED 0x80 600 #define CHIP_FLAG_SERDES 0x40 601 #define CHIP_FLAG_PARTIAL_CSUM 0x20 602 #define CHIP_FLAG_NO_JUMBO 0x1 603 604 /* 605 * Collection of physical-layer functions to: 606 * (re)initialise the physical layer 607 * update it to match software settings 608 * check for link status change 609 */ 610 typedef struct { 611 int (*phys_restart)(struct bge *, boolean_t); 612 int (*phys_update)(struct bge *); 613 boolean_t (*phys_check)(struct bge *, boolean_t); 614 } phys_ops_t; 615 616 /* 617 * Named Data (ND) Parameter Management Structure 618 */ 619 typedef struct { 620 int ndp_info; 621 int ndp_min; 622 int ndp_max; 623 int ndp_val; 624 char *ndp_name; 625 } nd_param_t; /* 0x18 (24) bytes */ 626 627 /* 628 * NDD parameter indexes, divided into: 629 * 630 * read-only parameters describing the hardware's capabilities 631 * read-write parameters controlling the advertised capabilities 632 * read-only parameters describing the partner's capabilities 633 * read-only parameters describing the link state 634 */ 635 enum { 636 PARAM_AUTONEG_CAP, 637 PARAM_PAUSE_CAP, 638 PARAM_ASYM_PAUSE_CAP, 639 PARAM_1000FDX_CAP, 640 PARAM_1000HDX_CAP, 641 PARAM_100T4_CAP, 642 PARAM_100FDX_CAP, 643 PARAM_100HDX_CAP, 644 PARAM_10FDX_CAP, 645 PARAM_10HDX_CAP, 646 647 PARAM_ADV_AUTONEG_CAP, 648 PARAM_ADV_PAUSE_CAP, 649 PARAM_ADV_ASYM_PAUSE_CAP, 650 PARAM_ADV_1000FDX_CAP, 651 PARAM_ADV_1000HDX_CAP, 652 PARAM_ADV_100T4_CAP, 653 PARAM_ADV_100FDX_CAP, 654 PARAM_ADV_100HDX_CAP, 655 PARAM_ADV_10FDX_CAP, 656 PARAM_ADV_10HDX_CAP, 657 658 PARAM_LP_AUTONEG_CAP, 659 PARAM_LP_PAUSE_CAP, 660 PARAM_LP_ASYM_PAUSE_CAP, 661 PARAM_LP_1000FDX_CAP, 662 PARAM_LP_1000HDX_CAP, 663 PARAM_LP_100T4_CAP, 664 PARAM_LP_100FDX_CAP, 665 PARAM_LP_100HDX_CAP, 666 PARAM_LP_10FDX_CAP, 667 PARAM_LP_10HDX_CAP, 668 669 PARAM_LINK_STATUS, 670 PARAM_LINK_SPEED, 671 PARAM_LINK_DUPLEX, 672 673 PARAM_LINK_AUTONEG, 674 PARAM_LINK_RX_PAUSE, 675 PARAM_LINK_TX_PAUSE, 676 677 PARAM_LOOP_MODE, 678 PARAM_MSI_CNT, 679 680 PARAM_COUNT 681 }; 682 683 /* 684 * Actual state of the BCM570x chip 685 */ 686 enum bge_chip_state { 687 BGE_CHIP_FAULT = -2, /* fault, need reset */ 688 BGE_CHIP_ERROR, /* error, want reset */ 689 BGE_CHIP_INITIAL, /* Initial state only */ 690 BGE_CHIP_RESET, /* reset, need init */ 691 BGE_CHIP_STOPPED, /* Tx/Rx stopped */ 692 BGE_CHIP_RUNNING /* with interrupts */ 693 }; 694 695 enum bge_mac_state { 696 BGE_MAC_STOPPED = 0, 697 BGE_MAC_STARTED 698 }; 699 700 /* 701 * (Internal) return values from ioctl subroutines 702 */ 703 enum ioc_reply { 704 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 705 IOC_DONE, /* OK, reply sent */ 706 IOC_ACK, /* OK, just send ACK */ 707 IOC_REPLY, /* OK, just send reply */ 708 IOC_RESTART_ACK, /* OK, restart & ACK */ 709 IOC_RESTART_REPLY /* OK, restart & reply */ 710 }; 711 712 /* 713 * (Internal) return values from send_msg subroutines 714 */ 715 enum send_status { 716 SEND_FAIL = -1, /* Not OK */ 717 SEND_KEEP, /* OK, msg queued */ 718 SEND_FREE /* OK, free msg */ 719 }; 720 721 /* 722 * (Internal) enumeration of this driver's kstats 723 */ 724 enum { 725 BGE_KSTAT_RAW = 0, 726 BGE_KSTAT_STATS, 727 BGE_KSTAT_PARAMS, 728 BGE_KSTAT_CHIPID, 729 BGE_KSTAT_DRIVER, 730 BGE_KSTAT_PHYS, 731 BGE_KSTAT_MII, 732 733 BGE_KSTAT_COUNT 734 }; 735 736 #define BGE_MAX_RESOURCES 255 737 738 /* 739 * Per-instance soft-state structure 740 */ 741 typedef struct bge { 742 /* 743 * These fields are set by attach() and unchanged thereafter ... 744 */ 745 dev_info_t *devinfo; /* device instance */ 746 mac_handle_t mh; /* mac module handle */ 747 ddi_acc_handle_t cfg_handle; /* DDI I/O handle */ 748 ddi_acc_handle_t io_handle; /* DDI I/O handle */ 749 void *io_regs; /* mapped registers */ 750 cyclic_id_t cyclic_id; /* cyclic callback */ 751 ddi_softintr_t factotum_id; /* factotum callback */ 752 ddi_softintr_t resched_id; /* reschedule callback */ 753 754 ddi_intr_handle_t *htable; /* For array of interrupts */ 755 int intr_type; /* What type of interrupt */ 756 int intr_cnt; /* # of intrs count returned */ 757 uint_t intr_pri; /* Interrupt priority */ 758 int intr_cap; /* Interrupt capabilities */ 759 uint32_t progress; /* attach tracking */ 760 uint32_t debug; /* per-instance debug */ 761 chip_id_t chipid; 762 const phys_ops_t *physops; 763 char ifname[8]; /* "bge0" ... "bge999" */ 764 765 int fm_capabilities; /* FMA capabilities */ 766 767 /* 768 * These structures describe the blocks of memory allocated during 769 * attach(). They remain unchanged thereafter, although the memory 770 * they describe is carved up into various separate regions and may 771 * therefore be described by other structures as well. 772 */ 773 dma_area_t tx_desc; /* transmit descriptors */ 774 dma_area_t rx_desc[BGE_RECV_RINGS_SPLIT]; 775 /* receive descriptors */ 776 dma_area_t tx_buff[BGE_SPLIT]; 777 dma_area_t rx_buff[BGE_SPLIT]; 778 779 /* 780 * The memory described by the <dma_area> structures above 781 * is carved up into various pieces, which are described by 782 * the structures below. 783 */ 784 dma_area_t statistics; /* describes hardware */ 785 /* statistics area */ 786 dma_area_t status_block; /* describes hardware */ 787 /* status block */ 788 /* 789 * For the BCM5705/5788/5721/5751/5752/5714 and 5715, 790 * the statistic block is not available,the statistic counter must 791 * be gotten from statistic registers.And bge_statistics_reg_t record 792 * the statistic registers value 793 */ 794 bge_statistics_reg_t stat_val; 795 796 /* 797 * Runtime read-write data starts here ... 798 * 799 * 3 Buffer Rings (std/jumbo/mini) 800 * 16 Receive (Return) Rings 801 * 16 Send Rings 802 * 803 * Note: they're not necessarily all used. 804 */ 805 buff_ring_t buff[BGE_BUFF_RINGS_MAX]; /* 3*0x0100 */ 806 recv_ring_t recv[BGE_RECV_RINGS_MAX]; /* 16*0x0090 */ 807 send_ring_t send[BGE_SEND_RINGS_MAX]; /* 16*0x0100 */ 808 809 /* 810 * Locks: 811 * 812 * Each buffer ring contains its own <rf_lock> which regulates 813 * ring refilling. 814 * 815 * Each receive (return) ring contains its own <rx_lock> which 816 * protects the critical cyclic counters etc. 817 * 818 * Each send ring contains two locks: <tx_lock> for the send-path 819 * protocol data and <tc_lock> for send-buffer recycling. 820 * 821 * Finally <genlock> is a general lock, protecting most other 822 * operational data in the state structure and chip register 823 * accesses. It is acquired by the interrupt handler and 824 * most "mode-control" routines. 825 * 826 * Any of the locks can be acquired singly, but where multiple 827 * locks are acquired, they *must* be in the order: 828 * 829 * genlock >>> rx_lock >>> rf_lock >>> tx_lock >>> tc_lock. 830 * 831 * and within any one class of lock the rings must be locked in 832 * ascending order (send[0].tc_lock >>> send[1].tc_lock), etc. 833 * 834 * Note: actually I don't believe there's any need to acquire 835 * locks on multiple rings, or even locks of all these classes 836 * concurrently; but I've set out the above order so there is a 837 * clear definition of lock hierarchy in case it's ever needed. 838 * 839 * Note: the combinations of locks that are actually held 840 * concurrently are: 841 * 842 * genlock >>> (bge_chip_interrupt()) 843 * rx_lock[i] >>> (bge_receive()) 844 * rf_lock[n] (bge_refill()) 845 * tc_lock[i] (bge_recycle()) 846 */ 847 kmutex_t genlock[1]; 848 krwlock_t errlock[1]; 849 kmutex_t softintrlock[1]; 850 851 /* 852 * Current Ethernet addresses and multicast hash (bitmap) and 853 * refcount tables, protected by <genlock> 854 */ 855 bge_mac_addr_t curr_addr[MAC_ADDRESS_REGS_MAX]; 856 uint32_t mcast_hash[BGE_HASH_TABLE_SIZE/32]; 857 uint8_t mcast_refs[BGE_HASH_TABLE_SIZE]; 858 uint32_t unicst_addr_total; /* total unicst addresses */ 859 uint32_t unicst_addr_avail; 860 /* unused unicst addr slots */ 861 862 /* 863 * Link state data (protected by genlock) 864 */ 865 const char *link_mode_msg; /* describes link mode */ 866 const char *link_down_msg; /* reason for link DOWN */ 867 const char *link_up_msg; /* comment on link UP */ 868 869 link_state_t link_state; 870 871 /* 872 * Physical layer (PHY/SerDes) state data (protected by genlock) 873 */ 874 hrtime_t phys_write_time; /* when last written */ 875 hrtime_t phys_event_time; /* when status changed */ 876 hrtime_t phys_delta_time; /* time to settle */ 877 878 /* 879 * Physical layer: copper only 880 */ 881 bge_regno_t phy_mii_addr; /* should be (const) 1! */ 882 uint16_t phy_gen_status; 883 uint16_t phy_aux_status; 884 885 /* 886 * Physical layer: serdes only 887 */ 888 uint32_t serdes_status; 889 uint32_t serdes_advert; 890 uint32_t serdes_lpadv; 891 892 /* 893 * Driver kstats, protected by <genlock> where necessary 894 */ 895 kstat_t *bge_kstats[BGE_KSTAT_COUNT]; 896 897 /* 898 * Miscellaneous operating variables (protected by genlock) 899 */ 900 uint64_t chip_resets; /* # of chip RESETs */ 901 uint64_t missed_dmas; /* # of missed DMAs */ 902 enum bge_mac_state bge_mac_state; /* definitions above */ 903 enum bge_chip_state bge_chip_state; /* definitions above */ 904 boolean_t send_hw_tcp_csum; 905 boolean_t recv_hw_tcp_csum; 906 boolean_t promisc; 907 908 /* 909 * Miscellaneous operating variables (not synchronised) 910 */ 911 uint32_t watchdog; /* watches for Tx stall */ 912 boolean_t bge_intr_running; 913 boolean_t bge_dma_error; 914 boolean_t resched_needed; 915 boolean_t resched_running; 916 uint32_t factotum_flag; /* softint pending */ 917 uintptr_t pagemask; 918 919 /* 920 * NDD parameters (protected by genlock) 921 */ 922 caddr_t nd_data_p; 923 nd_param_t nd_params[PARAM_COUNT]; 924 925 uintptr_t resmap[BGE_MAX_RESOURCES]; 926 927 /* 928 * A flag to prevent excessive config space accesses 929 * on platforms having BCM5714C/15C 930 */ 931 boolean_t lastWriteZeroData; 932 933 /* 934 * Spare space, plus guard element used to check data integrity 935 */ 936 uint64_t spare[5]; 937 uint64_t bge_guard; 938 939 /* 940 * Receive rules configure 941 */ 942 bge_recv_rule_t recv_rules[RECV_RULES_NUM_MAX]; 943 944 #ifdef BGE_IPMI_ASF 945 boolean_t asf_enabled; 946 boolean_t asf_wordswapped; 947 boolean_t asf_newhandshake; 948 boolean_t asf_pseudostop; 949 950 uint32_t asf_status; 951 timeout_id_t asf_timeout_id; 952 #endif 953 } bge_t; 954 955 /* 956 * 'Progress' bit flags ... 957 */ 958 #define PROGRESS_CFG 0x0001 /* config space mapped */ 959 #define PROGRESS_REGS 0x0002 /* registers mapped */ 960 #define PROGRESS_BUFS 0x0004 /* ring buffers allocated */ 961 #define PROGRESS_RESCHED 0x0010 /* resched softint registered */ 962 #define PROGRESS_FACTOTUM 0x0020 /* factotum softint registered */ 963 #define PROGRESS_HWINT 0x0040 /* h/w interrupt registered */ 964 /* and mutexen initialised */ 965 #define PROGRESS_INTR 0x0080 /* Intrs enabled */ 966 #define PROGRESS_PHY 0x0100 /* PHY initialised */ 967 #define PROGRESS_NDD 0x1000 /* NDD parameters set up */ 968 #define PROGRESS_KSTATS 0x2000 /* kstats created */ 969 #define PROGRESS_READY 0x8000 /* ready for work */ 970 971 /* 972 * Shorthand for the NDD parameters 973 */ 974 #define param_adv_autoneg nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val 975 #define param_adv_pause nd_params[PARAM_ADV_PAUSE_CAP].ndp_val 976 #define param_adv_asym_pause nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val 977 #define param_adv_1000fdx nd_params[PARAM_ADV_1000FDX_CAP].ndp_val 978 #define param_adv_1000hdx nd_params[PARAM_ADV_1000HDX_CAP].ndp_val 979 #define param_adv_100fdx nd_params[PARAM_ADV_100FDX_CAP].ndp_val 980 #define param_adv_100hdx nd_params[PARAM_ADV_100HDX_CAP].ndp_val 981 #define param_adv_10fdx nd_params[PARAM_ADV_10FDX_CAP].ndp_val 982 #define param_adv_10hdx nd_params[PARAM_ADV_10HDX_CAP].ndp_val 983 984 #define param_lp_autoneg nd_params[PARAM_LP_AUTONEG_CAP].ndp_val 985 #define param_lp_pause nd_params[PARAM_LP_PAUSE_CAP].ndp_val 986 #define param_lp_asym_pause nd_params[PARAM_LP_ASYM_PAUSE_CAP].ndp_val 987 #define param_lp_1000fdx nd_params[PARAM_LP_1000FDX_CAP].ndp_val 988 #define param_lp_1000hdx nd_params[PARAM_LP_1000HDX_CAP].ndp_val 989 #define param_lp_100fdx nd_params[PARAM_LP_100FDX_CAP].ndp_val 990 #define param_lp_100hdx nd_params[PARAM_LP_100HDX_CAP].ndp_val 991 #define param_lp_10fdx nd_params[PARAM_LP_10FDX_CAP].ndp_val 992 #define param_lp_10hdx nd_params[PARAM_LP_10HDX_CAP].ndp_val 993 994 #define param_link_up nd_params[PARAM_LINK_STATUS].ndp_val 995 #define param_link_speed nd_params[PARAM_LINK_SPEED].ndp_val 996 #define param_link_duplex nd_params[PARAM_LINK_DUPLEX].ndp_val 997 998 #define param_link_autoneg nd_params[PARAM_LINK_AUTONEG].ndp_val 999 #define param_link_rx_pause nd_params[PARAM_LINK_RX_PAUSE].ndp_val 1000 #define param_link_tx_pause nd_params[PARAM_LINK_TX_PAUSE].ndp_val 1001 1002 #define param_loop_mode nd_params[PARAM_LOOP_MODE].ndp_val 1003 #define param_msi_cnt nd_params[PARAM_MSI_CNT].ndp_val 1004 1005 /* 1006 * Sync a DMA area described by a dma_area_t 1007 */ 1008 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl, \ 1009 (area).offset, (area).alength, (flag))) 1010 1011 /* 1012 * Find the (kernel virtual) address of block of memory 1013 * described by a dma_area_t 1014 */ 1015 #define DMA_VPTR(area) ((area).mem_va) 1016 1017 /* 1018 * Zero a block of memory described by a dma_area_t 1019 */ 1020 #define DMA_ZERO(area) bzero(DMA_VPTR(area), (area).alength) 1021 1022 /* 1023 * Next value of a cyclic index 1024 */ 1025 #define NEXT(index, limit) ((index)+1 < (limit) ? (index)+1 : 0); 1026 1027 /* 1028 * Property lookups 1029 */ 1030 #define BGE_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 1031 DDI_PROP_DONTPASS, (n)) 1032 #define BGE_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 1033 DDI_PROP_DONTPASS, (n), -1) 1034 1035 /* 1036 * Copy an ethernet address 1037 */ 1038 #define ethaddr_copy(src, dst) bcopy((src), (dst), ETHERADDRL) 1039 1040 /* 1041 * Endian swap 1042 */ 1043 /* BEGIN CSTYLED */ 1044 #define BGE_BSWAP_32(x) ((((x) & 0xff000000) >> 24) | \ 1045 (((x) & 0x00ff0000) >> 8) | \ 1046 (((x) & 0x0000ff00) << 8) | \ 1047 (((x) & 0x000000ff) << 24)) 1048 /* END CSTYLED */ 1049 1050 /* 1051 * Marker value placed at the end of the driver's state 1052 */ 1053 #define BGE_GUARD 0x1919306009031802 1054 1055 /* 1056 * Bit flags in the 'debug' word ... 1057 */ 1058 #define BGE_DBG_STOP 0x00000001 /* early debug_enter() */ 1059 #define BGE_DBG_TRACE 0x00000002 /* general flow tracing */ 1060 1061 #define BGE_DBG_REGS 0x00000010 /* low-level accesses */ 1062 #define BGE_DBG_MII 0x00000020 /* low-level MII access */ 1063 #define BGE_DBG_SEEPROM 0x00000040 /* low-level SEEPROM IO */ 1064 #define BGE_DBG_CHIP 0x00000080 /* low(ish)-level code */ 1065 1066 #define BGE_DBG_RECV 0x00000100 /* receive-side code */ 1067 #define BGE_DBG_SEND 0x00000200 /* packet-send code */ 1068 1069 #define BGE_DBG_INT 0x00001000 /* interrupt handler */ 1070 #define BGE_DBG_FACT 0x00002000 /* factotum (softint) */ 1071 1072 #define BGE_DBG_PHY 0x00010000 /* Copper PHY code */ 1073 #define BGE_DBG_SERDES 0x00020000 /* SerDes code */ 1074 #define BGE_DBG_PHYS 0x00040000 /* Physical layer code */ 1075 #define BGE_DBG_LINK 0x00080000 /* Link status check */ 1076 1077 #define BGE_DBG_INIT 0x00100000 /* initialisation */ 1078 #define BGE_DBG_NEMO 0x00200000 /* nemo interaction */ 1079 #define BGE_DBG_ADDR 0x00400000 /* address-setting code */ 1080 #define BGE_DBG_STATS 0x00800000 /* statistics */ 1081 1082 #define BGE_DBG_IOCTL 0x01000000 /* ioctl handling */ 1083 #define BGE_DBG_LOOP 0x02000000 /* loopback ioctl code */ 1084 #define BGE_DBG_PPIO 0x04000000 /* Peek/poke ioctls */ 1085 #define BGE_DBG_BADIOC 0x08000000 /* unknown ioctls */ 1086 1087 #define BGE_DBG_MCTL 0x10000000 /* mctl (csum) code */ 1088 #define BGE_DBG_NDD 0x20000000 /* NDD operations */ 1089 1090 /* 1091 * Debugging ... 1092 */ 1093 #ifdef DEBUG 1094 #define BGE_DEBUGGING 1 1095 #else 1096 #define BGE_DEBUGGING 0 1097 #endif /* DEBUG */ 1098 1099 1100 /* 1101 * 'Do-if-debugging' macro. The parameter <command> should be one or more 1102 * C statements (but without the *final* semicolon), which will either be 1103 * compiled inline or completely ignored, depending on the BGE_DEBUGGING 1104 * compile-time flag. 1105 * 1106 * You should get a compile-time error (at least on a DEBUG build) if 1107 * your statement isn't actually a statement, rather than unexpected 1108 * run-time behaviour caused by unintended matching of if-then-elses etc. 1109 * 1110 * Note that the BGE_DDB() macro itself can only be used as a statement, 1111 * not an expression, and should always be followed by a semicolon. 1112 */ 1113 #if BGE_DEBUGGING 1114 #define BGE_DDB(command) do { \ 1115 { command; } \ 1116 _NOTE(CONSTANTCONDITION) \ 1117 } while (0) 1118 #else /* BGE_DEBUGGING */ 1119 #define BGE_DDB(command) do { \ 1120 { _NOTE(EMPTY); } \ 1121 _NOTE(CONSTANTCONDITION) \ 1122 } while (0) 1123 #endif /* BGE_DEBUGGING */ 1124 1125 /* 1126 * 'Internal' macros used to construct the TRACE/DEBUG macros below. 1127 * These provide the primitive conditional-call capability required. 1128 * Note: the parameter <args> is a parenthesised list of the actual 1129 * printf-style arguments to be passed to the debug function ... 1130 */ 1131 #define BGE_XDB(b, w, f, args) BGE_DDB(if ((b) & (w)) f args) 1132 #define BGE_GDB(b, args) BGE_XDB(b, bge_debug, (*bge_gdb()), args) 1133 #define BGE_LDB(b, args) BGE_XDB(b, bgep->debug, (*bge_db(bgep)), args) 1134 #define BGE_CDB(f, args) BGE_XDB(BGE_DBG, bgep->debug, f, args) 1135 1136 /* 1137 * Conditional-print macros. 1138 * 1139 * Define BGE_DBG to be the relevant member of the set of BGE_DBG_* values 1140 * above before using the BGE_GDEBUG() or BGE_DEBUG() macros. The 'G' 1141 * versions look at the Global debug flag word (bge_debug); the non-G 1142 * versions look in the per-instance data (bgep->debug) and so require a 1143 * variable called 'bgep' to be in scope (and initialised!) before use. 1144 * 1145 * You could redefine BGE_TRC too if you really need two different 1146 * flavours of debugging output in the same area of code, but I don't 1147 * really recommend it. 1148 * 1149 * Note: the parameter <args> is a parenthesised list of the actual 1150 * arguments to be passed to the debug function, usually a printf-style 1151 * format string and corresponding values to be formatted. 1152 */ 1153 1154 #define BGE_TRC BGE_DBG_TRACE /* default 'trace' bit */ 1155 #define BGE_GTRACE(args) BGE_GDB(BGE_TRC, args) 1156 #define BGE_GDEBUG(args) BGE_GDB(BGE_DBG, args) 1157 #define BGE_TRACE(args) BGE_LDB(BGE_TRC, args) 1158 #define BGE_DEBUG(args) BGE_LDB(BGE_DBG, args) 1159 1160 /* 1161 * Debug-only action macros 1162 */ 1163 #define BGE_BRKPT(bgep, s) BGE_DDB(bge_dbg_enter(bgep, s)) 1164 #define BGE_MARK(bgep) BGE_DDB(bge_led_mark(bgep)) 1165 #define BGE_PCICHK(bgep) BGE_DDB(bge_pci_check(bgep)) 1166 #define BGE_PKTDUMP(args) BGE_DDB(bge_pkt_dump args) 1167 #define BGE_REPORT(args) BGE_DDB(bge_log args) 1168 1169 /* 1170 * Inter-source-file linkage ... 1171 */ 1172 1173 /* bge_chip.c */ 1174 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1175 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t value); 1176 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 1177 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t value); 1178 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1179 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 1180 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t value); 1181 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 1182 int bge_chip_id_init(bge_t *bgep); 1183 int bge_chip_start(bge_t *bgep, boolean_t reset_phy); 1184 void bge_chip_stop(bge_t *bgep, boolean_t fault); 1185 #ifdef BGE_IPMI_ASF 1186 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 1187 #pragma inline(bge_nic_put32) 1188 uint32_t bge_nic_read32(bge_t *bgep, bge_regno_t addr); 1189 void bge_asf_update_status(bge_t *bgep); 1190 void bge_asf_heartbeat(void *bgep); 1191 void bge_asf_stop_timer(bge_t *bgep); 1192 void bge_asf_get_config(bge_t *bgep); 1193 void bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode); 1194 void bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode); 1195 void bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode); 1196 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 1197 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 1198 #else 1199 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 1200 int bge_chip_sync(bge_t *bgep); 1201 #endif 1202 void bge_chip_blank(void *arg, time_t ticks, uint_t count); 1203 uint_t bge_chip_factotum(caddr_t arg); 1204 void bge_chip_cyclic(void *arg); 1205 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 1206 struct iocblk *iocp); 1207 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 1208 extern uint32_t bge_rx_ticks_norm; 1209 extern uint32_t bge_tx_ticks_norm; 1210 extern uint32_t bge_rx_count_norm; 1211 extern uint32_t bge_tx_count_norm; 1212 extern boolean_t bge_jumbo_enable; 1213 void bge_chip_msi_trig(bge_t *bgep); 1214 1215 /* bge_kstats.c */ 1216 void bge_init_kstats(bge_t *bgep, int instance); 1217 void bge_fini_kstats(bge_t *bgep); 1218 int bge_m_stat(void *arg, uint_t stat, uint64_t *val); 1219 1220 /* bge_log.c */ 1221 #if BGE_DEBUGGING 1222 void (*bge_db(bge_t *bgep))(const char *fmt, ...); 1223 void (*bge_gdb(void))(const char *fmt, ...); 1224 void bge_pkt_dump(bge_t *bgep, bge_rbd_t *hbp, sw_rbd_t *sdp, const char *msg); 1225 void bge_dbg_enter(bge_t *bgep, const char *msg); 1226 #endif /* BGE_DEBUGGING */ 1227 void bge_problem(bge_t *bgep, const char *fmt, ...); 1228 void bge_notice(bge_t *bgep, const char *fmt, ...); 1229 void bge_log(bge_t *bgep, const char *fmt, ...); 1230 void bge_error(bge_t *bgep, const char *fmt, ...); 1231 void bge_fm_ereport(bge_t *bgep, char *detail); 1232 extern kmutex_t bge_log_mutex[1]; 1233 extern uint32_t bge_debug; 1234 1235 /* bge_main.c */ 1236 int bge_restart(bge_t *bgep, boolean_t reset_phy); 1237 int bge_check_acc_handle(bge_t *bgep, ddi_acc_handle_t handle); 1238 int bge_check_dma_handle(bge_t *bgep, ddi_dma_handle_t handle); 1239 void bge_init_rings(bge_t *bgep); 1240 void bge_fini_rings(bge_t *bgep); 1241 int bge_alloc_bufs(bge_t *bgep); 1242 void bge_free_bufs(bge_t *bgep); 1243 void bge_intr_enable(bge_t *bgep); 1244 void bge_intr_disable(bge_t *bgep); 1245 1246 /* bge_phys.c */ 1247 int bge_phys_init(bge_t *bgep); 1248 void bge_phys_reset(bge_t *bgep); 1249 int bge_phys_idle(bge_t *bgep); 1250 int bge_phys_update(bge_t *bgep); 1251 boolean_t bge_phys_check(bge_t *bgep); 1252 1253 /* bge_ndd.c */ 1254 int bge_nd_init(bge_t *bgep); 1255 enum ioc_reply bge_nd_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 1256 struct iocblk *iocp); 1257 void bge_nd_cleanup(bge_t *bgep); 1258 1259 /* bge_recv.c */ 1260 void bge_receive(bge_t *bgep, bge_status_t *bsp); 1261 1262 /* bge_send.c */ 1263 mblk_t *bge_m_tx(void *arg, mblk_t *mp); 1264 void bge_recycle(bge_t *bgep, bge_status_t *bsp); 1265 uint_t bge_reschedule(caddr_t arg); 1266 1267 /* bge_atomic_sparc.s/bge_atomic_intel.c */ 1268 uint64_t bge_atomic_reserve(uint64_t *count_p, uint64_t n); 1269 void bge_atomic_renounce(uint64_t *count_p, uint64_t n); 1270 uint64_t bge_atomic_claim(uint64_t *count_p, uint64_t limit); 1271 uint64_t bge_atomic_clr64(uint64_t *sp, uint64_t bits); 1272 uint32_t bge_atomic_shl32(uint32_t *sp, uint_t count); 1273 1274 1275 /* 1276 * Reset type 1277 */ 1278 #define BGE_SHUTDOWN_RESET 0 1279 #define BGE_INIT_RESET 1 1280 #define BGE_SUSPEND_RESET 2 1281 1282 /* For asf_status */ 1283 #define ASF_STAT_NONE 0 1284 #define ASF_STAT_STOP 1 1285 #define ASF_STAT_RUN 2 1286 #define ASF_STAT_RUN_INIT 3 /* attached but don't plumb */ 1287 1288 /* ASF modes for bge_reset() and bge_chip_reset() */ 1289 #define ASF_MODE_NONE 0 /* don't launch asf */ 1290 #define ASF_MODE_SHUTDOWN 1 /* asf shutdown mode */ 1291 #define ASF_MODE_INIT 2 /* asf init mode */ 1292 #define ASF_MODE_POST_SHUTDOWN 3 /* only do post-shutdown */ 1293 #define ASF_MODE_POST_INIT 4 /* only do post-init */ 1294 1295 #define BGE_ASF_HEARTBEAT_INTERVAL 1500000 1296 1297 #ifdef __cplusplus 1298 } 1299 #endif 1300 1301 #endif /* _SYS_BGE_IMPL_H */ 1302