1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _BGE_HW_H 28 #define _BGE_HW_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 38 39 /* 40 * First section: 41 * Identification of the various Broadcom chips 42 * 43 * Note: the various ID values are *not* all unique ;-( 44 * 45 * Note: the presence of an ID here does *not* imply that the chip is 46 * supported. At this time, only the 5703C, 5704C, and 5704S devices 47 * used on the motherboards of certain Sun products are supported. 48 * 49 * Note: the revision-id values in the PCI revision ID register are 50 * *NOT* guaranteed correct. Use the chip ID from the MHCR instead. 51 */ 52 53 #define VENDOR_ID_BROADCOM 0x14e4 54 #define VENDOR_ID_SUN 0x108e 55 56 #define DEVICE_ID_5700 0x1644 57 #define DEVICE_ID_5700x 0x0003 58 #define DEVICE_ID_5701 0x1645 59 #define DEVICE_ID_5702 0x16a6 60 #define DEVICE_ID_5702fe 0x164d 61 #define DEVICE_ID_5703C 0x1647 62 #define DEVICE_ID_5703S 0x16a7 63 #define DEVICE_ID_5703 0x16c7 64 #define DEVICE_ID_5704C 0x1648 65 #define DEVICE_ID_5704S 0x16a8 66 #define DEVICE_ID_5704 0x1649 67 #define DEVICE_ID_5705C 0x1653 68 #define DEVICE_ID_5705_2 0x1654 69 #define DEVICE_ID_5705M 0x165d 70 #define DEVICE_ID_5705MA3 0x165e 71 #define DEVICE_ID_5705F 0x166e 72 #define DEVICE_ID_5706 0x164a 73 #define DEVICE_ID_5782 0x1696 74 #define DEVICE_ID_5788 0x169c 75 #define DEVICE_ID_5789 0x169d 76 #define DEVICE_ID_5751 0x1677 77 #define DEVICE_ID_5751M 0x167d 78 #define DEVICE_ID_5752 0x1600 79 #define DEVICE_ID_5752M 0x1601 80 #define DEVICE_ID_5754 0x167a 81 #define DEVICE_ID_5721 0x1659 82 #define DEVICE_ID_5714C 0x1668 83 #define DEVICE_ID_5714S 0x1669 84 #define DEVICE_ID_5715C 0x1678 85 #define DEVICE_ID_5715S 0x1679 86 87 #define REVISION_ID_5700_B0 0x10 88 #define REVISION_ID_5700_B2 0x12 89 #define REVISION_ID_5700_B3 0x13 90 #define REVISION_ID_5700_C0 0x20 91 #define REVISION_ID_5700_C1 0x21 92 #define REVISION_ID_5700_C2 0x22 93 94 #define REVISION_ID_5701_A0 0x08 95 #define REVISION_ID_5701_A2 0x12 96 #define REVISION_ID_5701_A3 0x15 97 98 #define REVISION_ID_5702_A0 0x00 99 100 #define REVISION_ID_5703_A0 0x00 101 #define REVISION_ID_5703_A1 0x01 102 #define REVISION_ID_5703_A2 0x02 103 104 #define REVISION_ID_5704_A0 0x00 105 #define REVISION_ID_5704_A1 0x01 106 #define REVISION_ID_5704_A2 0x02 107 #define REVISION_ID_5704_A3 0x03 108 #define REVISION_ID_5704_B0 0x10 109 110 #define REVISION_ID_5705_A0 0x00 111 #define REVISION_ID_5705_A1 0x01 112 #define REVISION_ID_5705_A2 0x02 113 #define REVISION_ID_5705_A3 0x03 114 115 #define REVISION_ID_5721_A0 0x00 116 #define REVISION_ID_5721_A1 0x01 117 118 #define REVISION_ID_5751_A0 0x00 119 #define REVISION_ID_5751_A1 0x01 120 121 #define REVISION_ID_5714_A0 0x00 122 #define REVISION_ID_5714_A1 0x01 123 #define REVISION_ID_5714_A2 0xA2 124 #define REVISION_ID_5714_A3 0xA3 125 126 #define REVISION_ID_5715_A0 0x00 127 #define REVISION_ID_5715_A1 0x01 128 #define REVISION_ID_5715_A2 0xA2 129 130 #define REVISION_ID_5715S_A0 0x00 131 #define REVISION_ID_5715S_A1 0x01 132 133 #define REVISION_ID_5754_A0 0x00 134 #define REVISION_ID_5754_A1 0x01 135 136 #define DEVICE_5704_SERIES_CHIPSETS(bgep)\ 137 ((bgep->chipid.device == DEVICE_ID_5700) ||\ 138 (bgep->chipid.device == DEVICE_ID_5701) ||\ 139 (bgep->chipid.device == DEVICE_ID_5702) ||\ 140 (bgep->chipid.device == DEVICE_ID_5702fe)||\ 141 (bgep->chipid.device == DEVICE_ID_5703C) ||\ 142 (bgep->chipid.device == DEVICE_ID_5703S) ||\ 143 (bgep->chipid.device == DEVICE_ID_5703) ||\ 144 (bgep->chipid.device == DEVICE_ID_5704C) ||\ 145 (bgep->chipid.device == DEVICE_ID_5704S) ||\ 146 (bgep->chipid.device == DEVICE_ID_5704)) 147 148 #define DEVICE_5702_SERIES_CHIPSETS(bgep) \ 149 ((bgep->chipid.device == DEVICE_ID_5702) ||\ 150 (bgep->chipid.device == DEVICE_ID_5702fe)) 151 152 #define DEVICE_5705_SERIES_CHIPSETS(bgep) \ 153 ((bgep->chipid.device == DEVICE_ID_5705C) ||\ 154 (bgep->chipid.device == DEVICE_ID_5705M) ||\ 155 (bgep->chipid.device == DEVICE_ID_5705MA3) ||\ 156 (bgep->chipid.device == DEVICE_ID_5705F) ||\ 157 (bgep->chipid.device == DEVICE_ID_5782) ||\ 158 (bgep->chipid.device == DEVICE_ID_5788) ||\ 159 (bgep->chipid.device == DEVICE_ID_5705_2) ||\ 160 (bgep->chipid.device == DEVICE_ID_5754)) 161 162 #define DEVICE_5721_SERIES_CHIPSETS(bgep) \ 163 ((bgep->chipid.device == DEVICE_ID_5721) ||\ 164 (bgep->chipid.device == DEVICE_ID_5751) ||\ 165 (bgep->chipid.device == DEVICE_ID_5751M) ||\ 166 (bgep->chipid.device == DEVICE_ID_5752) ||\ 167 (bgep->chipid.device == DEVICE_ID_5752M) ||\ 168 (bgep->chipid.device == DEVICE_ID_5789)) 169 170 #define DEVICE_5714_SERIES_CHIPSETS(bgep) \ 171 ((bgep->chipid.device == DEVICE_ID_5714C) ||\ 172 (bgep->chipid.device == DEVICE_ID_5714S) ||\ 173 (bgep->chipid.device == DEVICE_ID_5715C) ||\ 174 (bgep->chipid.device == DEVICE_ID_5715S)) 175 176 /* 177 * Second section: 178 * Offsets of important registers & definitions for bits therein 179 */ 180 181 /* 182 * PCI-X registers & bits 183 */ 184 #define PCIX_CONF_COMM 0x42 185 #define PCIX_COMM_RELAXED 0x0002 186 187 /* 188 * Miscellaneous Host Control Register, in PCI config space 189 */ 190 #define PCI_CONF_BGE_MHCR 0x68 191 #define MHCR_CHIP_REV_MASK 0xffff0000 192 #define MHCR_ENABLE_TAGGED_STATUS_MODE 0x00000200 193 #define MHCR_MASK_INTERRUPT_MODE 0x00000100 194 #define MHCR_ENABLE_INDIRECT_ACCESS 0x00000080 195 #define MHCR_ENABLE_REGISTER_WORD_SWAP 0x00000040 196 #define MHCR_ENABLE_CLOCK_CONTROL_WRITE 0x00000020 197 #define MHCR_ENABLE_PCI_STATE_WRITE 0x00000010 198 #define MHCR_ENABLE_ENDIAN_WORD_SWAP 0x00000008 199 #define MHCR_ENABLE_ENDIAN_BYTE_SWAP 0x00000004 200 #define MHCR_MASK_PCI_INT_OUTPUT 0x00000002 201 #define MHCR_CLEAR_INTERRUPT_INTA 0x00000001 202 203 #define MHCR_CHIP_REV_5700_B0 0x71000000 204 #define MHCR_CHIP_REV_5700_B2 0x71020000 205 #define MHCR_CHIP_REV_5700_B3 0x71030000 206 #define MHCR_CHIP_REV_5700_C0 0x72000000 207 #define MHCR_CHIP_REV_5700_C1 0x72010000 208 #define MHCR_CHIP_REV_5700_C2 0x72020000 209 210 #define MHCR_CHIP_REV_5701_A0 0x00000000 211 #define MHCR_CHIP_REV_5701_A2 0x00020000 212 #define MHCR_CHIP_REV_5701_A3 0x00030000 213 #define MHCR_CHIP_REV_5701_A5 0x01050000 214 215 #define MHCR_CHIP_REV_5702_A0 0x10000000 216 #define MHCR_CHIP_REV_5702_A1 0x10010000 217 #define MHCR_CHIP_REV_5702_A2 0x10020000 218 219 #define MHCR_CHIP_REV_5703_A0 0x10000000 220 #define MHCR_CHIP_REV_5703_A1 0x10010000 221 #define MHCR_CHIP_REV_5703_A2 0x10020000 222 #define MHCR_CHIP_REV_5703_B0 0x11000000 223 #define MHCR_CHIP_REV_5703_B1 0x11010000 224 225 #define MHCR_CHIP_REV_5704_A0 0x20000000 226 #define MHCR_CHIP_REV_5704_A1 0x20010000 227 #define MHCR_CHIP_REV_5704_A2 0x20020000 228 #define MHCR_CHIP_REV_5704_A3 0x20030000 229 #define MHCR_CHIP_REV_5704_B0 0x21000000 230 231 #define MHCR_CHIP_REV_5705_A0 0x30000000 232 #define MHCR_CHIP_REV_5705_A1 0x30010000 233 #define MHCR_CHIP_REV_5705_A2 0x30020000 234 #define MHCR_CHIP_REV_5705_A3 0x30030000 235 #define MHCR_CHIP_REV_5705_A5 0x30050000 236 237 #define MHCR_CHIP_REV_5782_A0 0x30030000 238 #define MHCR_CHIP_REV_5782_A1 0x30030088 239 240 #define MHCR_CHIP_REV_5788_A1 0x30050000 241 242 #define MHCR_CHIP_REV_5751_A0 0x40000000 243 #define MHCR_CHIP_REV_5751_A1 0x40010000 244 245 #define MHCR_CHIP_REV_5721_A0 0x41000000 246 #define MHCR_CHIP_REV_5721_A1 0x41010000 247 248 #define MHCR_CHIP_REV_5714_A0 0x50000000 249 #define MHCR_CHIP_REV_5714_A1 0x90010000 250 251 #define MHCR_CHIP_REV_5715_A0 0x50000000 252 #define MHCR_CHIP_REV_5715_A1 0x90010000 253 254 #define MHCR_CHIP_REV_5715S_A0 0x50000000 255 #define MHCR_CHIP_REV_5715S_A1 0x90010000 256 257 #define MHCR_CHIP_REV_5754_A0 0xb0000000 258 #define MHCR_CHIP_REV_5754_A1 0xb0010000 259 260 #define MHCR_CHIP_ASIC_REV(ChipRevId) ((ChipRevId) & 0xf0000000) 261 #define MHCR_CHIP_ASIC_REV_5700 (0x7 << 28) 262 #define MHCR_CHIP_ASIC_REV_5701 (0x0 << 28) 263 #define MHCR_CHIP_ASIC_REV_5703 (0x1 << 28) 264 #define MHCR_CHIP_ASIC_REV_5704 (0x2 << 28) 265 #define MHCR_CHIP_ASIC_REV_5705 (0x3 << 28) 266 #define MHCR_CHIP_ASIC_REV_5721_5751 (0x4 << 28) 267 #define MHCR_CHIP_ASIC_REV_5714 (0x5 << 28) 268 #define MHCR_CHIP_ASIC_REV_5752 (0x6 << 28) 269 #define MHCR_CHIP_ASIC_REV_5754 (0xb << 28) 270 #define MHCR_CHIP_ASIC_REV_5715 ((uint32_t)0x9 << 28) 271 272 273 /* 274 * PCI DMA read/write Control Register, in PCI config space 275 * 276 * Note that several fields previously defined here have been deleted 277 * as they are not implemented in the 5703/4. 278 * 279 * Note: the value of this register is critical. It is possible to 280 * cause various unpleasant effects (DTOs, transaction deadlock, etc) 281 * by programming the wrong value. The value #defined below has been 282 * tested and shown to avoid all known problems. If it is to be changed, 283 * correct operation must be reverified on all supported platforms. 284 * 285 * In particular, we set both watermark fields to 2xCacheLineSize (128) 286 * bytes and DMA_MIN_BEATS to 0 in order to avoid unfortunate interactions 287 * with Tomatillo's internal pipelines, that otherwise result in stalls, 288 * repeated retries, and DTOs. 289 */ 290 #define PCI_CONF_BGE_PDRWCR 0x6c 291 #define PDRWCR_RWCMD_MASK 0xFF000000 292 #define PDRWCR_PCIX32_BUGFIX_MASK 0x00800000 293 #define PDRWCR_WRITE_WATERMARK_MASK 0x00380000 294 #define PDRWCR_READ_WATERMARK_MASK 0x00070000 295 #define PDRWCR_CONCURRENCY_MASK 0x0000c000 296 #define PDRWCR_5704_FLOP_ON_RETRY 0x00008000 297 #define PDRWCR_ONE_DMA_AT_ONCE 0x00004000 298 #define PDRWCR_MIN_BEAT_MASK 0x000000ff 299 300 /* 301 * These are the actual values to be put into the fields shown above 302 */ 303 #define PDRWCR_RWCMDS 0x76000000 /* MW and MR */ 304 #define PDRWCR_DMA_WRITE_WATERMARK 0x00180000 /* 011 => 128 */ 305 #define PDRWCR_DMA_READ_WATERMARK 0x00030000 /* 011 => 128 */ 306 #define PDRWCR_MIN_BEATS 0x00000000 307 308 #define PDRWCR_VAR_DEFAULT 0x761b0000 309 #define PDRWCR_VAR_5721 0x76180000 310 #define PDRWCR_VAR_5714 0x76148000 /* OR of above */ 311 #define PDRWCR_VAR_5715 0x76144000 /* OR of above */ 312 313 /* 314 * PCI State Register, in PCI config space 315 * 316 * Note: this register is read-only unless the ENABLE_PCI_STATE_WRITE bit 317 * is set in the MHCR, EXCEPT for the RETRY_SAME_DMA bit which is always RW 318 */ 319 #define PCI_CONF_BGE_PCISTATE 0x70 320 #define PCISTATE_RETRY_SAME_DMA 0x00002000 321 #define PCISTATE_FLAT_VIEW 0x00000100 322 #define PCISTATE_EXT_ROM_RETRY 0x00000040 323 #define PCISTATE_EXT_ROM_ENABLE 0x00000020 324 #define PCISTATE_BUS_IS_32_BIT 0x00000010 325 #define PCISTATE_BUS_IS_FAST 0x00000008 326 #define PCISTATE_BUS_IS_PCI 0x00000004 327 #define PCISTATE_INTA_STATE 0x00000002 328 #define PCISTATE_FORCE_RESET 0x00000001 329 330 /* 331 * PCI Clock Control Register, in PCI config space 332 */ 333 #define PCI_CONF_BGE_CLKCTL 0x74 334 #define CLKCTL_PCIE_PLP_DISABLE 0x80000000 335 #define CLKCTL_PCIE_DLP_DISABLE 0x40000000 336 #define CLKCTL_PCIE_TLP_DISABLE 0x20000000 337 #define CLKCTL_PCI_READ_TOO_LONG_FIX 0x04000000 338 #define CLKCTL_PCI_WRITE_TOO_LONG_FIX 0x02000000 339 #define CLKCTL_PCIE_A0_FIX 0x00101000 340 341 /* 342 * Dual MAC Control Register, in PCI config space 343 */ 344 #define PCI_CONF_BGE_DUAL_MAC_CONTROL 0xB8 345 #define DUALMAC_CHANNEL_CONTROL_MASK 0x00000003 /* RW */ 346 #define DUALMAC_CHANNEL_ID_MASK 0x00000004 /* RO */ 347 348 /* 349 * Register Indirect Access Address Register, 0x78 in PCI config 350 * space. Once this is set, accesses to the Register Indirect 351 * Access Data Register (0x80) refer to the register whose address 352 * is given by *this* register. This allows access to all the 353 * operating registers, while using only config space accesses. 354 * 355 * Note that the address written to the RIIAR should lie in one 356 * of the following ranges: 357 * 0x00000000 <= address < 0x00008000 (regular registers) 358 * 0x00030000 <= address < 0x00034000 (RxRISC scratchpad) 359 * 0x00034000 <= address < 0x00038000 (TxRISC scratchpad) 360 * 0x00038000 <= address < 0x00038800 (RxRISC ROM) 361 */ 362 #define PCI_CONF_BGE_RIAAR 0x78 363 #define PCI_CONF_BGE_RIADR 0x80 364 365 #define RIAAR_REGISTER_MIN 0x00000000 366 #define RIAAR_REGISTER_MAX 0x00008000 367 #define RIAAR_RX_SCRATCH_MIN 0x00030000 368 #define RIAAR_RX_SCRATCH_MAX 0x00034000 369 #define RIAAR_TX_SCRATCH_MIN 0x00034000 370 #define RIAAR_TX_SCRATCH_MAX 0x00038000 371 #define RIAAR_RXROM_MIN 0x00038000 372 #define RIAAR_RXROM_MAX 0x00038800 373 374 /* 375 * Memory Window Base Address Register, 0x7c in PCI config space 376 * Once this is set, accesses to the Memory Window Data Access Register 377 * (0x84) refer to the word of NIC-local memory whose address is given 378 * by this register. When used in this way, the whole of the address 379 * written to this register is significant. 380 * 381 * This register also provides the 32K-aligned base address for a 32K 382 * region of NIC-local memory that the host can directly address in 383 * the upper 32K of the 64K of PCI memory space allocated to the chip. 384 * In this case, the bottom 15 bits of the register are ignored. 385 * 386 * Note that the address written to the MWBAR should lie in the range 387 * 0x00000000 <= address < 0x00020000. The rest of the range up to 1M 388 * (i.e. 0x00200000 <= address < 0x01000000) would be valid if external 389 * memory were present, but it's only supported on the 5700, not the 390 * 5701/5703/5704. 391 */ 392 #define PCI_CONF_BGE_MWBAR 0x7c 393 #define PCI_CONF_BGE_MWDAR 0x84 394 #define MWBAR_GRANULARITY 0x00008000 /* 32k */ 395 #define MWBAR_GRANULE_MASK (MWBAR_GRANULARITY-1) 396 #define MWBAR_ONCHIP_MAX 0x00020000 /* 128k */ 397 398 /* 399 * The PCI express device control register and device status register 400 * which are only applicable on BCM5751 and BCM5721. 401 */ 402 #define PCI_CONF_DEV_CTRL 0xd8 403 #define READ_REQ_SIZE_MAX 0x5000 404 #define DEV_CTRL_NO_SNOOP 0x0800 405 #define DEV_CTRL_RELAXED 0x0010 406 407 #define PCI_CONF_DEV_STUS 0xda 408 #define DEVICE_ERROR_STUS 0xf 409 410 #define NIC_MEM_WINDOW_OFFSET 0x00008000 /* 32k */ 411 412 /* 413 * Where to find things in NIC-local (on-chip) memory 414 */ 415 #define NIC_MEM_SEND_RINGS 0x0100 416 #define NIC_MEM_SEND_RING(ring) (0x0100+16*(ring)) 417 #define NIC_MEM_RECV_RINGS 0x0200 418 #define NIC_MEM_RECV_RING(ring) (0x0200+16*(ring)) 419 #define NIC_MEM_STATISTICS 0x0300 420 #define NIC_MEM_STATISTICS_SIZE 0x0800 421 #define NIC_MEM_STATUS_BLOCK 0x0b00 422 #define NIC_MEM_STATUS_SIZE 0x0050 423 #define NIC_MEM_GENCOMM 0x0b50 424 425 426 /* 427 * Note: the (non-bogus) values below are appropriate for systems 428 * without external memory. They would be different on a 5700 with 429 * external memory. 430 * 431 * Note: The higher send ring addresses and the mini ring shadow 432 * buffer address are dummies - systems without external memory 433 * are limited to 4 send rings and no mini receive ring. 434 */ 435 #define NIC_MEM_SHADOW_DMA 0x2000 436 #define NIC_MEM_SHADOW_SEND_1_4 0x4000 437 #define NIC_MEM_SHADOW_SEND_5_6 0x6000 /* bogus */ 438 #define NIC_MEM_SHADOW_SEND_7_8 0x7000 /* bogus */ 439 #define NIC_MEM_SHADOW_SEND_9_16 0x8000 /* bogus */ 440 #define NIC_MEM_SHADOW_BUFF_STD 0x6000 441 #define NIC_MEM_SHADOW_BUFF_JUMBO 0x7000 442 #define NIC_MEM_SHADOW_BUFF_MINI 0x8000 /* bogus */ 443 #define NIC_MEM_SHADOW_SEND_RING(ring, nslots) (0x4000 + 4*(ring)*(nslots)) 444 445 /* 446 * Put this in the GENCOMM port to tell the firmware not to run PXE 447 */ 448 #define T3_MAGIC_NUMBER 0x4b657654u 449 450 /* 451 * The remaining registers appear in the low 32K of regular 452 * PCI Memory Address Space 453 */ 454 455 /* 456 * All the state machine control registers below have at least a 457 * <RESET> bit and an <ENABLE> bit as defined below. Some also 458 * have an <ATTN_ENABLE> bit. 459 */ 460 #define STATE_MACHINE_ATTN_ENABLE_BIT 0x00000004 461 #define STATE_MACHINE_ENABLE_BIT 0x00000002 462 #define STATE_MACHINE_RESET_BIT 0x00000001 463 464 #define TRANSMIT_MAC_MODE_REG 0x045c 465 #define SEND_DATA_INITIATOR_MODE_REG 0x0c00 466 #define SEND_DATA_COMPLETION_MODE_REG 0x1000 467 #define SEND_BD_SELECTOR_MODE_REG 0x1400 468 #define SEND_BD_INITIATOR_MODE_REG 0x1800 469 #define SEND_BD_COMPLETION_MODE_REG 0x1c00 470 471 #define RECEIVE_MAC_MODE_REG 0x0468 472 #define RCV_LIST_PLACEMENT_MODE_REG 0x2000 473 #define RCV_DATA_BD_INITIATOR_MODE_REG 0x2400 474 #define RCV_DATA_COMPLETION_MODE_REG 0x2800 475 #define RCV_BD_INITIATOR_MODE_REG 0x2c00 476 #define RCV_BD_COMPLETION_MODE_REG 0x3000 477 #define RCV_LIST_SELECTOR_MODE_REG 0x3400 478 479 #define MBUF_CLUSTER_FREE_MODE_REG 0x3800 480 #define HOST_COALESCE_MODE_REG 0x3c00 481 #define MEMORY_ARBITER_MODE_REG 0x4000 482 #define BUFFER_MANAGER_MODE_REG 0x4400 483 #define READ_DMA_MODE_REG 0x4800 484 #define WRITE_DMA_MODE_REG 0x4c00 485 #define DMA_COMPLETION_MODE_REG 0x6400 486 487 /* 488 * Other bits in some of the above state machine control registers 489 */ 490 491 /* 492 * Transmit MAC Mode Register 493 * (TRANSMIT_MAC_MODE_REG, 0x045c) 494 */ 495 #define TRANSMIT_MODE_LONG_PAUSE 0x00000040 496 #define TRANSMIT_MODE_BIG_BACKOFF 0x00000020 497 #define TRANSMIT_MODE_FLOW_CONTROL 0x00000010 498 499 /* 500 * Receive MAC Mode Register 501 * (RECEIVE_MAC_MODE_REG, 0x0468) 502 */ 503 #define RECEIVE_MODE_KEEP_VLAN_TAG 0x00000400 504 #define RECEIVE_MODE_NO_CRC_CHECK 0x00000200 505 #define RECEIVE_MODE_PROMISCUOUS 0x00000100 506 #define RECEIVE_MODE_LENGTH_CHECK 0x00000080 507 #define RECEIVE_MODE_ACCEPT_RUNTS 0x00000040 508 #define RECEIVE_MODE_ACCEPT_OVERSIZE 0x00000020 509 #define RECEIVE_MODE_KEEP_PAUSE 0x00000010 510 #define RECEIVE_MODE_FLOW_CONTROL 0x00000004 511 512 /* 513 * Receive BD Initiator Mode Register 514 * (RCV_BD_INITIATOR_MODE_REG, 0x2c00) 515 * 516 * Each of these bits controls whether ATTN is asserted 517 * on a particular condition 518 */ 519 #define RCV_BD_DISABLED_RING_ATTN 0x00000004 520 521 /* 522 * Receive Data & Receive BD Initiator Mode Register 523 * (RCV_DATA_BD_INITIATOR_MODE_REG, 0x2400) 524 * 525 * Each of these bits controls whether ATTN is asserted 526 * on a particular condition 527 */ 528 #define RCV_DATA_BD_ILL_RING_ATTN 0x00000010 529 #define RCV_DATA_BD_FRAME_SIZE_ATTN 0x00000008 530 #define RCV_DATA_BD_NEED_JUMBO_ATTN 0x00000004 531 532 #define RCV_DATA_BD_ALL_ATTN_BITS 0x0000001c 533 534 /* 535 * Host Coalescing Mode Control Register 536 * (HOST_COALESCE_MODE_REG, 0x3c00) 537 */ 538 #define COALESCE_64_BYTE_RINGS 12 539 #define COALESCE_NO_INT_ON_COAL_FORCE 0x00001000 540 #define COALESCE_NO_INT_ON_DMAD_FORCE 0x00000800 541 #define COALESCE_CLR_TICKS_TX 0x00000400 542 #define COALESCE_CLR_TICKS_RX 0x00000200 543 #define COALESCE_32_BYTE_STATUS 0x00000100 544 #define COALESCE_64_BYTE_STATUS 0x00000080 545 #define COALESCE_NOW 0x00000008 546 547 /* 548 * Buffer Manager Mode Register 549 * (BUFFER_MANAGER_MODE_REG, 0x4400) 550 * 551 * In addition to the usual error-attn common to most state machines 552 * this register has a separate bit for attn on running-low-on-mbufs 553 */ 554 #define BUFF_MGR_TEST_MODE 0x00000008 555 #define BUFF_MGR_MBUF_LOW_ATTN_ENABLE 0x00000010 556 557 #define BUFF_MGR_ALL_ATTN_BITS 0x00000014 558 559 /* 560 * Read and Write DMA Mode Registers (READ_DMA_MODE_REG, 561 * 0x4800 and WRITE_DMA_MODE_REG, 0x4c00) 562 * 563 * These registers each contain a 2-bit priority field, which controls 564 * the relative priority of that type of DMA (read vs. write vs. MSI), 565 * and a set of bits that control whether ATTN is asserted on each 566 * particular condition 567 */ 568 #define DMA_PRIORITY_MASK 0xc0000000 569 #define DMA_PRIORITY_SHIFT 30 570 #define ALL_DMA_ATTN_BITS 0x000003fc 571 572 /* 573 * End of state machine control register definitions 574 */ 575 576 577 /* 578 * Mailbox Registers (8 bytes each, but high half unused) 579 */ 580 #define INTERRUPT_MBOX_0_REG 0x0200 581 #define INTERRUPT_MBOX_1_REG 0x0208 582 #define INTERRUPT_MBOX_2_REG 0x0210 583 #define INTERRUPT_MBOX_3_REG 0x0218 584 #define INTERRUPT_MBOX_REG(n) (0x0200+8*(n)) 585 586 /* 587 * Ring Producer/Consumer Index (Mailbox) Registers 588 */ 589 #define RECV_STD_PROD_INDEX_REG 0x0268 590 #define RECV_JUMBO_PROD_INDEX_REG 0x0270 591 #define RECV_MINI_PROD_INDEX_REG 0x0278 592 #define RECV_RING_CONS_INDEX_REGS 0x0280 593 #define SEND_RING_HOST_PROD_INDEX_REGS 0x0300 594 #define SEND_RING_NIC_PROD_INDEX_REGS 0x0380 595 596 #define RECV_RING_CONS_INDEX_REG(ring) (0x0280+8*(ring)) 597 #define SEND_RING_HOST_INDEX_REG(ring) (0x0300+8*(ring)) 598 #define SEND_RING_NIC_INDEX_REG(ring) (0x0380+8*(ring)) 599 600 /* 601 * Ethernet MAC Mode Register 602 */ 603 #define ETHERNET_MAC_MODE_REG 0x0400 604 #define ETHERNET_MODE_ENABLE_FHDE 0x00800000 605 #define ETHERNET_MODE_ENABLE_RDE 0x00400000 606 #define ETHERNET_MODE_ENABLE_TDE 0x00200000 607 #define ETHERNET_MODE_ENABLE_MIP 0x00100000 608 #define ETHERNET_MODE_ENABLE_ACPI 0x00080000 609 #define ETHERNET_MODE_ENABLE_MAGIC_PKT 0x00040000 610 #define ETHERNET_MODE_SEND_CFGS 0x00020000 611 #define ETHERNET_MODE_FLUSH_TX_STATS 0x00010000 612 #define ETHERNET_MODE_CLEAR_TX_STATS 0x00008000 613 #define ETHERNET_MODE_ENABLE_TX_STATS 0x00004000 614 #define ETHERNET_MODE_FLUSH_RX_STATS 0x00002000 615 #define ETHERNET_MODE_CLEAR_RX_STATS 0x00001000 616 #define ETHERNET_MODE_ENABLE_RX_STATS 0x00000800 617 #define ETHERNET_MODE_LINK_POLARITY 0x00000400 618 #define ETHERNET_MODE_MAX_DEFER 0x00000200 619 #define ETHERNET_MODE_ENABLE_TX_BURST 0x00000100 620 #define ETHERNET_MODE_TAGGED_MODE 0x00000080 621 #define ETHERNET_MODE_MAC_LOOPBACK 0x00000010 622 #define ETHERNET_MODE_PORTMODE_MASK 0x0000000c 623 #define ETHERNET_MODE_PORTMODE_TBI 0x0000000c 624 #define ETHERNET_MODE_PORTMODE_GMII 0x00000008 625 #define ETHERNET_MODE_PORTMODE_MII 0x00000004 626 #define ETHERNET_MODE_PORTMODE_NONE 0x00000000 627 #define ETHERNET_MODE_HALF_DUPLEX 0x00000002 628 #define ETHERNET_MODE_GLOBAL_RESET 0x00000001 629 630 /* 631 * Ethernet MAC Status & Event Registers 632 */ 633 #define ETHERNET_MAC_STATUS_REG 0x0404 634 #define ETHERNET_STATUS_MI_INT 0x00800000 635 #define ETHERNET_STATUS_MI_COMPLETE 0x00400000 636 #define ETHERNET_STATUS_LINK_CHANGED 0x00001000 637 #define ETHERNET_STATUS_PCS_ERROR 0x00000400 638 #define ETHERNET_STATUS_SYNC_CHANGED 0x00000010 639 #define ETHERNET_STATUS_CFG_CHANGED 0x00000008 640 #define ETHERNET_STATUS_RECEIVING_CFG 0x00000004 641 #define ETHERNET_STATUS_SIGNAL_DETECT 0x00000002 642 #define ETHERNET_STATUS_PCS_SYNCHED 0x00000001 643 644 #define ETHERNET_MAC_EVENT_ENABLE_REG 0x0408 645 #define ETHERNET_EVENT_MI_INT 0x00800000 646 #define ETHERNET_EVENT_LINK_INT 0x00001000 647 #define ETHERNET_STATUS_PCS_ERROR_INT 0x00000400 648 649 /* 650 * Ethernet MAC LED Control Register 651 * 652 * NOTE: PHY mode 1 *MUST* be selected; this is the hardware default and 653 * the external LED driver circuitry is wired up to assume that this mode 654 * will always be selected. Software must not change it! 655 */ 656 #define ETHERNET_MAC_LED_CONTROL_REG 0x040c 657 #define LED_CONTROL_OVERRIDE_BLINK 0x80000000 658 #define LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000 659 #define LED_CONTROL_LED_MODE_MASK 0x00001800 660 #define LED_CONTROL_LED_MODE_5700 0x00000000 661 #define LED_CONTROL_LED_MODE_PHY_1 0x00000800 /* mandatory */ 662 #define LED_CONTROL_LED_MODE_PHY_2 0x00001000 663 #define LED_CONTROL_LED_MODE_RESERVED 0x00001800 664 #define LED_CONTROL_TRAFFIC_LED_STATUS 0x00000400 665 #define LED_CONTROL_10MBPS_LED_STATUS 0x00000200 666 #define LED_CONTROL_100MBPS_LED_STATUS 0x00000100 667 #define LED_CONTROL_1000MBPS_LED_STATUS 0x00000080 668 #define LED_CONTROL_BLINK_TRAFFIC 0x00000040 669 #define LED_CONTROL_TRAFFIC_LED 0x00000020 670 #define LED_CONTROL_OVERRIDE_TRAFFIC 0x00000010 671 #define LED_CONTROL_10MBPS_LED 0x00000008 672 #define LED_CONTROL_100MBPS_LED 0x00000004 673 #define LED_CONTROL_1000MBPS_LED 0x00000002 674 #define LED_CONTROL_OVERRIDE_LINK 0x00000001 675 #define LED_CONTROL_DEFAULT 0x02000800 676 677 /* 678 * MAC Address registers 679 * 680 * These four eight-byte registers each hold one unicast address 681 * (six bytes), right justified & zero-filled on the left. 682 * They will normally all be set to the same value, as a station 683 * usually only has one h/w address. The value in register 0 is 684 * used for pause packets; any of the four can be specified for 685 * substitution into other transmitted packets if required. 686 */ 687 #define MAC_ADDRESS_0_REG 0x0410 688 #define MAC_ADDRESS_1_REG 0x0418 689 #define MAC_ADDRESS_2_REG 0x0420 690 #define MAC_ADDRESS_3_REG 0x0428 691 692 #define MAC_ADDRESS_REG(n) (0x0410+8*(n)) 693 #define MAC_ADDRESS_REGS_MAX 4 694 695 /* 696 * More MAC Registers ... 697 */ 698 #define MAC_TX_RANDOM_BACKOFF_REG 0x0438 699 #define MAC_RX_MTU_SIZE_REG 0x043c 700 #define MAC_RX_MTU_DEFAULT 0x000005f2 /* 1522 */ 701 #define MAC_TX_LENGTHS_REG 0x0464 702 #define MAC_TX_LENGTHS_DEFAULT 0x00002620 703 704 /* 705 * MII access registers 706 */ 707 #define MI_COMMS_REG 0x044c 708 #define MI_COMMS_START 0x20000000 709 #define MI_COMMS_READ_FAILED 0x10000000 710 #define MI_COMMS_COMMAND_MASK 0x0c000000 711 #define MI_COMMS_COMMAND_READ 0x08000000 712 #define MI_COMMS_COMMAND_WRITE 0x04000000 713 #define MI_COMMS_ADDRESS_MASK 0x03e00000 714 #define MI_COMMS_ADDRESS_SHIFT 21 715 #define MI_COMMS_REGISTER_MASK 0x001f0000 716 #define MI_COMMS_REGISTER_SHIFT 16 717 #define MI_COMMS_DATA_MASK 0x0000ffff 718 #define MI_COMMS_DATA_SHIFT 0 719 720 #define MI_STATUS_REG 0x0450 721 #define MI_STATUS_10MBPS 0x00000002 722 #define MI_STATUS_LINK 0x00000001 723 724 #define MI_MODE_REG 0x0454 725 #define MI_MODE_CLOCK_MASK 0x001f0000 726 #define MI_MODE_AUTOPOLL 0x00000010 727 #define MI_MODE_POLL_SHORT_PREAMBLE 0x00000002 728 #define MI_MODE_DEFAULT 0x000c0000 729 730 #define MI_AUTOPOLL_STATUS_REG 0x0458 731 #define MI_AUTOPOLL_ERROR 0x00000001 732 733 #define TRANSMIT_MAC_STATUS_REG 0x0460 734 #define TRANSMIT_STATUS_ODI_OVERRUN 0x00000020 735 #define TRANSMIT_STATUS_ODI_UNDERRUN 0x00000010 736 #define TRANSMIT_STATUS_LINK_UP 0x00000008 737 #define TRANSMIT_STATUS_SENT_XON 0x00000004 738 #define TRANSMIT_STATUS_SENT_XOFF 0x00000002 739 #define TRANSMIT_STATUS_RCVD_XOFF 0x00000001 740 741 #define RECEIVE_MAC_STATUS_REG 0x046c 742 #define RECEIVE_STATUS_RCVD_XON 0x00000004 743 #define RECEIVE_STATUS_RCVD_XOFF 0x00000002 744 #define RECEIVE_STATUS_SENT_XOFF 0x00000001 745 746 /* 747 * These four-byte registers constitute a hash table for deciding 748 * whether to accept incoming multicast packets. The bits are 749 * numbered in big-endian fashion, from hash 0 => the MSB of 750 * register 0 to hash 127 => the LSB of the highest-numbered 751 * register. 752 * 753 * NOTE: the 5704 can use a 256-bit table (registers 0-7) if 754 * enabled by setting the appropriate bit in the Rx MAC mode 755 * register. Otherwise, and on all earlier chips, the table 756 * is only 128 bits (registers 0-3). 757 */ 758 #define MAC_HASH_0_REG 0x0470 759 #define MAC_HASH_1_REG 0x0474 760 #define MAC_HASH_2_REG 0x0478 761 #define MAC_HASH_3_REG 0x047c 762 #define MAC_HASH_4_REG 0x???? 763 #define MAC_HASH_5_REG 0x???? 764 #define MAC_HASH_6_REG 0x???? 765 #define MAC_HASH_7_REG 0x???? 766 #define MAC_HASH_REG(n) (0x470+4*(n)) 767 768 /* 769 * Receive Rules Registers: 16 pairs of control+mask/value pairs 770 */ 771 #define RCV_RULES_CONTROL_0_REG 0x0480 772 #define RCV_RULES_MASK_0_REG 0x0484 773 #define RCV_RULES_CONTROL_15_REG 0x04f8 774 #define RCV_RULES_MASK_15_REG 0x04fc 775 #define RCV_RULES_CONFIG_REG 0x0500 776 #define RCV_RULES_CONFIG_DEFAULT 0x00000008 777 778 #define RECV_RULES_NUM_MAX 16 779 #define RECV_RULE_CONTROL_REG(rule) (RCV_RULES_CONTROL_0_REG+8*(rule)) 780 #define RECV_RULE_MASK_REG(rule) (RCV_RULES_MASK_0_REG+8*(rule)) 781 782 #define RECV_RULE_CTL_ENABLE 0x80000000 783 #define RECV_RULE_CTL_AND 0x40000000 784 #define RECV_RULE_CTL_P1 0x20000000 785 #define RECV_RULE_CTL_P2 0x10000000 786 #define RECV_RULE_CTL_P3 0x08000000 787 #define RECV_RULE_CTL_MASK 0x04000000 788 #define RECV_RULE_CTL_DISCARD 0x02000000 789 #define RECV_RULE_CTL_MAP 0x01000000 790 #define RECV_RULE_CTL_RESV_BITS 0x00fc0000 791 #define RECV_RULE_CTL_OP 0x00030000 792 #define RECV_RULE_CTL_OP_EQ 0x00000000 793 #define RECV_RULE_CTL_OP_NEQ 0x00010000 794 #define RECV_RULE_CTL_OP_GREAT 0x00020000 795 #define RECV_RULE_CTL_OP_LESS 0x00030000 796 #define RECV_RULE_CTL_HEADER 0x0000e000 797 #define RECV_RULE_CTL_HEADER_FRAME 0x00000000 798 #define RECV_RULE_CTL_HEADER_IP 0x00002000 799 #define RECV_RULE_CTL_HEADER_TCP 0x00004000 800 #define RECV_RULE_CTL_HEADER_UDP 0x00006000 801 #define RECV_RULE_CTL_HEADER_DATA 0x00008000 802 #define RECV_RULE_CTL_CLASS_BITS 0x00001f00 803 #define RECV_RULE_CTL_CLASS(ring) (((ring) << 8) & \ 804 RECV_RULE_CTL_CLASS_BITS) 805 #define RECV_RULE_CTL_OFFSET 0x000000ff 806 807 /* 808 * Receive Rules definition 809 */ 810 #define RULE_MATCH_TO_RING 2 811 /* ring that traffic will go into when recv rule matches. */ 812 /* value is between 1 and 16, not 0 and 15 */ 813 814 #define IPHEADER_PROTO_OFFSET 0x08 815 #define IPHEADER_SIP_OFFSET 0x0c 816 817 #define RULE_PROTO_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_MASK | \ 818 RECV_RULE_CTL_OP_EQ | \ 819 RECV_RULE_CTL_HEADER_IP | \ 820 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 821 IPHEADER_PROTO_OFFSET) 822 #define RULE_TCP_MASK_VALUE 0x00ff0006 823 #define RULE_UDP_MASK_VALUE 0x00ff0011 824 #define RULE_ICMP_MASK_VALUE 0x00ff0001 825 826 #define RULE_SIP_ADDR 0x0a000001 827 /* ip address in 32-bit integer,such as, 0x0a000001 is "10.0.0.1" */ 828 829 #define RULE_SIP_CONTROL (RECV_RULE_CTL_ENABLE | RECV_RULE_CTL_OP_EQ | \ 830 RECV_RULE_CTL_HEADER_IP | \ 831 RECV_RULE_CTL_CLASS(RULE_MATCH_TO_RING) | \ 832 IPHEADER_SIP_OFFSET) 833 #define RULE_SIP_MASK_VALUE RULE_SIP_ADDR 834 835 /* 836 * 1000BaseX low-level access registers 837 */ 838 #define MAC_GIGABIT_PCS_TEST_REG 0x0440 839 #define MAC_GIGABIT_PCS_TEST_ENABLE 0x00100000 840 #define MAC_GIGABIT_PCS_TEST_PATTERN 0x000fffff 841 #define TX_1000BASEX_AUTONEG_REG 0x0444 842 #define RX_1000BASEX_AUTONEG_REG 0x0448 843 844 /* 845 * Autoneg code bits for the 1000BASE-X AUTONEG registers 846 */ 847 #define AUTONEG_CODE_PAUSE 0x00008000 848 #define AUTONEG_CODE_HALF_DUPLEX 0x00004000 849 #define AUTONEG_CODE_FULL_DUPLEX 0x00002000 850 #define AUTONEG_CODE_NEXT_PAGE 0x00000080 851 #define AUTONEG_CODE_ACKNOWLEDGE 0x00000040 852 #define AUTONEG_CODE_FAULT_MASK 0x00000030 853 #define AUTONEG_CODE_FAULT_ANEG_ERR 0x00000030 854 #define AUTONEG_CODE_FAULT_LINK_FAIL 0x00000020 855 #define AUTONEG_CODE_FAULT_OFFLINE 0x00000010 856 #define AUTONEG_CODE_ASYM_PAUSE 0x00000001 857 858 /* 859 * SerDes Registers (5703S/5704S only) 860 */ 861 #define SERDES_CONTROL_REG 0x0590 862 #define SERDES_CONTROL_TBI_LOOPBACK 0x00020000 863 #define SERDES_CONTROL_COMMA_DETECT 0x00010000 864 #define SERDES_CONTROL_TX_DISABLE 0x00004000 865 #define SERDES_STATUS_REG 0x0594 866 #define SERDES_STATUS_COMMA_DETECTED 0x00000100 867 #define SERDES_STATUS_RXSTAT 0x000000ff 868 869 /* 870 * Statistic Registers (5705/5788/5721/5751/5752/5714/5715 only) 871 */ 872 #define STAT_IFHCOUT_OCTETS_REG 0x0800 873 #define STAT_ETHER_COLLIS_REG 0x0808 874 #define STAT_OUTXON_SENT_REG 0x080c 875 #define STAT_OUTXOFF_SENT_REG 0x0810 876 #define STAT_DOT3_INTMACTX_ERR_REG 0x0818 877 #define STAT_DOT3_SCOLLI_FRAME_REG 0x081c 878 #define STAT_DOT3_MCOLLI_FRAME_REG 0x0820 879 #define STAT_DOT3_DEFERED_TX_REG 0x0824 880 #define STAT_DOT3_EXCE_COLLI_REG 0x082c 881 #define STAT_DOT3_LATE_COLLI_REG 0x0830 882 #define STAT_IFHCOUT_UPKGS_REG 0x086c 883 #define STAT_IFHCOUT_MPKGS_REG 0x0870 884 #define STAT_IFHCOUT_BPKGS_REG 0x0874 885 886 #define STAT_IFHCIN_OCTETS_REG 0x0880 887 #define STAT_ETHER_FRAGMENT_REG 0x0888 888 #define STAT_IFHCIN_UPKGS_REG 0x088c 889 #define STAT_IFHCIN_MPKGS_REG 0x0890 890 #define STAT_IFHCIN_BPKGS_REG 0x0894 891 892 #define STAT_DOT3_FCS_ERR_REG 0x0898 893 #define STAT_DOT3_ALIGN_ERR_REG 0x089c 894 #define STAT_XON_PAUSE_RX_REG 0x08a0 895 #define STAT_XOFF_PAUSE_RX_REG 0x08a4 896 #define STAT_MAC_CTRL_RX_REG 0x08a8 897 #define STAT_XOFF_STATE_ENTER_REG 0x08ac 898 #define STAT_DOT3_FRAME_TOOLONG_REG 0x08b0 899 #define STAT_ETHER_JABBERS_REG 0x08b4 900 #define STAT_ETHER_UNDERSIZE_REG 0x08b8 901 #define SIZE_OF_STATISTIC_REG 0x1B 902 /* 903 * Send Data Initiator Registers 904 */ 905 #define SEND_INIT_STATS_CONTROL_REG 0x0c08 906 #define SEND_INIT_STATS_ZERO 0x00000010 907 #define SEND_INIT_STATS_FLUSH 0x00000008 908 #define SEND_INIT_STATS_CLEAR 0x00000004 909 #define SEND_INIT_STATS_FASTER 0x00000002 910 #define SEND_INIT_STATS_ENABLE 0x00000001 911 912 #define SEND_INIT_STATS_ENABLE_MASK_REG 0x0c0c 913 914 /* 915 * Send Buffer Descriptor Selector Control Registers 916 */ 917 #define SEND_BD_SELECTOR_STATUS_REG 0x1404 918 #define SEND_BD_SELECTOR_HWDIAG_REG 0x1408 919 #define SEND_BD_SELECTOR_INDEX_REG(n) (0x1440+4*(n)) 920 921 /* 922 * Receive List Placement Registers 923 */ 924 #define RCV_LP_CONFIG_REG 0x2010 925 #define RCV_LP_CONFIG_DEFAULT 0x00000009 926 #define RCV_LP_CONFIG(rings) (((rings) << 3) | 0x1) 927 928 #define RCV_LP_STATS_CONTROL_REG 0x2014 929 #define RCV_LP_STATS_ZERO 0x00000010 930 #define RCV_LP_STATS_FLUSH 0x00000008 931 #define RCV_LP_STATS_CLEAR 0x00000004 932 #define RCV_LP_STATS_FASTER 0x00000002 933 #define RCV_LP_STATS_ENABLE 0x00000001 934 935 #define RCV_LP_STATS_ENABLE_MASK_REG 0x2018 936 #define RCV_LP_STATS_DISABLE_MACTQ 0x040000 937 938 /* 939 * Receive Data & BD Initiator Registers 940 */ 941 #define RCV_INITIATOR_STATUS_REG 0x2404 942 943 /* 944 * Receive Buffer Descriptor Ring Control Block Registers 945 * NB: sixteen bytes (128 bits) each 946 */ 947 #define JUMBO_RCV_BD_RING_RCB_REG 0x2440 948 #define STD_RCV_BD_RING_RCB_REG 0x2450 949 #define MINI_RCV_BD_RING_RCB_REG 0x2460 950 951 /* 952 * Receive Buffer Descriptor Ring Replenish Threshold Registers 953 */ 954 #define MINI_RCV_BD_REPLENISH_REG 0x2c14 955 #define MINI_RCV_BD_REPLENISH_DEFAULT 0x00000080 /* 128 */ 956 #define STD_RCV_BD_REPLENISH_REG 0x2c18 957 #define STD_RCV_BD_REPLENISH_DEFAULT 0x00000002 /* 2 */ 958 #define JUMBO_RCV_BD_REPLENISH_REG 0x2c1c 959 #define JUMBO_RCV_BD_REPLENISH_DEFAULT 0x00000020 /* 32 */ 960 961 /* 962 * Host Coalescing Engine Control Registers 963 */ 964 #define RCV_COALESCE_TICKS_REG 0x3c08 965 #define RCV_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 966 #define SEND_COALESCE_TICKS_REG 0x3c0c 967 #define SEND_COALESCE_TICKS_DEFAULT 0x00000096 /* 150 */ 968 #define RCV_COALESCE_MAX_BD_REG 0x3c10 969 #define RCV_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 970 #define SEND_COALESCE_MAX_BD_REG 0x3c14 971 #define SEND_COALESCE_MAX_BD_DEFAULT 0x0000000a /* 10 */ 972 #define RCV_COALESCE_INT_TICKS_REG 0x3c18 973 #define RCV_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 974 #define SEND_COALESCE_INT_TICKS_REG 0x3c1c 975 #define SEND_COALESCE_INT_TICKS_DEFAULT 0x00000000 /* 0 */ 976 #define RCV_COALESCE_INT_BD_REG 0x3c20 977 #define RCV_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 978 #define SEND_COALESCE_INT_BD_REG 0x3c24 979 #define SEND_COALESCE_INT_BD_DEFAULT 0x00000000 /* 0 */ 980 #define STATISTICS_TICKS_REG 0x3c28 981 #define STATISTICS_TICKS_DEFAULT 0x000f4240 /* 1000000 */ 982 #define STATISTICS_HOST_ADDR_REG 0x3c30 983 #define STATUS_BLOCK_HOST_ADDR_REG 0x3c38 984 #define STATISTICS_BASE_ADDR_REG 0x3c40 985 #define STATUS_BLOCK_BASE_ADDR_REG 0x3c44 986 #define FLOW_ATTN_REG 0x3c48 987 988 #define NIC_JUMBO_RECV_INDEX_REG 0x3c50 989 #define NIC_STD_RECV_INDEX_REG 0x3c54 990 #define NIC_MINI_RECV_INDEX_REG 0x3c58 991 #define NIC_DIAG_RETURN_INDEX_REG(n) (0x3c80+4*(n)) 992 #define NIC_DIAG_SEND_INDEX_REG(n) (0x3cc0+4*(n)) 993 994 /* 995 * Mbuf Pool Initialisation & Watermark Registers 996 * 997 * There are some conflicts in the PRM; compare the recommendations 998 * on pp. 115, 236, and 339. The values here were recommended by 999 * dkim@broadcom.com (and the PRM should be corrected soon ;-) 1000 */ 1001 #define BUFFER_MANAGER_STATUS_REG 0x4404 1002 #define MBUF_POOL_BASE_REG 0x4408 1003 #define MBUF_POOL_BASE_DEFAULT 0x00008000 1004 #define MBUF_POOL_BASE_5721 0x00010000 1005 #define MBUF_POOL_BASE_5704 0x00010000 1006 #define MBUF_POOL_BASE_5705 0x00010000 1007 #define MBUF_POOL_LENGTH_REG 0x440c 1008 #define MBUF_POOL_LENGTH_DEFAULT 0x00018000 1009 #define MBUF_POOL_LENGTH_5704 0x00010000 1010 #define MBUF_POOL_LENGTH_5705 0x00008000 1011 #define MBUF_POOL_LENGTH_5721 0x00008000 1012 #define RDMA_MBUF_LOWAT_REG 0x4410 1013 #define RDMA_MBUF_LOWAT_DEFAULT 0x00000050 1014 #define RDMA_MBUF_LOWAT_5705 0x00000000 1015 #define RDMA_MBUF_LOWAT_JUMBO 0x00000130 1016 #define RDMA_MBUF_LOWAT_5714_JUMBO 0x00000000 1017 #define MAC_RX_MBUF_LOWAT_REG 0x4414 1018 #define MAC_RX_MBUF_LOWAT_DEFAULT 0x00000020 1019 #define MAC_RX_MBUF_LOWAT_5705 0x00000010 1020 #define MAC_RX_MBUF_LOWAT_JUMBO 0x00000098 1021 #define MAC_RX_MBUF_LOWAT_5714_JUMBO 0x0000004b 1022 #define MBUF_HIWAT_REG 0x4418 1023 #define MBUF_HIWAT_DEFAULT 0x00000060 1024 #define MBUF_HIWAT_5705 0x00000060 1025 #define MBUF_HIWAT_JUMBO 0x0000017c 1026 #define MBUF_HIWAT_5714_JUMBO 0x00000096 1027 1028 /* 1029 * DMA Descriptor Pool Initialisation & Watermark Registers 1030 */ 1031 #define DMAD_POOL_BASE_REG 0x442c 1032 #define DMAD_POOL_BASE_DEFAULT 0x00002000 1033 #define DMAD_POOL_LENGTH_REG 0x4430 1034 #define DMAD_POOL_LENGTH_DEFAULT 0x00002000 1035 #define DMAD_POOL_LOWAT_REG 0x4434 1036 #define DMAD_POOL_LOWAT_DEFAULT 0x00000005 /* 5 */ 1037 #define DMAD_POOL_HIWAT_REG 0x4438 1038 #define DMAD_POOL_HIWAT_DEFAULT 0x0000000a /* 10 */ 1039 1040 /* 1041 * More threshold/watermark registers ... 1042 */ 1043 #define RECV_FLOW_THRESHOLD_REG 0x4458 1044 #define LOWAT_MAX_RECV_FRAMES_REG 0x0504 1045 #define LOWAT_MAX_RECV_FRAMES_DEFAULT 0x00000002 1046 1047 /* 1048 * Read/Write DMA Status Registers 1049 */ 1050 #define READ_DMA_STATUS_REG 0x4804 1051 #define WRITE_DMA_STATUS_REG 0x4c04 1052 1053 /* 1054 * RX/TX RISC Registers 1055 */ 1056 #define RX_RISC_MODE_REG 0x5000 1057 #define RX_RISC_STATE_REG 0x5004 1058 #define RX_RISC_PC_REG 0x501c 1059 #define TX_RISC_MODE_REG 0x5400 1060 #define TX_RISC_STATE_REG 0x5404 1061 #define TX_RISC_PC_REG 0x541c 1062 1063 #define FTQ_RESET_REG 0x5c00 1064 1065 #define MSI_MODE_REG 0x6000 1066 #define MSI_PRI_HIGHEST 0xc0000000 1067 #define MSI_MSI_ENABLE 0x00000002 1068 1069 #define MODE_CONTROL_REG 0x6800 1070 #define MODE_ROUTE_MCAST_TO_RX_RISC 0x40000000 1071 #define MODE_4X_NIC_SEND_RINGS 0x20000000 1072 #define MODE_INT_ON_FLOW_ATTN 0x10000000 1073 #define MODE_INT_ON_DMA_ATTN 0x08000000 1074 #define MODE_INT_ON_MAC_ATTN 0x04000000 1075 #define MODE_INT_ON_RXRISC_ATTN 0x02000000 1076 #define MODE_INT_ON_TXRISC_ATTN 0x01000000 1077 #define MODE_RECV_NO_PSEUDO_HDR_CSUM 0x00800000 1078 #define MODE_SEND_NO_PSEUDO_HDR_CSUM 0x00100000 1079 #define MODE_HOST_SEND_BDS 0x00020000 1080 #define MODE_HOST_STACK_UP 0x00010000 1081 #define MODE_FORCE_32_BIT_PCI 0x00008000 1082 #define MODE_NO_INT_ON_RECV 0x00004000 1083 #define MODE_NO_INT_ON_SEND 0x00002000 1084 #define MODE_ALLOW_BAD_FRAMES 0x00000800 1085 #define MODE_NO_CRC 0x00000400 1086 #define MODE_NO_FRAME_CRACKING 0x00000200 1087 #define MODE_WORD_SWAP_FRAME 0x00000020 1088 #define MODE_BYTE_SWAP_FRAME 0x00000010 1089 #define MODE_WORD_SWAP_NONFRAME 0x00000004 1090 #define MODE_BYTE_SWAP_NONFRAME 0x00000002 1091 #define MODE_UPDATE_ON_COAL_ONLY 0x00000001 1092 1093 /* 1094 * Miscellaneous Configuration Register 1095 * 1096 * This contains various bits relating to power control (which differ 1097 * among different members of the chip family), but the important bits 1098 * for our purposes are the RESET bit and the Timer Prescaler field. 1099 * 1100 * The RESET bit in this register serves to reset the whole chip, even 1101 * including the PCI interface(!) Once it's set, the chip will not 1102 * respond to ANY accesses -- not even CONFIG space -- until the reset 1103 * completes internally. According to the PRM, this should take less 1104 * than 100us. Any access during this period will get a bus error. 1105 * 1106 * The Timer Prescaler field must be programmed so that the timer period 1107 * is as near as possible to 1us. The value in this field should be 1108 * the Core Clock frequency in MHz minus 1. From my reading of the PRM, 1109 * the Core Clock should always be 66MHz (independently of the bus speed, 1110 * at least for PCI rather than PCI-X), so this register must be set to 1111 * the value 0x82 ((66-1) << 1). 1112 */ 1113 #define CORE_CLOCK_MHZ 66 1114 #define MISC_CONFIG_REG 0x6804 1115 #define MISC_CONFIG_GRC_RESET_DISABLE 0x20000000 1116 #define MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE 0x04000000 1117 #define MISC_CONFIG_POWERDOWN 0x00100000 1118 #define MISC_CONFIG_POWER_STATE 0x00060000 1119 #define MISC_CONFIG_PRESCALE_MASK 0x000000fe 1120 #define MISC_CONFIG_RESET_BIT 0x00000001 1121 #define MISC_CONFIG_DEFAULT (((CORE_CLOCK_MHZ)-1) << 1) 1122 1123 /* 1124 * Miscellaneous Local Control Register (MLCR) 1125 */ 1126 #define MISC_LOCAL_CONTROL_REG 0x6808 1127 #define MLCR_PCI_CTRL_SELECT 0x10000000 1128 #define MLCR_LEGACY_PCI_MODE 0x08000000 1129 #define MLCR_AUTO_SEEPROM_ACCESS 0x01000000 1130 #define MLCR_SSRAM_CYCLE_DESELECT 0x00800000 1131 #define MLCR_SSRAM_TYPE 0x00400000 1132 #define MLCR_BANK_SELECT 0x00200000 1133 #define MLCR_SRAM_SIZE_MASK 0x001c0000 1134 #define MLCR_ENABLE_EXTERNAL_MEMORY 0x00020000 1135 1136 #define MLCR_MISC_PINS_OUTPUT_2 0x00010000 1137 #define MLCR_MISC_PINS_OUTPUT_1 0x00008000 1138 #define MLCR_MISC_PINS_OUTPUT_0 0x00004000 1139 #define MLCR_MISC_PINS_OUTPUT_ENABLE_2 0x00002000 1140 #define MLCR_MISC_PINS_OUTPUT_ENABLE_1 0x00001000 1141 #define MLCR_MISC_PINS_OUTPUT_ENABLE_0 0x00000800 1142 #define MLCR_MISC_PINS_INPUT_2 0x00000400 /* R/O */ 1143 #define MLCR_MISC_PINS_INPUT_1 0x00000200 /* R/O */ 1144 #define MLCR_MISC_PINS_INPUT_0 0x00000100 /* R/O */ 1145 1146 #define MLCR_INT_ON_ATTN 0x00000008 /* R/W */ 1147 #define MLCR_SET_INT 0x00000004 /* W/O */ 1148 #define MLCR_CLR_INT 0x00000002 /* W/O */ 1149 #define MLCR_INTA_STATE 0x00000001 /* R/O */ 1150 1151 /* 1152 * This value defines all GPIO bits as INPUTS, but sets their default 1153 * values as outputs to HIGH, on the assumption that external circuits 1154 * (if any) will probably be active-LOW with passive pullups. 1155 * 1156 * The Claymore blade uses GPIO1 to control writing to the SEEPROM in 1157 * just this fashion. It has to be set as an OUTPUT and driven LOW to 1158 * enable writing. Otherwise, the SEEPROM is protected. 1159 */ 1160 #define MLCR_DEFAULT 0x0101c000 1161 #define MLCR_DEFAULT_5714 0x1901c000 1162 1163 /* 1164 * Serial EEPROM Data/Address Registers (auto-access mode) 1165 */ 1166 #define SERIAL_EEPROM_DATA_REG 0x683c 1167 #define SERIAL_EEPROM_ADDRESS_REG 0x6838 1168 #define SEEPROM_ACCESS_READ 0x80000000 1169 #define SEEPROM_ACCESS_WRITE 0x00000000 1170 #define SEEPROM_ACCESS_COMPLETE 0x40000000 1171 #define SEEPROM_ACCESS_RESET 0x20000000 1172 #define SEEPROM_ACCESS_DEVID_MASK 0x1c000000 1173 #define SEEPROM_ACCESS_START 0x02000000 1174 #define SEEPROM_ACCESS_HALFCLOCK_MASK 0x01ff0000 1175 #define SEEPROM_ACCESS_ADDRESS_MASK 0x0000fffc 1176 1177 #define SEEPROM_ACCESS_DEVID_SHIFT 26 /* bits */ 1178 #define SEEPROM_ACCESS_HALFCLOCK_SHIFT 16 /* bits */ 1179 #define SEEPROM_ACCESS_ADDRESS_SIZE 16 /* bits */ 1180 1181 #define SEEPROM_ACCESS_HALFCLOCK_340KHZ 0x0060 /* 340kHz */ 1182 #define SEEPROM_ACCESS_INIT 0x20600000 /* reset+clock */ 1183 1184 /* 1185 * "Linearised" address mask, treating multiple devices as consecutive 1186 */ 1187 #define SEEPROM_DEV_AND_ADDR_MASK 0x0007fffc /* 8x64k devices */ 1188 1189 /* 1190 * Non-Volatile Memory Interface Registers 1191 * Note: on chips that support the flash interface (5702+), flash is the 1192 * default and the legacy seeprom interface must be explicitly enabled 1193 * if required. On older chips (5700/01), SEEPROM is the default (and 1194 * only) non-volatile memory available, and these registers don't exist! 1195 */ 1196 #define NVM_FLASH_CMD_REG 0x7000 1197 #define NVM_FLASH_CMD_LAST 0x00000100 1198 #define NVM_FLASH_CMD_FIRST 0x00000080 1199 #define NVM_FLASH_CMD_RD 0x00000000 1200 #define NVM_FLASH_CMD_WR 0x00000020 1201 #define NVM_FLASH_CMD_DOIT 0x00000010 1202 #define NVM_FLASH_CMD_DONE 0x00000008 1203 1204 #define NVM_FLASH_WRITE_REG 0x7008 1205 #define NVM_FLASH_READ_REG 0x7010 1206 1207 #define NVM_FLASH_ADDR_REG 0x700c 1208 #define NVM_FLASH_ADDR_MASK 0x00fffffc 1209 1210 #define NVM_CONFIG1_REG 0x7014 1211 #define NVM_CFG1_LEGACY_SEEPROM_MODE 0x80000000 1212 #define NVM_CFG1_SEE_CLK_DIV_MASK 0x003ff800 1213 #define NVM_CFG1_SPI_CLK_DIV_MASK 0x00000780 1214 #define NVM_CFG1_BUFFERED_MODE 0x00000002 1215 #define NVM_CFG1_FLASH_MODE 0x00000001 1216 1217 #define NVM_SW_ARBITRATION_REG 0x7020 1218 #define NVM_READ_REQ3 0X00008000 1219 #define NVM_READ_REQ2 0X00004000 1220 #define NVM_READ_REQ1 0X00002000 1221 #define NVM_READ_REQ0 0X00001000 1222 #define NVM_WON_REQ3 0X00000800 1223 #define NVM_WON_REQ2 0X00000400 1224 #define NVM_WON_REQ1 0X00000200 1225 #define NVM_WON_REQ0 0X00000100 1226 #define NVM_RESET_REQ3 0X00000080 1227 #define NVM_RESET_REQ2 0X00000040 1228 #define NVM_RESET_REQ1 0X00000020 1229 #define NVM_RESET_REQ0 0X00000010 1230 #define NVM_SET_REQ3 0X00000008 1231 #define NVM_SET_REQ2 0X00000004 1232 #define NVM_SET_REQ1 0X00000002 1233 #define NVM_SET_REQ0 0X00000001 1234 1235 /* 1236 * NVM access register 1237 * Applicable to BCM5721,BCM5751,BCM5752,BCM5714 1238 * and BCM5715 only. 1239 */ 1240 #define NVM_ACCESS_REG 0X7024 1241 #define NVM_WRITE_ENABLE 0X00000002 1242 #define NVM_ACCESS_ENABLE 0X00000001 1243 1244 /* 1245 * TLP Control Register 1246 * Applicable to BCM5721 and BCM5751 only 1247 */ 1248 #define TLP_CONTROL_REG 0x7c00 1249 #define TLP_DATA_FIFO_PROTECT 0x02000000 1250 1251 /* 1252 * PHY Test Control Register 1253 * Applicable to BCM5721 and BCM5751 only 1254 */ 1255 #define PHY_TEST_CTRL_REG 0x7e2c 1256 #define PHY_PCIE_SCRAM_MODE 0x20 1257 #define PHY_PCIE_LTASS_MODE 0x40 1258 1259 /* 1260 * The internal firmware expects a certain layout of the non-volatile 1261 * memory (if fitted), and will check for it during startup, and use the 1262 * contents to initialise various internal parameters if it looks good. 1263 * 1264 * The offsets and field definitions below refer to where to find some 1265 * important values, and how to interpret them ... 1266 */ 1267 #define NVMEM_DATA_MAC_ADDRESS 0x007c /* 8 bytes */ 1268 1269 /* 1270 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1271 */ 1272 1273 #define MII_AN_LPNXTPG 8 1274 #define MII_1000BASE_T_CONTROL 9 1275 #define MII_1000BASE_T_STATUS 10 1276 #define MII_IEEE_EXT_STATUS 15 1277 1278 /* 1279 * New bits in the MII_CONTROL register 1280 */ 1281 #define MII_CONTROL_1000MB 0x0040 1282 1283 /* 1284 * New bits in the MII_AN_ADVERT register 1285 */ 1286 #define MII_ABILITY_ASYM_PAUSE 0x0800 1287 #define MII_ABILITY_PAUSE 0x0400 1288 1289 /* 1290 * Values for the <selector> field of the MII_AN_ADVERT register 1291 */ 1292 #define MII_AN_SELECTOR_8023 0x0001 1293 1294 /* 1295 * Bits in the MII_1000BASE_T_CONTROL register 1296 * 1297 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1298 * (otherwise, roles are automatically negotiated). When this bit is set, 1299 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1300 */ 1301 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1302 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1303 #define MII_1000BT_CTL_ADV_FDX 0x0200 1304 #define MII_1000BT_CTL_ADV_HDX 0x0100 1305 1306 /* 1307 * Bits in the MII_1000BASE_T_STATUS register 1308 */ 1309 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1310 #define MII_1000BT_STAT_MASTER_MODE 0x4000 /* shows role selected */ 1311 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1312 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1313 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1314 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1315 1316 /* 1317 * Vendor-specific MII registers 1318 */ 1319 #define MII_EXT_CONTROL MII_VENDOR(0) 1320 #define MII_EXT_STATUS MII_VENDOR(1) 1321 #define MII_RCV_ERR_COUNT MII_VENDOR(2) 1322 #define MII_FALSE_CARR_COUNT MII_VENDOR(3) 1323 #define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 1324 #define MII_AUX_CONTROL MII_VENDOR(8) 1325 #define MII_AUX_STATUS MII_VENDOR(9) 1326 #define MII_INTR_STATUS MII_VENDOR(10) 1327 #define MII_INTR_MASK MII_VENDOR(11) 1328 #define MII_HCD_STATUS MII_VENDOR(13) 1329 1330 #define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 1331 1332 /* 1333 * Bits in the MII_EXT_CONTROL register 1334 */ 1335 #define MII_EXT_CTRL_INTERFACE_TBI 0x8000 1336 #define MII_EXT_CTRL_DISABLE_AUTO_MDIX 0x4000 1337 #define MII_EXT_CTRL_DISABLE_TRANSMIT 0x2000 1338 #define MII_EXT_CTRL_DISABLE_INTERRUPT 0x1000 1339 #define MII_EXT_CTRL_FORCE_INTERRUPT 0x0800 1340 #define MII_EXT_CTRL_BYPASS_4B5B 0x0400 1341 #define MII_EXT_CTRL_BYPASS_SCRAMBLER 0x0200 1342 #define MII_EXT_CTRL_BYPASS_MLT3 0x0100 1343 #define MII_EXT_CTRL_BYPASS_RX_ALIGN 0x0080 1344 #define MII_EXT_CTRL_RESET_SCRAMBLER 0x0040 1345 #define MII_EXT_CTRL_LED_TRAFFIC_MODE 0x0020 1346 #define MII_EXT_CTRL_FORCE_LEDS_ON 0x0010 1347 #define MII_EXT_CTRL_FORCE_LEDS_OFF 0x0008 1348 #define MII_EXT_CTRL_EXTEND_TX_IPG 0x0004 1349 #define MII_EXT_CTRL_3LINK_LED_MODE 0x0002 1350 #define MII_EXT_CTRL_FIFO_ELASTICITY 0x0001 1351 1352 /* 1353 * Bits in the MII_EXT_STATUS register 1354 */ 1355 #define MII_EXT_STAT_S3MII_FIFO_ERROR 0x8000 1356 #define MII_EXT_STAT_WIRESPEED_DOWNGRADE 0x4000 1357 #define MII_EXT_STAT_MDIX_STATE 0x2000 1358 #define MII_EXT_STAT_INTERRUPT_STATUS 0x1000 1359 #define MII_EXT_STAT_REMOTE_RCVR_STATUS 0x0800 1360 #define MII_EXT_STAT_LOCAL_RDVR_STATUS 0x0400 1361 #define MII_EXT_STAT_DESCRAMBLER_LOCKED 0x0200 1362 #define MII_EXT_STAT_LINK_STATUS 0x0100 1363 #define MII_EXT_STAT_CRC_ERROR 0x0080 1364 #define MII_EXT_STAT_CARR_EXT_ERROR 0x0040 1365 #define MII_EXT_STAT_BAD_SSD_ERROR 0x0020 1366 #define MII_EXT_STAT_BAD_ESD_ERROR 0x0010 1367 #define MII_EXT_STAT_RECEIVE_ERROR 0x0008 1368 #define MII_EXT_STAT_TRANSMIT_ERROR 0x0004 1369 #define MII_EXT_STAT_LOCK_ERROR 0x0002 1370 #define MII_EXT_STAT_MLT3_CODE_ERROR 0x0001 1371 1372 /* 1373 * The AUX CONTROL register is seriously weird! 1374 * 1375 * It hides (up to) eight 'shadow' registers. When writing, which one 1376 * of them is written is determined by the low-order bits of the data 1377 * written(!), but when reading, which one is read is determined by the 1378 * value previously written to (part of) one of the shadow registers!!! 1379 */ 1380 1381 /* 1382 * Shadow register numbers 1383 */ 1384 #define MII_AUX_CTRL_NORMAL 0 1385 #define MII_AUX_CTRL_10BASE_T 1 1386 #define MII_AUX_CTRL_POWER 2 1387 #define MII_AUX_CTRL_TEST_1 4 1388 #define MII_AUX_CTRL_MISC 7 1389 1390 /* 1391 * Selected bits in some of the shadow registers ... 1392 */ 1393 #define MII_AUX_CTRL_NORM_EXT_LOOPBACK 0x8000 1394 #define MII_AUX_CTRL_NORM_LONG_PKTS 0x4000 1395 #define MII_AUX_CTRL_NORM_EDGE_CTRL 0x3000 1396 #define MII_AUX_CTRL_NORM_TX_MODE 0x0400 1397 #define MII_AUX_CTRL_NORM_CABLE_TEST 0x0008 1398 1399 #define MII_AUX_CTRL_TEST_TX_HALF 0x0008 1400 1401 #define MII_AUX_CTRL_MISC_WRITE_ENABLE 0x8000 1402 #define MII_AUX_CTRL_MISC_WIRE_SPEED 0x0010 1403 1404 /* 1405 * Write this value to the AUX control register 1406 * to select which shadow register will be read 1407 */ 1408 #define MII_AUX_CTRL_SHADOW_READ(x) (((x) << 12) | MII_AUX_CTRL_MISC) 1409 1410 /* 1411 * Bits in the MII_AUX_STATUS register 1412 */ 1413 #define MII_AUX_STATUS_MODE_MASK 0x0700 1414 #define MII_AUX_STATUS_MODE_1000_F 0x0700 1415 #define MII_AUX_STATUS_MODE_1000_H 0x0600 1416 #define MII_AUX_STATUS_MODE_100_F 0x0500 1417 #define MII_AUX_STATUS_MODE_100_4 0x0400 1418 #define MII_AUX_STATUS_MODE_100_H 0x0300 1419 #define MII_AUX_STATUS_MODE_10_F 0x0200 1420 #define MII_AUX_STATUS_MODE_10_H 0x0100 1421 #define MII_AUX_STATUS_MODE_NONE 0x0000 1422 #define MII_AUX_STATUS_MODE_SHIFT 8 1423 1424 #define MII_AUX_STATUS_PAR_FAULT 0x0080 1425 #define MII_AUX_STATUS_REM_FAULT 0x0040 1426 #define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 1427 #define MII_AUX_STATUS_LP_NP_ABLE 0x0008 1428 1429 #define MII_AUX_STATUS_LINKUP 0x0004 1430 #define MII_AUX_STATUS_RX_PAUSE 0x0002 1431 #define MII_AUX_STATUS_TX_PAUSE 0x0001 1432 1433 /* 1434 * Bits in the MII_INTR_STATUS and MII_INTR_MASK registers 1435 */ 1436 #define MII_INTR_RMT_RX_STATUS_CHANGE 0x0020 1437 #define MII_INTR_LCL_RX_STATUS_CHANGE 0x0010 1438 #define MII_INTR_LINK_DUPLEX_CHANGE 0x0008 1439 #define MII_INTR_LINK_SPEED_CHANGE 0x0004 1440 #define MII_INTR_LINK_STATUS_CHANGE 0x0002 1441 1442 1443 /* 1444 * Third section: 1445 * Hardware-defined data structures 1446 * 1447 * Note that the chip is naturally BIG-endian, so, for a big-endian 1448 * host, the structures defined below match those described in the PRM. 1449 * For little-endian hosts, some structures have to be swapped around. 1450 */ 1451 1452 #if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 1453 #error Host endianness not defined 1454 #endif 1455 1456 /* 1457 * Architectural constants: absolute maximum numbers of each type of ring 1458 */ 1459 #ifdef BGE_EXT_MEM 1460 #define BGE_SEND_RINGS_MAX 16 /* only with ext mem */ 1461 #else 1462 #define BGE_SEND_RINGS_MAX 4 1463 #endif 1464 #define BGE_SEND_RINGS_MAX_5705 1 1465 #define BGE_RECV_RINGS_MAX 16 1466 #define BGE_RECV_RINGS_MAX_5705 1 1467 #define BGE_BUFF_RINGS_MAX 3 /* jumbo/std/mini (mini */ 1468 /* only with ext mem) */ 1469 1470 #define BGE_SEND_SLOTS_MAX 512 1471 #define BGE_STD_SLOTS_MAX 512 1472 #define BGE_JUMBO_SLOTS_MAX 256 1473 #define BGE_MINI_SLOTS_MAX 1024 1474 #define BGE_RECV_SLOTS_MAX 2048 1475 #define BGE_RECV_SLOTS_5705 512 1476 #define BGE_RECV_SLOTS_5782 512 1477 #define BGE_RECV_SLOTS_5721 512 1478 1479 /* 1480 * Hardware-defined Ring Control Block 1481 */ 1482 typedef struct { 1483 uint64_t host_ring_addr; 1484 #ifdef _BIG_ENDIAN 1485 uint16_t max_len; 1486 uint16_t flags; 1487 uint32_t nic_ring_addr; 1488 #else 1489 uint32_t nic_ring_addr; 1490 uint16_t flags; 1491 uint16_t max_len; 1492 #endif /* _BIG_ENDIAN */ 1493 } bge_rcb_t; 1494 1495 #define RCB_FLAG_USE_EXT_RCV_BD 0x0001 1496 #define RCB_FLAG_RING_DISABLED 0x0002 1497 1498 /* 1499 * Hardware-defined Send Buffer Descriptor 1500 */ 1501 typedef struct { 1502 uint64_t host_buf_addr; 1503 #ifdef _BIG_ENDIAN 1504 uint16_t len; 1505 uint16_t flags; 1506 uint16_t reserved; 1507 uint16_t vlan_tci; 1508 #else 1509 uint16_t vlan_tci; 1510 uint16_t reserved; 1511 uint16_t flags; 1512 uint16_t len; 1513 #endif /* _BIG_ENDIAN */ 1514 } bge_sbd_t; 1515 1516 #define SBD_FLAG_TCP_UDP_CKSUM 0x0001 1517 #define SBD_FLAG_IP_CKSUM 0x0002 1518 #define SBD_FLAG_PACKET_END 0x0004 1519 #define SBD_FLAG_IP_FRAG 0x0008 1520 #define SBD_FLAG_IP_FRAG_END 0x0010 1521 1522 #define SBD_FLAG_VLAN_TAG 0x0040 1523 #define SBD_FLAG_COAL_NOW 0x0080 1524 #define SBD_FLAG_CPU_PRE_DMA 0x0100 1525 #define SBD_FLAG_CPU_POST_DMA 0x0200 1526 1527 #define SBD_FLAG_INSERT_SRC_ADDR 0x1000 1528 #define SBD_FLAG_CHOOSE_SRC_ADDR 0x6000 1529 #define SBD_FLAG_DONT_GEN_CRC 0x8000 1530 1531 /* 1532 * Hardware-defined Receive Buffer Descriptor 1533 */ 1534 typedef struct { 1535 uint64_t host_buf_addr; 1536 #ifdef _BIG_ENDIAN 1537 uint16_t index; 1538 uint16_t len; 1539 uint16_t type; 1540 uint16_t flags; 1541 uint16_t ip_cksum; 1542 uint16_t tcp_udp_cksum; 1543 uint16_t error_flag; 1544 uint16_t vlan_tci; 1545 uint32_t reserved; 1546 uint32_t opaque; 1547 #else 1548 uint16_t flags; 1549 uint16_t type; 1550 uint16_t len; 1551 uint16_t index; 1552 uint16_t vlan_tci; 1553 uint16_t error_flag; 1554 uint16_t tcp_udp_cksum; 1555 uint16_t ip_cksum; 1556 uint32_t opaque; 1557 uint32_t reserved; 1558 #endif /* _BIG_ENDIAN */ 1559 } bge_rbd_t; 1560 1561 #define RBD_FLAG_STD_RING 0x0000 1562 #define RBD_FLAG_PACKET_END 0x0004 1563 1564 #define RBD_FLAG_JUMBO_RING 0x0020 1565 #define RBD_FLAG_VLAN_TAG 0x0040 1566 1567 #define RBD_FLAG_FRAME_HAS_ERROR 0x0400 1568 #define RBD_FLAG_MINI_RING 0x0800 1569 #define RBD_FLAG_IP_CHECKSUM 0x1000 1570 #define RBD_FLAG_TCP_UDP_CHECKSUM 0x2000 1571 #define RBD_FLAG_TCP_UDP_IS_TCP 0x4000 1572 1573 #define RBD_FLAG_DEFAULT 0x0000 1574 1575 #define RBD_ERROR_BAD_CRC 0x00010000 1576 #define RBD_ERROR_COLL_DETECT 0x00020000 1577 #define RBD_ERROR_LINK_LOST 0x00040000 1578 #define RBD_ERROR_PHY_DECODE_ERR 0x00080000 1579 #define RBD_ERROR_ODD_NIBBLE_RX_MII 0x00100000 1580 #define RBD_ERROR_MAC_ABORT 0x00200000 1581 #define RBD_ERROR_LEN_LESS_64 0x00400000 1582 #define RBD_ERROR_TRUNC_NO_RES 0x00800000 1583 #define RBD_ERROR_GIANT_PKT_RCVD 0x01000000 1584 1585 /* 1586 * Hardware-defined Status Block,Size of status block 1587 * is actually 0x50 bytes.Use 0x80 bytes for cache line 1588 * alignment.For BCM5705/5788/5721/5751/5752/5714 1589 * and 5715,there is only 1 recv and send ring index,but 1590 * driver defined 16 indexs here,please pay attention only 1591 * one ring is enabled in these chipsets. 1592 */ 1593 typedef struct { 1594 uint64_t flags_n_tag; 1595 uint16_t buff_cons_index[4]; 1596 struct { 1597 #ifdef _BIG_ENDIAN 1598 uint16_t send_cons_index; 1599 uint16_t recv_prod_index; 1600 #else 1601 uint16_t recv_prod_index; 1602 uint16_t send_cons_index; 1603 #endif /* _BIG_ENDIAN */ 1604 } index[16]; 1605 } bge_status_t; 1606 1607 /* 1608 * Hardware-defined Receive BD Rule 1609 */ 1610 typedef struct { 1611 uint32_t control; 1612 uint32_t mask_value; 1613 } bge_recv_rule_t; 1614 1615 /* 1616 * Indexes into the <buff_cons_index> array 1617 */ 1618 #ifdef _BIG_ENDIAN 1619 #define STATUS_STD_BUFF_CONS_INDEX 0 1620 #define STATUS_JUMBO_BUFF_CONS_INDEX 1 1621 #define STATUS_MINI_BUFF_CONS_INDEX 3 1622 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].send_cons_index) 1623 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^0].recv_prod_index) 1624 #else 1625 #define STATUS_STD_BUFF_CONS_INDEX 3 1626 #define STATUS_JUMBO_BUFF_CONS_INDEX 2 1627 #define STATUS_MINI_BUFF_CONS_INDEX 0 1628 #define SEND_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].send_cons_index) 1629 #define RECV_INDEX_P(bsp, ring) (&(bsp)->index[(ring)^1].recv_prod_index) 1630 #endif /* _BIG_ENDIAN */ 1631 1632 /* 1633 * Bits in the <flags_n_tag> word 1634 */ 1635 #define STATUS_FLAG_UPDATED 0x0000000100000000ull 1636 #define STATUS_FLAG_LINK_CHANGED 0x0000000200000000ull 1637 #define STATUS_FLAG_ERROR 0x0000000400000000ull 1638 #define STATUS_TAG_MASK 0x00000000000000FFull 1639 1640 /* 1641 * The tag from the status block is fed back to Interrupt Mailbox 0 1642 * (INTERRUPT_MBOX_0_REG, 0x0200) after servicing an interrupt. This 1643 * lets the chip know what updates have been processed, so it can 1644 * reassert its interrupt if more updates have occurred since. 1645 * 1646 * These macros extract the tag from the <flags_n_tag> word, shift 1647 * it to the proper position in the Mailbox register, and provide 1648 * the complete values to write to INTERRUPT_MBOX_0_REG to disable 1649 * or enable interrupts 1650 */ 1651 #define STATUS_TAG(fnt) ((fnt) & STATUS_TAG_MASK) 1652 #define INTERRUPT_TAG(fnt) (STATUS_TAG(fnt) << 24) 1653 #define INTERRUPT_MBOX_DISABLE(fnt) (INTERRUPT_TAG(fnt) | 1) 1654 #define INTERRUPT_MBOX_ENABLE(fnt) (INTERRUPT_TAG(fnt) | 0) 1655 1656 /* 1657 * Hardware-defined Statistics Block Offsets 1658 * 1659 * These are given in the manual as addresses in NIC memory, starting 1660 * from the NIC statistics area base address of 0x300; but here we 1661 * convert them into indexes into an array of (uint64_t)s, so we can 1662 * use them directly for accessing the copy of the statistics block 1663 * that the chip DMAs into main memory ... 1664 */ 1665 1666 #define KS_BASE 0x300 1667 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint64_t)) 1668 1669 typedef enum { 1670 KS_ifHCInOctets = KS_ADDR(0x400), 1671 KS_etherStatsFragments = KS_ADDR(0x410), 1672 KS_ifHCInUcastPkts, 1673 KS_ifHCInMulticastPkts, 1674 KS_ifHCInBroadcastPkts, 1675 KS_dot3StatsFCSErrors, 1676 KS_dot3StatsAlignmentErrors, 1677 KS_xonPauseFramesReceived, 1678 KS_xoffPauseFramesReceived, 1679 KS_macControlFramesReceived, 1680 KS_xoffStateEntered, 1681 KS_dot3StatsFrameTooLongs, 1682 KS_etherStatsJabbers, 1683 KS_etherStatsUndersizePkts, 1684 KS_inRangeLengthError, 1685 KS_outRangeLengthError, 1686 KS_etherStatsPkts64Octets, 1687 KS_etherStatsPkts65to127Octets, 1688 KS_etherStatsPkts128to255Octets, 1689 KS_etherStatsPkts256to511Octets, 1690 KS_etherStatsPkts512to1023Octets, 1691 KS_etherStatsPkts1024to1518Octets, 1692 KS_etherStatsPkts1519to2047Octets, 1693 KS_etherStatsPkts2048to4095Octets, 1694 KS_etherStatsPkts4096to8191Octets, 1695 KS_etherStatsPkts8192to9022Octets, 1696 1697 KS_ifHCOutOctets = KS_ADDR(0x600), 1698 KS_etherStatsCollisions = KS_ADDR(0x610), 1699 KS_outXonSent, 1700 KS_outXoffSent, 1701 KS_flowControlDone, 1702 KS_dot3StatsInternalMacTransmitErrors, 1703 KS_dot3StatsSingleCollisionFrames, 1704 KS_dot3StatsMultipleCollisionFrames, 1705 KS_dot3StatsDeferredTransmissions, 1706 KS_dot3StatsExcessiveCollisions = KS_ADDR(0x658), 1707 KS_dot3StatsLateCollisions, 1708 KS_dot3Collided2Times, 1709 KS_dot3Collided3Times, 1710 KS_dot3Collided4Times, 1711 KS_dot3Collided5Times, 1712 KS_dot3Collided6Times, 1713 KS_dot3Collided7Times, 1714 KS_dot3Collided8Times, 1715 KS_dot3Collided9Times, 1716 KS_dot3Collided10Times, 1717 KS_dot3Collided11Times, 1718 KS_dot3Collided12Times, 1719 KS_dot3Collided13Times, 1720 KS_dot3Collided14Times, 1721 KS_dot3Collided15Times, 1722 KS_ifHCOutUcastPkts, 1723 KS_ifHCOutMulticastPkts, 1724 KS_ifHCOutBroadcastPkts, 1725 KS_dot3StatsCarrierSenseErrors, 1726 KS_ifOutDiscards, 1727 KS_ifOutErrors, 1728 1729 KS_COSIfHCInPkts_1 = KS_ADDR(0x800), /* [16] */ 1730 KS_COSIfHCInPkts_2, 1731 KS_COSIfHCInPkts_3, 1732 KS_COSIfHCInPkts_4, 1733 KS_COSIfHCInPkts_5, 1734 KS_COSIfHCInPkts_6, 1735 KS_COSIfHCInPkts_7, 1736 KS_COSIfHCInPkts_8, 1737 KS_COSIfHCInPkts_9, 1738 KS_COSIfHCInPkts_10, 1739 KS_COSIfHCInPkts_11, 1740 KS_COSIfHCInPkts_12, 1741 KS_COSIfHCInPkts_13, 1742 KS_COSIfHCInPkts_14, 1743 KS_COSIfHCInPkts_15, 1744 KS_COSIfHCInPkts_16, 1745 KS_COSFramesDroppedDueToFilters, 1746 KS_nicDmaWriteQueueFull, 1747 KS_nicDmaWriteHighPriQueueFull, 1748 KS_nicNoMoreRxBDs, 1749 KS_ifInDiscards, 1750 KS_ifInErrors, 1751 KS_nicRecvThresholdHit, 1752 1753 KS_COSIfHCOutPkts_1 = KS_ADDR(0x900), /* [16] */ 1754 KS_COSIfHCOutPkts_2, 1755 KS_COSIfHCOutPkts_3, 1756 KS_COSIfHCOutPkts_4, 1757 KS_COSIfHCOutPkts_5, 1758 KS_COSIfHCOutPkts_6, 1759 KS_COSIfHCOutPkts_7, 1760 KS_COSIfHCOutPkts_8, 1761 KS_COSIfHCOutPkts_9, 1762 KS_COSIfHCOutPkts_10, 1763 KS_COSIfHCOutPkts_11, 1764 KS_COSIfHCOutPkts_12, 1765 KS_COSIfHCOutPkts_13, 1766 KS_COSIfHCOutPkts_14, 1767 KS_COSIfHCOutPkts_15, 1768 KS_COSIfHCOutPkts_16, 1769 KS_nicDmaReadQueueFull, 1770 KS_nicDmaReadHighPriQueueFull, 1771 KS_nicSendDataCompQueueFull, 1772 KS_nicRingSetSendProdIndex, 1773 KS_nicRingStatusUpdate, 1774 KS_nicInterrupts, 1775 KS_nicAvoidedInterrupts, 1776 KS_nicSendThresholdHit, 1777 1778 KS_STATS_SIZE = KS_ADDR(0xb00) 1779 } bge_stats_offset_t; 1780 1781 /* 1782 * Hardware-defined Statistics Block 1783 * 1784 * Another view of the statistic block, as a array and a structure ... 1785 */ 1786 1787 typedef union { 1788 uint64_t a[KS_STATS_SIZE]; 1789 struct { 1790 uint64_t spare1[(0x400-0x300)/sizeof (uint64_t)]; 1791 1792 uint64_t ifHCInOctets; /* 0x0400 */ 1793 uint64_t spare2[1]; 1794 uint64_t etherStatsFragments; 1795 uint64_t ifHCInUcastPkts; 1796 uint64_t ifHCInMulticastPkts; 1797 uint64_t ifHCInBroadcastPkts; 1798 uint64_t dot3StatsFCSErrors; 1799 uint64_t dot3StatsAlignmentErrors; 1800 uint64_t xonPauseFramesReceived; 1801 uint64_t xoffPauseFramesReceived; 1802 uint64_t macControlFramesReceived; 1803 uint64_t xoffStateEntered; 1804 uint64_t dot3StatsFrameTooLongs; 1805 uint64_t etherStatsJabbers; 1806 uint64_t etherStatsUndersizePkts; 1807 uint64_t inRangeLengthError; 1808 uint64_t outRangeLengthError; 1809 uint64_t etherStatsPkts64Octets; 1810 uint64_t etherStatsPkts65to127Octets; 1811 uint64_t etherStatsPkts128to255Octets; 1812 uint64_t etherStatsPkts256to511Octets; 1813 uint64_t etherStatsPkts512to1023Octets; 1814 uint64_t etherStatsPkts1024to1518Octets; 1815 uint64_t etherStatsPkts1519to2047Octets; 1816 uint64_t etherStatsPkts2048to4095Octets; 1817 uint64_t etherStatsPkts4096to8191Octets; 1818 uint64_t etherStatsPkts8192to9022Octets; 1819 uint64_t spare3[(0x600-0x4d8)/sizeof (uint64_t)]; 1820 1821 uint64_t ifHCOutOctets; /* 0x0600 */ 1822 uint64_t spare4[1]; 1823 uint64_t etherStatsCollisions; 1824 uint64_t outXonSent; 1825 uint64_t outXoffSent; 1826 uint64_t flowControlDone; 1827 uint64_t dot3StatsInternalMacTransmitErrors; 1828 uint64_t dot3StatsSingleCollisionFrames; 1829 uint64_t dot3StatsMultipleCollisionFrames; 1830 uint64_t dot3StatsDeferredTransmissions; 1831 uint64_t spare5[1]; 1832 uint64_t dot3StatsExcessiveCollisions; 1833 uint64_t dot3StatsLateCollisions; 1834 uint64_t dot3Collided2Times; 1835 uint64_t dot3Collided3Times; 1836 uint64_t dot3Collided4Times; 1837 uint64_t dot3Collided5Times; 1838 uint64_t dot3Collided6Times; 1839 uint64_t dot3Collided7Times; 1840 uint64_t dot3Collided8Times; 1841 uint64_t dot3Collided9Times; 1842 uint64_t dot3Collided10Times; 1843 uint64_t dot3Collided11Times; 1844 uint64_t dot3Collided12Times; 1845 uint64_t dot3Collided13Times; 1846 uint64_t dot3Collided14Times; 1847 uint64_t dot3Collided15Times; 1848 uint64_t ifHCOutUcastPkts; 1849 uint64_t ifHCOutMulticastPkts; 1850 uint64_t ifHCOutBroadcastPkts; 1851 uint64_t dot3StatsCarrierSenseErrors; 1852 uint64_t ifOutDiscards; 1853 uint64_t ifOutErrors; 1854 uint64_t spare6[(0x800-0x708)/sizeof (uint64_t)]; 1855 1856 uint64_t COSIfHCInPkts[16]; /* 0x0800 */ 1857 uint64_t COSFramesDroppedDueToFilters; 1858 uint64_t nicDmaWriteQueueFull; 1859 uint64_t nicDmaWriteHighPriQueueFull; 1860 uint64_t nicNoMoreRxBDs; 1861 uint64_t ifInDiscards; 1862 uint64_t ifInErrors; 1863 uint64_t nicRecvThresholdHit; 1864 uint64_t spare7[(0x900-0x8b8)/sizeof (uint64_t)]; 1865 1866 uint64_t COSIfHCOutPkts[16]; /* 0x0900 */ 1867 uint64_t nicDmaReadQueueFull; 1868 uint64_t nicDmaReadHighPriQueueFull; 1869 uint64_t nicSendDataCompQueueFull; 1870 uint64_t nicRingSetSendProdIndex; 1871 uint64_t nicRingStatusUpdate; 1872 uint64_t nicInterrupts; 1873 uint64_t nicAvoidedInterrupts; 1874 uint64_t nicSendThresholdHit; 1875 uint64_t spare8[(0xb00-0x9c0)/sizeof (uint64_t)]; 1876 } s; 1877 } bge_statistics_t; 1878 1879 #define KS_STAT_REG_SIZE (0x1B) 1880 #define KS_STAT_REG_BASE (0x800) 1881 1882 typedef struct { 1883 uint32_t ifHCOutOctets; 1884 uint32_t etherStatsCollisions; 1885 uint32_t outXonSent; 1886 uint32_t outXoffSent; 1887 uint32_t dot3StatsInternalMacTransmitErrors; 1888 uint32_t dot3StatsSingleCollisionFrames; 1889 uint32_t dot3StatsMultipleCollisionFrames; 1890 uint32_t dot3StatsDeferredTransmissions; 1891 uint32_t dot3StatsExcessiveCollisions; 1892 uint32_t dot3StatsLateCollisions; 1893 uint32_t ifHCOutUcastPkts; 1894 uint32_t ifHCOutMulticastPkts; 1895 uint32_t ifHCOutBroadcastPkts; 1896 uint32_t ifHCInOctets; 1897 uint32_t etherStatsFragments; 1898 uint32_t ifHCInUcastPkts; 1899 uint32_t ifHCInMulticastPkts; 1900 uint32_t ifHCInBroadcastPkts; 1901 uint32_t dot3StatsFCSErrors; 1902 uint32_t dot3StatsAlignmentErrors; 1903 uint32_t xonPauseFramesReceived; 1904 uint32_t xoffPauseFramesReceived; 1905 uint32_t macControlFramesReceived; 1906 uint32_t xoffStateEntered; 1907 uint32_t dot3StatsFrameTooLongs; 1908 uint32_t etherStatsJabbers; 1909 uint32_t etherStatsUndersizePkts; 1910 } bge_statistics_reg_t; 1911 1912 1913 #ifdef BGE_IPMI_ASF 1914 1915 /* 1916 * Device internal memory entries 1917 */ 1918 1919 #define BGE_FIRMWARE_MAILBOX 0x0b50 1920 #define BGE_MAGIC_NUM_FIRMWARE_INIT_DONE 0x4b657654 1921 #define BGE_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE 0x4861764b 1922 1923 1924 #define BGE_NIC_DATA_SIG_ADDR 0x0b54 1925 #define BGE_NIC_DATA_SIG 0x4b657654 1926 1927 1928 #define BGE_NIC_DATA_NIC_CFG_ADDR 0x0b58 1929 1930 #define BGE_NIC_CFG_LED_MODE_TRIPLE_SPEED 0x000004 1931 #define BGE_NIC_CFG_LED_MODE_LINK_SPEED 0x000008 1932 #define BGE_NIC_CFG_LED_MODE_OPEN_DRAIN 0x000004 1933 #define BGE_NIC_CFG_LED_MODE_OUTPUT 0x000008 1934 #define BGE_NIC_CFG_LED_MODE_MASK 0x00000c 1935 1936 #define BGE_NIC_CFG_PHY_TYPE_UNKNOWN 0x000000 1937 #define BGE_NIC_CFG_PHY_TYPE_COPPER 0x000010 1938 #define BGE_NIC_CFG_PHY_TYPE_FIBER 0x000020 1939 #define BGE_NIC_CFG_PHY_TYPE_MASK 0x000030 1940 1941 #define BGE_NIC_CFG_ENABLE_WOL 0x000040 1942 #define BGE_NIC_CFG_ENABLE_ASF 0x000080 1943 #define BGE_NIC_CFG_EEPROM_WP 0x000100 1944 #define BGE_NIC_CFG_POWER_SAVING 0x000200 1945 #define BGE_NIC_CFG_SWAP_PORT 0x000800 1946 #define BGE_NIC_CFG_MINI_PCI 0x001000 1947 #define BGE_NIC_CFG_FIBER_WOL_CAPABLE 0x004000 1948 #define BGE_NIC_CFG_5753_12x12 0x100000 1949 1950 1951 #define BGE_NIC_DATA_FIRMWARE_VERSION 0x0b5c 1952 1953 1954 #define BGE_NIC_DATA_PHY_ID_ADDR 0x0b74 1955 #define BGE_NIC_PHY_ID1_MASK 0xffff0000 1956 #define BGE_NIC_PHY_ID2_MASK 0x0000ffff 1957 1958 1959 #define BGE_CMD_MAILBOX 0x0b78 1960 #define BGE_CMD_NICDRV_ALIVE 0x00000001 1961 #define BGE_CMD_NICDRV_PAUSE_FW 0x00000002 1962 #define BGE_CMD_NICDRV_IPV4ADDR_CHANGE 0x00000003 1963 #define BGE_CMD_NICDRV_IPV6ADDR_CHANGE 0x00000004 1964 1965 1966 #define BGE_CMD_LENGTH_MAILBOX 0x0b7c 1967 #define BGE_CMD_DATA_MAILBOX 0x0b80 1968 #define BGE_ASF_FW_STATUS_MAILBOX 0x0c00 1969 1970 #define BGE_DRV_STATE_MAILBOX 0x0c04 1971 #define BGE_DRV_STATE_START 0x00000001 1972 #define BGE_DRV_STATE_START_DONE 0x80000001 1973 #define BGE_DRV_STATE_UNLOAD 0x00000002 1974 #define BGE_DRV_STATE_UNLOAD_DONE 0x80000002 1975 #define BGE_DRV_STATE_WOL 0x00000003 1976 #define BGE_DRV_STATE_SUSPEND 0x00000004 1977 1978 1979 #define BGE_FW_LAST_RESET_TYPE_MAILBOX 0x0c08 1980 #define BGE_FW_LAST_RESET_TYPE_WARM 0x0001 1981 #define BGE_FW_LAST_RESET_TYPE_COLD 0x0002 1982 1983 1984 #define BGE_MAC_ADDR_HIGH_MAILBOX 0x0c14 1985 #define BGE_MAC_ADDR_LOW_MAILBOX 0x0c18 1986 1987 1988 /* 1989 * RX-RISC event register 1990 */ 1991 #define RX_RISC_EVENT_REG 0x6810 1992 #define RRER_ASF_EVENT 0x4000 1993 1994 #endif /* BGE_IPMI_ASF */ 1995 1996 #ifdef __cplusplus 1997 } 1998 #endif 1999 2000 #endif /* _BGE_HW_H */ 2001