1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 boolean_t bge_jumbo_enable = B_TRUE; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 245 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 246 247 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 248 (void *)bgep, regno, val)); 249 250 val = LE_32(val); 251 252 return (val); 253 } 254 255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 256 #pragma inline(bge_ind_put32) 257 258 void 259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 260 { 261 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 262 (void *)bgep, regno, val)); 263 264 val = LE_32(val); 265 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 267 } 268 269 #endif /* BGE_IND_IO32 */ 270 271 #if BGE_DEBUGGING 272 273 static void bge_pci_check(bge_t *bgep); 274 #pragma no_inline(bge_pci_check) 275 276 static void 277 bge_pci_check(bge_t *bgep) 278 { 279 uint16_t pcistatus; 280 281 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 282 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 283 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 284 (void *)bgep, pcistatus)); 285 } 286 287 #endif /* BGE_DEBUGGING */ 288 289 /* 290 * Perform first-stage chip (re-)initialisation, using only config-space 291 * accesses: 292 * 293 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 294 * returning the data in the structure pointed to by <idp>. 295 * + Configure the target-mode endianness (swap) options. 296 * + Disable interrupts and enable Memory Space accesses. 297 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 298 * 299 * This sequence is adapted from Broadcom document 570X-PG102-R, 300 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 301 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 302 * 303 * This function MUST be called before any non-config-space accesses 304 * are made; on this first call <enable_dma> is B_FALSE, and it 305 * effectively performs steps 3-1(!) of the initialisation sequence 306 * (the rest are not required but should be harmless). 307 * 308 * It MUST also be called after a chip reset, as this disables 309 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 310 * it is effectively performing steps 6-8. 311 */ 312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 313 #pragma no_inline(bge_chip_cfg_init) 314 315 void 316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 317 { 318 ddi_acc_handle_t handle; 319 uint16_t command; 320 uint32_t mhcr; 321 uint16_t value16; 322 int i; 323 324 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 325 (void *)bgep, (void *)cidp, enable_dma)); 326 327 /* 328 * Step 3: save PCI cache line size and subsystem vendor ID 329 * 330 * Read all the config-space registers that characterise the 331 * chip, specifically vendor/device/revision/subsystem vendor 332 * and subsystem device id. We expect (but don't check) that 333 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 334 * 335 * Also save all bus-transaction related registers (cache-line 336 * size, bus-grant/latency parameters, etc). Some of these are 337 * cleared by reset, so we'll have to restore them later. This 338 * comes from the Broadcom document 570X-PG102-R ... 339 * 340 * Note: Broadcom document 570X-PG102-R seems to be in error 341 * here w.r.t. the offsets of the Subsystem Vendor ID and 342 * Subsystem (Device) ID registers, which are the opposite way 343 * round according to the PCI standard. For good measure, we 344 * save/restore both anyway. 345 */ 346 handle = bgep->cfg_handle; 347 348 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 349 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 350 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 351 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 352 353 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 354 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 355 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 356 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 357 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 358 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 359 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 360 361 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 362 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 363 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 364 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 365 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 366 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 367 cidp->vendor, cidp->device, cidp->revision)); 368 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 369 cidp->subven, cidp->subdev, cidp->asic_rev)); 370 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 371 cidp->clsize, cidp->latency, cidp->command)); 372 373 /* 374 * Step 2 (also step 6): disable and clear interrupts. 375 * Steps 11-13: configure PIO endianness options, and enable 376 * indirect register access. We'll also select any other 377 * options controlled by the MHCR (e.g. tagged status, mask 378 * interrupt mode) at this stage ... 379 * 380 * Note: internally, the chip is 64-bit and BIG-endian, but 381 * since it talks to the host over a (LITTLE-endian) PCI bus, 382 * it normally swaps bytes around at the PCI interface. 383 * However, the PCI host bridge on SPARC systems normally 384 * swaps the byte lanes around too, since SPARCs are also 385 * BIG-endian. So it turns out that on SPARC, the right 386 * option is to tell the chip to swap (and the host bridge 387 * will swap back again), whereas on x86 we ask the chip 388 * NOT to swap, so the natural little-endianness of the 389 * PCI bus is assumed. Then the only thing that doesn't 390 * automatically work right is access to an 8-byte register 391 * by a little-endian host; but we don't want to set the 392 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 393 * accesses don't go where expected ;-( So we live with 394 * that, and perform word-swaps in software in the few cases 395 * where a chip register is defined as an 8-byte value -- 396 * see the code below for details ... 397 * 398 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 399 * very clear in the register description in the PRM, but 400 * Broadcom document 570X-PG104-R page 248 explains a little 401 * more (under "Broadcom Mask Mode"). The bit changes the way 402 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 403 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 404 * way as the 5700 did, which isn't very convenient. Setting 405 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 406 * bit do just what its name says -- MASK the PCI #INTA output 407 * (i.e. deassert the signal at the pin) leaving all internal 408 * state unchanged. This is much more convenient for our 409 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 410 * 411 * Note: the inconvenient semantics of the interrupt mailbox 412 * (nonzero disables and acknowledges/clears the interrupt, 413 * zero enables AND CLEARS it) would make race conditions 414 * likely in the interrupt handler: 415 * 416 * (1) acknowledge & disable interrupts 417 * (2) while (more to do) 418 * process packets 419 * (3) enable interrupts -- also clears pending 420 * 421 * If the chip received more packets and internally generated 422 * an interrupt between the check at (2) and the mbox write 423 * at (3), this interrupt would be lost :-( 424 * 425 * The best way to avoid this is to use TAGGED STATUS mode, 426 * where the chip includes a unique tag in each status block 427 * update, and the host, when re-enabling interrupts, passes 428 * the last tag it saw back to the chip; then the chip can 429 * see whether the host is truly up to date, and regenerate 430 * its interrupt if not. 431 */ 432 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 433 MHCR_ENABLE_TAGGED_STATUS_MODE | 434 MHCR_MASK_INTERRUPT_MODE | 435 MHCR_CLEAR_INTERRUPT_INTA; 436 437 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 438 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 439 440 #ifdef _BIG_ENDIAN 441 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 442 #endif /* _BIG_ENDIAN */ 443 444 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 445 446 #ifdef BGE_IPMI_ASF 447 bgep->asf_wordswapped = B_FALSE; 448 #endif 449 /* 450 * Step 1 (also step 7): Enable PCI Memory Space accesses 451 * Disable Memory Write/Invalidate 452 * Enable or disable Bus Mastering 453 * 454 * Note that all other bits are taken from the original value saved 455 * the first time through here, rather than from the current register 456 * value, 'cos that will have been cleared by a soft RESET since. 457 * In this way we preserve the OBP/nexus-parent's preferred settings 458 * of the parity-error and system-error enable bits across multiple 459 * chip RESETs. 460 */ 461 command = bgep->chipid.command | PCI_COMM_MAE; 462 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 463 if (enable_dma) 464 command |= PCI_COMM_ME; 465 /* 466 * on BCM5714 revision A0, false parity error gets generated 467 * due to a logic bug. Provide a workaround by disabling parity 468 * error. 469 */ 470 if (((cidp->device == DEVICE_ID_5714C) || 471 (cidp->device == DEVICE_ID_5714S)) && 472 (cidp->revision == REVISION_ID_5714_A0)) { 473 command &= ~PCI_COMM_PARITY_DETECT; 474 } 475 pci_config_put16(handle, PCI_CONF_COMM, command); 476 477 /* 478 * On some PCI-E device, there were instances when 479 * the device was still link training. 480 */ 481 if (bgep->chipid.pci_type == BGE_PCI_E) { 482 i = 0; 483 value16 = pci_config_get16(handle, PCI_CONF_COMM); 484 while ((value16 != command) && (i < 100)) { 485 drv_usecwait(200); 486 value16 = pci_config_get16(handle, PCI_CONF_COMM); 487 ++i; 488 } 489 } 490 491 /* 492 * Clear any remaining error status bits 493 */ 494 pci_config_put16(handle, PCI_CONF_STAT, ~0); 495 496 /* 497 * Do following if and only if the device is NOT BCM5714C OR 498 * BCM5715C 499 */ 500 if (!((cidp->device == DEVICE_ID_5714C) || 501 (cidp->device == DEVICE_ID_5715C))) { 502 /* 503 * Make sure these indirect-access registers are sane 504 * rather than random after power-up or reset 505 */ 506 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 507 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 508 } 509 /* 510 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 511 */ 512 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 513 514 if (cidp->pci_type == BGE_PCI_E) 515 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 516 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 517 } 518 519 #ifdef __amd64 520 /* 521 * Distinguish CPU types 522 * 523 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 524 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 525 * for PCI-Express based network interface card. This is the work-around 526 * for those nics. 527 */ 528 static boolean_t bge_get_em64t_type(void); 529 #pragma inline(bge_get_em64t_type) 530 531 static boolean_t 532 bge_get_em64t_type(void) 533 { 534 535 return (x86_vendor == X86_VENDOR_Intel); 536 } 537 #endif 538 539 /* 540 * Operating register get/set access routines 541 */ 542 543 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 544 #pragma inline(bge_reg_get32) 545 546 uint32_t 547 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 548 { 549 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 550 (void *)bgep, regno)); 551 552 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 553 } 554 555 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 556 #pragma inline(bge_reg_put32) 557 558 void 559 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 560 { 561 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 562 (void *)bgep, regno, data)); 563 564 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 565 BGE_PCICHK(bgep); 566 } 567 568 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 569 #pragma inline(bge_reg_set32) 570 571 void 572 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 573 { 574 uint32_t regval; 575 576 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 577 (void *)bgep, regno, bits)); 578 579 regval = bge_reg_get32(bgep, regno); 580 regval |= bits; 581 bge_reg_put32(bgep, regno, regval); 582 } 583 584 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 585 #pragma inline(bge_reg_clr32) 586 587 void 588 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 589 { 590 uint32_t regval; 591 592 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 593 (void *)bgep, regno, bits)); 594 595 regval = bge_reg_get32(bgep, regno); 596 regval &= ~bits; 597 bge_reg_put32(bgep, regno, regval); 598 } 599 600 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 601 #pragma inline(bge_reg_get64) 602 603 static uint64_t 604 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 605 { 606 uint64_t regval; 607 608 #ifdef __amd64 609 if (bge_get_em64t_type()) { 610 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 611 regval <<= 32; 612 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 613 } else { 614 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 615 } 616 #else 617 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 #endif 619 620 #ifdef _LITTLE_ENDIAN 621 regval = (regval >> 32) | (regval << 32); 622 #endif /* _LITTLE_ENDIAN */ 623 624 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 625 (void *)bgep, regno, regval)); 626 627 return (regval); 628 } 629 630 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 631 #pragma inline(bge_reg_put64) 632 633 static void 634 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 635 { 636 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 637 (void *)bgep, regno, data)); 638 639 #ifdef _LITTLE_ENDIAN 640 data = ((data >> 32) | (data << 32)); 641 #endif /* _LITTLE_ENDIAN */ 642 643 #ifdef __amd64 644 if (bge_get_em64t_type()) { 645 ddi_put32(bgep->io_handle, 646 PIO_ADDR(bgep, regno), (uint32_t)data); 647 BGE_PCICHK(bgep); 648 ddi_put32(bgep->io_handle, 649 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 650 651 } else { 652 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 653 } 654 #else 655 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 656 #endif 657 658 BGE_PCICHK(bgep); 659 } 660 661 /* 662 * The DDI doesn't provide get/put functions for 128 bit data 663 * so we put RCBs out as two 64-bit chunks instead. 664 */ 665 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 666 #pragma inline(bge_reg_putrcb) 667 668 static void 669 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 670 { 671 uint64_t *p; 672 673 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 674 (void *)bgep, addr, rcbp->host_ring_addr, 675 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 676 677 ASSERT((addr % sizeof (*rcbp)) == 0); 678 679 p = (void *)rcbp; 680 bge_reg_put64(bgep, addr, *p++); 681 bge_reg_put64(bgep, addr+8, *p); 682 } 683 684 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 685 #pragma inline(bge_mbx_put) 686 687 void 688 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 689 { 690 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 691 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 692 693 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 694 (void *)bgep, regno, data)); 695 696 /* 697 * Mailbox registers are nominally 64 bits on the 5701, but 698 * the MSW isn't used. On the 5703, they're only 32 bits 699 * anyway. So here we just write the lower(!) 32 bits - 700 * remembering that the chip is big-endian, even though the 701 * PCI bus is little-endian ... 702 */ 703 #ifdef _BIG_ENDIAN 704 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 705 #else 706 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 707 #endif /* _BIG_ENDIAN */ 708 BGE_PCICHK(bgep); 709 } 710 711 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 712 #pragma inline(bge_mbx_get) 713 714 uint32_t 715 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 716 { 717 uint32_t val32; 718 719 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 720 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 721 722 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 723 (void *)bgep, regno)); 724 725 #ifdef _BIG_ENDIAN 726 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 727 #else 728 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 729 #endif /* _BIG_ENDIAN */ 730 BGE_PCICHK(bgep); 731 732 return (val32); 733 } 734 735 736 #if BGE_DEBUGGING 737 738 void bge_led_mark(bge_t *bgep); 739 #pragma no_inline(bge_led_mark) 740 741 void 742 bge_led_mark(bge_t *bgep) 743 { 744 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 745 LED_CONTROL_1000MBPS_LED | 746 LED_CONTROL_100MBPS_LED | 747 LED_CONTROL_10MBPS_LED; 748 749 /* 750 * Blink all three LINK LEDs on simultaneously, then all off, 751 * then restore to automatic hardware control. This is used 752 * in laboratory testing to trigger a logic analyser or scope. 753 */ 754 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 755 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 756 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 757 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 758 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 759 } 760 761 #endif /* BGE_DEBUGGING */ 762 763 /* 764 * NIC on-chip memory access routines 765 * 766 * Only 32K of NIC memory is visible at a time, controlled by the 767 * Memory Window Base Address Register (in PCI config space). Once 768 * this is set, the 32K region of NIC-local memory that it refers 769 * to can be directly addressed in the upper 32K of the 64K of PCI 770 * memory space used for the device. 771 */ 772 773 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 774 #pragma inline(bge_nic_setwin) 775 776 static void 777 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 778 { 779 chip_id_t *cidp; 780 781 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 782 (void *)bgep, base)); 783 784 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 785 786 /* 787 * Don't do repeated zero data writes, 788 * if the device is BCM5714C/15C. 789 */ 790 cidp = &bgep->chipid; 791 if ((cidp->device == DEVICE_ID_5714C) || 792 (cidp->device == DEVICE_ID_5715C)) { 793 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 794 return; 795 /* Adjust lastWriteZeroData */ 796 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 797 B_TRUE : B_FALSE); 798 } 799 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 800 } 801 802 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 803 #pragma inline(bge_nic_get32) 804 805 static uint32_t 806 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 807 { 808 uint32_t data; 809 810 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 811 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 812 /* workaround for word swap error */ 813 if (addr & 4) 814 addr = addr - 4; 815 else 816 addr = addr + 4; 817 } 818 #endif 819 820 #ifdef __sparc 821 data = bge_nic_read32(bgep, addr); 822 #else 823 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 824 addr &= MWBAR_GRANULE_MASK; 825 addr += NIC_MEM_WINDOW_OFFSET; 826 827 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 828 #endif 829 830 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 831 (void *)bgep, addr, data)); 832 833 return (data); 834 } 835 836 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 837 #pragma inline(bge_nic_put32) 838 839 void 840 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 841 { 842 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 843 (void *)bgep, addr, data)); 844 845 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 846 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 847 /* workaround for word swap error */ 848 if (addr & 4) 849 addr = addr - 4; 850 else 851 addr = addr + 4; 852 } 853 #endif 854 855 #ifdef __sparc 856 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 857 data = LE_32(data); 858 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 859 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 860 #else 861 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 862 addr &= MWBAR_GRANULE_MASK; 863 addr += NIC_MEM_WINDOW_OFFSET; 864 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 865 BGE_PCICHK(bgep); 866 #endif 867 } 868 869 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 870 #pragma inline(bge_nic_get64) 871 872 static uint64_t 873 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 874 { 875 uint64_t data; 876 877 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 878 addr &= MWBAR_GRANULE_MASK; 879 addr += NIC_MEM_WINDOW_OFFSET; 880 881 #ifdef __amd64 882 if (bge_get_em64t_type()) { 883 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 884 data <<= 32; 885 data |= ddi_get32(bgep->io_handle, 886 PIO_ADDR(bgep, addr + 4)); 887 } else { 888 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 889 } 890 #else 891 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 892 #endif 893 894 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 895 (void *)bgep, addr, data)); 896 897 return (data); 898 } 899 900 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 901 #pragma inline(bge_nic_put64) 902 903 static void 904 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 905 { 906 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 907 (void *)bgep, addr, data)); 908 909 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 910 addr &= MWBAR_GRANULE_MASK; 911 addr += NIC_MEM_WINDOW_OFFSET; 912 913 #ifdef __amd64 914 if (bge_get_em64t_type()) { 915 ddi_put32(bgep->io_handle, 916 PIO_ADDR(bgep, addr), (uint32_t)data); 917 BGE_PCICHK(bgep); 918 ddi_put32(bgep->io_handle, 919 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 920 } else { 921 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 922 } 923 #else 924 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 925 #endif 926 927 BGE_PCICHK(bgep); 928 } 929 930 /* 931 * The DDI doesn't provide get/put functions for 128 bit data 932 * so we put RCBs out as two 64-bit chunks instead. 933 */ 934 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 935 #pragma inline(bge_nic_putrcb) 936 937 static void 938 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 939 { 940 uint64_t *p; 941 942 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 943 (void *)bgep, addr, rcbp->host_ring_addr, 944 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 945 946 ASSERT((addr % sizeof (*rcbp)) == 0); 947 948 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 949 addr &= MWBAR_GRANULE_MASK; 950 addr += NIC_MEM_WINDOW_OFFSET; 951 952 p = (void *)rcbp; 953 #ifdef __amd64 954 if (bge_get_em64t_type()) { 955 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 956 (uint32_t)(*p)); 957 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 958 (uint32_t)(*p >> 32)); 959 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 960 (uint32_t)(*(p + 1))); 961 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 962 (uint32_t)(*p >> 32)); 963 964 } else { 965 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 966 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 967 } 968 #else 969 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 970 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 971 #endif 972 973 BGE_PCICHK(bgep); 974 } 975 976 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 977 #pragma inline(bge_nic_zero) 978 979 static void 980 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 981 { 982 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 983 (void *)bgep, addr, nbytes)); 984 985 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 986 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 987 988 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 989 addr &= MWBAR_GRANULE_MASK; 990 addr += NIC_MEM_WINDOW_OFFSET; 991 992 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 993 nbytes, 1, DDI_DATA_SZ08_ACC); 994 BGE_PCICHK(bgep); 995 } 996 997 /* 998 * MII (PHY) register get/set access routines 999 * 1000 * These use the chip's MII auto-access method, controlled by the 1001 * MII Communication register at 0x044c, so the CPU doesn't have 1002 * to fiddle with the individual bits. 1003 */ 1004 1005 #undef BGE_DBG 1006 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1007 1008 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1009 uint16_t data, uint32_t cmd); 1010 #pragma no_inline(bge_mii_access) 1011 1012 static uint16_t 1013 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1014 { 1015 uint32_t timeout; 1016 uint32_t regval1; 1017 uint32_t regval2; 1018 1019 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1020 (void *)bgep, regno, data, cmd)); 1021 1022 ASSERT(mutex_owned(bgep->genlock)); 1023 1024 /* 1025 * Assemble the command ... 1026 */ 1027 cmd |= data << MI_COMMS_DATA_SHIFT; 1028 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1029 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1030 cmd |= MI_COMMS_START; 1031 1032 /* 1033 * Wait for any command already in progress ... 1034 * 1035 * Note: this *shouldn't* ever find that there is a command 1036 * in progress, because we already hold the <genlock> mutex. 1037 * Nonetheless, we have sometimes seen the MI_COMMS_START 1038 * bit set here -- it seems that the chip can initiate MII 1039 * accesses internally, even with polling OFF. 1040 */ 1041 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1042 for (timeout = 100; ; ) { 1043 if ((regval2 & MI_COMMS_START) == 0) { 1044 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1045 break; 1046 } 1047 if (--timeout == 0) 1048 break; 1049 drv_usecwait(10); 1050 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1051 } 1052 1053 if (timeout == 0) 1054 return ((uint16_t)~0u); 1055 1056 if (timeout != 100) 1057 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1058 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1059 cmd, 10*(100-timeout), regval1, regval2)); 1060 1061 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1062 for (timeout = 1000; ; ) { 1063 if ((regval1 & MI_COMMS_START) == 0) 1064 break; 1065 if (--timeout == 0) 1066 break; 1067 drv_usecwait(10); 1068 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1069 } 1070 1071 /* 1072 * Drop out early if the READ FAILED bit is set -- this chip 1073 * could be a 5703/4S, with a SerDes instead of a PHY! 1074 */ 1075 if (regval2 & MI_COMMS_READ_FAILED) 1076 return ((uint16_t)~0u); 1077 1078 if (timeout == 0) 1079 return ((uint16_t)~0u); 1080 1081 /* 1082 * The PRM says to wait 5us after seeing the START bit clear 1083 * and then re-read the register to get the final value of the 1084 * data field, in order to avoid a race condition where the 1085 * START bit is clear but the data field isn't yet valid. 1086 * 1087 * Note: we don't actually seem to be encounter this race; 1088 * except when the START bit is seen set again (see below), 1089 * the data field doesn't change during this 5us interval. 1090 */ 1091 drv_usecwait(5); 1092 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1093 1094 /* 1095 * Unfortunately, when following the PRMs instructions above, 1096 * we have occasionally seen the START bit set again(!) in the 1097 * value read after the 5us delay. This seems to be due to the 1098 * chip autonomously starting another MII access internally. 1099 * In such cases, the command/data/etc fields relate to the 1100 * internal command, rather than the one that we thought had 1101 * just finished. So in this case, we fall back to returning 1102 * the data from the original read that showed START clear. 1103 */ 1104 if (regval2 & MI_COMMS_START) { 1105 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1106 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1107 cmd, regval1, regval2)); 1108 regval2 = regval1; 1109 } 1110 1111 if (regval2 & MI_COMMS_START) 1112 return ((uint16_t)~0u); 1113 1114 if (regval2 & MI_COMMS_READ_FAILED) 1115 return ((uint16_t)~0u); 1116 1117 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1118 } 1119 1120 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1121 #pragma no_inline(bge_mii_get16) 1122 1123 uint16_t 1124 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1125 { 1126 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1127 (void *)bgep, regno)); 1128 1129 ASSERT(mutex_owned(bgep->genlock)); 1130 1131 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1132 (regno == MII_1000BASE_T_CONTROL))) 1133 return (0); 1134 1135 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1136 } 1137 1138 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1139 #pragma no_inline(bge_mii_put16) 1140 1141 void 1142 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1143 { 1144 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1145 (void *)bgep, regno, data)); 1146 1147 ASSERT(mutex_owned(bgep->genlock)); 1148 1149 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1150 (regno == MII_1000BASE_T_CONTROL))) 1151 return; 1152 1153 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1154 } 1155 1156 #undef BGE_DBG 1157 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1158 1159 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1160 1161 /* 1162 * Basic SEEPROM get/set access routine 1163 * 1164 * This uses the chip's SEEPROM auto-access method, controlled by the 1165 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1166 * doesn't have to fiddle with the individual bits. 1167 * 1168 * The caller should hold <genlock> and *also* have already acquired 1169 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1170 * 1171 * Return value: 1172 * 0 on success, 1173 * ENODATA on access timeout (maybe retryable: device may just be busy) 1174 * EPROTO on other h/w or s/w errors. 1175 * 1176 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1177 * from a (successful) SEEPROM_ACCESS_READ. 1178 */ 1179 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1180 uint32_t *dp); 1181 #pragma no_inline(bge_seeprom_access) 1182 1183 static int 1184 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1185 { 1186 uint32_t tries; 1187 uint32_t regval; 1188 1189 ASSERT(mutex_owned(bgep->genlock)); 1190 1191 /* 1192 * On the newer chips that support both SEEPROM & Flash, we need 1193 * to specifically enable SEEPROM access (Flash is the default). 1194 * On older chips, we don't; SEEPROM is the only NVtype supported, 1195 * and the NVM control registers don't exist ... 1196 */ 1197 switch (bgep->chipid.nvtype) { 1198 case BGE_NVTYPE_NONE: 1199 case BGE_NVTYPE_UNKNOWN: 1200 _NOTE(NOTREACHED) 1201 case BGE_NVTYPE_SEEPROM: 1202 break; 1203 1204 case BGE_NVTYPE_LEGACY_SEEPROM: 1205 case BGE_NVTYPE_UNBUFFERED_FLASH: 1206 case BGE_NVTYPE_BUFFERED_FLASH: 1207 default: 1208 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1209 NVM_CFG1_LEGACY_SEEPROM_MODE); 1210 break; 1211 } 1212 1213 /* 1214 * Check there's no command in progress. 1215 * 1216 * Note: this *shouldn't* ever find that there is a command 1217 * in progress, because we already hold the <genlock> mutex. 1218 * Also, to ensure we don't have a conflict with the chip's 1219 * internal firmware or a process accessing the same (shared) 1220 * SEEPROM through the other port of a 5704, we've already 1221 * been through the "software arbitration" protocol. 1222 * So this is just a final consistency check: we shouldn't 1223 * see EITHER the START bit (command started but not complete) 1224 * OR the COMPLETE bit (command completed but not cleared). 1225 */ 1226 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1227 if (regval & SEEPROM_ACCESS_START) 1228 return (EPROTO); 1229 if (regval & SEEPROM_ACCESS_COMPLETE) 1230 return (EPROTO); 1231 1232 /* 1233 * Assemble the command ... 1234 */ 1235 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1236 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1237 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1238 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1239 cmd |= SEEPROM_ACCESS_START; 1240 cmd |= SEEPROM_ACCESS_COMPLETE; 1241 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1242 1243 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1244 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1245 1246 /* 1247 * By observation, a successful access takes ~20us on a 5703/4, 1248 * but apparently much longer (up to 1000us) on the obsolescent 1249 * BCM5700/BCM5701. We want to be sure we don't get any false 1250 * timeouts here; but OTOH, we don't want a bogus access to lock 1251 * out interrupts for longer than necessary. So we'll allow up 1252 * to 1000us ... 1253 */ 1254 for (tries = 0; tries < 1000; ++tries) { 1255 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1256 if (regval & SEEPROM_ACCESS_COMPLETE) 1257 break; 1258 drv_usecwait(1); 1259 } 1260 1261 if (regval & SEEPROM_ACCESS_COMPLETE) { 1262 /* 1263 * All OK; read the SEEPROM data register, then write back 1264 * the value read from the address register in order to 1265 * clear the <complete> bit and leave the SEEPROM access 1266 * state machine idle, ready for the next access ... 1267 */ 1268 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1269 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1270 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1271 return (0); 1272 } 1273 1274 /* 1275 * Hmm ... what happened here? 1276 * 1277 * Most likely, the user addressed a non-existent SEEPROM. Or 1278 * maybe the SEEPROM was busy internally (e.g. processing a write) 1279 * and didn't respond to being addressed. Either way, it's left 1280 * the SEEPROM access state machine wedged. So we'll reset it 1281 * before we leave, so it's ready for next time ... 1282 */ 1283 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1284 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1285 return (ENODATA); 1286 } 1287 1288 /* 1289 * Basic Flash get/set access routine 1290 * 1291 * These use the chip's Flash auto-access method, controlled by the 1292 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1293 * fiddle with the individual bits. 1294 * 1295 * The caller should hold <genlock> and *also* have already acquired 1296 * the right to access the Flash, via bge_nvmem_acquire() above. 1297 * 1298 * Return value: 1299 * 0 on success, 1300 * ENODATA on access timeout (maybe retryable: device may just be busy) 1301 * ENODEV if the NVmem device is missing or otherwise unusable 1302 * 1303 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1304 * from a (successful) NVM_FLASH_CMD_RD. 1305 */ 1306 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1307 uint32_t *dp); 1308 #pragma no_inline(bge_flash_access) 1309 1310 static int 1311 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1312 { 1313 uint32_t tries; 1314 uint32_t regval; 1315 1316 ASSERT(mutex_owned(bgep->genlock)); 1317 1318 /* 1319 * On the newer chips that support both SEEPROM & Flash, we need 1320 * to specifically disable SEEPROM access while accessing Flash. 1321 * The older chips don't support Flash, and the NVM registers don't 1322 * exist, so we shouldn't be here at all! 1323 */ 1324 switch (bgep->chipid.nvtype) { 1325 case BGE_NVTYPE_NONE: 1326 case BGE_NVTYPE_UNKNOWN: 1327 _NOTE(NOTREACHED) 1328 case BGE_NVTYPE_SEEPROM: 1329 return (ENODEV); 1330 1331 case BGE_NVTYPE_LEGACY_SEEPROM: 1332 case BGE_NVTYPE_UNBUFFERED_FLASH: 1333 case BGE_NVTYPE_BUFFERED_FLASH: 1334 default: 1335 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1336 NVM_CFG1_LEGACY_SEEPROM_MODE); 1337 break; 1338 } 1339 1340 /* 1341 * Assemble the command ... 1342 */ 1343 addr &= NVM_FLASH_ADDR_MASK; 1344 cmd |= NVM_FLASH_CMD_DOIT; 1345 cmd |= NVM_FLASH_CMD_FIRST; 1346 cmd |= NVM_FLASH_CMD_LAST; 1347 cmd |= NVM_FLASH_CMD_DONE; 1348 1349 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1350 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1351 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1352 1353 /* 1354 * Allow up to 1000ms ... 1355 */ 1356 for (tries = 0; tries < 1000; ++tries) { 1357 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1358 if (regval & NVM_FLASH_CMD_DONE) 1359 break; 1360 drv_usecwait(1); 1361 } 1362 1363 if (regval & NVM_FLASH_CMD_DONE) { 1364 /* 1365 * All OK; read the data from the Flash read register 1366 */ 1367 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1368 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1369 return (0); 1370 } 1371 1372 /* 1373 * Hmm ... what happened here? 1374 * 1375 * Most likely, the user addressed a non-existent Flash. Or 1376 * maybe the Flash was busy internally (e.g. processing a write) 1377 * and didn't respond to being addressed. Either way, there's 1378 * nothing we can here ... 1379 */ 1380 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1381 return (ENODATA); 1382 } 1383 1384 /* 1385 * The next two functions regulate access to the NVram (if fitted). 1386 * 1387 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1388 * (SPI) interface, but they can be accessed through either port. These 1389 * are managed by different instance of this driver and have no software 1390 * state in common. 1391 * 1392 * In addition (and even on a single core chip) the chip's internal 1393 * firmware can access the SEEPROM/Flash, most notably after a RESET 1394 * when it may download code to run internally. 1395 * 1396 * So we need to arbitrate between these various software agents. For 1397 * this purpose, the chip provides the Software Arbitration Register, 1398 * which implements hardware(!) arbitration. 1399 * 1400 * This functionality didn't exist on older (5700/5701) chips, so there's 1401 * nothing we can do by way of arbitration on those; also, if there's no 1402 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1403 * nothing to do. 1404 * 1405 * The internal firmware appears to use Request 0, which is the highest 1406 * priority. So we'd like to use Request 2, leaving one higher and one 1407 * lower for any future developments ... but apparently this doesn't 1408 * always work. So for now, the code uses Request 1 ;-( 1409 */ 1410 1411 #define NVM_READ_REQ NVM_READ_REQ1 1412 #define NVM_RESET_REQ NVM_RESET_REQ1 1413 #define NVM_SET_REQ NVM_SET_REQ1 1414 1415 static void bge_nvmem_relinquish(bge_t *bgep); 1416 #pragma no_inline(bge_nvmem_relinquish) 1417 1418 static void 1419 bge_nvmem_relinquish(bge_t *bgep) 1420 { 1421 ASSERT(mutex_owned(bgep->genlock)); 1422 1423 switch (bgep->chipid.nvtype) { 1424 case BGE_NVTYPE_NONE: 1425 case BGE_NVTYPE_UNKNOWN: 1426 _NOTE(NOTREACHED) 1427 return; 1428 1429 case BGE_NVTYPE_SEEPROM: 1430 /* 1431 * No arbitration performed, no release needed 1432 */ 1433 return; 1434 1435 case BGE_NVTYPE_LEGACY_SEEPROM: 1436 case BGE_NVTYPE_UNBUFFERED_FLASH: 1437 case BGE_NVTYPE_BUFFERED_FLASH: 1438 default: 1439 break; 1440 } 1441 1442 /* 1443 * Our own request should be present (whether or not granted) ... 1444 */ 1445 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1446 1447 /* 1448 * ... this will make it go away. 1449 */ 1450 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1451 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1452 } 1453 1454 /* 1455 * Arbitrate for access to the NVmem, if necessary 1456 * 1457 * Return value: 1458 * 0 on success 1459 * EAGAIN if the device is in use (retryable) 1460 * ENODEV if the NVmem device is missing or otherwise unusable 1461 */ 1462 static int bge_nvmem_acquire(bge_t *bgep); 1463 #pragma no_inline(bge_nvmem_acquire) 1464 1465 static int 1466 bge_nvmem_acquire(bge_t *bgep) 1467 { 1468 uint32_t regval; 1469 uint32_t tries; 1470 1471 ASSERT(mutex_owned(bgep->genlock)); 1472 1473 switch (bgep->chipid.nvtype) { 1474 case BGE_NVTYPE_NONE: 1475 case BGE_NVTYPE_UNKNOWN: 1476 /* 1477 * Access denied: no (recognisable) device fitted 1478 */ 1479 return (ENODEV); 1480 1481 case BGE_NVTYPE_SEEPROM: 1482 /* 1483 * Access granted: no arbitration needed (or possible) 1484 */ 1485 return (0); 1486 1487 case BGE_NVTYPE_LEGACY_SEEPROM: 1488 case BGE_NVTYPE_UNBUFFERED_FLASH: 1489 case BGE_NVTYPE_BUFFERED_FLASH: 1490 default: 1491 /* 1492 * Access conditional: conduct arbitration protocol 1493 */ 1494 break; 1495 } 1496 1497 /* 1498 * We're holding the per-port mutex <genlock>, so no-one other 1499 * thread can be attempting to access the NVmem through *this* 1500 * port. But it could be in use by the *other* port (of a 5704), 1501 * or by the chip's internal firmware, so we have to go through 1502 * the full (hardware) arbitration protocol ... 1503 * 1504 * Note that *because* we're holding <genlock>, the interrupt handler 1505 * won't be able to progress. So we're only willing to spin for a 1506 * fairly short time. Specifically: 1507 * 1508 * We *must* wait long enough for the hardware to resolve all 1509 * requests and determine the winner. Fortunately, this is 1510 * "almost instantaneous", even as observed by GHz CPUs. 1511 * 1512 * A successful access by another Solaris thread (via either 1513 * port) typically takes ~20us. So waiting a bit longer than 1514 * that will give a good chance of success, if the other user 1515 * *is* another thread on the other port. 1516 * 1517 * However, the internal firmware can hold on to the NVmem 1518 * for *much* longer: at least 10 milliseconds just after a 1519 * RESET, and maybe even longer if the NVmem actually contains 1520 * code to download and run on the internal CPUs. 1521 * 1522 * So, we'll allow 50us; if that's not enough then it's up to the 1523 * caller to retry later (hence the choice of return code EAGAIN). 1524 */ 1525 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1526 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1527 1528 for (tries = 0; tries < 50; ++tries) { 1529 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1530 if (regval & NVM_WON_REQ1) 1531 break; 1532 drv_usecwait(1); 1533 } 1534 1535 if (regval & NVM_WON_REQ1) { 1536 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1537 return (0); 1538 } 1539 1540 /* 1541 * Somebody else must be accessing the NVmem, so abandon our 1542 * attempt take control of it. The caller can try again later ... 1543 */ 1544 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1545 bge_nvmem_relinquish(bgep); 1546 return (EAGAIN); 1547 } 1548 1549 /* 1550 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1551 * write protect line in such a way that the NVmem is protected when 1552 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1553 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1554 * 1555 * Note: there's only one set of GPIO pins on a 5704, even though they 1556 * can be accessed through either port. So the chip has to resolve what 1557 * happens if the two ports program a single pin differently ... the rule 1558 * it uses is that if the ports disagree about the *direction* of a pin, 1559 * "output" wins over "input", but if they disagree about its *value* as 1560 * an output, then the pin is TRISTATED instead! In such a case, no-one 1561 * wins, and the external signal does whatever the external circuitry 1562 * defines as the default -- which we've assumed is the PROTECTED state. 1563 * So, we always change GPIO1 back to being an *input* whenever we're not 1564 * specifically using it to unprotect the NVmem. This allows either port 1565 * to update the NVmem, although obviously only one at a time! 1566 * 1567 * The caller should hold <genlock> and *also* have already acquired the 1568 * right to access the NVmem, via bge_nvmem_acquire() above. 1569 */ 1570 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1571 #pragma inline(bge_nvmem_protect) 1572 1573 static void 1574 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1575 { 1576 uint32_t regval; 1577 1578 ASSERT(mutex_owned(bgep->genlock)); 1579 1580 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1581 if (protect) { 1582 regval |= MLCR_MISC_PINS_OUTPUT_1; 1583 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1584 } else { 1585 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1586 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1587 } 1588 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1589 } 1590 1591 /* 1592 * Now put it all together ... 1593 * 1594 * Try to acquire control of the NVmem; if successful, then: 1595 * unprotect it (if we want to write to it) 1596 * perform the requested access 1597 * reprotect it (after a write) 1598 * relinquish control 1599 * 1600 * Return value: 1601 * 0 on success, 1602 * EAGAIN if the device is in use (retryable) 1603 * ENODATA on access timeout (maybe retryable: device may just be busy) 1604 * ENODEV if the NVmem device is missing or otherwise unusable 1605 * EPROTO on other h/w or s/w errors. 1606 */ 1607 static int 1608 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1609 { 1610 int err; 1611 1612 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1613 switch (cmd) { 1614 case BGE_SEE_READ: 1615 err = bge_seeprom_access(bgep, 1616 SEEPROM_ACCESS_READ, addr, dp); 1617 break; 1618 1619 case BGE_SEE_WRITE: 1620 bge_nvmem_protect(bgep, B_FALSE); 1621 err = bge_seeprom_access(bgep, 1622 SEEPROM_ACCESS_WRITE, addr, dp); 1623 bge_nvmem_protect(bgep, B_TRUE); 1624 break; 1625 1626 case BGE_FLASH_READ: 1627 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1628 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1629 bge_reg_set32(bgep, NVM_ACCESS_REG, 1630 NVM_ACCESS_ENABLE); 1631 } 1632 err = bge_flash_access(bgep, 1633 NVM_FLASH_CMD_RD, addr, dp); 1634 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1635 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1636 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1637 NVM_ACCESS_ENABLE); 1638 } 1639 break; 1640 1641 case BGE_FLASH_WRITE: 1642 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1643 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1644 bge_reg_set32(bgep, NVM_ACCESS_REG, 1645 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1646 } 1647 bge_nvmem_protect(bgep, B_FALSE); 1648 err = bge_flash_access(bgep, 1649 NVM_FLASH_CMD_WR, addr, dp); 1650 bge_nvmem_protect(bgep, B_TRUE); 1651 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1652 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1653 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1654 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1655 } 1656 1657 break; 1658 1659 default: 1660 _NOTE(NOTREACHED) 1661 break; 1662 } 1663 bge_nvmem_relinquish(bgep); 1664 } 1665 1666 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1667 return (err); 1668 } 1669 1670 /* 1671 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1672 */ 1673 static uint64_t bge_get_nvmac(bge_t *bgep); 1674 #pragma no_inline(bge_get_nvmac) 1675 1676 static uint64_t 1677 bge_get_nvmac(bge_t *bgep) 1678 { 1679 uint32_t mac_high; 1680 uint32_t mac_low; 1681 uint32_t addr; 1682 uint32_t cmd; 1683 uint64_t mac; 1684 1685 BGE_TRACE(("bge_get_nvmac($%p)", 1686 (void *)bgep)); 1687 1688 switch (bgep->chipid.nvtype) { 1689 case BGE_NVTYPE_NONE: 1690 case BGE_NVTYPE_UNKNOWN: 1691 default: 1692 return (0ULL); 1693 1694 case BGE_NVTYPE_SEEPROM: 1695 case BGE_NVTYPE_LEGACY_SEEPROM: 1696 cmd = BGE_SEE_READ; 1697 break; 1698 1699 case BGE_NVTYPE_UNBUFFERED_FLASH: 1700 case BGE_NVTYPE_BUFFERED_FLASH: 1701 cmd = BGE_FLASH_READ; 1702 break; 1703 } 1704 1705 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1706 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1707 else 1708 addr = NVMEM_DATA_MAC_ADDRESS; 1709 1710 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1711 return (0ULL); 1712 addr += 4; 1713 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1714 return (0ULL); 1715 1716 /* 1717 * The Broadcom chip is natively BIG-endian, so that's how the 1718 * MAC address is represented in NVmem. We may need to swap it 1719 * around on a little-endian host ... 1720 */ 1721 #ifdef _BIG_ENDIAN 1722 mac = mac_high; 1723 mac = mac << 32; 1724 mac |= mac_low; 1725 #else 1726 mac = BGE_BSWAP_32(mac_high); 1727 mac = mac << 32; 1728 mac |= BGE_BSWAP_32(mac_low); 1729 #endif /* _BIG_ENDIAN */ 1730 1731 return (mac); 1732 } 1733 1734 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1735 1736 /* 1737 * Dummy version for when we're not supporting NVmem access 1738 */ 1739 static uint64_t bge_get_nvmac(bge_t *bgep); 1740 #pragma inline(bge_get_nvmac) 1741 1742 static uint64_t 1743 bge_get_nvmac(bge_t *bgep) 1744 { 1745 _NOTE(ARGUNUSED(bgep)) 1746 return (0ULL); 1747 } 1748 1749 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1750 1751 /* 1752 * Determine the type of NVmem that is (or may be) attached to this chip, 1753 */ 1754 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1755 #pragma no_inline(bge_nvmem_id) 1756 1757 static enum bge_nvmem_type 1758 bge_nvmem_id(bge_t *bgep) 1759 { 1760 enum bge_nvmem_type nvtype; 1761 uint32_t config1; 1762 1763 BGE_TRACE(("bge_nvmem_id($%p)", 1764 (void *)bgep)); 1765 1766 switch (bgep->chipid.device) { 1767 default: 1768 /* 1769 * We shouldn't get here; it means we don't recognise 1770 * the chip, which means we don't know how to determine 1771 * what sort of NVmem (if any) it has. So we'll say 1772 * NONE, to disable the NVmem access code ... 1773 */ 1774 nvtype = BGE_NVTYPE_NONE; 1775 break; 1776 1777 case DEVICE_ID_5700: 1778 case DEVICE_ID_5700x: 1779 case DEVICE_ID_5701: 1780 /* 1781 * These devices support *only* SEEPROMs 1782 */ 1783 nvtype = BGE_NVTYPE_SEEPROM; 1784 break; 1785 1786 case DEVICE_ID_5702: 1787 case DEVICE_ID_5702fe: 1788 case DEVICE_ID_5703C: 1789 case DEVICE_ID_5703S: 1790 case DEVICE_ID_5704C: 1791 case DEVICE_ID_5704S: 1792 case DEVICE_ID_5704: 1793 case DEVICE_ID_5705M: 1794 case DEVICE_ID_5705C: 1795 case DEVICE_ID_5705_2: 1796 case DEVICE_ID_5706: 1797 case DEVICE_ID_5780: 1798 case DEVICE_ID_5782: 1799 case DEVICE_ID_5787: 1800 case DEVICE_ID_5787M: 1801 case DEVICE_ID_5788: 1802 case DEVICE_ID_5789: 1803 case DEVICE_ID_5751: 1804 case DEVICE_ID_5751M: 1805 case DEVICE_ID_5752: 1806 case DEVICE_ID_5752M: 1807 case DEVICE_ID_5754: 1808 case DEVICE_ID_5755: 1809 case DEVICE_ID_5755M: 1810 case DEVICE_ID_5756M: 1811 case DEVICE_ID_5721: 1812 case DEVICE_ID_5722: 1813 case DEVICE_ID_5714C: 1814 case DEVICE_ID_5714S: 1815 case DEVICE_ID_5715C: 1816 case DEVICE_ID_5715S: 1817 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1818 if (config1 & NVM_CFG1_FLASH_MODE) 1819 if (config1 & NVM_CFG1_BUFFERED_MODE) 1820 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1821 else 1822 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1823 else 1824 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1825 break; 1826 case DEVICE_ID_5906: 1827 case DEVICE_ID_5906M: 1828 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1829 break; 1830 } 1831 1832 return (nvtype); 1833 } 1834 1835 #undef BGE_DBG 1836 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1837 1838 static void 1839 bge_init_recv_rule(bge_t *bgep) 1840 { 1841 bge_recv_rule_t *rulep; 1842 uint32_t i; 1843 1844 /* 1845 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1846 * 1. to direct UDP traffic, set: 1847 * rulep->control = RULE_PROTO_CONTROL; 1848 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1849 * 2. to direct ICMP traffic, set: 1850 * rulep->control = RULE_PROTO_CONTROL; 1851 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1852 * 3. to direct traffic by source ip, set: 1853 * rulep->control = RULE_SIP_CONTROL; 1854 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1855 */ 1856 rulep = bgep->recv_rules; 1857 rulep->control = RULE_PROTO_CONTROL; 1858 rulep->mask_value = RULE_TCP_MASK_VALUE; 1859 1860 /* 1861 * set receive rule registers 1862 */ 1863 rulep = bgep->recv_rules; 1864 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1865 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1866 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1867 } 1868 } 1869 1870 /* 1871 * Using the values captured by bge_chip_cfg_init(), and additional probes 1872 * as required, characterise the chip fully: determine the label by which 1873 * to refer to this chip, the correct settings for various registers, and 1874 * of course whether the device and/or subsystem are supported! 1875 */ 1876 int bge_chip_id_init(bge_t *bgep); 1877 #pragma no_inline(bge_chip_id_init) 1878 1879 int 1880 bge_chip_id_init(bge_t *bgep) 1881 { 1882 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1883 boolean_t sys_ok; 1884 boolean_t dev_ok; 1885 chip_id_t *cidp; 1886 uint32_t subid; 1887 char *devname; 1888 char *sysname; 1889 int *ids; 1890 int err; 1891 uint_t i; 1892 1893 sys_ok = dev_ok = B_FALSE; 1894 cidp = &bgep->chipid; 1895 1896 /* 1897 * Check the PCI device ID to determine the generic chip type and 1898 * select parameters that depend on this. 1899 * 1900 * Note: because the SPARC platforms in general don't fit the 1901 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1902 * as zero - which is why we use <asic_rev> rather than <revision> 1903 * below ... 1904 * 1905 * Note: in general we can't distinguish between the Copper/SerDes 1906 * versions by ID alone, as some Copper devices (e.g. some but not 1907 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1908 * treat them the same here, and the MII code works out the media 1909 * type later on ... 1910 */ 1911 cidp->mbuf_base = bge_mbuf_pool_base; 1912 cidp->mbuf_length = bge_mbuf_pool_len; 1913 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1914 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1915 cidp->pci_type = BGE_PCI_X; 1916 cidp->statistic_type = BGE_STAT_BLK; 1917 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1918 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1919 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1920 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1921 cidp->rx_count_norm = bge_rx_count_norm; 1922 1923 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1924 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1925 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1926 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1927 1928 cidp->msi_enabled = B_FALSE; 1929 1930 switch (cidp->device) { 1931 case DEVICE_ID_5700: 1932 case DEVICE_ID_5700x: 1933 cidp->chip_label = 5700; 1934 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1935 break; 1936 1937 case DEVICE_ID_5701: 1938 cidp->chip_label = 5701; 1939 dev_ok = B_TRUE; 1940 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1941 break; 1942 1943 case DEVICE_ID_5702: 1944 case DEVICE_ID_5702fe: 1945 cidp->chip_label = 5702; 1946 dev_ok = B_TRUE; 1947 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1948 cidp->pci_type = BGE_PCI; 1949 break; 1950 1951 case DEVICE_ID_5703C: 1952 case DEVICE_ID_5703S: 1953 case DEVICE_ID_5703: 1954 /* 1955 * Revision A0 of the 5703/5793 had various errata 1956 * that we can't or don't work around, so it's not 1957 * supported, but all later versions are 1958 */ 1959 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1960 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1961 dev_ok = B_TRUE; 1962 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1963 break; 1964 1965 case DEVICE_ID_5704C: 1966 case DEVICE_ID_5704S: 1967 case DEVICE_ID_5704: 1968 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1969 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1970 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1971 dev_ok = B_TRUE; 1972 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1973 break; 1974 1975 case DEVICE_ID_5705C: 1976 case DEVICE_ID_5705M: 1977 case DEVICE_ID_5705MA3: 1978 case DEVICE_ID_5705F: 1979 case DEVICE_ID_5705_2: 1980 case DEVICE_ID_5754: 1981 if (cidp->device == DEVICE_ID_5754) { 1982 cidp->chip_label = 5754; 1983 cidp->pci_type = BGE_PCI_E; 1984 } else { 1985 cidp->chip_label = 5705; 1986 cidp->pci_type = BGE_PCI; 1987 } 1988 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 1989 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 1990 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 1991 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1992 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1993 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1994 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1995 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 1996 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1997 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1998 cidp->statistic_type = BGE_STAT_REG; 1999 dev_ok = B_TRUE; 2000 break; 2001 2002 case DEVICE_ID_5906: 2003 case DEVICE_ID_5906M: 2004 cidp->chip_label = 5906; 2005 cidp->pci_type = BGE_PCI_E; 2006 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2007 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2008 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2009 cidp->mbuf_base = bge_mbuf_pool_base; 2010 cidp->mbuf_length = bge_mbuf_pool_len; 2011 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2012 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2013 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2014 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2015 cidp->statistic_type = BGE_STAT_REG; 2016 dev_ok = B_TRUE; 2017 break; 2018 2019 case DEVICE_ID_5753: 2020 cidp->chip_label = 5753; 2021 cidp->pci_type = BGE_PCI_E; 2022 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2023 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2024 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2025 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2026 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2027 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2028 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2029 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2030 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2031 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2032 cidp->statistic_type = BGE_STAT_REG; 2033 dev_ok = B_TRUE; 2034 break; 2035 2036 case DEVICE_ID_5755: 2037 case DEVICE_ID_5755M: 2038 cidp->chip_label = 5755; 2039 cidp->pci_type = BGE_PCI_E; 2040 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2041 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2042 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2043 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2044 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2045 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2046 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2047 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2048 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2049 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2050 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2051 cidp->statistic_type = BGE_STAT_REG; 2052 dev_ok = B_TRUE; 2053 break; 2054 2055 case DEVICE_ID_5756M: 2056 /* 2057 * This is nearly identical to the 5755M. 2058 * (Actually reports the 5755 chip ID.) 2059 */ 2060 cidp->chip_label = 5756; 2061 cidp->pci_type = BGE_PCI_E; 2062 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2063 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2064 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2065 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2066 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2067 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2068 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2069 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2070 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2071 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2072 cidp->statistic_type = BGE_STAT_REG; 2073 dev_ok = B_TRUE; 2074 break; 2075 2076 case DEVICE_ID_5787: 2077 case DEVICE_ID_5787M: 2078 cidp->chip_label = 5787; 2079 cidp->pci_type = BGE_PCI_E; 2080 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2081 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2082 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2083 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2084 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2085 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2086 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2087 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2088 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2089 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2090 cidp->statistic_type = BGE_STAT_REG; 2091 dev_ok = B_TRUE; 2092 break; 2093 2094 case DEVICE_ID_5706: 2095 cidp->chip_label = 5706; 2096 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2097 break; 2098 2099 case DEVICE_ID_5780: 2100 cidp->chip_label = 5780; 2101 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2102 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2103 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2104 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2105 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2106 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2107 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2108 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2109 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2110 cidp->statistic_type = BGE_STAT_REG; 2111 cidp->pci_type = BGE_PCI; 2112 dev_ok = B_TRUE; 2113 break; 2114 2115 case DEVICE_ID_5782: 2116 /* 2117 * Apart from the label, we treat this as a 5705(?) 2118 */ 2119 cidp->chip_label = 5782; 2120 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2121 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2122 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2123 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2124 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2125 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2126 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2127 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2128 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2129 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2130 cidp->statistic_type = BGE_STAT_REG; 2131 dev_ok = B_TRUE; 2132 break; 2133 2134 case DEVICE_ID_5788: 2135 /* 2136 * Apart from the label, we treat this as a 5705(?) 2137 */ 2138 cidp->chip_label = 5788; 2139 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2140 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2141 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2142 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2143 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2144 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2145 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2146 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2147 cidp->statistic_type = BGE_STAT_REG; 2148 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2149 dev_ok = B_TRUE; 2150 break; 2151 2152 case DEVICE_ID_5714C: 2153 if (cidp->revision >= REVISION_ID_5714_A2) 2154 cidp->msi_enabled = bge_enable_msi; 2155 /* FALLTHRU */ 2156 case DEVICE_ID_5714S: 2157 cidp->chip_label = 5714; 2158 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2159 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2160 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2161 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2162 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2163 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2164 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2165 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2166 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2167 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2168 cidp->pci_type = BGE_PCI_E; 2169 cidp->statistic_type = BGE_STAT_REG; 2170 dev_ok = B_TRUE; 2171 break; 2172 2173 case DEVICE_ID_5715C: 2174 case DEVICE_ID_5715S: 2175 cidp->chip_label = 5715; 2176 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2177 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2178 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2179 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2180 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2181 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2182 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2183 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2184 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2185 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2186 cidp->pci_type = BGE_PCI_E; 2187 cidp->statistic_type = BGE_STAT_REG; 2188 if (cidp->revision >= REVISION_ID_5715_A2) 2189 cidp->msi_enabled = bge_enable_msi; 2190 dev_ok = B_TRUE; 2191 break; 2192 2193 case DEVICE_ID_5721: 2194 cidp->chip_label = 5721; 2195 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2196 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2197 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2198 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2199 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2200 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2201 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2202 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2203 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2204 cidp->pci_type = BGE_PCI_E; 2205 cidp->statistic_type = BGE_STAT_REG; 2206 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2207 dev_ok = B_TRUE; 2208 break; 2209 2210 case DEVICE_ID_5722: 2211 cidp->chip_label = 5722; 2212 cidp->pci_type = BGE_PCI_E; 2213 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2214 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2215 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2216 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2217 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2218 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2219 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2220 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2221 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2222 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2223 cidp->statistic_type = BGE_STAT_REG; 2224 dev_ok = B_TRUE; 2225 break; 2226 2227 case DEVICE_ID_5751: 2228 case DEVICE_ID_5751M: 2229 cidp->chip_label = 5751; 2230 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2231 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2232 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2233 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2234 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2235 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2236 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2237 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2238 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2239 cidp->pci_type = BGE_PCI_E; 2240 cidp->statistic_type = BGE_STAT_REG; 2241 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2242 dev_ok = B_TRUE; 2243 break; 2244 2245 case DEVICE_ID_5752: 2246 case DEVICE_ID_5752M: 2247 cidp->chip_label = 5752; 2248 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2249 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2250 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2251 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2252 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2253 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2254 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2255 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2256 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2257 cidp->pci_type = BGE_PCI_E; 2258 cidp->statistic_type = BGE_STAT_REG; 2259 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2260 dev_ok = B_TRUE; 2261 break; 2262 2263 case DEVICE_ID_5789: 2264 cidp->chip_label = 5789; 2265 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2266 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2267 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2268 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2269 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2270 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2271 cidp->pci_type = BGE_PCI_E; 2272 cidp->statistic_type = BGE_STAT_REG; 2273 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2274 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2275 cidp->msi_enabled = B_TRUE; 2276 dev_ok = B_TRUE; 2277 break; 2278 2279 } 2280 2281 /* 2282 * Setup the default jumbo parameter. 2283 */ 2284 cidp->ethmax_size = ETHERMAX; 2285 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2286 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2287 2288 /* 2289 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2290 * setup below jumbo specific parameters. 2291 * 2292 * For BCM5714/5715, there is only one standard receive ring. So the 2293 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2294 * feature is enabled. 2295 */ 2296 if (bge_jumbo_enable && 2297 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2298 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2299 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2300 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2301 cidp->mbuf_lo_water_rdma = 2302 RDMA_MBUF_LOWAT_5714_JUMBO; 2303 cidp->mbuf_lo_water_rmac = 2304 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2305 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2306 cidp->jumbo_slots = 0; 2307 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2308 } else { 2309 cidp->mbuf_lo_water_rdma = 2310 RDMA_MBUF_LOWAT_JUMBO; 2311 cidp->mbuf_lo_water_rmac = 2312 MAC_RX_MBUF_LOWAT_JUMBO; 2313 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2314 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2315 } 2316 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2317 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2318 cidp->ethmax_size = cidp->default_mtu + 2319 sizeof (struct ether_header); 2320 } 2321 2322 /* 2323 * Identify the NV memory type: SEEPROM or Flash? 2324 */ 2325 cidp->nvtype = bge_nvmem_id(bgep); 2326 2327 /* 2328 * Now, we want to check whether this device is part of a 2329 * supported subsystem (e.g., on the motherboard of a Sun 2330 * branded platform). 2331 * 2332 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2333 */ 2334 if (cidp->subven == VENDOR_ID_SUN) 2335 sys_ok = B_TRUE; 2336 2337 /* 2338 * Rule 2: If it's on the list on known subsystems, then it's OK. 2339 * Note: 0x14e41647 should *not* appear in the list, but the code 2340 * doesn't enforce that. 2341 */ 2342 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2343 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2344 if (err == DDI_PROP_SUCCESS) { 2345 /* 2346 * Got the list; scan for a matching subsystem vendor/device 2347 */ 2348 subid = (cidp->subven << 16) | cidp->subdev; 2349 while (i--) 2350 if (ids[i] == subid) 2351 sys_ok = B_TRUE; 2352 ddi_prop_free(ids); 2353 } 2354 2355 /* 2356 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2357 * 2358 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2359 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2360 * we have to check specially for the exact device paths to the 2361 * motherboard devices on those platforms ;-( 2362 * 2363 * Note: we can't just use the "supported-subsystems" mechanism 2364 * above, because the entry would have to be 0x14e41647 -- which 2365 * would then accept *any* plugin card that *didn't* contain a 2366 * (valid) SEEPROM ;-( 2367 */ 2368 sysname = ddi_node_name(ddi_root_node()); 2369 devname = ddi_pathname(bgep->devinfo, buf); 2370 ASSERT(strlen(devname) > 0); 2371 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2372 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2373 sys_ok = B_TRUE; 2374 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2375 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2376 sys_ok = B_TRUE; 2377 2378 /* 2379 * Now check what we've discovered: is this truly a supported 2380 * chip on (the motherboard of) a supported platform? 2381 * 2382 * Possible problems here: 2383 * 1) it's a completely unheard-of chip (e.g. 5761) 2384 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2385 * 3) it's a chip we would support if it were on the motherboard 2386 * of a Sun platform, but this one isn't ;-( 2387 */ 2388 if (cidp->chip_label == 0) 2389 bge_problem(bgep, 2390 "Device 'pci%04x,%04x' not recognized (%d?)", 2391 cidp->vendor, cidp->device, cidp->device); 2392 else if (!dev_ok) 2393 bge_problem(bgep, 2394 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2395 cidp->vendor, cidp->device, cidp->chip_label, 2396 cidp->revision); 2397 #if BGE_DEBUGGING 2398 else if (!sys_ok) 2399 bge_problem(bgep, 2400 "%d-based subsystem 'pci%04x,%04x' not validated", 2401 cidp->chip_label, cidp->subven, cidp->subdev); 2402 #endif 2403 else 2404 cidp->flags |= CHIP_FLAG_SUPPORTED; 2405 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2406 return (EIO); 2407 return (0); 2408 } 2409 2410 void 2411 bge_chip_msi_trig(bge_t *bgep) 2412 { 2413 uint32_t regval; 2414 2415 regval = bgep->param_msi_cnt<<4; 2416 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2417 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2418 } 2419 2420 /* 2421 * Various registers that control the chip's internal engines (state 2422 * machines) have a <reset> and <enable> bits (fortunately, in the 2423 * same place in each such register :-). 2424 * 2425 * To reset the state machine, the <reset> bit must be written with 1; 2426 * it will then read back as 1 while the reset is in progress, but 2427 * self-clear to 0 when the reset completes. 2428 * 2429 * To enable a state machine, one must set the <enable> bit, which 2430 * will continue to read back as 0 until the state machine is running. 2431 * 2432 * To disable a state machine, the <enable> bit must be cleared, but 2433 * it will continue to read back as 1 until the state machine actually 2434 * stops. 2435 * 2436 * This routine implements polling for completion of a reset, enable 2437 * or disable operation, returning B_TRUE on success (bit reached the 2438 * required state) or B_FALSE on timeout (200*100us == 20ms). 2439 */ 2440 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2441 uint32_t mask, uint32_t val); 2442 #pragma no_inline(bge_chip_poll_engine) 2443 2444 static boolean_t 2445 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2446 uint32_t mask, uint32_t val) 2447 { 2448 uint32_t regval; 2449 uint32_t n; 2450 2451 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2452 (void *)bgep, regno, mask, val)); 2453 2454 for (n = 200; n; --n) { 2455 regval = bge_reg_get32(bgep, regno); 2456 if ((regval & mask) == val) 2457 return (B_TRUE); 2458 drv_usecwait(100); 2459 } 2460 2461 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2462 return (B_FALSE); 2463 } 2464 2465 /* 2466 * Various registers that control the chip's internal engines (state 2467 * machines) have a <reset> bit (fortunately, in the same place in 2468 * each such register :-). To reset the state machine, this bit must 2469 * be written with 1; it will then read back as 1 while the reset is 2470 * in progress, but self-clear to 0 when the reset completes. 2471 * 2472 * This code sets the bit, then polls for it to read back as zero. 2473 * The return value is B_TRUE on success (reset bit cleared itself), 2474 * or B_FALSE if the state machine didn't recover :( 2475 * 2476 * NOTE: the Core reset is similar to other resets, except that we 2477 * can't poll for completion, since the Core reset disables memory 2478 * access! So we just have to assume that it will all complete in 2479 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2480 */ 2481 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2482 #pragma no_inline(bge_chip_reset_engine) 2483 2484 static boolean_t 2485 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2486 { 2487 uint32_t regval; 2488 uint32_t val32; 2489 2490 regval = bge_reg_get32(bgep, regno); 2491 2492 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2493 (void *)bgep, regno)); 2494 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2495 regno, regval)); 2496 2497 regval |= STATE_MACHINE_RESET_BIT; 2498 2499 switch (regno) { 2500 case MISC_CONFIG_REG: 2501 /* 2502 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2503 * resetting PCIE block and bringing PCIE link down, bit 29 2504 * in the register needs to be set first, and then set it again 2505 * while the reset bit is written. 2506 * See:P500 of 57xx-PG102-RDS.pdf. 2507 */ 2508 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2509 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2510 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2511 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2512 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2513 if (bgep->chipid.pci_type == BGE_PCI_E) { 2514 if (bgep->chipid.asic_rev == 2515 MHCR_CHIP_REV_5751_A0 || 2516 bgep->chipid.asic_rev == 2517 MHCR_CHIP_REV_5721_A0 || 2518 bgep->chipid.asic_rev == 2519 MHCR_CHIP_REV_5755_A0) { 2520 val32 = bge_reg_get32(bgep, 2521 PHY_TEST_CTRL_REG); 2522 if (val32 == (PHY_PCIE_SCRAM_MODE | 2523 PHY_PCIE_LTASS_MODE)) 2524 bge_reg_put32(bgep, 2525 PHY_TEST_CTRL_REG, 2526 PHY_PCIE_SCRAM_MODE); 2527 val32 = pci_config_get32 2528 (bgep->cfg_handle, 2529 PCI_CONF_BGE_CLKCTL); 2530 val32 |= CLKCTL_PCIE_A0_FIX; 2531 pci_config_put32(bgep->cfg_handle, 2532 PCI_CONF_BGE_CLKCTL, val32); 2533 } 2534 bge_reg_set32(bgep, regno, 2535 MISC_CONFIG_GRC_RESET_DISABLE); 2536 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2537 } 2538 } 2539 2540 /* 2541 * Special case - causes Core reset 2542 * 2543 * On SPARC v9 we want to ensure that we don't start 2544 * timing until the I/O access has actually reached 2545 * the chip, otherwise we might make the next access 2546 * too early. And we can't just force the write out 2547 * by following it with a read (even to config space) 2548 * because that would cause the fault we're trying 2549 * to avoid. Hence the need for membar_sync() here. 2550 */ 2551 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2552 #ifdef __sparcv9 2553 membar_sync(); 2554 #endif /* __sparcv9 */ 2555 /* 2556 * On some platforms,system need about 300us for 2557 * link setup. 2558 */ 2559 drv_usecwait(300); 2560 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2561 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2562 bge_reg_clr32( 2563 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2564 } 2565 2566 if (bgep->chipid.pci_type == BGE_PCI_E) { 2567 /* PCI-E device need more reset time */ 2568 drv_usecwait(120000); 2569 2570 /* Set PCIE max payload size and clear error status. */ 2571 if ((bgep->chipid.chip_label == 5721) || 2572 (bgep->chipid.chip_label == 5751) || 2573 (bgep->chipid.chip_label == 5752) || 2574 (bgep->chipid.chip_label == 5789) || 2575 (bgep->chipid.chip_label == 5906)) { 2576 pci_config_put16(bgep->cfg_handle, 2577 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2578 pci_config_put16(bgep->cfg_handle, 2579 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2580 } 2581 } 2582 2583 BGE_PCICHK(bgep); 2584 return (B_TRUE); 2585 2586 default: 2587 bge_reg_put32(bgep, regno, regval); 2588 return (bge_chip_poll_engine(bgep, regno, 2589 STATE_MACHINE_RESET_BIT, 0)); 2590 } 2591 } 2592 2593 /* 2594 * Various registers that control the chip's internal engines (state 2595 * machines) have an <enable> bit (fortunately, in the same place in 2596 * each such register :-). To stop the state machine, this bit must 2597 * be written with 0, then polled to see when the state machine has 2598 * actually stopped. 2599 * 2600 * The return value is B_TRUE on success (enable bit cleared), or 2601 * B_FALSE if the state machine didn't stop :( 2602 */ 2603 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2604 uint32_t morebits); 2605 #pragma no_inline(bge_chip_disable_engine) 2606 2607 static boolean_t 2608 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2609 { 2610 uint32_t regval; 2611 2612 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2613 (void *)bgep, regno, morebits)); 2614 2615 switch (regno) { 2616 case FTQ_RESET_REG: 2617 /* 2618 * For Schumacher's bugfix CR6490108 2619 */ 2620 #ifdef BGE_IPMI_ASF 2621 #ifdef BGE_NETCONSOLE 2622 if (bgep->asf_enabled) 2623 return (B_TRUE); 2624 #endif 2625 #endif 2626 /* 2627 * Not quite like the others; it doesn't 2628 * have an <enable> bit, but instead we 2629 * have to set and then clear all the bits 2630 */ 2631 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2632 drv_usecwait(100); 2633 bge_reg_put32(bgep, regno, 0); 2634 return (B_TRUE); 2635 2636 default: 2637 regval = bge_reg_get32(bgep, regno); 2638 regval &= ~STATE_MACHINE_ENABLE_BIT; 2639 regval &= ~morebits; 2640 bge_reg_put32(bgep, regno, regval); 2641 return (bge_chip_poll_engine(bgep, regno, 2642 STATE_MACHINE_ENABLE_BIT, 0)); 2643 } 2644 } 2645 2646 /* 2647 * Various registers that control the chip's internal engines (state 2648 * machines) have an <enable> bit (fortunately, in the same place in 2649 * each such register :-). To start the state machine, this bit must 2650 * be written with 1, then polled to see when the state machine has 2651 * actually started. 2652 * 2653 * The return value is B_TRUE on success (enable bit set), or 2654 * B_FALSE if the state machine didn't start :( 2655 */ 2656 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2657 uint32_t morebits); 2658 #pragma no_inline(bge_chip_enable_engine) 2659 2660 static boolean_t 2661 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2662 { 2663 uint32_t regval; 2664 2665 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2666 (void *)bgep, regno, morebits)); 2667 2668 switch (regno) { 2669 case FTQ_RESET_REG: 2670 #ifdef BGE_IPMI_ASF 2671 #ifdef BGE_NETCONSOLE 2672 if (bgep->asf_enabled) 2673 return (B_TRUE); 2674 #endif 2675 #endif 2676 /* 2677 * Not quite like the others; it doesn't 2678 * have an <enable> bit, but instead we 2679 * have to set and then clear all the bits 2680 */ 2681 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2682 drv_usecwait(100); 2683 bge_reg_put32(bgep, regno, 0); 2684 return (B_TRUE); 2685 2686 default: 2687 regval = bge_reg_get32(bgep, regno); 2688 regval |= STATE_MACHINE_ENABLE_BIT; 2689 regval |= morebits; 2690 bge_reg_put32(bgep, regno, regval); 2691 return (bge_chip_poll_engine(bgep, regno, 2692 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2693 } 2694 } 2695 2696 /* 2697 * Reprogram the Ethernet, Transmit, and Receive MAC 2698 * modes to match the param_* variables 2699 */ 2700 void bge_sync_mac_modes(bge_t *bgep); 2701 #pragma no_inline(bge_sync_mac_modes) 2702 2703 void 2704 bge_sync_mac_modes(bge_t *bgep) 2705 { 2706 uint32_t macmode; 2707 uint32_t regval; 2708 2709 ASSERT(mutex_owned(bgep->genlock)); 2710 2711 /* 2712 * Reprogram the Ethernet MAC mode ... 2713 */ 2714 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2715 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2716 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2717 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2718 macmode |= ETHERNET_MODE_LINK_POLARITY; 2719 else 2720 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2721 else 2722 macmode |= ETHERNET_MODE_LINK_POLARITY; 2723 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2724 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2725 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2726 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2727 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2728 else 2729 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2730 } else if (bgep->param_link_speed == 10 || 2731 bgep->param_link_speed == 100) 2732 macmode |= ETHERNET_MODE_PORTMODE_MII; 2733 else 2734 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2735 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2736 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2737 else 2738 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2739 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2740 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2741 else 2742 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2743 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2744 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2745 (void *)bgep, regval, macmode)); 2746 2747 /* 2748 * ... the Transmit MAC mode ... 2749 */ 2750 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2751 if (bgep->param_link_tx_pause) 2752 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2753 else 2754 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2755 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2756 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2757 (void *)bgep, regval, macmode)); 2758 2759 /* 2760 * ... and the Receive MAC mode 2761 */ 2762 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2763 if (bgep->param_link_rx_pause) 2764 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2765 else 2766 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2767 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2768 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2769 (void *)bgep, regval, macmode)); 2770 } 2771 2772 /* 2773 * bge_chip_sync() -- program the chip with the unicast MAC address, 2774 * the multicast hash table, the required level of promiscuity, and 2775 * the current loopback mode ... 2776 */ 2777 #ifdef BGE_IPMI_ASF 2778 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2779 #else 2780 int bge_chip_sync(bge_t *bgep); 2781 #endif 2782 #pragma no_inline(bge_chip_sync) 2783 2784 int 2785 #ifdef BGE_IPMI_ASF 2786 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2787 #else 2788 bge_chip_sync(bge_t *bgep) 2789 #endif 2790 { 2791 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2792 boolean_t promisc; 2793 uint64_t macaddr; 2794 uint32_t fill; 2795 int i, j; 2796 int retval = DDI_SUCCESS; 2797 2798 BGE_TRACE(("bge_chip_sync($%p)", 2799 (void *)bgep)); 2800 2801 ASSERT(mutex_owned(bgep->genlock)); 2802 2803 promisc = B_FALSE; 2804 fill = ~(uint32_t)0; 2805 2806 if (bgep->promisc) 2807 promisc = B_TRUE; 2808 else 2809 fill = (uint32_t)0; 2810 2811 /* 2812 * If the TX/RX MAC engines are already running, we should stop 2813 * them (and reset the RX engine) before changing the parameters. 2814 * If they're not running, this will have no effect ... 2815 * 2816 * NOTE: this is currently disabled by default because stopping 2817 * and restarting the Tx engine may cause an outgoing packet in 2818 * transit to be truncated. Also, stopping and restarting the 2819 * Rx engine seems to not work correctly on the 5705. Testing 2820 * has not (yet!) revealed any problems with NOT stopping and 2821 * restarting these engines (and Broadcom say their drivers don't 2822 * do this), but if it is found to cause problems, this variable 2823 * can be patched to re-enable the old behaviour ... 2824 */ 2825 if (bge_stop_start_on_sync) { 2826 #ifdef BGE_IPMI_ASF 2827 if (!bgep->asf_enabled) { 2828 if (!bge_chip_disable_engine(bgep, 2829 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2830 retval = DDI_FAILURE; 2831 } else { 2832 if (!bge_chip_disable_engine(bgep, 2833 RECEIVE_MAC_MODE_REG, 0)) 2834 retval = DDI_FAILURE; 2835 } 2836 #else 2837 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2838 RECEIVE_MODE_KEEP_VLAN_TAG)) 2839 retval = DDI_FAILURE; 2840 #endif 2841 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2842 retval = DDI_FAILURE; 2843 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2844 retval = DDI_FAILURE; 2845 } 2846 2847 /* 2848 * Reprogram the hashed multicast address table ... 2849 */ 2850 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2851 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2852 2853 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2854 bge_reg_put32(bgep, MAC_HASH_REG(i), 2855 bgep->mcast_hash[i] | fill); 2856 2857 #ifdef BGE_IPMI_ASF 2858 if (!bgep->asf_enabled || !asf_keeplive) { 2859 #endif 2860 /* 2861 * Transform the MAC address(es) from host to chip format, then 2862 * reprogram the transmit random backoff seed and the unicast 2863 * MAC address(es) ... 2864 */ 2865 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2866 for (i = 0, fill = 0, macaddr = 0ull; 2867 i < ETHERADDRL; ++i) { 2868 macaddr <<= 8; 2869 macaddr |= bgep->curr_addr[j].addr[i]; 2870 fill += bgep->curr_addr[j].addr[i]; 2871 } 2872 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2873 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2874 } 2875 2876 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2877 (void *)bgep, macaddr)); 2878 #ifdef BGE_IPMI_ASF 2879 } 2880 #endif 2881 2882 /* 2883 * Set or clear the PROMISCUOUS mode bit 2884 */ 2885 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2886 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2887 2888 /* 2889 * Sync the rest of the MAC modes too ... 2890 */ 2891 bge_sync_mac_modes(bgep); 2892 2893 /* 2894 * Restart RX/TX MAC engines if required ... 2895 */ 2896 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2897 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2898 retval = DDI_FAILURE; 2899 #ifdef BGE_IPMI_ASF 2900 if (!bgep->asf_enabled) { 2901 if (!bge_chip_enable_engine(bgep, 2902 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2903 retval = DDI_FAILURE; 2904 } else { 2905 if (!bge_chip_enable_engine(bgep, 2906 RECEIVE_MAC_MODE_REG, 0)) 2907 retval = DDI_FAILURE; 2908 } 2909 #else 2910 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2911 RECEIVE_MODE_KEEP_VLAN_TAG)) 2912 retval = DDI_FAILURE; 2913 #endif 2914 } 2915 return (retval); 2916 } 2917 2918 /* 2919 * This array defines the sequence of state machine control registers 2920 * in which the <enable> bit must be cleared to bring the chip to a 2921 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2922 */ 2923 static bge_regno_t shutdown_engine_regs[] = { 2924 RECEIVE_MAC_MODE_REG, 2925 RCV_BD_INITIATOR_MODE_REG, 2926 RCV_LIST_PLACEMENT_MODE_REG, 2927 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2928 RCV_DATA_BD_INITIATOR_MODE_REG, 2929 RCV_DATA_COMPLETION_MODE_REG, 2930 RCV_BD_COMPLETION_MODE_REG, 2931 2932 SEND_BD_SELECTOR_MODE_REG, 2933 SEND_BD_INITIATOR_MODE_REG, 2934 SEND_DATA_INITIATOR_MODE_REG, 2935 READ_DMA_MODE_REG, 2936 SEND_DATA_COMPLETION_MODE_REG, 2937 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2938 SEND_BD_COMPLETION_MODE_REG, 2939 TRANSMIT_MAC_MODE_REG, 2940 2941 HOST_COALESCE_MODE_REG, 2942 WRITE_DMA_MODE_REG, 2943 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2944 FTQ_RESET_REG, /* special - see code */ 2945 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2946 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2947 BGE_REGNO_NONE /* terminator */ 2948 }; 2949 2950 #ifndef __sparc 2951 static bge_regno_t quiesce_regs[] = { 2952 READ_DMA_MODE_REG, 2953 DMA_COMPLETION_MODE_REG, 2954 WRITE_DMA_MODE_REG, 2955 BGE_REGNO_NONE 2956 }; 2957 2958 void bge_chip_stop_nonblocking(bge_t *bgep); 2959 #pragma no_inline(bge_chip_stop_nonblocking) 2960 2961 /* 2962 * This function is called by bge_quiesce(). We 2963 * turn off all the DMA engines here. 2964 */ 2965 void 2966 bge_chip_stop_nonblocking(bge_t *bgep) 2967 { 2968 bge_regno_t *rbp; 2969 2970 /* 2971 * Flag that no more activity may be initiated 2972 */ 2973 bgep->progress &= ~PROGRESS_READY; 2974 2975 rbp = quiesce_regs; 2976 while (*rbp != BGE_REGNO_NONE) { 2977 (void) bge_chip_disable_engine(bgep, *rbp, 0); 2978 ++rbp; 2979 } 2980 2981 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2982 } 2983 2984 #endif 2985 2986 /* 2987 * bge_chip_stop() -- stop all chip processing 2988 * 2989 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2990 * we've detected a problem internally; otherwise, this is a normal 2991 * (clean) stop (at user request i.e. the last STREAM has been closed). 2992 */ 2993 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2994 #pragma no_inline(bge_chip_stop) 2995 2996 void 2997 bge_chip_stop(bge_t *bgep, boolean_t fault) 2998 { 2999 bge_regno_t regno; 3000 bge_regno_t *rbp; 3001 boolean_t ok; 3002 3003 BGE_TRACE(("bge_chip_stop($%p)", 3004 (void *)bgep)); 3005 3006 ASSERT(mutex_owned(bgep->genlock)); 3007 3008 rbp = shutdown_engine_regs; 3009 /* 3010 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3011 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3012 * -ory arbiter should not be disabled. 3013 */ 3014 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3015 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3016 ok &= bge_chip_disable_engine(bgep, regno, 0); 3017 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3018 (regno != DMA_COMPLETION_MODE_REG) && 3019 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3020 (regno != BUFFER_MANAGER_MODE_REG) && 3021 (regno != MEMORY_ARBITER_MODE_REG)) 3022 ok &= bge_chip_disable_engine(bgep, 3023 regno, 0); 3024 } 3025 3026 if (!ok && !fault) 3027 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3028 3029 /* 3030 * Finally, disable (all) MAC events & clear the MAC status 3031 */ 3032 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3033 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3034 3035 /* 3036 * if we're stopping the chip because of a detected fault then do 3037 * appropriate actions 3038 */ 3039 if (fault) { 3040 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3041 bgep->bge_chip_state = BGE_CHIP_FAULT; 3042 if (!bgep->manual_reset) 3043 ddi_fm_service_impact(bgep->devinfo, 3044 DDI_SERVICE_LOST); 3045 if (bgep->bge_dma_error) { 3046 /* 3047 * need to free buffers in case the fault was 3048 * due to a memory error in a buffer - got to 3049 * do a fair bit of tidying first 3050 */ 3051 if (bgep->progress & PROGRESS_KSTATS) { 3052 bge_fini_kstats(bgep); 3053 bgep->progress &= ~PROGRESS_KSTATS; 3054 } 3055 if (bgep->progress & PROGRESS_INTR) { 3056 bge_intr_disable(bgep); 3057 rw_enter(bgep->errlock, RW_WRITER); 3058 bge_fini_rings(bgep); 3059 rw_exit(bgep->errlock); 3060 bgep->progress &= ~PROGRESS_INTR; 3061 } 3062 if (bgep->progress & PROGRESS_BUFS) { 3063 bge_free_bufs(bgep); 3064 bgep->progress &= ~PROGRESS_BUFS; 3065 } 3066 bgep->bge_dma_error = B_FALSE; 3067 } 3068 } 3069 } else 3070 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3071 } 3072 3073 /* 3074 * Poll for completion of chip's ROM firmware; also, at least on the 3075 * first time through, find and return the hardware MAC address, if any. 3076 */ 3077 static uint64_t bge_poll_firmware(bge_t *bgep); 3078 #pragma no_inline(bge_poll_firmware) 3079 3080 static uint64_t 3081 bge_poll_firmware(bge_t *bgep) 3082 { 3083 uint64_t magic; 3084 uint64_t mac; 3085 uint32_t gen, val; 3086 uint32_t i; 3087 3088 /* 3089 * Step 19: poll for firmware completion (GENCOMM port set 3090 * to the ones complement of T3_MAGIC_NUMBER). 3091 * 3092 * While we're at it, we also read the MAC address register; 3093 * at some stage the firmware will load this with the 3094 * factory-set value. 3095 * 3096 * When both the magic number and the MAC address are set, 3097 * we're done; but we impose a time limit of one second 3098 * (1000*1000us) in case the firmware fails in some fashion 3099 * or the SEEPROM that provides that MAC address isn't fitted. 3100 * 3101 * After the first time through (chip state != INITIAL), we 3102 * don't need the MAC address to be set (we've already got it 3103 * or not, from the first time), so we don't wait for it, but 3104 * we still have to wait for the T3_MAGIC_NUMBER. 3105 * 3106 * Note: the magic number is only a 32-bit quantity, but the NIC 3107 * memory is 64-bit (and big-endian) internally. Addressing the 3108 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3109 * it work correctly on both big- and little-endian hosts. 3110 */ 3111 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3112 MHCR_CHIP_ASIC_REV_5906) { 3113 for (i = 0; i < 1000; ++i) { 3114 drv_usecwait(1000); 3115 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3116 if (val & VCPU_INIT_DONE) 3117 break; 3118 } 3119 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3120 (void *)bgep, i)); 3121 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3122 } else { 3123 for (i = 0; i < 1000; ++i) { 3124 drv_usecwait(1000); 3125 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3126 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3127 drv_usecwait(100000); 3128 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3129 #ifdef BGE_IPMI_ASF 3130 if (!bgep->asf_enabled) { 3131 #endif 3132 if (gen != ~T3_MAGIC_NUMBER) 3133 continue; 3134 #ifdef BGE_IPMI_ASF 3135 } 3136 #endif 3137 if (mac != 0ULL) 3138 break; 3139 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3140 break; 3141 } 3142 } 3143 3144 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3145 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3146 (void *)bgep, gen, i)); 3147 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3148 mac, magic)); 3149 3150 return (mac); 3151 } 3152 3153 /* 3154 * Maximum times of trying to get the NVRAM access lock 3155 * by calling bge_nvmem_acquire() 3156 */ 3157 #define MAX_TRY_NVMEM_ACQUIRE 10000 3158 3159 #ifdef BGE_IPMI_ASF 3160 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3161 #else 3162 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3163 #endif 3164 #pragma no_inline(bge_chip_reset) 3165 3166 int 3167 #ifdef BGE_IPMI_ASF 3168 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3169 #else 3170 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3171 #endif 3172 { 3173 chip_id_t chipid; 3174 uint64_t mac; 3175 uint64_t magic; 3176 uint32_t modeflags; 3177 uint32_t mhcr; 3178 uint32_t sx0; 3179 uint32_t i, tries; 3180 #ifdef BGE_IPMI_ASF 3181 uint32_t mailbox; 3182 #endif 3183 int retval = DDI_SUCCESS; 3184 3185 BGE_TRACE(("bge_chip_reset($%p, %d)", 3186 (void *)bgep, enable_dma)); 3187 3188 ASSERT(mutex_owned(bgep->genlock)); 3189 3190 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3191 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3192 3193 /* 3194 * Do we need to stop the chip cleanly before resetting? 3195 */ 3196 switch (bgep->bge_chip_state) { 3197 default: 3198 _NOTE(NOTREACHED) 3199 return (DDI_FAILURE); 3200 3201 case BGE_CHIP_INITIAL: 3202 case BGE_CHIP_STOPPED: 3203 case BGE_CHIP_RESET: 3204 break; 3205 3206 case BGE_CHIP_RUNNING: 3207 case BGE_CHIP_ERROR: 3208 case BGE_CHIP_FAULT: 3209 bge_chip_stop(bgep, B_FALSE); 3210 break; 3211 } 3212 3213 #ifdef BGE_IPMI_ASF 3214 if (bgep->asf_enabled) { 3215 #ifdef __sparc 3216 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3217 MHCR_ENABLE_TAGGED_STATUS_MODE | 3218 MHCR_MASK_INTERRUPT_MODE | 3219 MHCR_MASK_PCI_INT_OUTPUT | 3220 MHCR_CLEAR_INTERRUPT_INTA | 3221 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3222 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3223 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3224 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3225 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3226 MEMORY_ARBITER_ENABLE); 3227 #endif 3228 if (asf_mode == ASF_MODE_INIT) { 3229 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3230 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3231 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3232 } 3233 } 3234 #endif 3235 /* 3236 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3237 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3238 * 3239 * Before reset Core clock,it is 3240 * also required to initialize the Memory Arbiter as specified in step9 3241 * and Misc Host Control Register as specified in step-13 3242 * Step 4-5: reset Core clock & wait for completion 3243 * Steps 6-8: are done by bge_chip_cfg_init() 3244 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3245 */ 3246 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3247 retval = DDI_FAILURE; 3248 3249 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3250 MHCR_ENABLE_TAGGED_STATUS_MODE | 3251 MHCR_MASK_INTERRUPT_MODE | 3252 MHCR_MASK_PCI_INT_OUTPUT | 3253 MHCR_CLEAR_INTERRUPT_INTA; 3254 #ifdef _BIG_ENDIAN 3255 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3256 #endif /* _BIG_ENDIAN */ 3257 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3258 #ifdef BGE_IPMI_ASF 3259 if (bgep->asf_enabled) 3260 bgep->asf_wordswapped = B_FALSE; 3261 #endif 3262 /* 3263 * NVRAM Corruption Workaround 3264 */ 3265 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3266 if (bge_nvmem_acquire(bgep) != EAGAIN) 3267 break; 3268 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3269 BGE_DEBUG(("%s: fail to acquire nvram lock", 3270 bgep->ifname)); 3271 3272 #ifdef BGE_IPMI_ASF 3273 if (!bgep->asf_enabled) { 3274 #endif 3275 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3276 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3277 #ifdef BGE_IPMI_ASF 3278 } 3279 #endif 3280 3281 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3282 retval = DDI_FAILURE; 3283 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3284 3285 /* 3286 * Step 8a: This may belong elsewhere, but BCM5721 needs 3287 * a bit set to avoid a fifo overflow/underflow bug. 3288 */ 3289 if ((bgep->chipid.chip_label == 5721) || 3290 (bgep->chipid.chip_label == 5751) || 3291 (bgep->chipid.chip_label == 5752) || 3292 (bgep->chipid.chip_label == 5755) || 3293 (bgep->chipid.chip_label == 5756) || 3294 (bgep->chipid.chip_label == 5789) || 3295 (bgep->chipid.chip_label == 5906)) 3296 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3297 3298 3299 /* 3300 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3301 * not be changed. 3302 */ 3303 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3304 retval = DDI_FAILURE; 3305 3306 /* 3307 * Steps 10-11: configure PIO endianness options and 3308 * enable indirect register access -- already done 3309 * Steps 12-13: enable writing to the PCI state & clock 3310 * control registers -- not required; we aren't going to 3311 * use those features. 3312 * Steps 14-15: Configure DMA endianness options. See 3313 * the comments on the setting of the MHCR above. 3314 */ 3315 #ifdef _BIG_ENDIAN 3316 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3317 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3318 #else 3319 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3320 #endif /* _BIG_ENDIAN */ 3321 #ifdef BGE_IPMI_ASF 3322 if (bgep->asf_enabled) 3323 modeflags |= MODE_HOST_STACK_UP; 3324 #endif 3325 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3326 3327 #ifdef BGE_IPMI_ASF 3328 if (bgep->asf_enabled) { 3329 #ifdef __sparc 3330 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3331 MEMORY_ARBITER_ENABLE | 3332 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3333 #endif 3334 3335 #ifdef BGE_NETCONSOLE 3336 if (!bgep->asf_newhandshake) { 3337 if ((asf_mode == ASF_MODE_INIT) || 3338 (asf_mode == ASF_MODE_POST_INIT)) { 3339 bge_asf_post_reset_old_mode(bgep, 3340 BGE_INIT_RESET); 3341 } else { 3342 bge_asf_post_reset_old_mode(bgep, 3343 BGE_SHUTDOWN_RESET); 3344 } 3345 } 3346 #endif 3347 3348 /* Wait for NVRAM init */ 3349 i = 0; 3350 drv_usecwait(5000); 3351 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3352 3353 while ((mailbox != (uint32_t) 3354 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3355 (i < 10000)) { 3356 drv_usecwait(100); 3357 mailbox = bge_nic_get32(bgep, 3358 BGE_FIRMWARE_MAILBOX); 3359 i++; 3360 } 3361 3362 #ifndef BGE_NETCONSOLE 3363 if (!bgep->asf_newhandshake) { 3364 if ((asf_mode == ASF_MODE_INIT) || 3365 (asf_mode == ASF_MODE_POST_INIT)) { 3366 3367 bge_asf_post_reset_old_mode(bgep, 3368 BGE_INIT_RESET); 3369 } else { 3370 bge_asf_post_reset_old_mode(bgep, 3371 BGE_SHUTDOWN_RESET); 3372 } 3373 } 3374 #endif 3375 } 3376 #endif 3377 /* 3378 * Steps 16-17: poll for firmware completion 3379 */ 3380 mac = bge_poll_firmware(bgep); 3381 3382 /* 3383 * Step 18: enable external memory -- doesn't apply. 3384 * 3385 * However we take the opportunity to set the MLCR anyway, as 3386 * this register also controls the SEEPROM auto-access method 3387 * which we may want to use later ... 3388 * 3389 * The proper value here depends on the way the chip is wired 3390 * into the circuit board, as this register *also* controls which 3391 * of the "Miscellaneous I/O" pins are driven as outputs and the 3392 * values driven onto those pins! 3393 * 3394 * See also step 74 in the PRM ... 3395 */ 3396 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3397 bgep->chipid.bge_mlcr_default); 3398 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3399 3400 /* 3401 * Step 20: clear the Ethernet MAC mode register 3402 */ 3403 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3404 3405 /* 3406 * Step 21: restore cache-line-size, latency timer, and 3407 * subsystem ID registers to their original values (not 3408 * those read into the local structure <chipid>, 'cos 3409 * that was after they were cleared by the RESET). 3410 * 3411 * Note: the Subsystem Vendor/Device ID registers are not 3412 * directly writable in config space, so we use the shadow 3413 * copy in "Page Zero" of register space to restore them 3414 * both in one go ... 3415 */ 3416 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3417 bgep->chipid.clsize); 3418 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3419 bgep->chipid.latency); 3420 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3421 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3422 3423 /* 3424 * The SEND INDEX registers should be reset to zero by the 3425 * global chip reset; if they're not, there'll be trouble 3426 * later on. 3427 */ 3428 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3429 if (sx0 != 0) { 3430 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3431 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3432 retval = DDI_FAILURE; 3433 } 3434 3435 /* Enable MSI code */ 3436 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3437 bge_reg_set32(bgep, MSI_MODE_REG, 3438 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3439 3440 /* 3441 * On the first time through, save the factory-set MAC address 3442 * (if any). If bge_poll_firmware() above didn't return one 3443 * (from a chip register) consider looking in the attached NV 3444 * memory device, if any. Once we have it, we save it in both 3445 * register-image (64-bit) and byte-array forms. All-zero and 3446 * all-one addresses are not valid, and we refuse to stash those. 3447 */ 3448 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3449 if (mac == 0ULL) 3450 mac = bge_get_nvmac(bgep); 3451 if (mac != 0ULL && mac != ~0ULL) { 3452 bgep->chipid.hw_mac_addr = mac; 3453 for (i = ETHERADDRL; i-- != 0; ) { 3454 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3455 mac >>= 8; 3456 } 3457 bgep->chipid.vendor_addr.set = B_TRUE; 3458 } 3459 } 3460 3461 #ifdef BGE_IPMI_ASF 3462 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3463 if (asf_mode != ASF_MODE_NONE) { 3464 if ((asf_mode == ASF_MODE_INIT) || 3465 (asf_mode == ASF_MODE_POST_INIT)) { 3466 3467 bge_asf_post_reset_new_mode(bgep, 3468 BGE_INIT_RESET); 3469 } else { 3470 bge_asf_post_reset_new_mode(bgep, 3471 BGE_SHUTDOWN_RESET); 3472 } 3473 } 3474 } 3475 #endif 3476 3477 /* 3478 * Record the new state 3479 */ 3480 bgep->chip_resets += 1; 3481 bgep->bge_chip_state = BGE_CHIP_RESET; 3482 return (retval); 3483 } 3484 3485 /* 3486 * bge_chip_start() -- start the chip transmitting and/or receiving, 3487 * including enabling interrupts 3488 */ 3489 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3490 #pragma no_inline(bge_chip_start) 3491 3492 int 3493 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3494 { 3495 uint32_t coalmode; 3496 uint32_t ledctl; 3497 uint32_t mtu; 3498 uint32_t maxring; 3499 uint32_t stats_mask; 3500 uint32_t dma_wrprio; 3501 uint64_t ring; 3502 int retval = DDI_SUCCESS; 3503 3504 BGE_TRACE(("bge_chip_start($%p)", 3505 (void *)bgep)); 3506 3507 ASSERT(mutex_owned(bgep->genlock)); 3508 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3509 3510 /* 3511 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3512 * The document specifies 95 separate steps to fully 3513 * initialise the chip!!!! 3514 * 3515 * The reset code above has already got us as far as step 3516 * 21, so we continue with ... 3517 * 3518 * Step 22: clear the MAC statistics block 3519 * (0x0300-0x0aff in NIC-local memory) 3520 */ 3521 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3522 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3523 NIC_MEM_STATISTICS_SIZE); 3524 3525 /* 3526 * Step 23: clear the status block (in host memory) 3527 */ 3528 DMA_ZERO(bgep->status_block); 3529 3530 /* 3531 * Step 24: set DMA read/write control register 3532 */ 3533 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3534 bgep->chipid.bge_dma_rwctrl); 3535 3536 /* 3537 * Step 25: Configure DMA endianness -- already done (16/17) 3538 * Step 26: Configure Host-Based Send Rings 3539 * Step 27: Indicate Host Stack Up 3540 */ 3541 bge_reg_set32(bgep, MODE_CONTROL_REG, 3542 MODE_HOST_SEND_BDS | 3543 MODE_HOST_STACK_UP); 3544 3545 /* 3546 * Step 28: Configure checksum options: 3547 * Solaris supports the hardware default checksum options. 3548 * 3549 * Workaround for Incorrect pseudo-header checksum calculation. 3550 */ 3551 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3552 bge_reg_set32(bgep, MODE_CONTROL_REG, 3553 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3554 3555 /* 3556 * Step 29: configure Timer Prescaler. The value is always the 3557 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3558 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3559 * for the whole chip! 3560 */ 3561 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3562 3563 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3564 drv_usecwait(40); 3565 /* put PHY into ready state */ 3566 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3567 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3568 drv_usecwait(40); 3569 } 3570 3571 /* 3572 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3573 * 3574 * If the mbuf_length is specified as 0, we just leave these at 3575 * their hardware defaults, rather than explicitly setting them. 3576 * As the Broadcom HRM,driver better not change the parameters 3577 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3578 */ 3579 if ((bgep->chipid.mbuf_length != 0) && 3580 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3581 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3582 bgep->chipid.mbuf_base); 3583 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3584 bgep->chipid.mbuf_length); 3585 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3586 DMAD_POOL_BASE_DEFAULT); 3587 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3588 DMAD_POOL_LENGTH_DEFAULT); 3589 } 3590 3591 /* 3592 * Step 32: configure MAC memory pool watermarks 3593 */ 3594 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3595 bgep->chipid.mbuf_lo_water_rdma); 3596 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3597 bgep->chipid.mbuf_lo_water_rmac); 3598 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3599 bgep->chipid.mbuf_hi_water); 3600 3601 /* 3602 * Step 33: configure DMA resource watermarks 3603 */ 3604 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3605 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3606 bge_dmad_lo_water); 3607 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3608 bge_dmad_hi_water); 3609 } 3610 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3611 3612 /* 3613 * Steps 34-36: enable buffer manager & internal h/w queues 3614 */ 3615 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3616 STATE_MACHINE_ATTN_ENABLE_BIT)) 3617 retval = DDI_FAILURE; 3618 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3619 retval = DDI_FAILURE; 3620 3621 /* 3622 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3623 */ 3624 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3625 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3626 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3627 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3628 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3629 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3630 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3631 } 3632 3633 /* 3634 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3635 */ 3636 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3637 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3638 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3639 bge_replenish_jumbo); 3640 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3641 bge_replenish_mini); 3642 } 3643 3644 /* 3645 * Steps 41-43: clear Send Ring Producer Indices and initialise 3646 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3647 */ 3648 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3649 maxring = BGE_SEND_RINGS_MAX; 3650 else 3651 maxring = BGE_SEND_RINGS_MAX_5705; 3652 for (ring = 0; ring < maxring; ++ring) { 3653 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3654 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3655 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3656 &bgep->send[ring].hw_rcb); 3657 } 3658 3659 /* 3660 * Steps 44-45: initialise Receive Return Rings 3661 * (0x0200-0x02ff in NIC-local memory) 3662 */ 3663 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3664 maxring = BGE_RECV_RINGS_MAX; 3665 else 3666 maxring = BGE_RECV_RINGS_MAX_5705; 3667 for (ring = 0; ring < maxring; ++ring) 3668 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3669 &bgep->recv[ring].hw_rcb); 3670 3671 /* 3672 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3673 */ 3674 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3675 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3676 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3677 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3678 } 3679 /* 3680 * Step 47: configure the MAC unicast address 3681 * Step 48: configure the random backoff seed 3682 * Step 96: set up multicast filters 3683 */ 3684 #ifdef BGE_IPMI_ASF 3685 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3686 #else 3687 if (bge_chip_sync(bgep) == DDI_FAILURE) 3688 #endif 3689 retval = DDI_FAILURE; 3690 3691 /* 3692 * Step 49: configure the MTU 3693 */ 3694 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3695 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3696 3697 /* 3698 * Step 50: configure the IPG et al 3699 */ 3700 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3701 3702 /* 3703 * Step 51: configure the default Rx Return Ring 3704 */ 3705 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3706 3707 /* 3708 * Steps 52-54: configure Receive List Placement, 3709 * and enable Receive List Placement Statistics 3710 */ 3711 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3712 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3713 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3714 case MHCR_CHIP_ASIC_REV_5700: 3715 case MHCR_CHIP_ASIC_REV_5701: 3716 case MHCR_CHIP_ASIC_REV_5703: 3717 case MHCR_CHIP_ASIC_REV_5704: 3718 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3719 break; 3720 case MHCR_CHIP_ASIC_REV_5705: 3721 break; 3722 default: 3723 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3724 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3725 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3726 break; 3727 } 3728 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3729 3730 if (bgep->chipid.rx_rings > 1) 3731 bge_init_recv_rule(bgep); 3732 3733 /* 3734 * Steps 55-56: enable Send Data Initiator Statistics 3735 */ 3736 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3737 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3738 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3739 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3740 } else { 3741 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3742 SEND_INIT_STATS_ENABLE); 3743 } 3744 /* 3745 * Steps 57-58: stop (?) the Host Coalescing Engine 3746 */ 3747 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3748 retval = DDI_FAILURE; 3749 3750 /* 3751 * Steps 59-62: initialise Host Coalescing parameters 3752 */ 3753 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3754 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3755 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3756 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3757 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3758 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3759 bge_tx_count_intr); 3760 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3761 bge_tx_ticks_intr); 3762 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3763 bge_rx_count_intr); 3764 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3765 bge_rx_ticks_intr); 3766 } 3767 3768 /* 3769 * Steps 63-64: initialise status block & statistics 3770 * host memory addresses 3771 * The statistic block does not exist in some chipsets 3772 * Step 65: initialise Statistics Coalescing Tick Counter 3773 */ 3774 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3775 bgep->status_block.cookie.dmac_laddress); 3776 3777 /* 3778 * Steps 66-67: initialise status block & statistics 3779 * NIC-local memory addresses 3780 */ 3781 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3782 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3783 bgep->statistics.cookie.dmac_laddress); 3784 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3785 STATISTICS_TICKS_DEFAULT); 3786 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3787 NIC_MEM_STATUS_BLOCK); 3788 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3789 NIC_MEM_STATISTICS); 3790 } 3791 3792 /* 3793 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3794 * Completion Engine, the Receive List Placement Engine, and the 3795 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3796 * and BCM5715. 3797 */ 3798 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3799 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3800 coalmode = COALESCE_64_BYTE_STATUS; 3801 else 3802 coalmode = 0; 3803 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3804 retval = DDI_FAILURE; 3805 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3806 STATE_MACHINE_ATTN_ENABLE_BIT)) 3807 retval = DDI_FAILURE; 3808 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3809 retval = DDI_FAILURE; 3810 3811 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3812 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3813 STATE_MACHINE_ATTN_ENABLE_BIT)) 3814 retval = DDI_FAILURE; 3815 3816 /* 3817 * Step 72: Enable MAC DMA engines 3818 * Step 73: Clear & enable MAC statistics 3819 */ 3820 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3821 ETHERNET_MODE_ENABLE_FHDE | 3822 ETHERNET_MODE_ENABLE_RDE | 3823 ETHERNET_MODE_ENABLE_TDE); 3824 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3825 ETHERNET_MODE_ENABLE_TX_STATS | 3826 ETHERNET_MODE_ENABLE_RX_STATS | 3827 ETHERNET_MODE_CLEAR_TX_STATS | 3828 ETHERNET_MODE_CLEAR_RX_STATS); 3829 3830 /* 3831 * Step 74: configure the MLCR (Miscellaneous Local Control 3832 * Register); not required, as we set up the MLCR in step 10 3833 * (part of the reset code) above. 3834 * 3835 * Step 75: clear Interrupt Mailbox 0 3836 */ 3837 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3838 3839 /* 3840 * Steps 76-87: Gentlemen, start your engines ... 3841 * 3842 * Enable the DMA Completion Engine, the Write DMA Engine, 3843 * the Read DMA Engine, Receive Data Completion Engine, 3844 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3845 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3846 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3847 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3848 * 3849 * Beware exhaust fumes? 3850 */ 3851 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3852 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3853 retval = DDI_FAILURE; 3854 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3855 ALL_DMA_ATTN_BITS; 3856 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3857 MHCR_CHIP_ASIC_REV_5755) || 3858 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3859 MHCR_CHIP_ASIC_REV_5906)) { 3860 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3861 } 3862 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3863 dma_wrprio)) 3864 retval = DDI_FAILURE; 3865 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3866 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3867 retval = DDI_FAILURE; 3868 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3869 STATE_MACHINE_ATTN_ENABLE_BIT)) 3870 retval = DDI_FAILURE; 3871 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3872 if (!bge_chip_enable_engine(bgep, 3873 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3874 retval = DDI_FAILURE; 3875 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3876 retval = DDI_FAILURE; 3877 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3878 STATE_MACHINE_ATTN_ENABLE_BIT)) 3879 retval = DDI_FAILURE; 3880 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3881 RCV_BD_DISABLED_RING_ATTN)) 3882 retval = DDI_FAILURE; 3883 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3884 RCV_DATA_BD_ILL_RING_ATTN)) 3885 retval = DDI_FAILURE; 3886 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3887 retval = DDI_FAILURE; 3888 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3889 STATE_MACHINE_ATTN_ENABLE_BIT)) 3890 retval = DDI_FAILURE; 3891 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3892 STATE_MACHINE_ATTN_ENABLE_BIT)) 3893 retval = DDI_FAILURE; 3894 3895 /* 3896 * Step 88: download firmware -- doesn't apply 3897 * Steps 89-90: enable Transmit & Receive MAC Engines 3898 */ 3899 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3900 retval = DDI_FAILURE; 3901 #ifdef BGE_IPMI_ASF 3902 if (!bgep->asf_enabled) { 3903 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3904 RECEIVE_MODE_KEEP_VLAN_TAG)) 3905 retval = DDI_FAILURE; 3906 } else { 3907 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3908 retval = DDI_FAILURE; 3909 } 3910 #else 3911 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3912 RECEIVE_MODE_KEEP_VLAN_TAG)) 3913 retval = DDI_FAILURE; 3914 #endif 3915 3916 /* 3917 * Step 91: disable auto-polling of PHY status 3918 */ 3919 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3920 3921 /* 3922 * Step 92: configure D0 power state (not required) 3923 * Step 93: initialise LED control register () 3924 */ 3925 ledctl = LED_CONTROL_DEFAULT; 3926 switch (bgep->chipid.device) { 3927 case DEVICE_ID_5700: 3928 case DEVICE_ID_5700x: 3929 case DEVICE_ID_5701: 3930 /* 3931 * Switch to 5700 (MAC) mode on these older chips 3932 */ 3933 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3934 ledctl |= LED_CONTROL_LED_MODE_5700; 3935 break; 3936 3937 default: 3938 break; 3939 } 3940 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3941 3942 /* 3943 * Step 94: activate link 3944 */ 3945 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3946 3947 /* 3948 * Step 95: set up physical layer (PHY/SerDes) 3949 * restart autoneg (if required) 3950 */ 3951 if (reset_phys) 3952 if (bge_phys_update(bgep) == DDI_FAILURE) 3953 retval = DDI_FAILURE; 3954 3955 /* 3956 * Extra step (DSG): hand over all the Receive Buffers to the chip 3957 */ 3958 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3959 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3960 bgep->buff[ring].rf_next); 3961 3962 /* 3963 * MSI bits:The least significant MSI 16-bit word. 3964 * ISR will be triggered different. 3965 */ 3966 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3967 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3968 3969 /* 3970 * Extra step (DSG): select which interrupts are enabled 3971 * 3972 * Program the Ethernet MAC engine to signal attention on 3973 * Link Change events, then enable interrupts on MAC, DMA, 3974 * and FLOW attention signals. 3975 */ 3976 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3977 ETHERNET_EVENT_LINK_INT | 3978 ETHERNET_STATUS_PCS_ERROR_INT); 3979 #ifdef BGE_IPMI_ASF 3980 if (bgep->asf_enabled) { 3981 bge_reg_set32(bgep, MODE_CONTROL_REG, 3982 MODE_INT_ON_FLOW_ATTN | 3983 MODE_INT_ON_DMA_ATTN | 3984 MODE_HOST_STACK_UP| 3985 MODE_INT_ON_MAC_ATTN); 3986 } else { 3987 #endif 3988 bge_reg_set32(bgep, MODE_CONTROL_REG, 3989 MODE_INT_ON_FLOW_ATTN | 3990 MODE_INT_ON_DMA_ATTN | 3991 MODE_INT_ON_MAC_ATTN); 3992 #ifdef BGE_IPMI_ASF 3993 } 3994 #endif 3995 3996 /* 3997 * Step 97: enable PCI interrupts!!! 3998 */ 3999 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4000 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4001 MHCR_MASK_PCI_INT_OUTPUT); 4002 4003 /* 4004 * All done! 4005 */ 4006 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4007 return (retval); 4008 } 4009 4010 4011 /* 4012 * ========== Hardware interrupt handler ========== 4013 */ 4014 4015 #undef BGE_DBG 4016 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4017 4018 /* 4019 * Sync the status block, then atomically clear the specified bits in 4020 * the <flags-and-tag> field of the status block. 4021 * the <flags> word of the status block, returning the value of the 4022 * <tag> and the <flags> before the bits were cleared. 4023 */ 4024 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4025 #pragma inline(bge_status_sync) 4026 4027 static int 4028 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4029 { 4030 bge_status_t *bsp; 4031 int retval; 4032 4033 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4034 (void *)bgep, bits)); 4035 4036 ASSERT(bgep->bge_guard == BGE_GUARD); 4037 4038 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4039 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4040 if (retval != DDI_FM_OK) 4041 return (retval); 4042 4043 bsp = DMA_VPTR(bgep->status_block); 4044 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4045 4046 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4047 (void *)bgep, bits, *flags)); 4048 4049 return (retval); 4050 } 4051 4052 void bge_wake_factotum(bge_t *bgep); 4053 #pragma inline(bge_wake_factotum) 4054 4055 void 4056 bge_wake_factotum(bge_t *bgep) 4057 { 4058 mutex_enter(bgep->softintrlock); 4059 if (bgep->factotum_flag == 0) { 4060 bgep->factotum_flag = 1; 4061 ddi_trigger_softintr(bgep->factotum_id); 4062 } 4063 mutex_exit(bgep->softintrlock); 4064 } 4065 4066 /* 4067 * bge_intr() -- handle chip interrupts 4068 */ 4069 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4070 #pragma no_inline(bge_intr) 4071 4072 uint_t 4073 bge_intr(caddr_t arg1, caddr_t arg2) 4074 { 4075 bge_t *bgep = (void *)arg1; /* private device info */ 4076 bge_status_t *bsp; 4077 uint64_t flags; 4078 uint32_t regval; 4079 uint_t result; 4080 int retval, loop_cnt = 0; 4081 4082 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4083 4084 /* 4085 * GLD v2 checks that s/w setup is complete before passing 4086 * interrupts to this routine, thus eliminating the old 4087 * (and well-known) race condition around ddi_add_intr() 4088 */ 4089 ASSERT(bgep->progress & PROGRESS_HWINT); 4090 4091 result = DDI_INTR_UNCLAIMED; 4092 mutex_enter(bgep->genlock); 4093 4094 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4095 /* 4096 * Check whether chip's says it's asserting #INTA; 4097 * if not, don't process or claim the interrupt. 4098 * 4099 * Note that the PCI signal is active low, so the 4100 * bit is *zero* when the interrupt is asserted. 4101 */ 4102 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4103 if (regval & MLCR_INTA_STATE) { 4104 if (bge_check_acc_handle(bgep, bgep->io_handle) 4105 != DDI_FM_OK) 4106 goto chip_stop; 4107 mutex_exit(bgep->genlock); 4108 return (result); 4109 } 4110 4111 /* 4112 * Block further PCI interrupts ... 4113 */ 4114 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4115 MHCR_MASK_PCI_INT_OUTPUT); 4116 4117 } else { 4118 /* 4119 * Check MSI status 4120 */ 4121 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4122 if (regval & MSI_ERROR_ATTENTION) { 4123 BGE_REPORT((bgep, "msi error attention," 4124 " status=0x%x", regval)); 4125 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4126 } 4127 } 4128 4129 result = DDI_INTR_CLAIMED; 4130 4131 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4132 4133 /* 4134 * Sync the status block and grab the flags-n-tag from it. 4135 * We count the number of interrupts where there doesn't 4136 * seem to have been a DMA update of the status block; if 4137 * it *has* been updated, the counter will be cleared in 4138 * the while() loop below ... 4139 */ 4140 bgep->missed_dmas += 1; 4141 bsp = DMA_VPTR(bgep->status_block); 4142 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4143 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4144 /* 4145 * bge_chip_stop() may have freed dma area etc 4146 * while we were in this interrupt handler - 4147 * better not call bge_status_sync() 4148 */ 4149 (void) bge_check_acc_handle(bgep, 4150 bgep->io_handle); 4151 mutex_exit(bgep->genlock); 4152 return (DDI_INTR_CLAIMED); 4153 } 4154 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4155 &flags); 4156 if (retval != DDI_FM_OK) { 4157 bgep->bge_dma_error = B_TRUE; 4158 goto chip_stop; 4159 } 4160 4161 if (!(flags & STATUS_FLAG_UPDATED)) 4162 break; 4163 4164 /* 4165 * Tell the chip that we're processing the interrupt 4166 */ 4167 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4168 INTERRUPT_MBOX_DISABLE(flags)); 4169 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4170 DDI_FM_OK) 4171 goto chip_stop; 4172 4173 /* 4174 * Drop the mutex while we: 4175 * Receive any newly-arrived packets 4176 * Recycle any newly-finished send buffers 4177 */ 4178 bgep->bge_intr_running = B_TRUE; 4179 mutex_exit(bgep->genlock); 4180 bge_receive(bgep, bsp); 4181 bge_recycle(bgep, bsp); 4182 mutex_enter(bgep->genlock); 4183 bgep->bge_intr_running = B_FALSE; 4184 4185 /* 4186 * Tell the chip we've finished processing, and 4187 * give it the tag that we got from the status 4188 * block earlier, so that it knows just how far 4189 * we've gone. If it's got more for us to do, 4190 * it will now update the status block and try 4191 * to assert an interrupt (but we've got the 4192 * #INTA blocked at present). If we see the 4193 * update, we'll loop around to do some more. 4194 * Eventually we'll get out of here ... 4195 */ 4196 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4197 INTERRUPT_MBOX_ENABLE(flags)); 4198 if (bgep->chipid.pci_type == BGE_PCI_E) 4199 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4200 bgep->missed_dmas = 0; 4201 } 4202 4203 /* 4204 * Check for exceptional conditions that we need to handle 4205 * 4206 * Link status changed 4207 * Status block not updated 4208 */ 4209 if (flags & STATUS_FLAG_LINK_CHANGED) 4210 bge_wake_factotum(bgep); 4211 4212 if (bgep->missed_dmas) { 4213 /* 4214 * Probably due to the internal status tag not 4215 * being reset. Force a status block update now; 4216 * this should ensure that we get an update and 4217 * a new interrupt. After that, we should be in 4218 * sync again ... 4219 */ 4220 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4221 "not updated?", flags)); 4222 bgep->missed_updates++; 4223 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4224 COALESCE_NOW); 4225 4226 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4227 /* 4228 * If this happens multiple times in a row, 4229 * it means DMA is just not working. Maybe 4230 * the chip's failed, or maybe there's a 4231 * problem on the PCI bus or in the host-PCI 4232 * bridge (Tomatillo). 4233 * 4234 * At all events, we want to stop further 4235 * interrupts and let the recovery code take 4236 * over to see whether anything can be done 4237 * about it ... 4238 */ 4239 bge_fm_ereport(bgep, 4240 DDI_FM_DEVICE_BADINT_LIMIT); 4241 goto chip_stop; 4242 } 4243 } 4244 4245 /* 4246 * Reenable assertion of #INTA, unless there's a DMA fault 4247 */ 4248 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4249 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4250 MHCR_MASK_PCI_INT_OUTPUT); 4251 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4252 DDI_FM_OK) 4253 goto chip_stop; 4254 } 4255 4256 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4257 goto chip_stop; 4258 4259 mutex_exit(bgep->genlock); 4260 return (result); 4261 4262 chip_stop: 4263 #ifdef BGE_IPMI_ASF 4264 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4265 /* 4266 * We must stop ASF heart beat before 4267 * bge_chip_stop(), otherwise some 4268 * computers (ex. IBM HS20 blade 4269 * server) may crash. 4270 */ 4271 bge_asf_update_status(bgep); 4272 bge_asf_stop_timer(bgep); 4273 bgep->asf_status = ASF_STAT_STOP; 4274 4275 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4276 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4277 } 4278 #endif 4279 bge_chip_stop(bgep, B_TRUE); 4280 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4281 mutex_exit(bgep->genlock); 4282 return (result); 4283 } 4284 4285 /* 4286 * ========== Factotum, implemented as a softint handler ========== 4287 */ 4288 4289 #undef BGE_DBG 4290 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4291 4292 static void bge_factotum_error_handler(bge_t *bgep); 4293 #pragma no_inline(bge_factotum_error_handler) 4294 4295 static void 4296 bge_factotum_error_handler(bge_t *bgep) 4297 { 4298 uint32_t flow; 4299 uint32_t rdma; 4300 uint32_t wdma; 4301 uint32_t tmac; 4302 uint32_t rmac; 4303 uint32_t rxrs; 4304 uint32_t txrs = 0; 4305 4306 ASSERT(mutex_owned(bgep->genlock)); 4307 4308 /* 4309 * Read all the registers that show the possible 4310 * reasons for the ERROR bit to be asserted 4311 */ 4312 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4313 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4314 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4315 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4316 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4317 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4318 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4319 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4320 4321 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4322 (void *)bgep, flow, rdma, wdma)); 4323 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4324 (void *)bgep, tmac, rmac, rxrs, txrs)); 4325 4326 /* 4327 * For now, just clear all the errors ... 4328 */ 4329 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4330 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4331 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4332 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4333 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4334 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4335 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4336 } 4337 4338 /* 4339 * Handler for hardware link state change. 4340 * 4341 * When this routine is called, the hardware link state has changed 4342 * and the new state is reflected in the param_* variables. Here 4343 * we must update the softstate and reprogram the MAC to match. 4344 */ 4345 static void bge_factotum_link_handler(bge_t *bgep); 4346 #pragma no_inline(bge_factotum_link_handler) 4347 4348 static void 4349 bge_factotum_link_handler(bge_t *bgep) 4350 { 4351 ASSERT(mutex_owned(bgep->genlock)); 4352 4353 /* 4354 * Update the s/w link_state 4355 */ 4356 if (bgep->param_link_up) 4357 bgep->link_state = LINK_STATE_UP; 4358 else 4359 bgep->link_state = LINK_STATE_DOWN; 4360 4361 /* 4362 * Reprogram the MAC modes to match 4363 */ 4364 bge_sync_mac_modes(bgep); 4365 } 4366 4367 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4368 #pragma no_inline(bge_factotum_link_check) 4369 4370 static boolean_t 4371 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4372 { 4373 boolean_t check; 4374 uint64_t flags; 4375 uint32_t tmac_status; 4376 4377 ASSERT(mutex_owned(bgep->genlock)); 4378 4379 /* 4380 * Get & clear the writable status bits in the Tx status register 4381 * (some bits are write-1-to-clear, others are just readonly). 4382 */ 4383 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4384 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4385 4386 /* 4387 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4388 */ 4389 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4390 STATUS_FLAG_LINK_CHANGED, &flags); 4391 if (*dma_state != DDI_FM_OK) 4392 return (B_FALSE); 4393 4394 /* 4395 * Clear any errors flagged in the status block ... 4396 */ 4397 if (flags & STATUS_FLAG_ERROR) 4398 bge_factotum_error_handler(bgep); 4399 4400 /* 4401 * We need to check the link status if: 4402 * the status block says there's been a link change 4403 * or there's any discrepancy between the various 4404 * flags indicating the link state (link_state, 4405 * param_link_up, and the LINK STATE bit in the 4406 * Transmit MAC status register). 4407 */ 4408 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4409 switch (bgep->link_state) { 4410 case LINK_STATE_UP: 4411 check |= (bgep->param_link_up == B_FALSE); 4412 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4413 break; 4414 4415 case LINK_STATE_DOWN: 4416 check |= (bgep->param_link_up != B_FALSE); 4417 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4418 break; 4419 4420 default: 4421 check = B_TRUE; 4422 break; 4423 } 4424 4425 /* 4426 * If <check> is false, we're sure the link hasn't changed. 4427 * If true, however, it's not yet definitive; we have to call 4428 * bge_phys_check() to determine whether the link has settled 4429 * into a new state yet ... and if it has, then call the link 4430 * state change handler.But when the chip is 5700 in Dell 6650 4431 * ,even if check is false, the link may have changed.So we 4432 * have to call bge_phys_check() to determine the link state. 4433 */ 4434 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4435 check = bge_phys_check(bgep); 4436 if (check) 4437 bge_factotum_link_handler(bgep); 4438 } 4439 4440 return (check); 4441 } 4442 4443 /* 4444 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4445 */ 4446 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4447 #pragma no_inline(bge_factotum_stall_check) 4448 4449 static boolean_t 4450 bge_factotum_stall_check(bge_t *bgep) 4451 { 4452 uint32_t dogval; 4453 4454 ASSERT(mutex_owned(bgep->genlock)); 4455 4456 /* 4457 * Specific check for Tx stall ... 4458 * 4459 * The 'watchdog' counter is incremented whenever a packet 4460 * is queued, reset to 1 when some (but not all) buffers 4461 * are reclaimed, reset to 0 (disabled) when all buffers 4462 * are reclaimed, and shifted left here. If it exceeds the 4463 * threshold value, the chip is assumed to have stalled and 4464 * is put into the ERROR state. The factotum will then reset 4465 * it on the next pass. 4466 * 4467 * All of which should ensure that we don't get into a state 4468 * where packets are left pending indefinitely! 4469 */ 4470 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4471 if (dogval < bge_watchdog_count) 4472 return (B_FALSE); 4473 4474 #if !defined(BGE_NETCONSOLE) 4475 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4476 #endif 4477 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4478 return (B_TRUE); 4479 } 4480 4481 /* 4482 * The factotum is woken up when there's something to do that we'd rather 4483 * not do from inside a hardware interrupt handler or high-level cyclic. 4484 * Its two main tasks are: 4485 * reset & restart the chip after an error 4486 * check the link status whenever necessary 4487 */ 4488 uint_t bge_chip_factotum(caddr_t arg); 4489 #pragma no_inline(bge_chip_factotum) 4490 4491 uint_t 4492 bge_chip_factotum(caddr_t arg) 4493 { 4494 bge_t *bgep; 4495 uint_t result; 4496 boolean_t error; 4497 boolean_t linkchg; 4498 int dma_state; 4499 4500 bgep = (void *)arg; 4501 4502 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4503 4504 mutex_enter(bgep->softintrlock); 4505 if (bgep->factotum_flag == 0) { 4506 mutex_exit(bgep->softintrlock); 4507 return (DDI_INTR_UNCLAIMED); 4508 } 4509 bgep->factotum_flag = 0; 4510 mutex_exit(bgep->softintrlock); 4511 4512 result = DDI_INTR_CLAIMED; 4513 error = B_FALSE; 4514 linkchg = B_FALSE; 4515 4516 mutex_enter(bgep->genlock); 4517 switch (bgep->bge_chip_state) { 4518 default: 4519 break; 4520 4521 case BGE_CHIP_RUNNING: 4522 linkchg = bge_factotum_link_check(bgep, &dma_state); 4523 error = bge_factotum_stall_check(bgep); 4524 if (dma_state != DDI_FM_OK) { 4525 bgep->bge_dma_error = B_TRUE; 4526 error = B_TRUE; 4527 } 4528 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4529 error = B_TRUE; 4530 if (error) 4531 bgep->bge_chip_state = BGE_CHIP_ERROR; 4532 break; 4533 4534 case BGE_CHIP_ERROR: 4535 error = B_TRUE; 4536 break; 4537 4538 case BGE_CHIP_FAULT: 4539 /* 4540 * Fault detected, time to reset ... 4541 */ 4542 if (bge_autorecover) { 4543 if (!(bgep->progress & PROGRESS_BUFS)) { 4544 /* 4545 * if we can't allocate the ring buffers, 4546 * try later 4547 */ 4548 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4549 mutex_exit(bgep->genlock); 4550 return (result); 4551 } 4552 bgep->progress |= PROGRESS_BUFS; 4553 } 4554 if (!(bgep->progress & PROGRESS_INTR)) { 4555 bge_init_rings(bgep); 4556 bge_intr_enable(bgep); 4557 bgep->progress |= PROGRESS_INTR; 4558 } 4559 if (!(bgep->progress & PROGRESS_KSTATS)) { 4560 bge_init_kstats(bgep, 4561 ddi_get_instance(bgep->devinfo)); 4562 bgep->progress |= PROGRESS_KSTATS; 4563 } 4564 4565 BGE_REPORT((bgep, "automatic recovery activated")); 4566 4567 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4568 bgep->bge_chip_state = BGE_CHIP_ERROR; 4569 error = B_TRUE; 4570 } 4571 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4572 DDI_FM_OK) { 4573 bgep->bge_chip_state = BGE_CHIP_ERROR; 4574 error = B_TRUE; 4575 } 4576 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4577 DDI_FM_OK) { 4578 bgep->bge_chip_state = BGE_CHIP_ERROR; 4579 error = B_TRUE; 4580 } 4581 if (error == B_FALSE) { 4582 #ifdef BGE_IPMI_ASF 4583 if (bgep->asf_enabled && 4584 bgep->asf_status != ASF_STAT_RUN) { 4585 bgep->asf_timeout_id = timeout( 4586 bge_asf_heartbeat, (void *)bgep, 4587 drv_usectohz( 4588 BGE_ASF_HEARTBEAT_INTERVAL)); 4589 bgep->asf_status = ASF_STAT_RUN; 4590 } 4591 #endif 4592 if (!bgep->manual_reset) { 4593 ddi_fm_service_impact(bgep->devinfo, 4594 DDI_SERVICE_RESTORED); 4595 } 4596 } 4597 } 4598 break; 4599 } 4600 4601 4602 /* 4603 * If an error is detected, stop the chip now, marking it as 4604 * faulty, so that it will be reset next time through ... 4605 * 4606 * Note that if intr_running is set, then bge_intr() has dropped 4607 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4608 * this point so have to wait until the next time the factotum runs. 4609 */ 4610 if (error && !bgep->bge_intr_running) { 4611 #ifdef BGE_IPMI_ASF 4612 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4613 /* 4614 * We must stop ASF heart beat before bge_chip_stop(), 4615 * otherwise some computers (ex. IBM HS20 blade server) 4616 * may crash. 4617 */ 4618 bge_asf_update_status(bgep); 4619 bge_asf_stop_timer(bgep); 4620 bgep->asf_status = ASF_STAT_STOP; 4621 4622 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4623 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4624 } 4625 #endif 4626 bge_chip_stop(bgep, B_TRUE); 4627 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4628 } 4629 mutex_exit(bgep->genlock); 4630 4631 /* 4632 * If the link state changed, tell the world about it. 4633 * Note: can't do this while still holding the mutex. 4634 */ 4635 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4636 bgep->link_state != LINK_STATE_UNKNOWN) 4637 linkchg = B_TRUE; 4638 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4639 bgep->link_state == LINK_STATE_DOWN) 4640 linkchg = B_FALSE; 4641 4642 if (linkchg) { 4643 mac_link_update(bgep->mh, bgep->link_state); 4644 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4645 } 4646 if (bgep->manual_reset) { 4647 bgep->manual_reset = B_FALSE; 4648 } 4649 4650 return (result); 4651 } 4652 4653 /* 4654 * High-level cyclic handler 4655 * 4656 * This routine schedules a (low-level) softint callback to the 4657 * factotum, and prods the chip to update the status block (which 4658 * will cause a hardware interrupt when complete). 4659 */ 4660 void bge_chip_cyclic(void *arg); 4661 #pragma no_inline(bge_chip_cyclic) 4662 4663 void 4664 bge_chip_cyclic(void *arg) 4665 { 4666 bge_t *bgep; 4667 4668 bgep = arg; 4669 4670 switch (bgep->bge_chip_state) { 4671 default: 4672 return; 4673 4674 case BGE_CHIP_RUNNING: 4675 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4676 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4677 ddi_fm_service_impact(bgep->devinfo, 4678 DDI_SERVICE_UNAFFECTED); 4679 4680 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4681 bgep->link_update_timer++; 4682 4683 break; 4684 4685 case BGE_CHIP_FAULT: 4686 case BGE_CHIP_ERROR: 4687 break; 4688 } 4689 4690 bge_wake_factotum(bgep); 4691 } 4692 4693 4694 /* 4695 * ========== Ioctl subfunctions ========== 4696 */ 4697 4698 #undef BGE_DBG 4699 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4700 4701 #if BGE_DEBUGGING || BGE_DO_PPIO 4702 4703 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4704 #pragma no_inline(bge_chip_peek_cfg) 4705 4706 static void 4707 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4708 { 4709 uint64_t regval; 4710 uint64_t regno; 4711 4712 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4713 (void *)bgep, (void *)ppd)); 4714 4715 regno = ppd->pp_acc_offset; 4716 4717 switch (ppd->pp_acc_size) { 4718 case 1: 4719 regval = pci_config_get8(bgep->cfg_handle, regno); 4720 break; 4721 4722 case 2: 4723 regval = pci_config_get16(bgep->cfg_handle, regno); 4724 break; 4725 4726 case 4: 4727 regval = pci_config_get32(bgep->cfg_handle, regno); 4728 break; 4729 4730 case 8: 4731 regval = pci_config_get64(bgep->cfg_handle, regno); 4732 break; 4733 } 4734 4735 ppd->pp_acc_data = regval; 4736 } 4737 4738 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4739 #pragma no_inline(bge_chip_poke_cfg) 4740 4741 static void 4742 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4743 { 4744 uint64_t regval; 4745 uint64_t regno; 4746 4747 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4748 (void *)bgep, (void *)ppd)); 4749 4750 regno = ppd->pp_acc_offset; 4751 regval = ppd->pp_acc_data; 4752 4753 switch (ppd->pp_acc_size) { 4754 case 1: 4755 pci_config_put8(bgep->cfg_handle, regno, regval); 4756 break; 4757 4758 case 2: 4759 pci_config_put16(bgep->cfg_handle, regno, regval); 4760 break; 4761 4762 case 4: 4763 pci_config_put32(bgep->cfg_handle, regno, regval); 4764 break; 4765 4766 case 8: 4767 pci_config_put64(bgep->cfg_handle, regno, regval); 4768 break; 4769 } 4770 } 4771 4772 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4773 #pragma no_inline(bge_chip_peek_reg) 4774 4775 static void 4776 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4777 { 4778 uint64_t regval; 4779 void *regaddr; 4780 4781 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4782 (void *)bgep, (void *)ppd)); 4783 4784 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4785 4786 switch (ppd->pp_acc_size) { 4787 case 1: 4788 regval = ddi_get8(bgep->io_handle, regaddr); 4789 break; 4790 4791 case 2: 4792 regval = ddi_get16(bgep->io_handle, regaddr); 4793 break; 4794 4795 case 4: 4796 regval = ddi_get32(bgep->io_handle, regaddr); 4797 break; 4798 4799 case 8: 4800 regval = ddi_get64(bgep->io_handle, regaddr); 4801 break; 4802 } 4803 4804 ppd->pp_acc_data = regval; 4805 } 4806 4807 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4808 #pragma no_inline(bge_chip_peek_reg) 4809 4810 static void 4811 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4812 { 4813 uint64_t regval; 4814 void *regaddr; 4815 4816 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4817 (void *)bgep, (void *)ppd)); 4818 4819 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4820 regval = ppd->pp_acc_data; 4821 4822 switch (ppd->pp_acc_size) { 4823 case 1: 4824 ddi_put8(bgep->io_handle, regaddr, regval); 4825 break; 4826 4827 case 2: 4828 ddi_put16(bgep->io_handle, regaddr, regval); 4829 break; 4830 4831 case 4: 4832 ddi_put32(bgep->io_handle, regaddr, regval); 4833 break; 4834 4835 case 8: 4836 ddi_put64(bgep->io_handle, regaddr, regval); 4837 break; 4838 } 4839 BGE_PCICHK(bgep); 4840 } 4841 4842 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4843 #pragma no_inline(bge_chip_peek_nic) 4844 4845 static void 4846 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4847 { 4848 uint64_t regoff; 4849 uint64_t regval; 4850 void *regaddr; 4851 4852 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4853 (void *)bgep, (void *)ppd)); 4854 4855 regoff = ppd->pp_acc_offset; 4856 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4857 regoff &= MWBAR_GRANULE_MASK; 4858 regoff += NIC_MEM_WINDOW_OFFSET; 4859 regaddr = PIO_ADDR(bgep, regoff); 4860 4861 switch (ppd->pp_acc_size) { 4862 case 1: 4863 regval = ddi_get8(bgep->io_handle, regaddr); 4864 break; 4865 4866 case 2: 4867 regval = ddi_get16(bgep->io_handle, regaddr); 4868 break; 4869 4870 case 4: 4871 regval = ddi_get32(bgep->io_handle, regaddr); 4872 break; 4873 4874 case 8: 4875 regval = ddi_get64(bgep->io_handle, regaddr); 4876 break; 4877 } 4878 4879 ppd->pp_acc_data = regval; 4880 } 4881 4882 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4883 #pragma no_inline(bge_chip_poke_nic) 4884 4885 static void 4886 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4887 { 4888 uint64_t regoff; 4889 uint64_t regval; 4890 void *regaddr; 4891 4892 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4893 (void *)bgep, (void *)ppd)); 4894 4895 regoff = ppd->pp_acc_offset; 4896 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4897 regoff &= MWBAR_GRANULE_MASK; 4898 regoff += NIC_MEM_WINDOW_OFFSET; 4899 regaddr = PIO_ADDR(bgep, regoff); 4900 regval = ppd->pp_acc_data; 4901 4902 switch (ppd->pp_acc_size) { 4903 case 1: 4904 ddi_put8(bgep->io_handle, regaddr, regval); 4905 break; 4906 4907 case 2: 4908 ddi_put16(bgep->io_handle, regaddr, regval); 4909 break; 4910 4911 case 4: 4912 ddi_put32(bgep->io_handle, regaddr, regval); 4913 break; 4914 4915 case 8: 4916 ddi_put64(bgep->io_handle, regaddr, regval); 4917 break; 4918 } 4919 BGE_PCICHK(bgep); 4920 } 4921 4922 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4923 #pragma no_inline(bge_chip_peek_mii) 4924 4925 static void 4926 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4927 { 4928 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4929 (void *)bgep, (void *)ppd)); 4930 4931 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4932 } 4933 4934 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4935 #pragma no_inline(bge_chip_poke_mii) 4936 4937 static void 4938 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4939 { 4940 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4941 (void *)bgep, (void *)ppd)); 4942 4943 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4944 } 4945 4946 #if BGE_SEE_IO32 4947 4948 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4949 #pragma no_inline(bge_chip_peek_seeprom) 4950 4951 static void 4952 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4953 { 4954 uint32_t data; 4955 int err; 4956 4957 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4958 (void *)bgep, (void *)ppd)); 4959 4960 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4961 ppd->pp_acc_data = err ? ~0ull : data; 4962 } 4963 4964 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4965 #pragma no_inline(bge_chip_poke_seeprom) 4966 4967 static void 4968 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4969 { 4970 uint32_t data; 4971 4972 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4973 (void *)bgep, (void *)ppd)); 4974 4975 data = ppd->pp_acc_data; 4976 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4977 } 4978 #endif /* BGE_SEE_IO32 */ 4979 4980 #if BGE_FLASH_IO32 4981 4982 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4983 #pragma no_inline(bge_chip_peek_flash) 4984 4985 static void 4986 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4987 { 4988 uint32_t data; 4989 int err; 4990 4991 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4992 (void *)bgep, (void *)ppd)); 4993 4994 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4995 ppd->pp_acc_data = err ? ~0ull : data; 4996 } 4997 4998 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4999 #pragma no_inline(bge_chip_poke_flash) 5000 5001 static void 5002 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5003 { 5004 uint32_t data; 5005 5006 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5007 (void *)bgep, (void *)ppd)); 5008 5009 data = ppd->pp_acc_data; 5010 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5011 ppd->pp_acc_offset, &data); 5012 } 5013 #endif /* BGE_FLASH_IO32 */ 5014 5015 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5016 #pragma no_inline(bge_chip_peek_mem) 5017 5018 static void 5019 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5020 { 5021 uint64_t regval; 5022 void *vaddr; 5023 5024 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5025 (void *)bgep, (void *)ppd)); 5026 5027 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5028 5029 switch (ppd->pp_acc_size) { 5030 case 1: 5031 regval = *(uint8_t *)vaddr; 5032 break; 5033 5034 case 2: 5035 regval = *(uint16_t *)vaddr; 5036 break; 5037 5038 case 4: 5039 regval = *(uint32_t *)vaddr; 5040 break; 5041 5042 case 8: 5043 regval = *(uint64_t *)vaddr; 5044 break; 5045 } 5046 5047 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5048 (void *)bgep, (void *)ppd, regval, vaddr)); 5049 5050 ppd->pp_acc_data = regval; 5051 } 5052 5053 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5054 #pragma no_inline(bge_chip_poke_mem) 5055 5056 static void 5057 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5058 { 5059 uint64_t regval; 5060 void *vaddr; 5061 5062 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5063 (void *)bgep, (void *)ppd)); 5064 5065 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5066 regval = ppd->pp_acc_data; 5067 5068 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5069 (void *)bgep, (void *)ppd, regval, vaddr)); 5070 5071 switch (ppd->pp_acc_size) { 5072 case 1: 5073 *(uint8_t *)vaddr = (uint8_t)regval; 5074 break; 5075 5076 case 2: 5077 *(uint16_t *)vaddr = (uint16_t)regval; 5078 break; 5079 5080 case 4: 5081 *(uint32_t *)vaddr = (uint32_t)regval; 5082 break; 5083 5084 case 8: 5085 *(uint64_t *)vaddr = (uint64_t)regval; 5086 break; 5087 } 5088 } 5089 5090 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5091 struct iocblk *iocp); 5092 #pragma no_inline(bge_pp_ioctl) 5093 5094 static enum ioc_reply 5095 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5096 { 5097 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5098 bge_peekpoke_t *ppd; 5099 dma_area_t *areap; 5100 uint64_t sizemask; 5101 uint64_t mem_va; 5102 uint64_t maxoff; 5103 boolean_t peek; 5104 5105 switch (cmd) { 5106 default: 5107 /* NOTREACHED */ 5108 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5109 return (IOC_INVAL); 5110 5111 case BGE_PEEK: 5112 peek = B_TRUE; 5113 break; 5114 5115 case BGE_POKE: 5116 peek = B_FALSE; 5117 break; 5118 } 5119 5120 /* 5121 * Validate format of ioctl 5122 */ 5123 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5124 return (IOC_INVAL); 5125 if (mp->b_cont == NULL) 5126 return (IOC_INVAL); 5127 ppd = (void *)mp->b_cont->b_rptr; 5128 5129 /* 5130 * Validate request parameters 5131 */ 5132 switch (ppd->pp_acc_space) { 5133 default: 5134 return (IOC_INVAL); 5135 5136 case BGE_PP_SPACE_CFG: 5137 /* 5138 * Config space 5139 */ 5140 sizemask = 8|4|2|1; 5141 mem_va = 0; 5142 maxoff = PCI_CONF_HDR_SIZE; 5143 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5144 break; 5145 5146 case BGE_PP_SPACE_REG: 5147 /* 5148 * Memory-mapped I/O space 5149 */ 5150 sizemask = 8|4|2|1; 5151 mem_va = 0; 5152 maxoff = RIAAR_REGISTER_MAX; 5153 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5154 break; 5155 5156 case BGE_PP_SPACE_NIC: 5157 /* 5158 * NIC on-chip memory 5159 */ 5160 sizemask = 8|4|2|1; 5161 mem_va = 0; 5162 maxoff = MWBAR_ONCHIP_MAX; 5163 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5164 break; 5165 5166 case BGE_PP_SPACE_MII: 5167 /* 5168 * PHY's MII registers 5169 * NB: all PHY registers are two bytes, but the 5170 * addresses increment in ones (word addressing). 5171 * So we scale the address here, then undo the 5172 * transformation inside the peek/poke functions. 5173 */ 5174 ppd->pp_acc_offset *= 2; 5175 sizemask = 2; 5176 mem_va = 0; 5177 maxoff = (MII_MAXREG+1)*2; 5178 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5179 break; 5180 5181 #if BGE_SEE_IO32 5182 case BGE_PP_SPACE_SEEPROM: 5183 /* 5184 * Attached SEEPROM(s), if any. 5185 * NB: we use the high-order bits of the 'address' as 5186 * a device select to accommodate multiple SEEPROMS, 5187 * If each one is the maximum size (64kbytes), this 5188 * makes them appear contiguous. Otherwise, there may 5189 * be holes in the mapping. ENxS doesn't have any 5190 * SEEPROMs anyway ... 5191 */ 5192 sizemask = 4; 5193 mem_va = 0; 5194 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5195 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5196 break; 5197 #endif /* BGE_SEE_IO32 */ 5198 5199 #if BGE_FLASH_IO32 5200 case BGE_PP_SPACE_FLASH: 5201 /* 5202 * Attached Flash device (if any); a maximum of one device 5203 * is currently supported. But it can be up to 1MB (unlike 5204 * the 64k limit on SEEPROMs) so why would you need more ;-) 5205 */ 5206 sizemask = 4; 5207 mem_va = 0; 5208 maxoff = NVM_FLASH_ADDR_MASK; 5209 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5210 break; 5211 #endif /* BGE_FLASH_IO32 */ 5212 5213 case BGE_PP_SPACE_BGE: 5214 /* 5215 * BGE data structure! 5216 */ 5217 sizemask = 8|4|2|1; 5218 mem_va = (uintptr_t)bgep; 5219 maxoff = sizeof (*bgep); 5220 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5221 break; 5222 5223 case BGE_PP_SPACE_STATUS: 5224 case BGE_PP_SPACE_STATISTICS: 5225 case BGE_PP_SPACE_TXDESC: 5226 case BGE_PP_SPACE_TXBUFF: 5227 case BGE_PP_SPACE_RXDESC: 5228 case BGE_PP_SPACE_RXBUFF: 5229 /* 5230 * Various DMA_AREAs 5231 */ 5232 switch (ppd->pp_acc_space) { 5233 case BGE_PP_SPACE_TXDESC: 5234 areap = &bgep->tx_desc; 5235 break; 5236 case BGE_PP_SPACE_TXBUFF: 5237 areap = &bgep->tx_buff[0]; 5238 break; 5239 case BGE_PP_SPACE_RXDESC: 5240 areap = &bgep->rx_desc[0]; 5241 break; 5242 case BGE_PP_SPACE_RXBUFF: 5243 areap = &bgep->rx_buff[0]; 5244 break; 5245 case BGE_PP_SPACE_STATUS: 5246 areap = &bgep->status_block; 5247 break; 5248 case BGE_PP_SPACE_STATISTICS: 5249 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5250 areap = &bgep->statistics; 5251 break; 5252 } 5253 5254 sizemask = 8|4|2|1; 5255 mem_va = (uintptr_t)areap->mem_va; 5256 maxoff = areap->alength; 5257 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5258 break; 5259 } 5260 5261 switch (ppd->pp_acc_size) { 5262 default: 5263 return (IOC_INVAL); 5264 5265 case 8: 5266 case 4: 5267 case 2: 5268 case 1: 5269 if ((ppd->pp_acc_size & sizemask) == 0) 5270 return (IOC_INVAL); 5271 break; 5272 } 5273 5274 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5275 return (IOC_INVAL); 5276 5277 if (ppd->pp_acc_offset >= maxoff) 5278 return (IOC_INVAL); 5279 5280 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5281 return (IOC_INVAL); 5282 5283 /* 5284 * All OK - go do it! 5285 */ 5286 ppd->pp_acc_offset += mem_va; 5287 (*ppfn)(bgep, ppd); 5288 return (peek ? IOC_REPLY : IOC_ACK); 5289 } 5290 5291 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5292 struct iocblk *iocp); 5293 #pragma no_inline(bge_diag_ioctl) 5294 5295 static enum ioc_reply 5296 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5297 { 5298 ASSERT(mutex_owned(bgep->genlock)); 5299 5300 switch (cmd) { 5301 default: 5302 /* NOTREACHED */ 5303 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5304 return (IOC_INVAL); 5305 5306 case BGE_DIAG: 5307 /* 5308 * Currently a no-op 5309 */ 5310 return (IOC_ACK); 5311 5312 case BGE_PEEK: 5313 case BGE_POKE: 5314 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5315 5316 case BGE_PHY_RESET: 5317 return (IOC_RESTART_ACK); 5318 5319 case BGE_SOFT_RESET: 5320 case BGE_HARD_RESET: 5321 /* 5322 * Reset and reinitialise the 570x hardware 5323 */ 5324 bgep->bge_chip_state = BGE_CHIP_FAULT; 5325 ddi_trigger_softintr(bgep->factotum_id); 5326 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5327 return (IOC_ACK); 5328 } 5329 5330 /* NOTREACHED */ 5331 } 5332 5333 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5334 5335 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5336 struct iocblk *iocp); 5337 #pragma no_inline(bge_mii_ioctl) 5338 5339 static enum ioc_reply 5340 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5341 { 5342 struct bge_mii_rw *miirwp; 5343 5344 /* 5345 * Validate format of ioctl 5346 */ 5347 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5348 return (IOC_INVAL); 5349 if (mp->b_cont == NULL) 5350 return (IOC_INVAL); 5351 miirwp = (void *)mp->b_cont->b_rptr; 5352 5353 /* 5354 * Validate request parameters ... 5355 */ 5356 if (miirwp->mii_reg > MII_MAXREG) 5357 return (IOC_INVAL); 5358 5359 switch (cmd) { 5360 default: 5361 /* NOTREACHED */ 5362 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5363 return (IOC_INVAL); 5364 5365 case BGE_MII_READ: 5366 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5367 return (IOC_REPLY); 5368 5369 case BGE_MII_WRITE: 5370 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5371 return (IOC_ACK); 5372 } 5373 5374 /* NOTREACHED */ 5375 } 5376 5377 #if BGE_SEE_IO32 5378 5379 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5380 struct iocblk *iocp); 5381 #pragma no_inline(bge_see_ioctl) 5382 5383 static enum ioc_reply 5384 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5385 { 5386 struct bge_see_rw *seerwp; 5387 5388 /* 5389 * Validate format of ioctl 5390 */ 5391 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5392 return (IOC_INVAL); 5393 if (mp->b_cont == NULL) 5394 return (IOC_INVAL); 5395 seerwp = (void *)mp->b_cont->b_rptr; 5396 5397 /* 5398 * Validate request parameters ... 5399 */ 5400 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5401 return (IOC_INVAL); 5402 5403 switch (cmd) { 5404 default: 5405 /* NOTREACHED */ 5406 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5407 return (IOC_INVAL); 5408 5409 case BGE_SEE_READ: 5410 case BGE_SEE_WRITE: 5411 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5412 seerwp->see_addr, &seerwp->see_data); 5413 return (IOC_REPLY); 5414 } 5415 5416 /* NOTREACHED */ 5417 } 5418 5419 #endif /* BGE_SEE_IO32 */ 5420 5421 #if BGE_FLASH_IO32 5422 5423 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5424 struct iocblk *iocp); 5425 #pragma no_inline(bge_flash_ioctl) 5426 5427 static enum ioc_reply 5428 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5429 { 5430 struct bge_flash_rw *flashrwp; 5431 5432 /* 5433 * Validate format of ioctl 5434 */ 5435 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5436 return (IOC_INVAL); 5437 if (mp->b_cont == NULL) 5438 return (IOC_INVAL); 5439 flashrwp = (void *)mp->b_cont->b_rptr; 5440 5441 /* 5442 * Validate request parameters ... 5443 */ 5444 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5445 return (IOC_INVAL); 5446 5447 switch (cmd) { 5448 default: 5449 /* NOTREACHED */ 5450 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5451 return (IOC_INVAL); 5452 5453 case BGE_FLASH_READ: 5454 case BGE_FLASH_WRITE: 5455 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5456 flashrwp->flash_addr, &flashrwp->flash_data); 5457 return (IOC_REPLY); 5458 } 5459 5460 /* NOTREACHED */ 5461 } 5462 5463 #endif /* BGE_FLASH_IO32 */ 5464 5465 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5466 struct iocblk *iocp); 5467 #pragma no_inline(bge_chip_ioctl) 5468 5469 enum ioc_reply 5470 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5471 { 5472 int cmd; 5473 5474 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5475 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5476 5477 ASSERT(mutex_owned(bgep->genlock)); 5478 5479 cmd = iocp->ioc_cmd; 5480 switch (cmd) { 5481 default: 5482 /* NOTREACHED */ 5483 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5484 return (IOC_INVAL); 5485 5486 case BGE_DIAG: 5487 case BGE_PEEK: 5488 case BGE_POKE: 5489 case BGE_PHY_RESET: 5490 case BGE_SOFT_RESET: 5491 case BGE_HARD_RESET: 5492 #if BGE_DEBUGGING || BGE_DO_PPIO 5493 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5494 #else 5495 return (IOC_INVAL); 5496 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5497 5498 case BGE_MII_READ: 5499 case BGE_MII_WRITE: 5500 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5501 5502 #if BGE_SEE_IO32 5503 case BGE_SEE_READ: 5504 case BGE_SEE_WRITE: 5505 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5506 #endif /* BGE_SEE_IO32 */ 5507 5508 #if BGE_FLASH_IO32 5509 case BGE_FLASH_READ: 5510 case BGE_FLASH_WRITE: 5511 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5512 #endif /* BGE_FLASH_IO32 */ 5513 } 5514 5515 /* NOTREACHED */ 5516 } 5517 5518 void 5519 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5520 { 5521 bge_t *bgep = arg; 5522 5523 mutex_enter(bgep->genlock); 5524 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5525 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5526 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5527 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5528 mutex_exit(bgep->genlock); 5529 } 5530 5531 #ifdef BGE_IPMI_ASF 5532 5533 uint32_t 5534 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5535 { 5536 uint32_t data; 5537 5538 #ifndef __sparc 5539 if (!bgep->asf_wordswapped) { 5540 /* a workaround word swap error */ 5541 if (addr & 4) 5542 addr = addr - 4; 5543 else 5544 addr = addr + 4; 5545 } 5546 #endif 5547 5548 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5549 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5550 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5551 5552 data = LE_32(data); 5553 return (data); 5554 } 5555 5556 void 5557 bge_asf_update_status(bge_t *bgep) 5558 { 5559 uint32_t event; 5560 5561 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5562 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5563 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5564 5565 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5566 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5567 } 5568 5569 5570 /* 5571 * The driver is supposed to notify ASF that the OS is still running 5572 * every three seconds, otherwise the management server may attempt 5573 * to reboot the machine. If it hasn't actually failed, this is 5574 * not a desirable result. However, this isn't running as a real-time 5575 * thread, and even if it were, it might not be able to generate the 5576 * heartbeat in a timely manner due to system load. As it isn't a 5577 * significant strain on the machine, we will set the interval to half 5578 * of the required value. 5579 */ 5580 void 5581 bge_asf_heartbeat(void *arg) 5582 { 5583 bge_t *bgep = (bge_t *)arg; 5584 5585 mutex_enter(bgep->genlock); 5586 bge_asf_update_status((bge_t *)bgep); 5587 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5588 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5589 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5590 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5591 mutex_exit(bgep->genlock); 5592 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5593 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5594 } 5595 5596 5597 void 5598 bge_asf_stop_timer(bge_t *bgep) 5599 { 5600 timeout_id_t tmp_id = 0; 5601 5602 while ((bgep->asf_timeout_id != 0) && 5603 (tmp_id != bgep->asf_timeout_id)) { 5604 tmp_id = bgep->asf_timeout_id; 5605 (void) untimeout(tmp_id); 5606 } 5607 bgep->asf_timeout_id = 0; 5608 } 5609 5610 5611 5612 /* 5613 * This function should be placed at the earliest position of bge_attach(). 5614 */ 5615 void 5616 bge_asf_get_config(bge_t *bgep) 5617 { 5618 uint32_t nicsig; 5619 uint32_t niccfg; 5620 5621 bgep->asf_enabled = B_FALSE; 5622 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5623 if (nicsig == BGE_NIC_DATA_SIG) { 5624 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5625 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5626 /* 5627 * Here, we don't consider BAXTER, because BGE haven't 5628 * supported BAXTER (that is 5752). Also, as I know, 5629 * BAXTER doesn't support ASF feature. 5630 */ 5631 bgep->asf_enabled = B_TRUE; 5632 else 5633 bgep->asf_enabled = B_FALSE; 5634 } else 5635 bgep->asf_enabled = B_FALSE; 5636 } 5637 5638 5639 void 5640 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5641 { 5642 uint32_t tries; 5643 uint32_t event; 5644 5645 ASSERT(bgep->asf_enabled); 5646 5647 /* Issues "pause firmware" command and wait for ACK */ 5648 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5649 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5650 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5651 5652 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5653 tries = 0; 5654 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5655 drv_usecwait(1); 5656 tries ++; 5657 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5658 } 5659 5660 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5661 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5662 5663 if (bgep->asf_newhandshake) { 5664 switch (mode) { 5665 case BGE_INIT_RESET: 5666 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5667 BGE_DRV_STATE_START); 5668 break; 5669 case BGE_SHUTDOWN_RESET: 5670 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5671 BGE_DRV_STATE_UNLOAD); 5672 break; 5673 case BGE_SUSPEND_RESET: 5674 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5675 BGE_DRV_STATE_SUSPEND); 5676 break; 5677 default: 5678 break; 5679 } 5680 } 5681 } 5682 5683 5684 void 5685 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5686 { 5687 switch (mode) { 5688 case BGE_INIT_RESET: 5689 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5690 BGE_DRV_STATE_START); 5691 break; 5692 case BGE_SHUTDOWN_RESET: 5693 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5694 BGE_DRV_STATE_UNLOAD); 5695 break; 5696 case BGE_SUSPEND_RESET: 5697 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5698 BGE_DRV_STATE_SUSPEND); 5699 break; 5700 default: 5701 break; 5702 } 5703 } 5704 5705 5706 void 5707 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5708 { 5709 switch (mode) { 5710 case BGE_INIT_RESET: 5711 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5712 BGE_DRV_STATE_START_DONE); 5713 break; 5714 case BGE_SHUTDOWN_RESET: 5715 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5716 BGE_DRV_STATE_UNLOAD_DONE); 5717 break; 5718 default: 5719 break; 5720 } 5721 } 5722 5723 #endif /* BGE_IPMI_ASF */ 5724