1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 boolean_t bge_jumbo_enable = B_TRUE; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 245 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 246 247 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 248 (void *)bgep, regno, val)); 249 250 val = LE_32(val); 251 252 return (val); 253 } 254 255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 256 #pragma inline(bge_ind_put32) 257 258 void 259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 260 { 261 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 262 (void *)bgep, regno, val)); 263 264 val = LE_32(val); 265 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 267 } 268 269 #endif /* BGE_IND_IO32 */ 270 271 #if BGE_DEBUGGING 272 273 static void bge_pci_check(bge_t *bgep); 274 #pragma no_inline(bge_pci_check) 275 276 static void 277 bge_pci_check(bge_t *bgep) 278 { 279 uint16_t pcistatus; 280 281 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 282 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 283 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 284 (void *)bgep, pcistatus)); 285 } 286 287 #endif /* BGE_DEBUGGING */ 288 289 /* 290 * Perform first-stage chip (re-)initialisation, using only config-space 291 * accesses: 292 * 293 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 294 * returning the data in the structure pointed to by <idp>. 295 * + Configure the target-mode endianness (swap) options. 296 * + Disable interrupts and enable Memory Space accesses. 297 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 298 * 299 * This sequence is adapted from Broadcom document 570X-PG102-R, 300 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 301 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 302 * 303 * This function MUST be called before any non-config-space accesses 304 * are made; on this first call <enable_dma> is B_FALSE, and it 305 * effectively performs steps 3-1(!) of the initialisation sequence 306 * (the rest are not required but should be harmless). 307 * 308 * It MUST also be called after a chip reset, as this disables 309 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 310 * it is effectively performing steps 6-8. 311 */ 312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 313 #pragma no_inline(bge_chip_cfg_init) 314 315 void 316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 317 { 318 ddi_acc_handle_t handle; 319 uint16_t command; 320 uint32_t mhcr; 321 uint16_t value16; 322 int i; 323 324 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 325 (void *)bgep, (void *)cidp, enable_dma)); 326 327 /* 328 * Step 3: save PCI cache line size and subsystem vendor ID 329 * 330 * Read all the config-space registers that characterise the 331 * chip, specifically vendor/device/revision/subsystem vendor 332 * and subsystem device id. We expect (but don't check) that 333 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 334 * 335 * Also save all bus-transaction related registers (cache-line 336 * size, bus-grant/latency parameters, etc). Some of these are 337 * cleared by reset, so we'll have to restore them later. This 338 * comes from the Broadcom document 570X-PG102-R ... 339 * 340 * Note: Broadcom document 570X-PG102-R seems to be in error 341 * here w.r.t. the offsets of the Subsystem Vendor ID and 342 * Subsystem (Device) ID registers, which are the opposite way 343 * round according to the PCI standard. For good measure, we 344 * save/restore both anyway. 345 */ 346 handle = bgep->cfg_handle; 347 348 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 349 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 350 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 351 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 352 353 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 354 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 355 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 356 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 357 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 358 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 359 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 360 361 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 362 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 363 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 364 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 365 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 366 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 367 cidp->vendor, cidp->device, cidp->revision)); 368 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 369 cidp->subven, cidp->subdev, cidp->asic_rev)); 370 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 371 cidp->clsize, cidp->latency, cidp->command)); 372 373 /* 374 * Step 2 (also step 6): disable and clear interrupts. 375 * Steps 11-13: configure PIO endianness options, and enable 376 * indirect register access. We'll also select any other 377 * options controlled by the MHCR (e.g. tagged status, mask 378 * interrupt mode) at this stage ... 379 * 380 * Note: internally, the chip is 64-bit and BIG-endian, but 381 * since it talks to the host over a (LITTLE-endian) PCI bus, 382 * it normally swaps bytes around at the PCI interface. 383 * However, the PCI host bridge on SPARC systems normally 384 * swaps the byte lanes around too, since SPARCs are also 385 * BIG-endian. So it turns out that on SPARC, the right 386 * option is to tell the chip to swap (and the host bridge 387 * will swap back again), whereas on x86 we ask the chip 388 * NOT to swap, so the natural little-endianness of the 389 * PCI bus is assumed. Then the only thing that doesn't 390 * automatically work right is access to an 8-byte register 391 * by a little-endian host; but we don't want to set the 392 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 393 * accesses don't go where expected ;-( So we live with 394 * that, and perform word-swaps in software in the few cases 395 * where a chip register is defined as an 8-byte value -- 396 * see the code below for details ... 397 * 398 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 399 * very clear in the register description in the PRM, but 400 * Broadcom document 570X-PG104-R page 248 explains a little 401 * more (under "Broadcom Mask Mode"). The bit changes the way 402 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 403 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 404 * way as the 5700 did, which isn't very convenient. Setting 405 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 406 * bit do just what its name says -- MASK the PCI #INTA output 407 * (i.e. deassert the signal at the pin) leaving all internal 408 * state unchanged. This is much more convenient for our 409 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 410 * 411 * Note: the inconvenient semantics of the interrupt mailbox 412 * (nonzero disables and acknowledges/clears the interrupt, 413 * zero enables AND CLEARS it) would make race conditions 414 * likely in the interrupt handler: 415 * 416 * (1) acknowledge & disable interrupts 417 * (2) while (more to do) 418 * process packets 419 * (3) enable interrupts -- also clears pending 420 * 421 * If the chip received more packets and internally generated 422 * an interrupt between the check at (2) and the mbox write 423 * at (3), this interrupt would be lost :-( 424 * 425 * The best way to avoid this is to use TAGGED STATUS mode, 426 * where the chip includes a unique tag in each status block 427 * update, and the host, when re-enabling interrupts, passes 428 * the last tag it saw back to the chip; then the chip can 429 * see whether the host is truly up to date, and regenerate 430 * its interrupt if not. 431 */ 432 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 433 MHCR_ENABLE_TAGGED_STATUS_MODE | 434 MHCR_MASK_INTERRUPT_MODE | 435 MHCR_CLEAR_INTERRUPT_INTA; 436 437 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 438 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 439 440 #ifdef _BIG_ENDIAN 441 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 442 #endif /* _BIG_ENDIAN */ 443 444 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 445 446 #ifdef BGE_IPMI_ASF 447 bgep->asf_wordswapped = B_FALSE; 448 #endif 449 /* 450 * Step 1 (also step 7): Enable PCI Memory Space accesses 451 * Disable Memory Write/Invalidate 452 * Enable or disable Bus Mastering 453 * 454 * Note that all other bits are taken from the original value saved 455 * the first time through here, rather than from the current register 456 * value, 'cos that will have been cleared by a soft RESET since. 457 * In this way we preserve the OBP/nexus-parent's preferred settings 458 * of the parity-error and system-error enable bits across multiple 459 * chip RESETs. 460 */ 461 command = bgep->chipid.command | PCI_COMM_MAE; 462 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 463 if (enable_dma) 464 command |= PCI_COMM_ME; 465 /* 466 * on BCM5714 revision A0, false parity error gets generated 467 * due to a logic bug. Provide a workaround by disabling parity 468 * error. 469 */ 470 if (((cidp->device == DEVICE_ID_5714C) || 471 (cidp->device == DEVICE_ID_5714S)) && 472 (cidp->revision == REVISION_ID_5714_A0)) { 473 command &= ~PCI_COMM_PARITY_DETECT; 474 } 475 pci_config_put16(handle, PCI_CONF_COMM, command); 476 477 /* 478 * On some PCI-E device, there were instances when 479 * the device was still link training. 480 */ 481 if (bgep->chipid.pci_type == BGE_PCI_E) { 482 i = 0; 483 value16 = pci_config_get16(handle, PCI_CONF_COMM); 484 while ((value16 != command) && (i < 100)) { 485 drv_usecwait(200); 486 value16 = pci_config_get16(handle, PCI_CONF_COMM); 487 ++i; 488 } 489 } 490 491 /* 492 * Clear any remaining error status bits 493 */ 494 pci_config_put16(handle, PCI_CONF_STAT, ~0); 495 496 /* 497 * Do following if and only if the device is NOT BCM5714C OR 498 * BCM5715C 499 */ 500 if (!((cidp->device == DEVICE_ID_5714C) || 501 (cidp->device == DEVICE_ID_5715C))) { 502 /* 503 * Make sure these indirect-access registers are sane 504 * rather than random after power-up or reset 505 */ 506 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 507 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 508 } 509 /* 510 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 511 */ 512 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 513 514 if (cidp->pci_type == BGE_PCI_E) 515 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 516 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 517 } 518 519 #ifdef __amd64 520 /* 521 * Distinguish CPU types 522 * 523 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 524 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 525 * for PCI-Express based network interface card. This is the work-around 526 * for those nics. 527 */ 528 static boolean_t bge_get_em64t_type(void); 529 #pragma inline(bge_get_em64t_type) 530 531 static boolean_t 532 bge_get_em64t_type(void) 533 { 534 535 return (x86_vendor == X86_VENDOR_Intel); 536 } 537 #endif 538 539 /* 540 * Operating register get/set access routines 541 */ 542 543 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 544 #pragma inline(bge_reg_get32) 545 546 uint32_t 547 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 548 { 549 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 550 (void *)bgep, regno)); 551 552 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 553 } 554 555 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 556 #pragma inline(bge_reg_put32) 557 558 void 559 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 560 { 561 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 562 (void *)bgep, regno, data)); 563 564 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 565 BGE_PCICHK(bgep); 566 } 567 568 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 569 #pragma inline(bge_reg_set32) 570 571 void 572 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 573 { 574 uint32_t regval; 575 576 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 577 (void *)bgep, regno, bits)); 578 579 regval = bge_reg_get32(bgep, regno); 580 regval |= bits; 581 bge_reg_put32(bgep, regno, regval); 582 } 583 584 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 585 #pragma inline(bge_reg_clr32) 586 587 void 588 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 589 { 590 uint32_t regval; 591 592 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 593 (void *)bgep, regno, bits)); 594 595 regval = bge_reg_get32(bgep, regno); 596 regval &= ~bits; 597 bge_reg_put32(bgep, regno, regval); 598 } 599 600 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 601 #pragma inline(bge_reg_get64) 602 603 static uint64_t 604 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 605 { 606 uint64_t regval; 607 608 #ifdef __amd64 609 if (bge_get_em64t_type()) { 610 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 611 regval <<= 32; 612 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 613 } else { 614 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 615 } 616 #else 617 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 #endif 619 620 #ifdef _LITTLE_ENDIAN 621 regval = (regval >> 32) | (regval << 32); 622 #endif /* _LITTLE_ENDIAN */ 623 624 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 625 (void *)bgep, regno, regval)); 626 627 return (regval); 628 } 629 630 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 631 #pragma inline(bge_reg_put64) 632 633 static void 634 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 635 { 636 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 637 (void *)bgep, regno, data)); 638 639 #ifdef _LITTLE_ENDIAN 640 data = ((data >> 32) | (data << 32)); 641 #endif /* _LITTLE_ENDIAN */ 642 643 #ifdef __amd64 644 if (bge_get_em64t_type()) { 645 ddi_put32(bgep->io_handle, 646 PIO_ADDR(bgep, regno), (uint32_t)data); 647 BGE_PCICHK(bgep); 648 ddi_put32(bgep->io_handle, 649 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 650 651 } else { 652 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 653 } 654 #else 655 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 656 #endif 657 658 BGE_PCICHK(bgep); 659 } 660 661 /* 662 * The DDI doesn't provide get/put functions for 128 bit data 663 * so we put RCBs out as two 64-bit chunks instead. 664 */ 665 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 666 #pragma inline(bge_reg_putrcb) 667 668 static void 669 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 670 { 671 uint64_t *p; 672 673 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 674 (void *)bgep, addr, rcbp->host_ring_addr, 675 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 676 677 ASSERT((addr % sizeof (*rcbp)) == 0); 678 679 p = (void *)rcbp; 680 bge_reg_put64(bgep, addr, *p++); 681 bge_reg_put64(bgep, addr+8, *p); 682 } 683 684 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 685 #pragma inline(bge_mbx_put) 686 687 void 688 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 689 { 690 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 691 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 692 693 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 694 (void *)bgep, regno, data)); 695 696 /* 697 * Mailbox registers are nominally 64 bits on the 5701, but 698 * the MSW isn't used. On the 5703, they're only 32 bits 699 * anyway. So here we just write the lower(!) 32 bits - 700 * remembering that the chip is big-endian, even though the 701 * PCI bus is little-endian ... 702 */ 703 #ifdef _BIG_ENDIAN 704 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 705 #else 706 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 707 #endif /* _BIG_ENDIAN */ 708 BGE_PCICHK(bgep); 709 } 710 711 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 712 #pragma inline(bge_mbx_get) 713 714 uint32_t 715 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 716 { 717 uint32_t val32; 718 719 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 720 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 721 722 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 723 (void *)bgep, regno)); 724 725 #ifdef _BIG_ENDIAN 726 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 727 #else 728 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 729 #endif /* _BIG_ENDIAN */ 730 BGE_PCICHK(bgep); 731 732 return (val32); 733 } 734 735 736 #if BGE_DEBUGGING 737 738 void bge_led_mark(bge_t *bgep); 739 #pragma no_inline(bge_led_mark) 740 741 void 742 bge_led_mark(bge_t *bgep) 743 { 744 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 745 LED_CONTROL_1000MBPS_LED | 746 LED_CONTROL_100MBPS_LED | 747 LED_CONTROL_10MBPS_LED; 748 749 /* 750 * Blink all three LINK LEDs on simultaneously, then all off, 751 * then restore to automatic hardware control. This is used 752 * in laboratory testing to trigger a logic analyser or scope. 753 */ 754 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 755 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 756 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 757 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 758 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 759 } 760 761 #endif /* BGE_DEBUGGING */ 762 763 /* 764 * NIC on-chip memory access routines 765 * 766 * Only 32K of NIC memory is visible at a time, controlled by the 767 * Memory Window Base Address Register (in PCI config space). Once 768 * this is set, the 32K region of NIC-local memory that it refers 769 * to can be directly addressed in the upper 32K of the 64K of PCI 770 * memory space used for the device. 771 */ 772 773 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 774 #pragma inline(bge_nic_setwin) 775 776 static void 777 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 778 { 779 chip_id_t *cidp; 780 781 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 782 (void *)bgep, base)); 783 784 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 785 786 /* 787 * Don't do repeated zero data writes, 788 * if the device is BCM5714C/15C. 789 */ 790 cidp = &bgep->chipid; 791 if ((cidp->device == DEVICE_ID_5714C) || 792 (cidp->device == DEVICE_ID_5715C)) { 793 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 794 return; 795 /* Adjust lastWriteZeroData */ 796 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 797 B_TRUE : B_FALSE); 798 } 799 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 800 } 801 802 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 803 #pragma inline(bge_nic_get32) 804 805 static uint32_t 806 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 807 { 808 uint32_t data; 809 810 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 811 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 812 /* workaround for word swap error */ 813 if (addr & 4) 814 addr = addr - 4; 815 else 816 addr = addr + 4; 817 } 818 #endif 819 820 #ifdef __sparc 821 data = bge_nic_read32(bgep, addr); 822 #else 823 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 824 addr &= MWBAR_GRANULE_MASK; 825 addr += NIC_MEM_WINDOW_OFFSET; 826 827 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 828 #endif 829 830 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 831 (void *)bgep, addr, data)); 832 833 return (data); 834 } 835 836 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 837 #pragma inline(bge_nic_put32) 838 839 void 840 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 841 { 842 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 843 (void *)bgep, addr, data)); 844 845 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 846 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 847 /* workaround for word swap error */ 848 if (addr & 4) 849 addr = addr - 4; 850 else 851 addr = addr + 4; 852 } 853 #endif 854 855 #ifdef __sparc 856 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 857 data = LE_32(data); 858 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 859 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 860 #else 861 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 862 addr &= MWBAR_GRANULE_MASK; 863 addr += NIC_MEM_WINDOW_OFFSET; 864 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 865 BGE_PCICHK(bgep); 866 #endif 867 } 868 869 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 870 #pragma inline(bge_nic_get64) 871 872 static uint64_t 873 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 874 { 875 uint64_t data; 876 877 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 878 addr &= MWBAR_GRANULE_MASK; 879 addr += NIC_MEM_WINDOW_OFFSET; 880 881 #ifdef __amd64 882 if (bge_get_em64t_type()) { 883 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 884 data <<= 32; 885 data |= ddi_get32(bgep->io_handle, 886 PIO_ADDR(bgep, addr + 4)); 887 } else { 888 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 889 } 890 #else 891 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 892 #endif 893 894 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 895 (void *)bgep, addr, data)); 896 897 return (data); 898 } 899 900 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 901 #pragma inline(bge_nic_put64) 902 903 static void 904 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 905 { 906 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 907 (void *)bgep, addr, data)); 908 909 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 910 addr &= MWBAR_GRANULE_MASK; 911 addr += NIC_MEM_WINDOW_OFFSET; 912 913 #ifdef __amd64 914 if (bge_get_em64t_type()) { 915 ddi_put32(bgep->io_handle, 916 PIO_ADDR(bgep, addr), (uint32_t)data); 917 BGE_PCICHK(bgep); 918 ddi_put32(bgep->io_handle, 919 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 920 } else { 921 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 922 } 923 #else 924 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 925 #endif 926 927 BGE_PCICHK(bgep); 928 } 929 930 /* 931 * The DDI doesn't provide get/put functions for 128 bit data 932 * so we put RCBs out as two 64-bit chunks instead. 933 */ 934 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 935 #pragma inline(bge_nic_putrcb) 936 937 static void 938 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 939 { 940 uint64_t *p; 941 942 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 943 (void *)bgep, addr, rcbp->host_ring_addr, 944 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 945 946 ASSERT((addr % sizeof (*rcbp)) == 0); 947 948 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 949 addr &= MWBAR_GRANULE_MASK; 950 addr += NIC_MEM_WINDOW_OFFSET; 951 952 p = (void *)rcbp; 953 #ifdef __amd64 954 if (bge_get_em64t_type()) { 955 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 956 (uint32_t)(*p)); 957 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 958 (uint32_t)(*p >> 32)); 959 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 960 (uint32_t)(*(p + 1))); 961 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 962 (uint32_t)(*p >> 32)); 963 964 } else { 965 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 966 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 967 } 968 #else 969 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 970 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 971 #endif 972 973 BGE_PCICHK(bgep); 974 } 975 976 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 977 #pragma inline(bge_nic_zero) 978 979 static void 980 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 981 { 982 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 983 (void *)bgep, addr, nbytes)); 984 985 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 986 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 987 988 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 989 addr &= MWBAR_GRANULE_MASK; 990 addr += NIC_MEM_WINDOW_OFFSET; 991 992 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 993 nbytes, 1, DDI_DATA_SZ08_ACC); 994 BGE_PCICHK(bgep); 995 } 996 997 /* 998 * MII (PHY) register get/set access routines 999 * 1000 * These use the chip's MII auto-access method, controlled by the 1001 * MII Communication register at 0x044c, so the CPU doesn't have 1002 * to fiddle with the individual bits. 1003 */ 1004 1005 #undef BGE_DBG 1006 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1007 1008 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1009 uint16_t data, uint32_t cmd); 1010 #pragma no_inline(bge_mii_access) 1011 1012 static uint16_t 1013 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1014 { 1015 uint32_t timeout; 1016 uint32_t regval1; 1017 uint32_t regval2; 1018 1019 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1020 (void *)bgep, regno, data, cmd)); 1021 1022 ASSERT(mutex_owned(bgep->genlock)); 1023 1024 /* 1025 * Assemble the command ... 1026 */ 1027 cmd |= data << MI_COMMS_DATA_SHIFT; 1028 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1029 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1030 cmd |= MI_COMMS_START; 1031 1032 /* 1033 * Wait for any command already in progress ... 1034 * 1035 * Note: this *shouldn't* ever find that there is a command 1036 * in progress, because we already hold the <genlock> mutex. 1037 * Nonetheless, we have sometimes seen the MI_COMMS_START 1038 * bit set here -- it seems that the chip can initiate MII 1039 * accesses internally, even with polling OFF. 1040 */ 1041 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1042 for (timeout = 100; ; ) { 1043 if ((regval2 & MI_COMMS_START) == 0) { 1044 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1045 break; 1046 } 1047 if (--timeout == 0) 1048 break; 1049 drv_usecwait(10); 1050 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1051 } 1052 1053 if (timeout == 0) 1054 return ((uint16_t)~0u); 1055 1056 if (timeout != 100) 1057 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1058 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1059 cmd, 10*(100-timeout), regval1, regval2)); 1060 1061 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1062 for (timeout = 1000; ; ) { 1063 if ((regval1 & MI_COMMS_START) == 0) 1064 break; 1065 if (--timeout == 0) 1066 break; 1067 drv_usecwait(10); 1068 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1069 } 1070 1071 /* 1072 * Drop out early if the READ FAILED bit is set -- this chip 1073 * could be a 5703/4S, with a SerDes instead of a PHY! 1074 */ 1075 if (regval2 & MI_COMMS_READ_FAILED) 1076 return ((uint16_t)~0u); 1077 1078 if (timeout == 0) 1079 return ((uint16_t)~0u); 1080 1081 /* 1082 * The PRM says to wait 5us after seeing the START bit clear 1083 * and then re-read the register to get the final value of the 1084 * data field, in order to avoid a race condition where the 1085 * START bit is clear but the data field isn't yet valid. 1086 * 1087 * Note: we don't actually seem to be encounter this race; 1088 * except when the START bit is seen set again (see below), 1089 * the data field doesn't change during this 5us interval. 1090 */ 1091 drv_usecwait(5); 1092 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1093 1094 /* 1095 * Unfortunately, when following the PRMs instructions above, 1096 * we have occasionally seen the START bit set again(!) in the 1097 * value read after the 5us delay. This seems to be due to the 1098 * chip autonomously starting another MII access internally. 1099 * In such cases, the command/data/etc fields relate to the 1100 * internal command, rather than the one that we thought had 1101 * just finished. So in this case, we fall back to returning 1102 * the data from the original read that showed START clear. 1103 */ 1104 if (regval2 & MI_COMMS_START) { 1105 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1106 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1107 cmd, regval1, regval2)); 1108 regval2 = regval1; 1109 } 1110 1111 if (regval2 & MI_COMMS_START) 1112 return ((uint16_t)~0u); 1113 1114 if (regval2 & MI_COMMS_READ_FAILED) 1115 return ((uint16_t)~0u); 1116 1117 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1118 } 1119 1120 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1121 #pragma no_inline(bge_mii_get16) 1122 1123 uint16_t 1124 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1125 { 1126 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1127 (void *)bgep, regno)); 1128 1129 ASSERT(mutex_owned(bgep->genlock)); 1130 1131 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1132 (regno == MII_1000BASE_T_CONTROL))) 1133 return (0); 1134 1135 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1136 } 1137 1138 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1139 #pragma no_inline(bge_mii_put16) 1140 1141 void 1142 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1143 { 1144 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1145 (void *)bgep, regno, data)); 1146 1147 ASSERT(mutex_owned(bgep->genlock)); 1148 1149 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1150 (regno == MII_1000BASE_T_CONTROL))) 1151 return; 1152 1153 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1154 } 1155 1156 #undef BGE_DBG 1157 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1158 1159 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1160 1161 /* 1162 * Basic SEEPROM get/set access routine 1163 * 1164 * This uses the chip's SEEPROM auto-access method, controlled by the 1165 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1166 * doesn't have to fiddle with the individual bits. 1167 * 1168 * The caller should hold <genlock> and *also* have already acquired 1169 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1170 * 1171 * Return value: 1172 * 0 on success, 1173 * ENODATA on access timeout (maybe retryable: device may just be busy) 1174 * EPROTO on other h/w or s/w errors. 1175 * 1176 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1177 * from a (successful) SEEPROM_ACCESS_READ. 1178 */ 1179 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1180 uint32_t *dp); 1181 #pragma no_inline(bge_seeprom_access) 1182 1183 static int 1184 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1185 { 1186 uint32_t tries; 1187 uint32_t regval; 1188 1189 ASSERT(mutex_owned(bgep->genlock)); 1190 1191 /* 1192 * On the newer chips that support both SEEPROM & Flash, we need 1193 * to specifically enable SEEPROM access (Flash is the default). 1194 * On older chips, we don't; SEEPROM is the only NVtype supported, 1195 * and the NVM control registers don't exist ... 1196 */ 1197 switch (bgep->chipid.nvtype) { 1198 case BGE_NVTYPE_NONE: 1199 case BGE_NVTYPE_UNKNOWN: 1200 _NOTE(NOTREACHED) 1201 case BGE_NVTYPE_SEEPROM: 1202 break; 1203 1204 case BGE_NVTYPE_LEGACY_SEEPROM: 1205 case BGE_NVTYPE_UNBUFFERED_FLASH: 1206 case BGE_NVTYPE_BUFFERED_FLASH: 1207 default: 1208 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1209 NVM_CFG1_LEGACY_SEEPROM_MODE); 1210 break; 1211 } 1212 1213 /* 1214 * Check there's no command in progress. 1215 * 1216 * Note: this *shouldn't* ever find that there is a command 1217 * in progress, because we already hold the <genlock> mutex. 1218 * Also, to ensure we don't have a conflict with the chip's 1219 * internal firmware or a process accessing the same (shared) 1220 * SEEPROM through the other port of a 5704, we've already 1221 * been through the "software arbitration" protocol. 1222 * So this is just a final consistency check: we shouldn't 1223 * see EITHER the START bit (command started but not complete) 1224 * OR the COMPLETE bit (command completed but not cleared). 1225 */ 1226 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1227 if (regval & SEEPROM_ACCESS_START) 1228 return (EPROTO); 1229 if (regval & SEEPROM_ACCESS_COMPLETE) 1230 return (EPROTO); 1231 1232 /* 1233 * Assemble the command ... 1234 */ 1235 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1236 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1237 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1238 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1239 cmd |= SEEPROM_ACCESS_START; 1240 cmd |= SEEPROM_ACCESS_COMPLETE; 1241 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1242 1243 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1244 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1245 1246 /* 1247 * By observation, a successful access takes ~20us on a 5703/4, 1248 * but apparently much longer (up to 1000us) on the obsolescent 1249 * BCM5700/BCM5701. We want to be sure we don't get any false 1250 * timeouts here; but OTOH, we don't want a bogus access to lock 1251 * out interrupts for longer than necessary. So we'll allow up 1252 * to 1000us ... 1253 */ 1254 for (tries = 0; tries < 1000; ++tries) { 1255 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1256 if (regval & SEEPROM_ACCESS_COMPLETE) 1257 break; 1258 drv_usecwait(1); 1259 } 1260 1261 if (regval & SEEPROM_ACCESS_COMPLETE) { 1262 /* 1263 * All OK; read the SEEPROM data register, then write back 1264 * the value read from the address register in order to 1265 * clear the <complete> bit and leave the SEEPROM access 1266 * state machine idle, ready for the next access ... 1267 */ 1268 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1269 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1270 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1271 return (0); 1272 } 1273 1274 /* 1275 * Hmm ... what happened here? 1276 * 1277 * Most likely, the user addressed a non-existent SEEPROM. Or 1278 * maybe the SEEPROM was busy internally (e.g. processing a write) 1279 * and didn't respond to being addressed. Either way, it's left 1280 * the SEEPROM access state machine wedged. So we'll reset it 1281 * before we leave, so it's ready for next time ... 1282 */ 1283 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1284 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1285 return (ENODATA); 1286 } 1287 1288 /* 1289 * Basic Flash get/set access routine 1290 * 1291 * These use the chip's Flash auto-access method, controlled by the 1292 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1293 * fiddle with the individual bits. 1294 * 1295 * The caller should hold <genlock> and *also* have already acquired 1296 * the right to access the Flash, via bge_nvmem_acquire() above. 1297 * 1298 * Return value: 1299 * 0 on success, 1300 * ENODATA on access timeout (maybe retryable: device may just be busy) 1301 * ENODEV if the NVmem device is missing or otherwise unusable 1302 * 1303 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1304 * from a (successful) NVM_FLASH_CMD_RD. 1305 */ 1306 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1307 uint32_t *dp); 1308 #pragma no_inline(bge_flash_access) 1309 1310 static int 1311 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1312 { 1313 uint32_t tries; 1314 uint32_t regval; 1315 1316 ASSERT(mutex_owned(bgep->genlock)); 1317 1318 /* 1319 * On the newer chips that support both SEEPROM & Flash, we need 1320 * to specifically disable SEEPROM access while accessing Flash. 1321 * The older chips don't support Flash, and the NVM registers don't 1322 * exist, so we shouldn't be here at all! 1323 */ 1324 switch (bgep->chipid.nvtype) { 1325 case BGE_NVTYPE_NONE: 1326 case BGE_NVTYPE_UNKNOWN: 1327 _NOTE(NOTREACHED) 1328 case BGE_NVTYPE_SEEPROM: 1329 return (ENODEV); 1330 1331 case BGE_NVTYPE_LEGACY_SEEPROM: 1332 case BGE_NVTYPE_UNBUFFERED_FLASH: 1333 case BGE_NVTYPE_BUFFERED_FLASH: 1334 default: 1335 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1336 NVM_CFG1_LEGACY_SEEPROM_MODE); 1337 break; 1338 } 1339 1340 /* 1341 * Assemble the command ... 1342 */ 1343 addr &= NVM_FLASH_ADDR_MASK; 1344 cmd |= NVM_FLASH_CMD_DOIT; 1345 cmd |= NVM_FLASH_CMD_FIRST; 1346 cmd |= NVM_FLASH_CMD_LAST; 1347 cmd |= NVM_FLASH_CMD_DONE; 1348 1349 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1350 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1351 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1352 1353 /* 1354 * Allow up to 1000ms ... 1355 */ 1356 for (tries = 0; tries < 1000; ++tries) { 1357 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1358 if (regval & NVM_FLASH_CMD_DONE) 1359 break; 1360 drv_usecwait(1); 1361 } 1362 1363 if (regval & NVM_FLASH_CMD_DONE) { 1364 /* 1365 * All OK; read the data from the Flash read register 1366 */ 1367 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1368 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1369 return (0); 1370 } 1371 1372 /* 1373 * Hmm ... what happened here? 1374 * 1375 * Most likely, the user addressed a non-existent Flash. Or 1376 * maybe the Flash was busy internally (e.g. processing a write) 1377 * and didn't respond to being addressed. Either way, there's 1378 * nothing we can here ... 1379 */ 1380 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1381 return (ENODATA); 1382 } 1383 1384 /* 1385 * The next two functions regulate access to the NVram (if fitted). 1386 * 1387 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1388 * (SPI) interface, but they can be accessed through either port. These 1389 * are managed by different instance of this driver and have no software 1390 * state in common. 1391 * 1392 * In addition (and even on a single core chip) the chip's internal 1393 * firmware can access the SEEPROM/Flash, most notably after a RESET 1394 * when it may download code to run internally. 1395 * 1396 * So we need to arbitrate between these various software agents. For 1397 * this purpose, the chip provides the Software Arbitration Register, 1398 * which implements hardware(!) arbitration. 1399 * 1400 * This functionality didn't exist on older (5700/5701) chips, so there's 1401 * nothing we can do by way of arbitration on those; also, if there's no 1402 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1403 * nothing to do. 1404 * 1405 * The internal firmware appears to use Request 0, which is the highest 1406 * priority. So we'd like to use Request 2, leaving one higher and one 1407 * lower for any future developments ... but apparently this doesn't 1408 * always work. So for now, the code uses Request 1 ;-( 1409 */ 1410 1411 #define NVM_READ_REQ NVM_READ_REQ1 1412 #define NVM_RESET_REQ NVM_RESET_REQ1 1413 #define NVM_SET_REQ NVM_SET_REQ1 1414 1415 static void bge_nvmem_relinquish(bge_t *bgep); 1416 #pragma no_inline(bge_nvmem_relinquish) 1417 1418 static void 1419 bge_nvmem_relinquish(bge_t *bgep) 1420 { 1421 ASSERT(mutex_owned(bgep->genlock)); 1422 1423 switch (bgep->chipid.nvtype) { 1424 case BGE_NVTYPE_NONE: 1425 case BGE_NVTYPE_UNKNOWN: 1426 _NOTE(NOTREACHED) 1427 return; 1428 1429 case BGE_NVTYPE_SEEPROM: 1430 /* 1431 * No arbitration performed, no release needed 1432 */ 1433 return; 1434 1435 case BGE_NVTYPE_LEGACY_SEEPROM: 1436 case BGE_NVTYPE_UNBUFFERED_FLASH: 1437 case BGE_NVTYPE_BUFFERED_FLASH: 1438 default: 1439 break; 1440 } 1441 1442 /* 1443 * Our own request should be present (whether or not granted) ... 1444 */ 1445 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1446 1447 /* 1448 * ... this will make it go away. 1449 */ 1450 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1451 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1452 } 1453 1454 /* 1455 * Arbitrate for access to the NVmem, if necessary 1456 * 1457 * Return value: 1458 * 0 on success 1459 * EAGAIN if the device is in use (retryable) 1460 * ENODEV if the NVmem device is missing or otherwise unusable 1461 */ 1462 static int bge_nvmem_acquire(bge_t *bgep); 1463 #pragma no_inline(bge_nvmem_acquire) 1464 1465 static int 1466 bge_nvmem_acquire(bge_t *bgep) 1467 { 1468 uint32_t regval; 1469 uint32_t tries; 1470 1471 ASSERT(mutex_owned(bgep->genlock)); 1472 1473 switch (bgep->chipid.nvtype) { 1474 case BGE_NVTYPE_NONE: 1475 case BGE_NVTYPE_UNKNOWN: 1476 /* 1477 * Access denied: no (recognisable) device fitted 1478 */ 1479 return (ENODEV); 1480 1481 case BGE_NVTYPE_SEEPROM: 1482 /* 1483 * Access granted: no arbitration needed (or possible) 1484 */ 1485 return (0); 1486 1487 case BGE_NVTYPE_LEGACY_SEEPROM: 1488 case BGE_NVTYPE_UNBUFFERED_FLASH: 1489 case BGE_NVTYPE_BUFFERED_FLASH: 1490 default: 1491 /* 1492 * Access conditional: conduct arbitration protocol 1493 */ 1494 break; 1495 } 1496 1497 /* 1498 * We're holding the per-port mutex <genlock>, so no-one other 1499 * thread can be attempting to access the NVmem through *this* 1500 * port. But it could be in use by the *other* port (of a 5704), 1501 * or by the chip's internal firmware, so we have to go through 1502 * the full (hardware) arbitration protocol ... 1503 * 1504 * Note that *because* we're holding <genlock>, the interrupt handler 1505 * won't be able to progress. So we're only willing to spin for a 1506 * fairly short time. Specifically: 1507 * 1508 * We *must* wait long enough for the hardware to resolve all 1509 * requests and determine the winner. Fortunately, this is 1510 * "almost instantaneous", even as observed by GHz CPUs. 1511 * 1512 * A successful access by another Solaris thread (via either 1513 * port) typically takes ~20us. So waiting a bit longer than 1514 * that will give a good chance of success, if the other user 1515 * *is* another thread on the other port. 1516 * 1517 * However, the internal firmware can hold on to the NVmem 1518 * for *much* longer: at least 10 milliseconds just after a 1519 * RESET, and maybe even longer if the NVmem actually contains 1520 * code to download and run on the internal CPUs. 1521 * 1522 * So, we'll allow 50us; if that's not enough then it's up to the 1523 * caller to retry later (hence the choice of return code EAGAIN). 1524 */ 1525 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1526 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1527 1528 for (tries = 0; tries < 50; ++tries) { 1529 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1530 if (regval & NVM_WON_REQ1) 1531 break; 1532 drv_usecwait(1); 1533 } 1534 1535 if (regval & NVM_WON_REQ1) { 1536 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1537 return (0); 1538 } 1539 1540 /* 1541 * Somebody else must be accessing the NVmem, so abandon our 1542 * attempt take control of it. The caller can try again later ... 1543 */ 1544 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1545 bge_nvmem_relinquish(bgep); 1546 return (EAGAIN); 1547 } 1548 1549 /* 1550 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1551 * write protect line in such a way that the NVmem is protected when 1552 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1553 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1554 * 1555 * Note: there's only one set of GPIO pins on a 5704, even though they 1556 * can be accessed through either port. So the chip has to resolve what 1557 * happens if the two ports program a single pin differently ... the rule 1558 * it uses is that if the ports disagree about the *direction* of a pin, 1559 * "output" wins over "input", but if they disagree about its *value* as 1560 * an output, then the pin is TRISTATED instead! In such a case, no-one 1561 * wins, and the external signal does whatever the external circuitry 1562 * defines as the default -- which we've assumed is the PROTECTED state. 1563 * So, we always change GPIO1 back to being an *input* whenever we're not 1564 * specifically using it to unprotect the NVmem. This allows either port 1565 * to update the NVmem, although obviously only one at a time! 1566 * 1567 * The caller should hold <genlock> and *also* have already acquired the 1568 * right to access the NVmem, via bge_nvmem_acquire() above. 1569 */ 1570 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1571 #pragma inline(bge_nvmem_protect) 1572 1573 static void 1574 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1575 { 1576 uint32_t regval; 1577 1578 ASSERT(mutex_owned(bgep->genlock)); 1579 1580 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1581 if (protect) { 1582 regval |= MLCR_MISC_PINS_OUTPUT_1; 1583 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1584 } else { 1585 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1586 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1587 } 1588 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1589 } 1590 1591 /* 1592 * Now put it all together ... 1593 * 1594 * Try to acquire control of the NVmem; if successful, then: 1595 * unprotect it (if we want to write to it) 1596 * perform the requested access 1597 * reprotect it (after a write) 1598 * relinquish control 1599 * 1600 * Return value: 1601 * 0 on success, 1602 * EAGAIN if the device is in use (retryable) 1603 * ENODATA on access timeout (maybe retryable: device may just be busy) 1604 * ENODEV if the NVmem device is missing or otherwise unusable 1605 * EPROTO on other h/w or s/w errors. 1606 */ 1607 static int 1608 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1609 { 1610 int err; 1611 1612 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1613 switch (cmd) { 1614 case BGE_SEE_READ: 1615 err = bge_seeprom_access(bgep, 1616 SEEPROM_ACCESS_READ, addr, dp); 1617 break; 1618 1619 case BGE_SEE_WRITE: 1620 bge_nvmem_protect(bgep, B_FALSE); 1621 err = bge_seeprom_access(bgep, 1622 SEEPROM_ACCESS_WRITE, addr, dp); 1623 bge_nvmem_protect(bgep, B_TRUE); 1624 break; 1625 1626 case BGE_FLASH_READ: 1627 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1628 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1629 bge_reg_set32(bgep, NVM_ACCESS_REG, 1630 NVM_ACCESS_ENABLE); 1631 } 1632 err = bge_flash_access(bgep, 1633 NVM_FLASH_CMD_RD, addr, dp); 1634 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1635 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1636 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1637 NVM_ACCESS_ENABLE); 1638 } 1639 break; 1640 1641 case BGE_FLASH_WRITE: 1642 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1643 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1644 bge_reg_set32(bgep, NVM_ACCESS_REG, 1645 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1646 } 1647 bge_nvmem_protect(bgep, B_FALSE); 1648 err = bge_flash_access(bgep, 1649 NVM_FLASH_CMD_WR, addr, dp); 1650 bge_nvmem_protect(bgep, B_TRUE); 1651 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1652 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1653 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1654 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1655 } 1656 1657 break; 1658 1659 default: 1660 _NOTE(NOTREACHED) 1661 break; 1662 } 1663 bge_nvmem_relinquish(bgep); 1664 } 1665 1666 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1667 return (err); 1668 } 1669 1670 /* 1671 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1672 */ 1673 static uint64_t bge_get_nvmac(bge_t *bgep); 1674 #pragma no_inline(bge_get_nvmac) 1675 1676 static uint64_t 1677 bge_get_nvmac(bge_t *bgep) 1678 { 1679 uint32_t mac_high; 1680 uint32_t mac_low; 1681 uint32_t addr; 1682 uint32_t cmd; 1683 uint64_t mac; 1684 1685 BGE_TRACE(("bge_get_nvmac($%p)", 1686 (void *)bgep)); 1687 1688 switch (bgep->chipid.nvtype) { 1689 case BGE_NVTYPE_NONE: 1690 case BGE_NVTYPE_UNKNOWN: 1691 default: 1692 return (0ULL); 1693 1694 case BGE_NVTYPE_SEEPROM: 1695 case BGE_NVTYPE_LEGACY_SEEPROM: 1696 cmd = BGE_SEE_READ; 1697 break; 1698 1699 case BGE_NVTYPE_UNBUFFERED_FLASH: 1700 case BGE_NVTYPE_BUFFERED_FLASH: 1701 cmd = BGE_FLASH_READ; 1702 break; 1703 } 1704 1705 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1706 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1707 else 1708 addr = NVMEM_DATA_MAC_ADDRESS; 1709 1710 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1711 return (0ULL); 1712 addr += 4; 1713 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1714 return (0ULL); 1715 1716 /* 1717 * The Broadcom chip is natively BIG-endian, so that's how the 1718 * MAC address is represented in NVmem. We may need to swap it 1719 * around on a little-endian host ... 1720 */ 1721 #ifdef _BIG_ENDIAN 1722 mac = mac_high; 1723 mac = mac << 32; 1724 mac |= mac_low; 1725 #else 1726 mac = BGE_BSWAP_32(mac_high); 1727 mac = mac << 32; 1728 mac |= BGE_BSWAP_32(mac_low); 1729 #endif /* _BIG_ENDIAN */ 1730 1731 return (mac); 1732 } 1733 1734 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1735 1736 /* 1737 * Dummy version for when we're not supporting NVmem access 1738 */ 1739 static uint64_t bge_get_nvmac(bge_t *bgep); 1740 #pragma inline(bge_get_nvmac) 1741 1742 static uint64_t 1743 bge_get_nvmac(bge_t *bgep) 1744 { 1745 _NOTE(ARGUNUSED(bgep)) 1746 return (0ULL); 1747 } 1748 1749 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1750 1751 /* 1752 * Determine the type of NVmem that is (or may be) attached to this chip, 1753 */ 1754 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1755 #pragma no_inline(bge_nvmem_id) 1756 1757 static enum bge_nvmem_type 1758 bge_nvmem_id(bge_t *bgep) 1759 { 1760 enum bge_nvmem_type nvtype; 1761 uint32_t config1; 1762 1763 BGE_TRACE(("bge_nvmem_id($%p)", 1764 (void *)bgep)); 1765 1766 switch (bgep->chipid.device) { 1767 default: 1768 /* 1769 * We shouldn't get here; it means we don't recognise 1770 * the chip, which means we don't know how to determine 1771 * what sort of NVmem (if any) it has. So we'll say 1772 * NONE, to disable the NVmem access code ... 1773 */ 1774 nvtype = BGE_NVTYPE_NONE; 1775 break; 1776 1777 case DEVICE_ID_5700: 1778 case DEVICE_ID_5700x: 1779 case DEVICE_ID_5701: 1780 /* 1781 * These devices support *only* SEEPROMs 1782 */ 1783 nvtype = BGE_NVTYPE_SEEPROM; 1784 break; 1785 1786 case DEVICE_ID_5702: 1787 case DEVICE_ID_5702fe: 1788 case DEVICE_ID_5703C: 1789 case DEVICE_ID_5703S: 1790 case DEVICE_ID_5704C: 1791 case DEVICE_ID_5704S: 1792 case DEVICE_ID_5704: 1793 case DEVICE_ID_5705M: 1794 case DEVICE_ID_5705C: 1795 case DEVICE_ID_5705_2: 1796 case DEVICE_ID_5706: 1797 case DEVICE_ID_5782: 1798 case DEVICE_ID_5787: 1799 case DEVICE_ID_5787M: 1800 case DEVICE_ID_5788: 1801 case DEVICE_ID_5789: 1802 case DEVICE_ID_5751: 1803 case DEVICE_ID_5751M: 1804 case DEVICE_ID_5752: 1805 case DEVICE_ID_5752M: 1806 case DEVICE_ID_5754: 1807 case DEVICE_ID_5755: 1808 case DEVICE_ID_5755M: 1809 case DEVICE_ID_5721: 1810 case DEVICE_ID_5722: 1811 case DEVICE_ID_5714C: 1812 case DEVICE_ID_5714S: 1813 case DEVICE_ID_5715C: 1814 case DEVICE_ID_5715S: 1815 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1816 if (config1 & NVM_CFG1_FLASH_MODE) 1817 if (config1 & NVM_CFG1_BUFFERED_MODE) 1818 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1819 else 1820 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1821 else 1822 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1823 break; 1824 case DEVICE_ID_5906: 1825 case DEVICE_ID_5906M: 1826 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1827 break; 1828 } 1829 1830 return (nvtype); 1831 } 1832 1833 #undef BGE_DBG 1834 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1835 1836 static void 1837 bge_init_recv_rule(bge_t *bgep) 1838 { 1839 bge_recv_rule_t *rulep; 1840 uint32_t i; 1841 1842 /* 1843 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1844 * 1. to direct UDP traffic, set: 1845 * rulep->control = RULE_PROTO_CONTROL; 1846 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1847 * 2. to direct ICMP traffic, set: 1848 * rulep->control = RULE_PROTO_CONTROL; 1849 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1850 * 3. to direct traffic by source ip, set: 1851 * rulep->control = RULE_SIP_CONTROL; 1852 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1853 */ 1854 rulep = bgep->recv_rules; 1855 rulep->control = RULE_PROTO_CONTROL; 1856 rulep->mask_value = RULE_TCP_MASK_VALUE; 1857 1858 /* 1859 * set receive rule registers 1860 */ 1861 rulep = bgep->recv_rules; 1862 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1863 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1864 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1865 } 1866 } 1867 1868 /* 1869 * Using the values captured by bge_chip_cfg_init(), and additional probes 1870 * as required, characterise the chip fully: determine the label by which 1871 * to refer to this chip, the correct settings for various registers, and 1872 * of course whether the device and/or subsystem are supported! 1873 */ 1874 int bge_chip_id_init(bge_t *bgep); 1875 #pragma no_inline(bge_chip_id_init) 1876 1877 int 1878 bge_chip_id_init(bge_t *bgep) 1879 { 1880 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1881 boolean_t sys_ok; 1882 boolean_t dev_ok; 1883 chip_id_t *cidp; 1884 uint32_t subid; 1885 char *devname; 1886 char *sysname; 1887 int *ids; 1888 int err; 1889 uint_t i; 1890 1891 sys_ok = dev_ok = B_FALSE; 1892 cidp = &bgep->chipid; 1893 1894 /* 1895 * Check the PCI device ID to determine the generic chip type and 1896 * select parameters that depend on this. 1897 * 1898 * Note: because the SPARC platforms in general don't fit the 1899 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1900 * as zero - which is why we use <asic_rev> rather than <revision> 1901 * below ... 1902 * 1903 * Note: in general we can't distinguish between the Copper/SerDes 1904 * versions by ID alone, as some Copper devices (e.g. some but not 1905 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1906 * treat them the same here, and the MII code works out the media 1907 * type later on ... 1908 */ 1909 cidp->mbuf_base = bge_mbuf_pool_base; 1910 cidp->mbuf_length = bge_mbuf_pool_len; 1911 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1912 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1913 cidp->pci_type = BGE_PCI_X; 1914 cidp->statistic_type = BGE_STAT_BLK; 1915 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1916 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1917 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1918 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1919 cidp->rx_count_norm = bge_rx_count_norm; 1920 1921 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1922 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1923 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1924 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1925 1926 cidp->msi_enabled = B_FALSE; 1927 1928 switch (cidp->device) { 1929 case DEVICE_ID_5700: 1930 case DEVICE_ID_5700x: 1931 cidp->chip_label = 5700; 1932 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1933 break; 1934 1935 case DEVICE_ID_5701: 1936 cidp->chip_label = 5701; 1937 dev_ok = B_TRUE; 1938 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1939 break; 1940 1941 case DEVICE_ID_5702: 1942 case DEVICE_ID_5702fe: 1943 cidp->chip_label = 5702; 1944 dev_ok = B_TRUE; 1945 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1946 cidp->pci_type = BGE_PCI; 1947 break; 1948 1949 case DEVICE_ID_5703C: 1950 case DEVICE_ID_5703S: 1951 case DEVICE_ID_5703: 1952 /* 1953 * Revision A0 of the 5703/5793 had various errata 1954 * that we can't or don't work around, so it's not 1955 * supported, but all later versions are 1956 */ 1957 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1958 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1959 dev_ok = B_TRUE; 1960 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1961 break; 1962 1963 case DEVICE_ID_5704C: 1964 case DEVICE_ID_5704S: 1965 case DEVICE_ID_5704: 1966 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1967 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1968 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1969 dev_ok = B_TRUE; 1970 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1971 break; 1972 1973 case DEVICE_ID_5705C: 1974 case DEVICE_ID_5705M: 1975 case DEVICE_ID_5705MA3: 1976 case DEVICE_ID_5705F: 1977 case DEVICE_ID_5705_2: 1978 case DEVICE_ID_5754: 1979 if (cidp->device == DEVICE_ID_5754) { 1980 cidp->chip_label = 5754; 1981 cidp->pci_type = BGE_PCI_E; 1982 } else { 1983 cidp->chip_label = 5705; 1984 cidp->pci_type = BGE_PCI; 1985 } 1986 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 1987 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 1988 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 1989 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1990 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1991 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1992 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1993 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 1994 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1995 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1996 cidp->statistic_type = BGE_STAT_REG; 1997 dev_ok = B_TRUE; 1998 break; 1999 2000 case DEVICE_ID_5906: 2001 case DEVICE_ID_5906M: 2002 cidp->chip_label = 5906; 2003 cidp->pci_type = BGE_PCI_E; 2004 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2005 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2006 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2007 cidp->mbuf_base = bge_mbuf_pool_base; 2008 cidp->mbuf_length = bge_mbuf_pool_len; 2009 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2010 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2011 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2012 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2013 cidp->statistic_type = BGE_STAT_REG; 2014 dev_ok = B_TRUE; 2015 break; 2016 2017 case DEVICE_ID_5753: 2018 cidp->chip_label = 5753; 2019 cidp->pci_type = BGE_PCI_E; 2020 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2021 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2022 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2023 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2024 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2025 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2026 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2027 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2028 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2029 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2030 cidp->statistic_type = BGE_STAT_REG; 2031 dev_ok = B_TRUE; 2032 break; 2033 2034 case DEVICE_ID_5755: 2035 case DEVICE_ID_5755M: 2036 cidp->chip_label = 5755; 2037 cidp->pci_type = BGE_PCI_E; 2038 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2039 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2040 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2041 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2042 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2043 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2044 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2045 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2046 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2047 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2048 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2049 cidp->statistic_type = BGE_STAT_REG; 2050 dev_ok = B_TRUE; 2051 break; 2052 2053 case DEVICE_ID_5787: 2054 case DEVICE_ID_5787M: 2055 cidp->chip_label = 5787; 2056 cidp->pci_type = BGE_PCI_E; 2057 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2058 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2059 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2060 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2061 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2062 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2063 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2064 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2065 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2066 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2067 cidp->statistic_type = BGE_STAT_REG; 2068 dev_ok = B_TRUE; 2069 break; 2070 2071 case DEVICE_ID_5706: 2072 cidp->chip_label = 5706; 2073 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2074 break; 2075 2076 case DEVICE_ID_5782: 2077 /* 2078 * Apart from the label, we treat this as a 5705(?) 2079 */ 2080 cidp->chip_label = 5782; 2081 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2082 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2083 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2084 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2085 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2086 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2087 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2088 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2089 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2090 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2091 cidp->statistic_type = BGE_STAT_REG; 2092 dev_ok = B_TRUE; 2093 break; 2094 2095 case DEVICE_ID_5788: 2096 /* 2097 * Apart from the label, we treat this as a 5705(?) 2098 */ 2099 cidp->chip_label = 5788; 2100 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2101 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2102 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2103 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2104 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2105 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2106 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2107 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2108 cidp->statistic_type = BGE_STAT_REG; 2109 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2110 dev_ok = B_TRUE; 2111 break; 2112 2113 case DEVICE_ID_5714C: 2114 if (cidp->revision >= REVISION_ID_5714_A2) 2115 cidp->msi_enabled = bge_enable_msi; 2116 /* FALLTHRU */ 2117 case DEVICE_ID_5714S: 2118 cidp->chip_label = 5714; 2119 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2120 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2121 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2122 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2123 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2124 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2125 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2126 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2127 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2128 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2129 cidp->pci_type = BGE_PCI_E; 2130 cidp->statistic_type = BGE_STAT_REG; 2131 dev_ok = B_TRUE; 2132 break; 2133 2134 case DEVICE_ID_5715C: 2135 case DEVICE_ID_5715S: 2136 cidp->chip_label = 5715; 2137 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2138 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2139 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2140 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2141 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2142 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2143 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2144 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2145 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2146 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2147 cidp->pci_type = BGE_PCI_E; 2148 cidp->statistic_type = BGE_STAT_REG; 2149 if (cidp->revision >= REVISION_ID_5715_A2) 2150 cidp->msi_enabled = bge_enable_msi; 2151 dev_ok = B_TRUE; 2152 break; 2153 2154 case DEVICE_ID_5721: 2155 cidp->chip_label = 5721; 2156 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2157 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2158 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2159 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2160 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2161 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2162 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2163 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2164 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2165 cidp->pci_type = BGE_PCI_E; 2166 cidp->statistic_type = BGE_STAT_REG; 2167 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2168 dev_ok = B_TRUE; 2169 break; 2170 2171 case DEVICE_ID_5722: 2172 cidp->chip_label = 5722; 2173 cidp->pci_type = BGE_PCI_E; 2174 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2175 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2176 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2177 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2178 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2179 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2180 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2181 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2182 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2183 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2184 cidp->statistic_type = BGE_STAT_REG; 2185 dev_ok = B_TRUE; 2186 break; 2187 2188 case DEVICE_ID_5751: 2189 case DEVICE_ID_5751M: 2190 cidp->chip_label = 5751; 2191 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2192 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2193 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2194 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2195 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2196 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2197 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2198 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2199 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2200 cidp->pci_type = BGE_PCI_E; 2201 cidp->statistic_type = BGE_STAT_REG; 2202 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2203 dev_ok = B_TRUE; 2204 break; 2205 2206 case DEVICE_ID_5752: 2207 case DEVICE_ID_5752M: 2208 cidp->chip_label = 5752; 2209 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2210 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2211 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2212 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2213 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2214 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2215 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2216 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2217 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2218 cidp->pci_type = BGE_PCI_E; 2219 cidp->statistic_type = BGE_STAT_REG; 2220 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2221 dev_ok = B_TRUE; 2222 break; 2223 2224 case DEVICE_ID_5789: 2225 cidp->chip_label = 5789; 2226 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2227 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2228 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2229 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2230 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2231 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2232 cidp->pci_type = BGE_PCI_E; 2233 cidp->statistic_type = BGE_STAT_REG; 2234 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2235 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2236 cidp->msi_enabled = B_TRUE; 2237 dev_ok = B_TRUE; 2238 break; 2239 2240 } 2241 2242 /* 2243 * Setup the default jumbo parameter. 2244 */ 2245 cidp->ethmax_size = ETHERMAX; 2246 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2247 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2248 2249 /* 2250 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2251 * setup below jumbo specific parameters. 2252 * 2253 * For BCM5714/5715, there is only one standard receive ring. So the 2254 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2255 * feature is enabled. 2256 */ 2257 if (bge_jumbo_enable && 2258 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2259 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2260 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2261 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2262 cidp->mbuf_lo_water_rdma = 2263 RDMA_MBUF_LOWAT_5714_JUMBO; 2264 cidp->mbuf_lo_water_rmac = 2265 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2266 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2267 cidp->jumbo_slots = 0; 2268 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2269 } else { 2270 cidp->mbuf_lo_water_rdma = 2271 RDMA_MBUF_LOWAT_JUMBO; 2272 cidp->mbuf_lo_water_rmac = 2273 MAC_RX_MBUF_LOWAT_JUMBO; 2274 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2275 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2276 } 2277 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2278 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2279 cidp->ethmax_size = cidp->default_mtu + 2280 sizeof (struct ether_header); 2281 } 2282 2283 /* 2284 * Identify the NV memory type: SEEPROM or Flash? 2285 */ 2286 cidp->nvtype = bge_nvmem_id(bgep); 2287 2288 /* 2289 * Now, we want to check whether this device is part of a 2290 * supported subsystem (e.g., on the motherboard of a Sun 2291 * branded platform). 2292 * 2293 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2294 */ 2295 if (cidp->subven == VENDOR_ID_SUN) 2296 sys_ok = B_TRUE; 2297 2298 /* 2299 * Rule 2: If it's on the list on known subsystems, then it's OK. 2300 * Note: 0x14e41647 should *not* appear in the list, but the code 2301 * doesn't enforce that. 2302 */ 2303 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2304 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2305 if (err == DDI_PROP_SUCCESS) { 2306 /* 2307 * Got the list; scan for a matching subsystem vendor/device 2308 */ 2309 subid = (cidp->subven << 16) | cidp->subdev; 2310 while (i--) 2311 if (ids[i] == subid) 2312 sys_ok = B_TRUE; 2313 ddi_prop_free(ids); 2314 } 2315 2316 /* 2317 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2318 * 2319 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2320 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2321 * we have to check specially for the exact device paths to the 2322 * motherboard devices on those platforms ;-( 2323 * 2324 * Note: we can't just use the "supported-subsystems" mechanism 2325 * above, because the entry would have to be 0x14e41647 -- which 2326 * would then accept *any* plugin card that *didn't* contain a 2327 * (valid) SEEPROM ;-( 2328 */ 2329 sysname = ddi_node_name(ddi_root_node()); 2330 devname = ddi_pathname(bgep->devinfo, buf); 2331 ASSERT(strlen(devname) > 0); 2332 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2333 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2334 sys_ok = B_TRUE; 2335 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2336 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2337 sys_ok = B_TRUE; 2338 2339 /* 2340 * Now check what we've discovered: is this truly a supported 2341 * chip on (the motherboard of) a supported platform? 2342 * 2343 * Possible problems here: 2344 * 1) it's a completely unheard-of chip (e.g. 5761) 2345 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2346 * 3) it's a chip we would support if it were on the motherboard 2347 * of a Sun platform, but this one isn't ;-( 2348 */ 2349 if (cidp->chip_label == 0) 2350 bge_problem(bgep, 2351 "Device 'pci%04x,%04x' not recognized (%d?)", 2352 cidp->vendor, cidp->device, cidp->device); 2353 else if (!dev_ok) 2354 bge_problem(bgep, 2355 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2356 cidp->vendor, cidp->device, cidp->chip_label, 2357 cidp->revision); 2358 #if BGE_DEBUGGING 2359 else if (!sys_ok) 2360 bge_problem(bgep, 2361 "%d-based subsystem 'pci%04x,%04x' not validated", 2362 cidp->chip_label, cidp->subven, cidp->subdev); 2363 #endif 2364 else 2365 cidp->flags |= CHIP_FLAG_SUPPORTED; 2366 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2367 return (EIO); 2368 return (0); 2369 } 2370 2371 void 2372 bge_chip_msi_trig(bge_t *bgep) 2373 { 2374 uint32_t regval; 2375 2376 regval = bgep->param_msi_cnt<<4; 2377 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2378 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2379 } 2380 2381 /* 2382 * Various registers that control the chip's internal engines (state 2383 * machines) have a <reset> and <enable> bits (fortunately, in the 2384 * same place in each such register :-). 2385 * 2386 * To reset the state machine, the <reset> bit must be written with 1; 2387 * it will then read back as 1 while the reset is in progress, but 2388 * self-clear to 0 when the reset completes. 2389 * 2390 * To enable a state machine, one must set the <enable> bit, which 2391 * will continue to read back as 0 until the state machine is running. 2392 * 2393 * To disable a state machine, the <enable> bit must be cleared, but 2394 * it will continue to read back as 1 until the state machine actually 2395 * stops. 2396 * 2397 * This routine implements polling for completion of a reset, enable 2398 * or disable operation, returning B_TRUE on success (bit reached the 2399 * required state) or B_FALSE on timeout (200*100us == 20ms). 2400 */ 2401 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2402 uint32_t mask, uint32_t val); 2403 #pragma no_inline(bge_chip_poll_engine) 2404 2405 static boolean_t 2406 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2407 uint32_t mask, uint32_t val) 2408 { 2409 uint32_t regval; 2410 uint32_t n; 2411 2412 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2413 (void *)bgep, regno, mask, val)); 2414 2415 for (n = 200; n; --n) { 2416 regval = bge_reg_get32(bgep, regno); 2417 if ((regval & mask) == val) 2418 return (B_TRUE); 2419 drv_usecwait(100); 2420 } 2421 2422 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2423 return (B_FALSE); 2424 } 2425 2426 /* 2427 * Various registers that control the chip's internal engines (state 2428 * machines) have a <reset> bit (fortunately, in the same place in 2429 * each such register :-). To reset the state machine, this bit must 2430 * be written with 1; it will then read back as 1 while the reset is 2431 * in progress, but self-clear to 0 when the reset completes. 2432 * 2433 * This code sets the bit, then polls for it to read back as zero. 2434 * The return value is B_TRUE on success (reset bit cleared itself), 2435 * or B_FALSE if the state machine didn't recover :( 2436 * 2437 * NOTE: the Core reset is similar to other resets, except that we 2438 * can't poll for completion, since the Core reset disables memory 2439 * access! So we just have to assume that it will all complete in 2440 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2441 */ 2442 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2443 #pragma no_inline(bge_chip_reset_engine) 2444 2445 static boolean_t 2446 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2447 { 2448 uint32_t regval; 2449 uint32_t val32; 2450 2451 regval = bge_reg_get32(bgep, regno); 2452 2453 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2454 (void *)bgep, regno)); 2455 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2456 regno, regval)); 2457 2458 regval |= STATE_MACHINE_RESET_BIT; 2459 2460 switch (regno) { 2461 case MISC_CONFIG_REG: 2462 /* 2463 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2464 * resetting PCIE block and bringing PCIE link down, bit 29 2465 * in the register needs to be set first, and then set it again 2466 * while the reset bit is written. 2467 * See:P500 of 57xx-PG102-RDS.pdf. 2468 */ 2469 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2470 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2471 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2472 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2473 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2474 if (bgep->chipid.pci_type == BGE_PCI_E) { 2475 if (bgep->chipid.asic_rev == 2476 MHCR_CHIP_REV_5751_A0 || 2477 bgep->chipid.asic_rev == 2478 MHCR_CHIP_REV_5721_A0 || 2479 bgep->chipid.asic_rev == 2480 MHCR_CHIP_REV_5755_A0) { 2481 val32 = bge_reg_get32(bgep, 2482 PHY_TEST_CTRL_REG); 2483 if (val32 == (PHY_PCIE_SCRAM_MODE | 2484 PHY_PCIE_LTASS_MODE)) 2485 bge_reg_put32(bgep, 2486 PHY_TEST_CTRL_REG, 2487 PHY_PCIE_SCRAM_MODE); 2488 val32 = pci_config_get32 2489 (bgep->cfg_handle, 2490 PCI_CONF_BGE_CLKCTL); 2491 val32 |= CLKCTL_PCIE_A0_FIX; 2492 pci_config_put32(bgep->cfg_handle, 2493 PCI_CONF_BGE_CLKCTL, val32); 2494 } 2495 bge_reg_set32(bgep, regno, 2496 MISC_CONFIG_GRC_RESET_DISABLE); 2497 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2498 } 2499 } 2500 2501 /* 2502 * Special case - causes Core reset 2503 * 2504 * On SPARC v9 we want to ensure that we don't start 2505 * timing until the I/O access has actually reached 2506 * the chip, otherwise we might make the next access 2507 * too early. And we can't just force the write out 2508 * by following it with a read (even to config space) 2509 * because that would cause the fault we're trying 2510 * to avoid. Hence the need for membar_sync() here. 2511 */ 2512 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2513 #ifdef __sparcv9 2514 membar_sync(); 2515 #endif /* __sparcv9 */ 2516 /* 2517 * On some platforms,system need about 300us for 2518 * link setup. 2519 */ 2520 drv_usecwait(300); 2521 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2522 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2523 bge_reg_clr32( 2524 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2525 } 2526 2527 if (bgep->chipid.pci_type == BGE_PCI_E) { 2528 /* PCI-E device need more reset time */ 2529 drv_usecwait(120000); 2530 2531 /* Set PCIE max payload size and clear error status. */ 2532 if ((bgep->chipid.chip_label == 5721) || 2533 (bgep->chipid.chip_label == 5751) || 2534 (bgep->chipid.chip_label == 5752) || 2535 (bgep->chipid.chip_label == 5789) || 2536 (bgep->chipid.chip_label == 5906)) { 2537 pci_config_put16(bgep->cfg_handle, 2538 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2539 pci_config_put16(bgep->cfg_handle, 2540 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2541 } 2542 } 2543 2544 BGE_PCICHK(bgep); 2545 return (B_TRUE); 2546 2547 default: 2548 bge_reg_put32(bgep, regno, regval); 2549 return (bge_chip_poll_engine(bgep, regno, 2550 STATE_MACHINE_RESET_BIT, 0)); 2551 } 2552 } 2553 2554 /* 2555 * Various registers that control the chip's internal engines (state 2556 * machines) have an <enable> bit (fortunately, in the same place in 2557 * each such register :-). To stop the state machine, this bit must 2558 * be written with 0, then polled to see when the state machine has 2559 * actually stopped. 2560 * 2561 * The return value is B_TRUE on success (enable bit cleared), or 2562 * B_FALSE if the state machine didn't stop :( 2563 */ 2564 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2565 uint32_t morebits); 2566 #pragma no_inline(bge_chip_disable_engine) 2567 2568 static boolean_t 2569 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2570 { 2571 uint32_t regval; 2572 2573 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2574 (void *)bgep, regno, morebits)); 2575 2576 switch (regno) { 2577 case FTQ_RESET_REG: 2578 /* 2579 * For Schumacher's bugfix CR6490108 2580 */ 2581 #ifdef BGE_IPMI_ASF 2582 #ifdef BGE_NETCONSOLE 2583 if (bgep->asf_enabled) 2584 return (B_TRUE); 2585 #endif 2586 #endif 2587 /* 2588 * Not quite like the others; it doesn't 2589 * have an <enable> bit, but instead we 2590 * have to set and then clear all the bits 2591 */ 2592 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2593 drv_usecwait(100); 2594 bge_reg_put32(bgep, regno, 0); 2595 return (B_TRUE); 2596 2597 default: 2598 regval = bge_reg_get32(bgep, regno); 2599 regval &= ~STATE_MACHINE_ENABLE_BIT; 2600 regval &= ~morebits; 2601 bge_reg_put32(bgep, regno, regval); 2602 return (bge_chip_poll_engine(bgep, regno, 2603 STATE_MACHINE_ENABLE_BIT, 0)); 2604 } 2605 } 2606 2607 /* 2608 * Various registers that control the chip's internal engines (state 2609 * machines) have an <enable> bit (fortunately, in the same place in 2610 * each such register :-). To start the state machine, this bit must 2611 * be written with 1, then polled to see when the state machine has 2612 * actually started. 2613 * 2614 * The return value is B_TRUE on success (enable bit set), or 2615 * B_FALSE if the state machine didn't start :( 2616 */ 2617 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2618 uint32_t morebits); 2619 #pragma no_inline(bge_chip_enable_engine) 2620 2621 static boolean_t 2622 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2623 { 2624 uint32_t regval; 2625 2626 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2627 (void *)bgep, regno, morebits)); 2628 2629 switch (regno) { 2630 case FTQ_RESET_REG: 2631 #ifdef BGE_IPMI_ASF 2632 #ifdef BGE_NETCONSOLE 2633 if (bgep->asf_enabled) 2634 return (B_TRUE); 2635 #endif 2636 #endif 2637 /* 2638 * Not quite like the others; it doesn't 2639 * have an <enable> bit, but instead we 2640 * have to set and then clear all the bits 2641 */ 2642 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2643 drv_usecwait(100); 2644 bge_reg_put32(bgep, regno, 0); 2645 return (B_TRUE); 2646 2647 default: 2648 regval = bge_reg_get32(bgep, regno); 2649 regval |= STATE_MACHINE_ENABLE_BIT; 2650 regval |= morebits; 2651 bge_reg_put32(bgep, regno, regval); 2652 return (bge_chip_poll_engine(bgep, regno, 2653 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2654 } 2655 } 2656 2657 /* 2658 * Reprogram the Ethernet, Transmit, and Receive MAC 2659 * modes to match the param_* variables 2660 */ 2661 void bge_sync_mac_modes(bge_t *bgep); 2662 #pragma no_inline(bge_sync_mac_modes) 2663 2664 void 2665 bge_sync_mac_modes(bge_t *bgep) 2666 { 2667 uint32_t macmode; 2668 uint32_t regval; 2669 2670 ASSERT(mutex_owned(bgep->genlock)); 2671 2672 /* 2673 * Reprogram the Ethernet MAC mode ... 2674 */ 2675 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2676 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2677 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2678 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2679 macmode |= ETHERNET_MODE_LINK_POLARITY; 2680 else 2681 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2682 else 2683 macmode |= ETHERNET_MODE_LINK_POLARITY; 2684 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2685 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2686 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2687 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2688 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2689 else 2690 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2691 } else if (bgep->param_link_speed == 10 || 2692 bgep->param_link_speed == 100) 2693 macmode |= ETHERNET_MODE_PORTMODE_MII; 2694 else 2695 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2696 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2697 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2698 else 2699 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2700 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2701 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2702 else 2703 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2704 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2705 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2706 (void *)bgep, regval, macmode)); 2707 2708 /* 2709 * ... the Transmit MAC mode ... 2710 */ 2711 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2712 if (bgep->param_link_tx_pause) 2713 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2714 else 2715 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2716 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2717 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2718 (void *)bgep, regval, macmode)); 2719 2720 /* 2721 * ... and the Receive MAC mode 2722 */ 2723 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2724 if (bgep->param_link_rx_pause) 2725 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2726 else 2727 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2728 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2729 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2730 (void *)bgep, regval, macmode)); 2731 } 2732 2733 /* 2734 * bge_chip_sync() -- program the chip with the unicast MAC address, 2735 * the multicast hash table, the required level of promiscuity, and 2736 * the current loopback mode ... 2737 */ 2738 #ifdef BGE_IPMI_ASF 2739 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2740 #else 2741 int bge_chip_sync(bge_t *bgep); 2742 #endif 2743 #pragma no_inline(bge_chip_sync) 2744 2745 int 2746 #ifdef BGE_IPMI_ASF 2747 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2748 #else 2749 bge_chip_sync(bge_t *bgep) 2750 #endif 2751 { 2752 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2753 boolean_t promisc; 2754 uint64_t macaddr; 2755 uint32_t fill; 2756 int i, j; 2757 int retval = DDI_SUCCESS; 2758 2759 BGE_TRACE(("bge_chip_sync($%p)", 2760 (void *)bgep)); 2761 2762 ASSERT(mutex_owned(bgep->genlock)); 2763 2764 promisc = B_FALSE; 2765 fill = ~(uint32_t)0; 2766 2767 if (bgep->promisc) 2768 promisc = B_TRUE; 2769 else 2770 fill = (uint32_t)0; 2771 2772 /* 2773 * If the TX/RX MAC engines are already running, we should stop 2774 * them (and reset the RX engine) before changing the parameters. 2775 * If they're not running, this will have no effect ... 2776 * 2777 * NOTE: this is currently disabled by default because stopping 2778 * and restarting the Tx engine may cause an outgoing packet in 2779 * transit to be truncated. Also, stopping and restarting the 2780 * Rx engine seems to not work correctly on the 5705. Testing 2781 * has not (yet!) revealed any problems with NOT stopping and 2782 * restarting these engines (and Broadcom say their drivers don't 2783 * do this), but if it is found to cause problems, this variable 2784 * can be patched to re-enable the old behaviour ... 2785 */ 2786 if (bge_stop_start_on_sync) { 2787 #ifdef BGE_IPMI_ASF 2788 if (!bgep->asf_enabled) { 2789 if (!bge_chip_disable_engine(bgep, 2790 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2791 retval = DDI_FAILURE; 2792 } else { 2793 if (!bge_chip_disable_engine(bgep, 2794 RECEIVE_MAC_MODE_REG, 0)) 2795 retval = DDI_FAILURE; 2796 } 2797 #else 2798 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2799 RECEIVE_MODE_KEEP_VLAN_TAG)) 2800 retval = DDI_FAILURE; 2801 #endif 2802 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2803 retval = DDI_FAILURE; 2804 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2805 retval = DDI_FAILURE; 2806 } 2807 2808 /* 2809 * Reprogram the hashed multicast address table ... 2810 */ 2811 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2812 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2813 2814 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2815 bge_reg_put32(bgep, MAC_HASH_REG(i), 2816 bgep->mcast_hash[i] | fill); 2817 2818 #ifdef BGE_IPMI_ASF 2819 if (!bgep->asf_enabled || !asf_keeplive) { 2820 #endif 2821 /* 2822 * Transform the MAC address(es) from host to chip format, then 2823 * reprogram the transmit random backoff seed and the unicast 2824 * MAC address(es) ... 2825 */ 2826 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2827 for (i = 0, fill = 0, macaddr = 0ull; 2828 i < ETHERADDRL; ++i) { 2829 macaddr <<= 8; 2830 macaddr |= bgep->curr_addr[j].addr[i]; 2831 fill += bgep->curr_addr[j].addr[i]; 2832 } 2833 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2834 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2835 } 2836 2837 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2838 (void *)bgep, macaddr)); 2839 #ifdef BGE_IPMI_ASF 2840 } 2841 #endif 2842 2843 /* 2844 * Set or clear the PROMISCUOUS mode bit 2845 */ 2846 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2847 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2848 2849 /* 2850 * Sync the rest of the MAC modes too ... 2851 */ 2852 bge_sync_mac_modes(bgep); 2853 2854 /* 2855 * Restart RX/TX MAC engines if required ... 2856 */ 2857 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2858 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2859 retval = DDI_FAILURE; 2860 #ifdef BGE_IPMI_ASF 2861 if (!bgep->asf_enabled) { 2862 if (!bge_chip_enable_engine(bgep, 2863 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2864 retval = DDI_FAILURE; 2865 } else { 2866 if (!bge_chip_enable_engine(bgep, 2867 RECEIVE_MAC_MODE_REG, 0)) 2868 retval = DDI_FAILURE; 2869 } 2870 #else 2871 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2872 RECEIVE_MODE_KEEP_VLAN_TAG)) 2873 retval = DDI_FAILURE; 2874 #endif 2875 } 2876 return (retval); 2877 } 2878 2879 /* 2880 * This array defines the sequence of state machine control registers 2881 * in which the <enable> bit must be cleared to bring the chip to a 2882 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2883 */ 2884 static bge_regno_t shutdown_engine_regs[] = { 2885 RECEIVE_MAC_MODE_REG, 2886 RCV_BD_INITIATOR_MODE_REG, 2887 RCV_LIST_PLACEMENT_MODE_REG, 2888 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2889 RCV_DATA_BD_INITIATOR_MODE_REG, 2890 RCV_DATA_COMPLETION_MODE_REG, 2891 RCV_BD_COMPLETION_MODE_REG, 2892 2893 SEND_BD_SELECTOR_MODE_REG, 2894 SEND_BD_INITIATOR_MODE_REG, 2895 SEND_DATA_INITIATOR_MODE_REG, 2896 READ_DMA_MODE_REG, 2897 SEND_DATA_COMPLETION_MODE_REG, 2898 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2899 SEND_BD_COMPLETION_MODE_REG, 2900 TRANSMIT_MAC_MODE_REG, 2901 2902 HOST_COALESCE_MODE_REG, 2903 WRITE_DMA_MODE_REG, 2904 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2905 FTQ_RESET_REG, /* special - see code */ 2906 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2907 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2908 BGE_REGNO_NONE /* terminator */ 2909 }; 2910 2911 #ifndef __sparc 2912 static bge_regno_t quiesce_regs[] = { 2913 READ_DMA_MODE_REG, 2914 DMA_COMPLETION_MODE_REG, 2915 WRITE_DMA_MODE_REG, 2916 BGE_REGNO_NONE 2917 }; 2918 2919 void bge_chip_stop_nonblocking(bge_t *bgep); 2920 #pragma no_inline(bge_chip_stop_nonblocking) 2921 2922 /* 2923 * This function is called by bge_quiesce(). We 2924 * turn off all the DMA engines here. 2925 */ 2926 void 2927 bge_chip_stop_nonblocking(bge_t *bgep) 2928 { 2929 bge_regno_t *rbp; 2930 2931 /* 2932 * Flag that no more activity may be initiated 2933 */ 2934 bgep->progress &= ~PROGRESS_READY; 2935 2936 rbp = quiesce_regs; 2937 while (*rbp != BGE_REGNO_NONE) { 2938 (void) bge_chip_disable_engine(bgep, *rbp, 0); 2939 ++rbp; 2940 } 2941 2942 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2943 } 2944 2945 #endif 2946 2947 /* 2948 * bge_chip_stop() -- stop all chip processing 2949 * 2950 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2951 * we've detected a problem internally; otherwise, this is a normal 2952 * (clean) stop (at user request i.e. the last STREAM has been closed). 2953 */ 2954 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2955 #pragma no_inline(bge_chip_stop) 2956 2957 void 2958 bge_chip_stop(bge_t *bgep, boolean_t fault) 2959 { 2960 bge_regno_t regno; 2961 bge_regno_t *rbp; 2962 boolean_t ok; 2963 2964 BGE_TRACE(("bge_chip_stop($%p)", 2965 (void *)bgep)); 2966 2967 ASSERT(mutex_owned(bgep->genlock)); 2968 2969 rbp = shutdown_engine_regs; 2970 /* 2971 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2972 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2973 * -ory arbiter should not be disabled. 2974 */ 2975 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2976 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2977 ok &= bge_chip_disable_engine(bgep, regno, 0); 2978 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2979 (regno != DMA_COMPLETION_MODE_REG) && 2980 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2981 (regno != BUFFER_MANAGER_MODE_REG) && 2982 (regno != MEMORY_ARBITER_MODE_REG)) 2983 ok &= bge_chip_disable_engine(bgep, 2984 regno, 0); 2985 } 2986 2987 if (!ok && !fault) 2988 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2989 2990 /* 2991 * Finally, disable (all) MAC events & clear the MAC status 2992 */ 2993 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2994 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2995 2996 /* 2997 * if we're stopping the chip because of a detected fault then do 2998 * appropriate actions 2999 */ 3000 if (fault) { 3001 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3002 bgep->bge_chip_state = BGE_CHIP_FAULT; 3003 if (!bgep->manual_reset) 3004 ddi_fm_service_impact(bgep->devinfo, 3005 DDI_SERVICE_LOST); 3006 if (bgep->bge_dma_error) { 3007 /* 3008 * need to free buffers in case the fault was 3009 * due to a memory error in a buffer - got to 3010 * do a fair bit of tidying first 3011 */ 3012 if (bgep->progress & PROGRESS_KSTATS) { 3013 bge_fini_kstats(bgep); 3014 bgep->progress &= ~PROGRESS_KSTATS; 3015 } 3016 if (bgep->progress & PROGRESS_INTR) { 3017 bge_intr_disable(bgep); 3018 rw_enter(bgep->errlock, RW_WRITER); 3019 bge_fini_rings(bgep); 3020 rw_exit(bgep->errlock); 3021 bgep->progress &= ~PROGRESS_INTR; 3022 } 3023 if (bgep->progress & PROGRESS_BUFS) { 3024 bge_free_bufs(bgep); 3025 bgep->progress &= ~PROGRESS_BUFS; 3026 } 3027 bgep->bge_dma_error = B_FALSE; 3028 } 3029 } 3030 } else 3031 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3032 } 3033 3034 /* 3035 * Poll for completion of chip's ROM firmware; also, at least on the 3036 * first time through, find and return the hardware MAC address, if any. 3037 */ 3038 static uint64_t bge_poll_firmware(bge_t *bgep); 3039 #pragma no_inline(bge_poll_firmware) 3040 3041 static uint64_t 3042 bge_poll_firmware(bge_t *bgep) 3043 { 3044 uint64_t magic; 3045 uint64_t mac; 3046 uint32_t gen, val; 3047 uint32_t i; 3048 3049 /* 3050 * Step 19: poll for firmware completion (GENCOMM port set 3051 * to the ones complement of T3_MAGIC_NUMBER). 3052 * 3053 * While we're at it, we also read the MAC address register; 3054 * at some stage the firmware will load this with the 3055 * factory-set value. 3056 * 3057 * When both the magic number and the MAC address are set, 3058 * we're done; but we impose a time limit of one second 3059 * (1000*1000us) in case the firmware fails in some fashion 3060 * or the SEEPROM that provides that MAC address isn't fitted. 3061 * 3062 * After the first time through (chip state != INITIAL), we 3063 * don't need the MAC address to be set (we've already got it 3064 * or not, from the first time), so we don't wait for it, but 3065 * we still have to wait for the T3_MAGIC_NUMBER. 3066 * 3067 * Note: the magic number is only a 32-bit quantity, but the NIC 3068 * memory is 64-bit (and big-endian) internally. Addressing the 3069 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3070 * it work correctly on both big- and little-endian hosts. 3071 */ 3072 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3073 MHCR_CHIP_ASIC_REV_5906) { 3074 for (i = 0; i < 1000; ++i) { 3075 drv_usecwait(1000); 3076 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3077 if (val & VCPU_INIT_DONE) 3078 break; 3079 } 3080 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3081 (void *)bgep, i)); 3082 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3083 } else { 3084 for (i = 0; i < 1000; ++i) { 3085 drv_usecwait(1000); 3086 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3087 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3088 drv_usecwait(100000); 3089 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3090 #ifdef BGE_IPMI_ASF 3091 if (!bgep->asf_enabled) { 3092 #endif 3093 if (gen != ~T3_MAGIC_NUMBER) 3094 continue; 3095 #ifdef BGE_IPMI_ASF 3096 } 3097 #endif 3098 if (mac != 0ULL) 3099 break; 3100 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3101 break; 3102 } 3103 } 3104 3105 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3106 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3107 (void *)bgep, gen, i)); 3108 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3109 mac, magic)); 3110 3111 return (mac); 3112 } 3113 3114 /* 3115 * Maximum times of trying to get the NVRAM access lock 3116 * by calling bge_nvmem_acquire() 3117 */ 3118 #define MAX_TRY_NVMEM_ACQUIRE 10000 3119 3120 #ifdef BGE_IPMI_ASF 3121 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3122 #else 3123 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3124 #endif 3125 #pragma no_inline(bge_chip_reset) 3126 3127 int 3128 #ifdef BGE_IPMI_ASF 3129 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3130 #else 3131 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3132 #endif 3133 { 3134 chip_id_t chipid; 3135 uint64_t mac; 3136 uint64_t magic; 3137 uint32_t modeflags; 3138 uint32_t mhcr; 3139 uint32_t sx0; 3140 uint32_t i, tries; 3141 #ifdef BGE_IPMI_ASF 3142 uint32_t mailbox; 3143 #endif 3144 int retval = DDI_SUCCESS; 3145 3146 BGE_TRACE(("bge_chip_reset($%p, %d)", 3147 (void *)bgep, enable_dma)); 3148 3149 ASSERT(mutex_owned(bgep->genlock)); 3150 3151 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3152 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3153 3154 /* 3155 * Do we need to stop the chip cleanly before resetting? 3156 */ 3157 switch (bgep->bge_chip_state) { 3158 default: 3159 _NOTE(NOTREACHED) 3160 return (DDI_FAILURE); 3161 3162 case BGE_CHIP_INITIAL: 3163 case BGE_CHIP_STOPPED: 3164 case BGE_CHIP_RESET: 3165 break; 3166 3167 case BGE_CHIP_RUNNING: 3168 case BGE_CHIP_ERROR: 3169 case BGE_CHIP_FAULT: 3170 bge_chip_stop(bgep, B_FALSE); 3171 break; 3172 } 3173 3174 #ifdef BGE_IPMI_ASF 3175 if (bgep->asf_enabled) { 3176 #ifdef __sparc 3177 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3178 MHCR_ENABLE_TAGGED_STATUS_MODE | 3179 MHCR_MASK_INTERRUPT_MODE | 3180 MHCR_MASK_PCI_INT_OUTPUT | 3181 MHCR_CLEAR_INTERRUPT_INTA | 3182 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3183 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3184 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3185 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3186 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3187 MEMORY_ARBITER_ENABLE); 3188 #endif 3189 if (asf_mode == ASF_MODE_INIT) { 3190 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3191 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3192 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3193 } 3194 } 3195 #endif 3196 /* 3197 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3198 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3199 * 3200 * Before reset Core clock,it is 3201 * also required to initialize the Memory Arbiter as specified in step9 3202 * and Misc Host Control Register as specified in step-13 3203 * Step 4-5: reset Core clock & wait for completion 3204 * Steps 6-8: are done by bge_chip_cfg_init() 3205 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3206 */ 3207 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3208 retval = DDI_FAILURE; 3209 3210 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3211 MHCR_ENABLE_TAGGED_STATUS_MODE | 3212 MHCR_MASK_INTERRUPT_MODE | 3213 MHCR_MASK_PCI_INT_OUTPUT | 3214 MHCR_CLEAR_INTERRUPT_INTA; 3215 #ifdef _BIG_ENDIAN 3216 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3217 #endif /* _BIG_ENDIAN */ 3218 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3219 #ifdef BGE_IPMI_ASF 3220 if (bgep->asf_enabled) 3221 bgep->asf_wordswapped = B_FALSE; 3222 #endif 3223 /* 3224 * NVRAM Corruption Workaround 3225 */ 3226 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3227 if (bge_nvmem_acquire(bgep) != EAGAIN) 3228 break; 3229 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3230 BGE_DEBUG(("%s: fail to acquire nvram lock", 3231 bgep->ifname)); 3232 3233 #ifdef BGE_IPMI_ASF 3234 if (!bgep->asf_enabled) { 3235 #endif 3236 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3237 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3238 #ifdef BGE_IPMI_ASF 3239 } 3240 #endif 3241 3242 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3243 retval = DDI_FAILURE; 3244 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3245 3246 /* 3247 * Step 8a: This may belong elsewhere, but BCM5721 needs 3248 * a bit set to avoid a fifo overflow/underflow bug. 3249 */ 3250 if ((bgep->chipid.chip_label == 5721) || 3251 (bgep->chipid.chip_label == 5751) || 3252 (bgep->chipid.chip_label == 5752) || 3253 (bgep->chipid.chip_label == 5755) || 3254 (bgep->chipid.chip_label == 5789) || 3255 (bgep->chipid.chip_label == 5906)) 3256 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3257 3258 3259 /* 3260 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3261 * not be changed. 3262 */ 3263 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3264 retval = DDI_FAILURE; 3265 3266 /* 3267 * Steps 10-11: configure PIO endianness options and 3268 * enable indirect register access -- already done 3269 * Steps 12-13: enable writing to the PCI state & clock 3270 * control registers -- not required; we aren't going to 3271 * use those features. 3272 * Steps 14-15: Configure DMA endianness options. See 3273 * the comments on the setting of the MHCR above. 3274 */ 3275 #ifdef _BIG_ENDIAN 3276 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3277 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3278 #else 3279 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3280 #endif /* _BIG_ENDIAN */ 3281 #ifdef BGE_IPMI_ASF 3282 if (bgep->asf_enabled) 3283 modeflags |= MODE_HOST_STACK_UP; 3284 #endif 3285 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3286 3287 #ifdef BGE_IPMI_ASF 3288 if (bgep->asf_enabled) { 3289 #ifdef __sparc 3290 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3291 MEMORY_ARBITER_ENABLE | 3292 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3293 #endif 3294 3295 #ifdef BGE_NETCONSOLE 3296 if (!bgep->asf_newhandshake) { 3297 if ((asf_mode == ASF_MODE_INIT) || 3298 (asf_mode == ASF_MODE_POST_INIT)) { 3299 bge_asf_post_reset_old_mode(bgep, 3300 BGE_INIT_RESET); 3301 } else { 3302 bge_asf_post_reset_old_mode(bgep, 3303 BGE_SHUTDOWN_RESET); 3304 } 3305 } 3306 #endif 3307 3308 /* Wait for NVRAM init */ 3309 i = 0; 3310 drv_usecwait(5000); 3311 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3312 3313 while ((mailbox != (uint32_t) 3314 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3315 (i < 10000)) { 3316 drv_usecwait(100); 3317 mailbox = bge_nic_get32(bgep, 3318 BGE_FIRMWARE_MAILBOX); 3319 i++; 3320 } 3321 3322 #ifndef BGE_NETCONSOLE 3323 if (!bgep->asf_newhandshake) { 3324 if ((asf_mode == ASF_MODE_INIT) || 3325 (asf_mode == ASF_MODE_POST_INIT)) { 3326 3327 bge_asf_post_reset_old_mode(bgep, 3328 BGE_INIT_RESET); 3329 } else { 3330 bge_asf_post_reset_old_mode(bgep, 3331 BGE_SHUTDOWN_RESET); 3332 } 3333 } 3334 #endif 3335 } 3336 #endif 3337 /* 3338 * Steps 16-17: poll for firmware completion 3339 */ 3340 mac = bge_poll_firmware(bgep); 3341 3342 /* 3343 * Step 18: enable external memory -- doesn't apply. 3344 * 3345 * However we take the opportunity to set the MLCR anyway, as 3346 * this register also controls the SEEPROM auto-access method 3347 * which we may want to use later ... 3348 * 3349 * The proper value here depends on the way the chip is wired 3350 * into the circuit board, as this register *also* controls which 3351 * of the "Miscellaneous I/O" pins are driven as outputs and the 3352 * values driven onto those pins! 3353 * 3354 * See also step 74 in the PRM ... 3355 */ 3356 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3357 bgep->chipid.bge_mlcr_default); 3358 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3359 3360 /* 3361 * Step 20: clear the Ethernet MAC mode register 3362 */ 3363 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3364 3365 /* 3366 * Step 21: restore cache-line-size, latency timer, and 3367 * subsystem ID registers to their original values (not 3368 * those read into the local structure <chipid>, 'cos 3369 * that was after they were cleared by the RESET). 3370 * 3371 * Note: the Subsystem Vendor/Device ID registers are not 3372 * directly writable in config space, so we use the shadow 3373 * copy in "Page Zero" of register space to restore them 3374 * both in one go ... 3375 */ 3376 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3377 bgep->chipid.clsize); 3378 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3379 bgep->chipid.latency); 3380 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3381 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3382 3383 /* 3384 * The SEND INDEX registers should be reset to zero by the 3385 * global chip reset; if they're not, there'll be trouble 3386 * later on. 3387 */ 3388 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3389 if (sx0 != 0) { 3390 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3391 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3392 retval = DDI_FAILURE; 3393 } 3394 3395 /* Enable MSI code */ 3396 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3397 bge_reg_set32(bgep, MSI_MODE_REG, 3398 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3399 3400 /* 3401 * On the first time through, save the factory-set MAC address 3402 * (if any). If bge_poll_firmware() above didn't return one 3403 * (from a chip register) consider looking in the attached NV 3404 * memory device, if any. Once we have it, we save it in both 3405 * register-image (64-bit) and byte-array forms. All-zero and 3406 * all-one addresses are not valid, and we refuse to stash those. 3407 */ 3408 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3409 if (mac == 0ULL) 3410 mac = bge_get_nvmac(bgep); 3411 if (mac != 0ULL && mac != ~0ULL) { 3412 bgep->chipid.hw_mac_addr = mac; 3413 for (i = ETHERADDRL; i-- != 0; ) { 3414 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3415 mac >>= 8; 3416 } 3417 bgep->chipid.vendor_addr.set = B_TRUE; 3418 } 3419 } 3420 3421 #ifdef BGE_IPMI_ASF 3422 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3423 if (asf_mode != ASF_MODE_NONE) { 3424 if ((asf_mode == ASF_MODE_INIT) || 3425 (asf_mode == ASF_MODE_POST_INIT)) { 3426 3427 bge_asf_post_reset_new_mode(bgep, 3428 BGE_INIT_RESET); 3429 } else { 3430 bge_asf_post_reset_new_mode(bgep, 3431 BGE_SHUTDOWN_RESET); 3432 } 3433 } 3434 } 3435 #endif 3436 3437 /* 3438 * Record the new state 3439 */ 3440 bgep->chip_resets += 1; 3441 bgep->bge_chip_state = BGE_CHIP_RESET; 3442 return (retval); 3443 } 3444 3445 /* 3446 * bge_chip_start() -- start the chip transmitting and/or receiving, 3447 * including enabling interrupts 3448 */ 3449 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3450 #pragma no_inline(bge_chip_start) 3451 3452 int 3453 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3454 { 3455 uint32_t coalmode; 3456 uint32_t ledctl; 3457 uint32_t mtu; 3458 uint32_t maxring; 3459 uint32_t stats_mask; 3460 uint32_t dma_wrprio; 3461 uint64_t ring; 3462 int retval = DDI_SUCCESS; 3463 3464 BGE_TRACE(("bge_chip_start($%p)", 3465 (void *)bgep)); 3466 3467 ASSERT(mutex_owned(bgep->genlock)); 3468 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3469 3470 /* 3471 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3472 * The document specifies 95 separate steps to fully 3473 * initialise the chip!!!! 3474 * 3475 * The reset code above has already got us as far as step 3476 * 21, so we continue with ... 3477 * 3478 * Step 22: clear the MAC statistics block 3479 * (0x0300-0x0aff in NIC-local memory) 3480 */ 3481 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3482 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3483 NIC_MEM_STATISTICS_SIZE); 3484 3485 /* 3486 * Step 23: clear the status block (in host memory) 3487 */ 3488 DMA_ZERO(bgep->status_block); 3489 3490 /* 3491 * Step 24: set DMA read/write control register 3492 */ 3493 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3494 bgep->chipid.bge_dma_rwctrl); 3495 3496 /* 3497 * Step 25: Configure DMA endianness -- already done (16/17) 3498 * Step 26: Configure Host-Based Send Rings 3499 * Step 27: Indicate Host Stack Up 3500 */ 3501 bge_reg_set32(bgep, MODE_CONTROL_REG, 3502 MODE_HOST_SEND_BDS | 3503 MODE_HOST_STACK_UP); 3504 3505 /* 3506 * Step 28: Configure checksum options: 3507 * Solaris supports the hardware default checksum options. 3508 * 3509 * Workaround for Incorrect pseudo-header checksum calculation. 3510 */ 3511 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3512 bge_reg_set32(bgep, MODE_CONTROL_REG, 3513 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3514 3515 /* 3516 * Step 29: configure Timer Prescaler. The value is always the 3517 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3518 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3519 * for the whole chip! 3520 */ 3521 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3522 3523 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3524 drv_usecwait(40); 3525 /* put PHY into ready state */ 3526 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3527 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3528 drv_usecwait(40); 3529 } 3530 3531 /* 3532 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3533 * 3534 * If the mbuf_length is specified as 0, we just leave these at 3535 * their hardware defaults, rather than explicitly setting them. 3536 * As the Broadcom HRM,driver better not change the parameters 3537 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3538 */ 3539 if ((bgep->chipid.mbuf_length != 0) && 3540 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3541 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3542 bgep->chipid.mbuf_base); 3543 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3544 bgep->chipid.mbuf_length); 3545 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3546 DMAD_POOL_BASE_DEFAULT); 3547 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3548 DMAD_POOL_LENGTH_DEFAULT); 3549 } 3550 3551 /* 3552 * Step 32: configure MAC memory pool watermarks 3553 */ 3554 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3555 bgep->chipid.mbuf_lo_water_rdma); 3556 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3557 bgep->chipid.mbuf_lo_water_rmac); 3558 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3559 bgep->chipid.mbuf_hi_water); 3560 3561 /* 3562 * Step 33: configure DMA resource watermarks 3563 */ 3564 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3565 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3566 bge_dmad_lo_water); 3567 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3568 bge_dmad_hi_water); 3569 } 3570 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3571 3572 /* 3573 * Steps 34-36: enable buffer manager & internal h/w queues 3574 */ 3575 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3576 STATE_MACHINE_ATTN_ENABLE_BIT)) 3577 retval = DDI_FAILURE; 3578 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3579 retval = DDI_FAILURE; 3580 3581 /* 3582 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3583 */ 3584 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3585 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3586 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3587 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3588 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3589 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3590 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3591 } 3592 3593 /* 3594 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3595 */ 3596 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3597 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3598 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3599 bge_replenish_jumbo); 3600 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3601 bge_replenish_mini); 3602 } 3603 3604 /* 3605 * Steps 41-43: clear Send Ring Producer Indices and initialise 3606 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3607 */ 3608 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3609 maxring = BGE_SEND_RINGS_MAX; 3610 else 3611 maxring = BGE_SEND_RINGS_MAX_5705; 3612 for (ring = 0; ring < maxring; ++ring) { 3613 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3614 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3615 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3616 &bgep->send[ring].hw_rcb); 3617 } 3618 3619 /* 3620 * Steps 44-45: initialise Receive Return Rings 3621 * (0x0200-0x02ff in NIC-local memory) 3622 */ 3623 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3624 maxring = BGE_RECV_RINGS_MAX; 3625 else 3626 maxring = BGE_RECV_RINGS_MAX_5705; 3627 for (ring = 0; ring < maxring; ++ring) 3628 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3629 &bgep->recv[ring].hw_rcb); 3630 3631 /* 3632 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3633 */ 3634 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3635 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3636 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3637 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3638 } 3639 /* 3640 * Step 47: configure the MAC unicast address 3641 * Step 48: configure the random backoff seed 3642 * Step 96: set up multicast filters 3643 */ 3644 #ifdef BGE_IPMI_ASF 3645 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3646 #else 3647 if (bge_chip_sync(bgep) == DDI_FAILURE) 3648 #endif 3649 retval = DDI_FAILURE; 3650 3651 /* 3652 * Step 49: configure the MTU 3653 */ 3654 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3655 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3656 3657 /* 3658 * Step 50: configure the IPG et al 3659 */ 3660 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3661 3662 /* 3663 * Step 51: configure the default Rx Return Ring 3664 */ 3665 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3666 3667 /* 3668 * Steps 52-54: configure Receive List Placement, 3669 * and enable Receive List Placement Statistics 3670 */ 3671 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3672 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3673 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3674 case MHCR_CHIP_ASIC_REV_5700: 3675 case MHCR_CHIP_ASIC_REV_5701: 3676 case MHCR_CHIP_ASIC_REV_5703: 3677 case MHCR_CHIP_ASIC_REV_5704: 3678 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3679 break; 3680 case MHCR_CHIP_ASIC_REV_5705: 3681 break; 3682 default: 3683 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3684 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3685 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3686 break; 3687 } 3688 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3689 3690 if (bgep->chipid.rx_rings > 1) 3691 bge_init_recv_rule(bgep); 3692 3693 /* 3694 * Steps 55-56: enable Send Data Initiator Statistics 3695 */ 3696 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3697 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3698 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3699 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3700 } else { 3701 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3702 SEND_INIT_STATS_ENABLE); 3703 } 3704 /* 3705 * Steps 57-58: stop (?) the Host Coalescing Engine 3706 */ 3707 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3708 retval = DDI_FAILURE; 3709 3710 /* 3711 * Steps 59-62: initialise Host Coalescing parameters 3712 */ 3713 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3714 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3715 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3716 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3717 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3718 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3719 bge_tx_count_intr); 3720 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3721 bge_tx_ticks_intr); 3722 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3723 bge_rx_count_intr); 3724 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3725 bge_rx_ticks_intr); 3726 } 3727 3728 /* 3729 * Steps 63-64: initialise status block & statistics 3730 * host memory addresses 3731 * The statistic block does not exist in some chipsets 3732 * Step 65: initialise Statistics Coalescing Tick Counter 3733 */ 3734 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3735 bgep->status_block.cookie.dmac_laddress); 3736 3737 /* 3738 * Steps 66-67: initialise status block & statistics 3739 * NIC-local memory addresses 3740 */ 3741 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3742 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3743 bgep->statistics.cookie.dmac_laddress); 3744 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3745 STATISTICS_TICKS_DEFAULT); 3746 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3747 NIC_MEM_STATUS_BLOCK); 3748 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3749 NIC_MEM_STATISTICS); 3750 } 3751 3752 /* 3753 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3754 * Completion Engine, the Receive List Placement Engine, and the 3755 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3756 * and BCM5715. 3757 */ 3758 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3759 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3760 coalmode = COALESCE_64_BYTE_STATUS; 3761 else 3762 coalmode = 0; 3763 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3764 retval = DDI_FAILURE; 3765 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3766 STATE_MACHINE_ATTN_ENABLE_BIT)) 3767 retval = DDI_FAILURE; 3768 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3769 retval = DDI_FAILURE; 3770 3771 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3772 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3773 STATE_MACHINE_ATTN_ENABLE_BIT)) 3774 retval = DDI_FAILURE; 3775 3776 /* 3777 * Step 72: Enable MAC DMA engines 3778 * Step 73: Clear & enable MAC statistics 3779 */ 3780 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3781 ETHERNET_MODE_ENABLE_FHDE | 3782 ETHERNET_MODE_ENABLE_RDE | 3783 ETHERNET_MODE_ENABLE_TDE); 3784 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3785 ETHERNET_MODE_ENABLE_TX_STATS | 3786 ETHERNET_MODE_ENABLE_RX_STATS | 3787 ETHERNET_MODE_CLEAR_TX_STATS | 3788 ETHERNET_MODE_CLEAR_RX_STATS); 3789 3790 /* 3791 * Step 74: configure the MLCR (Miscellaneous Local Control 3792 * Register); not required, as we set up the MLCR in step 10 3793 * (part of the reset code) above. 3794 * 3795 * Step 75: clear Interrupt Mailbox 0 3796 */ 3797 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3798 3799 /* 3800 * Steps 76-87: Gentlemen, start your engines ... 3801 * 3802 * Enable the DMA Completion Engine, the Write DMA Engine, 3803 * the Read DMA Engine, Receive Data Completion Engine, 3804 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3805 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3806 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3807 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3808 * 3809 * Beware exhaust fumes? 3810 */ 3811 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3812 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3813 retval = DDI_FAILURE; 3814 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3815 ALL_DMA_ATTN_BITS; 3816 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3817 MHCR_CHIP_ASIC_REV_5755) || 3818 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3819 MHCR_CHIP_ASIC_REV_5906)) { 3820 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3821 } 3822 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3823 dma_wrprio)) 3824 retval = DDI_FAILURE; 3825 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3826 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3827 retval = DDI_FAILURE; 3828 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3829 STATE_MACHINE_ATTN_ENABLE_BIT)) 3830 retval = DDI_FAILURE; 3831 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3832 if (!bge_chip_enable_engine(bgep, 3833 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3834 retval = DDI_FAILURE; 3835 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3836 retval = DDI_FAILURE; 3837 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3838 STATE_MACHINE_ATTN_ENABLE_BIT)) 3839 retval = DDI_FAILURE; 3840 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3841 RCV_BD_DISABLED_RING_ATTN)) 3842 retval = DDI_FAILURE; 3843 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3844 RCV_DATA_BD_ILL_RING_ATTN)) 3845 retval = DDI_FAILURE; 3846 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3847 retval = DDI_FAILURE; 3848 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3849 STATE_MACHINE_ATTN_ENABLE_BIT)) 3850 retval = DDI_FAILURE; 3851 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3852 STATE_MACHINE_ATTN_ENABLE_BIT)) 3853 retval = DDI_FAILURE; 3854 3855 /* 3856 * Step 88: download firmware -- doesn't apply 3857 * Steps 89-90: enable Transmit & Receive MAC Engines 3858 */ 3859 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3860 retval = DDI_FAILURE; 3861 #ifdef BGE_IPMI_ASF 3862 if (!bgep->asf_enabled) { 3863 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3864 RECEIVE_MODE_KEEP_VLAN_TAG)) 3865 retval = DDI_FAILURE; 3866 } else { 3867 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3868 retval = DDI_FAILURE; 3869 } 3870 #else 3871 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3872 RECEIVE_MODE_KEEP_VLAN_TAG)) 3873 retval = DDI_FAILURE; 3874 #endif 3875 3876 /* 3877 * Step 91: disable auto-polling of PHY status 3878 */ 3879 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3880 3881 /* 3882 * Step 92: configure D0 power state (not required) 3883 * Step 93: initialise LED control register () 3884 */ 3885 ledctl = LED_CONTROL_DEFAULT; 3886 switch (bgep->chipid.device) { 3887 case DEVICE_ID_5700: 3888 case DEVICE_ID_5700x: 3889 case DEVICE_ID_5701: 3890 /* 3891 * Switch to 5700 (MAC) mode on these older chips 3892 */ 3893 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3894 ledctl |= LED_CONTROL_LED_MODE_5700; 3895 break; 3896 3897 default: 3898 break; 3899 } 3900 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3901 3902 /* 3903 * Step 94: activate link 3904 */ 3905 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3906 3907 /* 3908 * Step 95: set up physical layer (PHY/SerDes) 3909 * restart autoneg (if required) 3910 */ 3911 if (reset_phys) 3912 if (bge_phys_update(bgep) == DDI_FAILURE) 3913 retval = DDI_FAILURE; 3914 3915 /* 3916 * Extra step (DSG): hand over all the Receive Buffers to the chip 3917 */ 3918 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3919 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3920 bgep->buff[ring].rf_next); 3921 3922 /* 3923 * MSI bits:The least significant MSI 16-bit word. 3924 * ISR will be triggered different. 3925 */ 3926 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3927 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3928 3929 /* 3930 * Extra step (DSG): select which interrupts are enabled 3931 * 3932 * Program the Ethernet MAC engine to signal attention on 3933 * Link Change events, then enable interrupts on MAC, DMA, 3934 * and FLOW attention signals. 3935 */ 3936 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3937 ETHERNET_EVENT_LINK_INT | 3938 ETHERNET_STATUS_PCS_ERROR_INT); 3939 #ifdef BGE_IPMI_ASF 3940 if (bgep->asf_enabled) { 3941 bge_reg_set32(bgep, MODE_CONTROL_REG, 3942 MODE_INT_ON_FLOW_ATTN | 3943 MODE_INT_ON_DMA_ATTN | 3944 MODE_HOST_STACK_UP| 3945 MODE_INT_ON_MAC_ATTN); 3946 } else { 3947 #endif 3948 bge_reg_set32(bgep, MODE_CONTROL_REG, 3949 MODE_INT_ON_FLOW_ATTN | 3950 MODE_INT_ON_DMA_ATTN | 3951 MODE_INT_ON_MAC_ATTN); 3952 #ifdef BGE_IPMI_ASF 3953 } 3954 #endif 3955 3956 /* 3957 * Step 97: enable PCI interrupts!!! 3958 */ 3959 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3960 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3961 MHCR_MASK_PCI_INT_OUTPUT); 3962 3963 /* 3964 * All done! 3965 */ 3966 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3967 return (retval); 3968 } 3969 3970 3971 /* 3972 * ========== Hardware interrupt handler ========== 3973 */ 3974 3975 #undef BGE_DBG 3976 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3977 3978 /* 3979 * Sync the status block, then atomically clear the specified bits in 3980 * the <flags-and-tag> field of the status block. 3981 * the <flags> word of the status block, returning the value of the 3982 * <tag> and the <flags> before the bits were cleared. 3983 */ 3984 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3985 #pragma inline(bge_status_sync) 3986 3987 static int 3988 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3989 { 3990 bge_status_t *bsp; 3991 int retval; 3992 3993 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3994 (void *)bgep, bits)); 3995 3996 ASSERT(bgep->bge_guard == BGE_GUARD); 3997 3998 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3999 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4000 if (retval != DDI_FM_OK) 4001 return (retval); 4002 4003 bsp = DMA_VPTR(bgep->status_block); 4004 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4005 4006 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4007 (void *)bgep, bits, *flags)); 4008 4009 return (retval); 4010 } 4011 4012 void bge_wake_factotum(bge_t *bgep); 4013 #pragma inline(bge_wake_factotum) 4014 4015 void 4016 bge_wake_factotum(bge_t *bgep) 4017 { 4018 mutex_enter(bgep->softintrlock); 4019 if (bgep->factotum_flag == 0) { 4020 bgep->factotum_flag = 1; 4021 ddi_trigger_softintr(bgep->factotum_id); 4022 } 4023 mutex_exit(bgep->softintrlock); 4024 } 4025 4026 /* 4027 * bge_intr() -- handle chip interrupts 4028 */ 4029 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4030 #pragma no_inline(bge_intr) 4031 4032 uint_t 4033 bge_intr(caddr_t arg1, caddr_t arg2) 4034 { 4035 bge_t *bgep = (void *)arg1; /* private device info */ 4036 bge_status_t *bsp; 4037 uint64_t flags; 4038 uint32_t regval; 4039 uint_t result; 4040 int retval, loop_cnt = 0; 4041 4042 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4043 4044 /* 4045 * GLD v2 checks that s/w setup is complete before passing 4046 * interrupts to this routine, thus eliminating the old 4047 * (and well-known) race condition around ddi_add_intr() 4048 */ 4049 ASSERT(bgep->progress & PROGRESS_HWINT); 4050 4051 result = DDI_INTR_UNCLAIMED; 4052 mutex_enter(bgep->genlock); 4053 4054 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4055 /* 4056 * Check whether chip's says it's asserting #INTA; 4057 * if not, don't process or claim the interrupt. 4058 * 4059 * Note that the PCI signal is active low, so the 4060 * bit is *zero* when the interrupt is asserted. 4061 */ 4062 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4063 if (regval & MLCR_INTA_STATE) { 4064 if (bge_check_acc_handle(bgep, bgep->io_handle) 4065 != DDI_FM_OK) 4066 goto chip_stop; 4067 mutex_exit(bgep->genlock); 4068 return (result); 4069 } 4070 4071 /* 4072 * Block further PCI interrupts ... 4073 */ 4074 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4075 MHCR_MASK_PCI_INT_OUTPUT); 4076 4077 } else { 4078 /* 4079 * Check MSI status 4080 */ 4081 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4082 if (regval & MSI_ERROR_ATTENTION) { 4083 BGE_REPORT((bgep, "msi error attention," 4084 " status=0x%x", regval)); 4085 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4086 } 4087 } 4088 4089 result = DDI_INTR_CLAIMED; 4090 4091 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4092 4093 /* 4094 * Sync the status block and grab the flags-n-tag from it. 4095 * We count the number of interrupts where there doesn't 4096 * seem to have been a DMA update of the status block; if 4097 * it *has* been updated, the counter will be cleared in 4098 * the while() loop below ... 4099 */ 4100 bgep->missed_dmas += 1; 4101 bsp = DMA_VPTR(bgep->status_block); 4102 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4103 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4104 /* 4105 * bge_chip_stop() may have freed dma area etc 4106 * while we were in this interrupt handler - 4107 * better not call bge_status_sync() 4108 */ 4109 (void) bge_check_acc_handle(bgep, 4110 bgep->io_handle); 4111 mutex_exit(bgep->genlock); 4112 return (DDI_INTR_CLAIMED); 4113 } 4114 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4115 &flags); 4116 if (retval != DDI_FM_OK) { 4117 bgep->bge_dma_error = B_TRUE; 4118 goto chip_stop; 4119 } 4120 4121 if (!(flags & STATUS_FLAG_UPDATED)) 4122 break; 4123 4124 /* 4125 * Tell the chip that we're processing the interrupt 4126 */ 4127 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4128 INTERRUPT_MBOX_DISABLE(flags)); 4129 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4130 DDI_FM_OK) 4131 goto chip_stop; 4132 4133 /* 4134 * Drop the mutex while we: 4135 * Receive any newly-arrived packets 4136 * Recycle any newly-finished send buffers 4137 */ 4138 bgep->bge_intr_running = B_TRUE; 4139 mutex_exit(bgep->genlock); 4140 bge_receive(bgep, bsp); 4141 bge_recycle(bgep, bsp); 4142 mutex_enter(bgep->genlock); 4143 bgep->bge_intr_running = B_FALSE; 4144 4145 /* 4146 * Tell the chip we've finished processing, and 4147 * give it the tag that we got from the status 4148 * block earlier, so that it knows just how far 4149 * we've gone. If it's got more for us to do, 4150 * it will now update the status block and try 4151 * to assert an interrupt (but we've got the 4152 * #INTA blocked at present). If we see the 4153 * update, we'll loop around to do some more. 4154 * Eventually we'll get out of here ... 4155 */ 4156 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4157 INTERRUPT_MBOX_ENABLE(flags)); 4158 if (bgep->chipid.pci_type == BGE_PCI_E) 4159 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4160 bgep->missed_dmas = 0; 4161 } 4162 4163 /* 4164 * Check for exceptional conditions that we need to handle 4165 * 4166 * Link status changed 4167 * Status block not updated 4168 */ 4169 if (flags & STATUS_FLAG_LINK_CHANGED) 4170 bge_wake_factotum(bgep); 4171 4172 if (bgep->missed_dmas) { 4173 /* 4174 * Probably due to the internal status tag not 4175 * being reset. Force a status block update now; 4176 * this should ensure that we get an update and 4177 * a new interrupt. After that, we should be in 4178 * sync again ... 4179 */ 4180 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4181 "not updated?", flags)); 4182 bgep->missed_updates++; 4183 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4184 COALESCE_NOW); 4185 4186 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4187 /* 4188 * If this happens multiple times in a row, 4189 * it means DMA is just not working. Maybe 4190 * the chip's failed, or maybe there's a 4191 * problem on the PCI bus or in the host-PCI 4192 * bridge (Tomatillo). 4193 * 4194 * At all events, we want to stop further 4195 * interrupts and let the recovery code take 4196 * over to see whether anything can be done 4197 * about it ... 4198 */ 4199 bge_fm_ereport(bgep, 4200 DDI_FM_DEVICE_BADINT_LIMIT); 4201 goto chip_stop; 4202 } 4203 } 4204 4205 /* 4206 * Reenable assertion of #INTA, unless there's a DMA fault 4207 */ 4208 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4209 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4210 MHCR_MASK_PCI_INT_OUTPUT); 4211 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4212 DDI_FM_OK) 4213 goto chip_stop; 4214 } 4215 4216 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4217 goto chip_stop; 4218 4219 mutex_exit(bgep->genlock); 4220 return (result); 4221 4222 chip_stop: 4223 #ifdef BGE_IPMI_ASF 4224 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4225 /* 4226 * We must stop ASF heart beat before 4227 * bge_chip_stop(), otherwise some 4228 * computers (ex. IBM HS20 blade 4229 * server) may crash. 4230 */ 4231 bge_asf_update_status(bgep); 4232 bge_asf_stop_timer(bgep); 4233 bgep->asf_status = ASF_STAT_STOP; 4234 4235 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4236 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4237 } 4238 #endif 4239 bge_chip_stop(bgep, B_TRUE); 4240 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4241 mutex_exit(bgep->genlock); 4242 return (result); 4243 } 4244 4245 /* 4246 * ========== Factotum, implemented as a softint handler ========== 4247 */ 4248 4249 #undef BGE_DBG 4250 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4251 4252 static void bge_factotum_error_handler(bge_t *bgep); 4253 #pragma no_inline(bge_factotum_error_handler) 4254 4255 static void 4256 bge_factotum_error_handler(bge_t *bgep) 4257 { 4258 uint32_t flow; 4259 uint32_t rdma; 4260 uint32_t wdma; 4261 uint32_t tmac; 4262 uint32_t rmac; 4263 uint32_t rxrs; 4264 uint32_t txrs = 0; 4265 4266 ASSERT(mutex_owned(bgep->genlock)); 4267 4268 /* 4269 * Read all the registers that show the possible 4270 * reasons for the ERROR bit to be asserted 4271 */ 4272 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4273 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4274 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4275 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4276 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4277 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4278 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4279 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4280 4281 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4282 (void *)bgep, flow, rdma, wdma)); 4283 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4284 (void *)bgep, tmac, rmac, rxrs, txrs)); 4285 4286 /* 4287 * For now, just clear all the errors ... 4288 */ 4289 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4290 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4291 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4292 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4293 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4294 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4295 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4296 } 4297 4298 /* 4299 * Handler for hardware link state change. 4300 * 4301 * When this routine is called, the hardware link state has changed 4302 * and the new state is reflected in the param_* variables. Here 4303 * we must update the softstate and reprogram the MAC to match. 4304 */ 4305 static void bge_factotum_link_handler(bge_t *bgep); 4306 #pragma no_inline(bge_factotum_link_handler) 4307 4308 static void 4309 bge_factotum_link_handler(bge_t *bgep) 4310 { 4311 ASSERT(mutex_owned(bgep->genlock)); 4312 4313 /* 4314 * Update the s/w link_state 4315 */ 4316 if (bgep->param_link_up) 4317 bgep->link_state = LINK_STATE_UP; 4318 else 4319 bgep->link_state = LINK_STATE_DOWN; 4320 4321 /* 4322 * Reprogram the MAC modes to match 4323 */ 4324 bge_sync_mac_modes(bgep); 4325 } 4326 4327 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4328 #pragma no_inline(bge_factotum_link_check) 4329 4330 static boolean_t 4331 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4332 { 4333 boolean_t check; 4334 uint64_t flags; 4335 uint32_t tmac_status; 4336 4337 ASSERT(mutex_owned(bgep->genlock)); 4338 4339 /* 4340 * Get & clear the writable status bits in the Tx status register 4341 * (some bits are write-1-to-clear, others are just readonly). 4342 */ 4343 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4344 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4345 4346 /* 4347 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4348 */ 4349 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4350 STATUS_FLAG_LINK_CHANGED, &flags); 4351 if (*dma_state != DDI_FM_OK) 4352 return (B_FALSE); 4353 4354 /* 4355 * Clear any errors flagged in the status block ... 4356 */ 4357 if (flags & STATUS_FLAG_ERROR) 4358 bge_factotum_error_handler(bgep); 4359 4360 /* 4361 * We need to check the link status if: 4362 * the status block says there's been a link change 4363 * or there's any discrepancy between the various 4364 * flags indicating the link state (link_state, 4365 * param_link_up, and the LINK STATE bit in the 4366 * Transmit MAC status register). 4367 */ 4368 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4369 switch (bgep->link_state) { 4370 case LINK_STATE_UP: 4371 check |= (bgep->param_link_up == B_FALSE); 4372 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4373 break; 4374 4375 case LINK_STATE_DOWN: 4376 check |= (bgep->param_link_up != B_FALSE); 4377 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4378 break; 4379 4380 default: 4381 check = B_TRUE; 4382 break; 4383 } 4384 4385 /* 4386 * If <check> is false, we're sure the link hasn't changed. 4387 * If true, however, it's not yet definitive; we have to call 4388 * bge_phys_check() to determine whether the link has settled 4389 * into a new state yet ... and if it has, then call the link 4390 * state change handler.But when the chip is 5700 in Dell 6650 4391 * ,even if check is false, the link may have changed.So we 4392 * have to call bge_phys_check() to determine the link state. 4393 */ 4394 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4395 check = bge_phys_check(bgep); 4396 if (check) 4397 bge_factotum_link_handler(bgep); 4398 } 4399 4400 return (check); 4401 } 4402 4403 /* 4404 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4405 */ 4406 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4407 #pragma no_inline(bge_factotum_stall_check) 4408 4409 static boolean_t 4410 bge_factotum_stall_check(bge_t *bgep) 4411 { 4412 uint32_t dogval; 4413 4414 ASSERT(mutex_owned(bgep->genlock)); 4415 4416 /* 4417 * Specific check for Tx stall ... 4418 * 4419 * The 'watchdog' counter is incremented whenever a packet 4420 * is queued, reset to 1 when some (but not all) buffers 4421 * are reclaimed, reset to 0 (disabled) when all buffers 4422 * are reclaimed, and shifted left here. If it exceeds the 4423 * threshold value, the chip is assumed to have stalled and 4424 * is put into the ERROR state. The factotum will then reset 4425 * it on the next pass. 4426 * 4427 * All of which should ensure that we don't get into a state 4428 * where packets are left pending indefinitely! 4429 */ 4430 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4431 if (dogval < bge_watchdog_count) 4432 return (B_FALSE); 4433 4434 #if !defined(BGE_NETCONSOLE) 4435 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4436 #endif 4437 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4438 return (B_TRUE); 4439 } 4440 4441 /* 4442 * The factotum is woken up when there's something to do that we'd rather 4443 * not do from inside a hardware interrupt handler or high-level cyclic. 4444 * Its two main tasks are: 4445 * reset & restart the chip after an error 4446 * check the link status whenever necessary 4447 */ 4448 uint_t bge_chip_factotum(caddr_t arg); 4449 #pragma no_inline(bge_chip_factotum) 4450 4451 uint_t 4452 bge_chip_factotum(caddr_t arg) 4453 { 4454 bge_t *bgep; 4455 uint_t result; 4456 boolean_t error; 4457 boolean_t linkchg; 4458 int dma_state; 4459 4460 bgep = (void *)arg; 4461 4462 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4463 4464 mutex_enter(bgep->softintrlock); 4465 if (bgep->factotum_flag == 0) { 4466 mutex_exit(bgep->softintrlock); 4467 return (DDI_INTR_UNCLAIMED); 4468 } 4469 bgep->factotum_flag = 0; 4470 mutex_exit(bgep->softintrlock); 4471 4472 result = DDI_INTR_CLAIMED; 4473 error = B_FALSE; 4474 linkchg = B_FALSE; 4475 4476 mutex_enter(bgep->genlock); 4477 switch (bgep->bge_chip_state) { 4478 default: 4479 break; 4480 4481 case BGE_CHIP_RUNNING: 4482 linkchg = bge_factotum_link_check(bgep, &dma_state); 4483 error = bge_factotum_stall_check(bgep); 4484 if (dma_state != DDI_FM_OK) { 4485 bgep->bge_dma_error = B_TRUE; 4486 error = B_TRUE; 4487 } 4488 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4489 error = B_TRUE; 4490 if (error) 4491 bgep->bge_chip_state = BGE_CHIP_ERROR; 4492 break; 4493 4494 case BGE_CHIP_ERROR: 4495 error = B_TRUE; 4496 break; 4497 4498 case BGE_CHIP_FAULT: 4499 /* 4500 * Fault detected, time to reset ... 4501 */ 4502 if (bge_autorecover) { 4503 if (!(bgep->progress & PROGRESS_BUFS)) { 4504 /* 4505 * if we can't allocate the ring buffers, 4506 * try later 4507 */ 4508 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4509 mutex_exit(bgep->genlock); 4510 return (result); 4511 } 4512 bgep->progress |= PROGRESS_BUFS; 4513 } 4514 if (!(bgep->progress & PROGRESS_INTR)) { 4515 bge_init_rings(bgep); 4516 bge_intr_enable(bgep); 4517 bgep->progress |= PROGRESS_INTR; 4518 } 4519 if (!(bgep->progress & PROGRESS_KSTATS)) { 4520 bge_init_kstats(bgep, 4521 ddi_get_instance(bgep->devinfo)); 4522 bgep->progress |= PROGRESS_KSTATS; 4523 } 4524 4525 BGE_REPORT((bgep, "automatic recovery activated")); 4526 4527 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4528 bgep->bge_chip_state = BGE_CHIP_ERROR; 4529 error = B_TRUE; 4530 } 4531 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4532 DDI_FM_OK) { 4533 bgep->bge_chip_state = BGE_CHIP_ERROR; 4534 error = B_TRUE; 4535 } 4536 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4537 DDI_FM_OK) { 4538 bgep->bge_chip_state = BGE_CHIP_ERROR; 4539 error = B_TRUE; 4540 } 4541 if (error == B_FALSE) { 4542 #ifdef BGE_IPMI_ASF 4543 if (bgep->asf_enabled && 4544 bgep->asf_status != ASF_STAT_RUN) { 4545 bgep->asf_timeout_id = timeout( 4546 bge_asf_heartbeat, (void *)bgep, 4547 drv_usectohz( 4548 BGE_ASF_HEARTBEAT_INTERVAL)); 4549 bgep->asf_status = ASF_STAT_RUN; 4550 } 4551 #endif 4552 if (!bgep->manual_reset) { 4553 ddi_fm_service_impact(bgep->devinfo, 4554 DDI_SERVICE_RESTORED); 4555 } 4556 } 4557 } 4558 break; 4559 } 4560 4561 4562 /* 4563 * If an error is detected, stop the chip now, marking it as 4564 * faulty, so that it will be reset next time through ... 4565 * 4566 * Note that if intr_running is set, then bge_intr() has dropped 4567 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4568 * this point so have to wait until the next time the factotum runs. 4569 */ 4570 if (error && !bgep->bge_intr_running) { 4571 #ifdef BGE_IPMI_ASF 4572 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4573 /* 4574 * We must stop ASF heart beat before bge_chip_stop(), 4575 * otherwise some computers (ex. IBM HS20 blade server) 4576 * may crash. 4577 */ 4578 bge_asf_update_status(bgep); 4579 bge_asf_stop_timer(bgep); 4580 bgep->asf_status = ASF_STAT_STOP; 4581 4582 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4583 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4584 } 4585 #endif 4586 bge_chip_stop(bgep, B_TRUE); 4587 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4588 } 4589 mutex_exit(bgep->genlock); 4590 4591 /* 4592 * If the link state changed, tell the world about it. 4593 * Note: can't do this while still holding the mutex. 4594 */ 4595 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4596 bgep->link_state != LINK_STATE_UNKNOWN) 4597 linkchg = B_TRUE; 4598 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4599 bgep->link_state == LINK_STATE_DOWN) 4600 linkchg = B_FALSE; 4601 4602 if (linkchg) { 4603 mac_link_update(bgep->mh, bgep->link_state); 4604 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4605 } 4606 if (bgep->manual_reset) { 4607 bgep->manual_reset = B_FALSE; 4608 } 4609 4610 return (result); 4611 } 4612 4613 /* 4614 * High-level cyclic handler 4615 * 4616 * This routine schedules a (low-level) softint callback to the 4617 * factotum, and prods the chip to update the status block (which 4618 * will cause a hardware interrupt when complete). 4619 */ 4620 void bge_chip_cyclic(void *arg); 4621 #pragma no_inline(bge_chip_cyclic) 4622 4623 void 4624 bge_chip_cyclic(void *arg) 4625 { 4626 bge_t *bgep; 4627 4628 bgep = arg; 4629 4630 switch (bgep->bge_chip_state) { 4631 default: 4632 return; 4633 4634 case BGE_CHIP_RUNNING: 4635 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4636 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4637 ddi_fm_service_impact(bgep->devinfo, 4638 DDI_SERVICE_UNAFFECTED); 4639 4640 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4641 bgep->link_update_timer++; 4642 4643 break; 4644 4645 case BGE_CHIP_FAULT: 4646 case BGE_CHIP_ERROR: 4647 break; 4648 } 4649 4650 bge_wake_factotum(bgep); 4651 } 4652 4653 4654 /* 4655 * ========== Ioctl subfunctions ========== 4656 */ 4657 4658 #undef BGE_DBG 4659 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4660 4661 #if BGE_DEBUGGING || BGE_DO_PPIO 4662 4663 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4664 #pragma no_inline(bge_chip_peek_cfg) 4665 4666 static void 4667 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4668 { 4669 uint64_t regval; 4670 uint64_t regno; 4671 4672 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4673 (void *)bgep, (void *)ppd)); 4674 4675 regno = ppd->pp_acc_offset; 4676 4677 switch (ppd->pp_acc_size) { 4678 case 1: 4679 regval = pci_config_get8(bgep->cfg_handle, regno); 4680 break; 4681 4682 case 2: 4683 regval = pci_config_get16(bgep->cfg_handle, regno); 4684 break; 4685 4686 case 4: 4687 regval = pci_config_get32(bgep->cfg_handle, regno); 4688 break; 4689 4690 case 8: 4691 regval = pci_config_get64(bgep->cfg_handle, regno); 4692 break; 4693 } 4694 4695 ppd->pp_acc_data = regval; 4696 } 4697 4698 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4699 #pragma no_inline(bge_chip_poke_cfg) 4700 4701 static void 4702 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4703 { 4704 uint64_t regval; 4705 uint64_t regno; 4706 4707 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4708 (void *)bgep, (void *)ppd)); 4709 4710 regno = ppd->pp_acc_offset; 4711 regval = ppd->pp_acc_data; 4712 4713 switch (ppd->pp_acc_size) { 4714 case 1: 4715 pci_config_put8(bgep->cfg_handle, regno, regval); 4716 break; 4717 4718 case 2: 4719 pci_config_put16(bgep->cfg_handle, regno, regval); 4720 break; 4721 4722 case 4: 4723 pci_config_put32(bgep->cfg_handle, regno, regval); 4724 break; 4725 4726 case 8: 4727 pci_config_put64(bgep->cfg_handle, regno, regval); 4728 break; 4729 } 4730 } 4731 4732 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4733 #pragma no_inline(bge_chip_peek_reg) 4734 4735 static void 4736 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4737 { 4738 uint64_t regval; 4739 void *regaddr; 4740 4741 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4742 (void *)bgep, (void *)ppd)); 4743 4744 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4745 4746 switch (ppd->pp_acc_size) { 4747 case 1: 4748 regval = ddi_get8(bgep->io_handle, regaddr); 4749 break; 4750 4751 case 2: 4752 regval = ddi_get16(bgep->io_handle, regaddr); 4753 break; 4754 4755 case 4: 4756 regval = ddi_get32(bgep->io_handle, regaddr); 4757 break; 4758 4759 case 8: 4760 regval = ddi_get64(bgep->io_handle, regaddr); 4761 break; 4762 } 4763 4764 ppd->pp_acc_data = regval; 4765 } 4766 4767 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4768 #pragma no_inline(bge_chip_peek_reg) 4769 4770 static void 4771 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4772 { 4773 uint64_t regval; 4774 void *regaddr; 4775 4776 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4777 (void *)bgep, (void *)ppd)); 4778 4779 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4780 regval = ppd->pp_acc_data; 4781 4782 switch (ppd->pp_acc_size) { 4783 case 1: 4784 ddi_put8(bgep->io_handle, regaddr, regval); 4785 break; 4786 4787 case 2: 4788 ddi_put16(bgep->io_handle, regaddr, regval); 4789 break; 4790 4791 case 4: 4792 ddi_put32(bgep->io_handle, regaddr, regval); 4793 break; 4794 4795 case 8: 4796 ddi_put64(bgep->io_handle, regaddr, regval); 4797 break; 4798 } 4799 BGE_PCICHK(bgep); 4800 } 4801 4802 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4803 #pragma no_inline(bge_chip_peek_nic) 4804 4805 static void 4806 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4807 { 4808 uint64_t regoff; 4809 uint64_t regval; 4810 void *regaddr; 4811 4812 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4813 (void *)bgep, (void *)ppd)); 4814 4815 regoff = ppd->pp_acc_offset; 4816 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4817 regoff &= MWBAR_GRANULE_MASK; 4818 regoff += NIC_MEM_WINDOW_OFFSET; 4819 regaddr = PIO_ADDR(bgep, regoff); 4820 4821 switch (ppd->pp_acc_size) { 4822 case 1: 4823 regval = ddi_get8(bgep->io_handle, regaddr); 4824 break; 4825 4826 case 2: 4827 regval = ddi_get16(bgep->io_handle, regaddr); 4828 break; 4829 4830 case 4: 4831 regval = ddi_get32(bgep->io_handle, regaddr); 4832 break; 4833 4834 case 8: 4835 regval = ddi_get64(bgep->io_handle, regaddr); 4836 break; 4837 } 4838 4839 ppd->pp_acc_data = regval; 4840 } 4841 4842 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4843 #pragma no_inline(bge_chip_poke_nic) 4844 4845 static void 4846 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4847 { 4848 uint64_t regoff; 4849 uint64_t regval; 4850 void *regaddr; 4851 4852 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4853 (void *)bgep, (void *)ppd)); 4854 4855 regoff = ppd->pp_acc_offset; 4856 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4857 regoff &= MWBAR_GRANULE_MASK; 4858 regoff += NIC_MEM_WINDOW_OFFSET; 4859 regaddr = PIO_ADDR(bgep, regoff); 4860 regval = ppd->pp_acc_data; 4861 4862 switch (ppd->pp_acc_size) { 4863 case 1: 4864 ddi_put8(bgep->io_handle, regaddr, regval); 4865 break; 4866 4867 case 2: 4868 ddi_put16(bgep->io_handle, regaddr, regval); 4869 break; 4870 4871 case 4: 4872 ddi_put32(bgep->io_handle, regaddr, regval); 4873 break; 4874 4875 case 8: 4876 ddi_put64(bgep->io_handle, regaddr, regval); 4877 break; 4878 } 4879 BGE_PCICHK(bgep); 4880 } 4881 4882 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4883 #pragma no_inline(bge_chip_peek_mii) 4884 4885 static void 4886 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4887 { 4888 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4889 (void *)bgep, (void *)ppd)); 4890 4891 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4892 } 4893 4894 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4895 #pragma no_inline(bge_chip_poke_mii) 4896 4897 static void 4898 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4899 { 4900 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4901 (void *)bgep, (void *)ppd)); 4902 4903 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4904 } 4905 4906 #if BGE_SEE_IO32 4907 4908 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4909 #pragma no_inline(bge_chip_peek_seeprom) 4910 4911 static void 4912 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4913 { 4914 uint32_t data; 4915 int err; 4916 4917 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4918 (void *)bgep, (void *)ppd)); 4919 4920 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4921 ppd->pp_acc_data = err ? ~0ull : data; 4922 } 4923 4924 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4925 #pragma no_inline(bge_chip_poke_seeprom) 4926 4927 static void 4928 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4929 { 4930 uint32_t data; 4931 4932 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4933 (void *)bgep, (void *)ppd)); 4934 4935 data = ppd->pp_acc_data; 4936 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4937 } 4938 #endif /* BGE_SEE_IO32 */ 4939 4940 #if BGE_FLASH_IO32 4941 4942 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4943 #pragma no_inline(bge_chip_peek_flash) 4944 4945 static void 4946 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4947 { 4948 uint32_t data; 4949 int err; 4950 4951 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4952 (void *)bgep, (void *)ppd)); 4953 4954 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4955 ppd->pp_acc_data = err ? ~0ull : data; 4956 } 4957 4958 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4959 #pragma no_inline(bge_chip_poke_flash) 4960 4961 static void 4962 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4963 { 4964 uint32_t data; 4965 4966 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4967 (void *)bgep, (void *)ppd)); 4968 4969 data = ppd->pp_acc_data; 4970 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4971 ppd->pp_acc_offset, &data); 4972 } 4973 #endif /* BGE_FLASH_IO32 */ 4974 4975 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4976 #pragma no_inline(bge_chip_peek_mem) 4977 4978 static void 4979 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4980 { 4981 uint64_t regval; 4982 void *vaddr; 4983 4984 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4985 (void *)bgep, (void *)ppd)); 4986 4987 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4988 4989 switch (ppd->pp_acc_size) { 4990 case 1: 4991 regval = *(uint8_t *)vaddr; 4992 break; 4993 4994 case 2: 4995 regval = *(uint16_t *)vaddr; 4996 break; 4997 4998 case 4: 4999 regval = *(uint32_t *)vaddr; 5000 break; 5001 5002 case 8: 5003 regval = *(uint64_t *)vaddr; 5004 break; 5005 } 5006 5007 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5008 (void *)bgep, (void *)ppd, regval, vaddr)); 5009 5010 ppd->pp_acc_data = regval; 5011 } 5012 5013 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5014 #pragma no_inline(bge_chip_poke_mem) 5015 5016 static void 5017 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5018 { 5019 uint64_t regval; 5020 void *vaddr; 5021 5022 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5023 (void *)bgep, (void *)ppd)); 5024 5025 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5026 regval = ppd->pp_acc_data; 5027 5028 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5029 (void *)bgep, (void *)ppd, regval, vaddr)); 5030 5031 switch (ppd->pp_acc_size) { 5032 case 1: 5033 *(uint8_t *)vaddr = (uint8_t)regval; 5034 break; 5035 5036 case 2: 5037 *(uint16_t *)vaddr = (uint16_t)regval; 5038 break; 5039 5040 case 4: 5041 *(uint32_t *)vaddr = (uint32_t)regval; 5042 break; 5043 5044 case 8: 5045 *(uint64_t *)vaddr = (uint64_t)regval; 5046 break; 5047 } 5048 } 5049 5050 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5051 struct iocblk *iocp); 5052 #pragma no_inline(bge_pp_ioctl) 5053 5054 static enum ioc_reply 5055 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5056 { 5057 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5058 bge_peekpoke_t *ppd; 5059 dma_area_t *areap; 5060 uint64_t sizemask; 5061 uint64_t mem_va; 5062 uint64_t maxoff; 5063 boolean_t peek; 5064 5065 switch (cmd) { 5066 default: 5067 /* NOTREACHED */ 5068 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5069 return (IOC_INVAL); 5070 5071 case BGE_PEEK: 5072 peek = B_TRUE; 5073 break; 5074 5075 case BGE_POKE: 5076 peek = B_FALSE; 5077 break; 5078 } 5079 5080 /* 5081 * Validate format of ioctl 5082 */ 5083 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5084 return (IOC_INVAL); 5085 if (mp->b_cont == NULL) 5086 return (IOC_INVAL); 5087 ppd = (void *)mp->b_cont->b_rptr; 5088 5089 /* 5090 * Validate request parameters 5091 */ 5092 switch (ppd->pp_acc_space) { 5093 default: 5094 return (IOC_INVAL); 5095 5096 case BGE_PP_SPACE_CFG: 5097 /* 5098 * Config space 5099 */ 5100 sizemask = 8|4|2|1; 5101 mem_va = 0; 5102 maxoff = PCI_CONF_HDR_SIZE; 5103 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5104 break; 5105 5106 case BGE_PP_SPACE_REG: 5107 /* 5108 * Memory-mapped I/O space 5109 */ 5110 sizemask = 8|4|2|1; 5111 mem_va = 0; 5112 maxoff = RIAAR_REGISTER_MAX; 5113 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5114 break; 5115 5116 case BGE_PP_SPACE_NIC: 5117 /* 5118 * NIC on-chip memory 5119 */ 5120 sizemask = 8|4|2|1; 5121 mem_va = 0; 5122 maxoff = MWBAR_ONCHIP_MAX; 5123 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5124 break; 5125 5126 case BGE_PP_SPACE_MII: 5127 /* 5128 * PHY's MII registers 5129 * NB: all PHY registers are two bytes, but the 5130 * addresses increment in ones (word addressing). 5131 * So we scale the address here, then undo the 5132 * transformation inside the peek/poke functions. 5133 */ 5134 ppd->pp_acc_offset *= 2; 5135 sizemask = 2; 5136 mem_va = 0; 5137 maxoff = (MII_MAXREG+1)*2; 5138 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5139 break; 5140 5141 #if BGE_SEE_IO32 5142 case BGE_PP_SPACE_SEEPROM: 5143 /* 5144 * Attached SEEPROM(s), if any. 5145 * NB: we use the high-order bits of the 'address' as 5146 * a device select to accommodate multiple SEEPROMS, 5147 * If each one is the maximum size (64kbytes), this 5148 * makes them appear contiguous. Otherwise, there may 5149 * be holes in the mapping. ENxS doesn't have any 5150 * SEEPROMs anyway ... 5151 */ 5152 sizemask = 4; 5153 mem_va = 0; 5154 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5155 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5156 break; 5157 #endif /* BGE_SEE_IO32 */ 5158 5159 #if BGE_FLASH_IO32 5160 case BGE_PP_SPACE_FLASH: 5161 /* 5162 * Attached Flash device (if any); a maximum of one device 5163 * is currently supported. But it can be up to 1MB (unlike 5164 * the 64k limit on SEEPROMs) so why would you need more ;-) 5165 */ 5166 sizemask = 4; 5167 mem_va = 0; 5168 maxoff = NVM_FLASH_ADDR_MASK; 5169 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5170 break; 5171 #endif /* BGE_FLASH_IO32 */ 5172 5173 case BGE_PP_SPACE_BGE: 5174 /* 5175 * BGE data structure! 5176 */ 5177 sizemask = 8|4|2|1; 5178 mem_va = (uintptr_t)bgep; 5179 maxoff = sizeof (*bgep); 5180 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5181 break; 5182 5183 case BGE_PP_SPACE_STATUS: 5184 case BGE_PP_SPACE_STATISTICS: 5185 case BGE_PP_SPACE_TXDESC: 5186 case BGE_PP_SPACE_TXBUFF: 5187 case BGE_PP_SPACE_RXDESC: 5188 case BGE_PP_SPACE_RXBUFF: 5189 /* 5190 * Various DMA_AREAs 5191 */ 5192 switch (ppd->pp_acc_space) { 5193 case BGE_PP_SPACE_TXDESC: 5194 areap = &bgep->tx_desc; 5195 break; 5196 case BGE_PP_SPACE_TXBUFF: 5197 areap = &bgep->tx_buff[0]; 5198 break; 5199 case BGE_PP_SPACE_RXDESC: 5200 areap = &bgep->rx_desc[0]; 5201 break; 5202 case BGE_PP_SPACE_RXBUFF: 5203 areap = &bgep->rx_buff[0]; 5204 break; 5205 case BGE_PP_SPACE_STATUS: 5206 areap = &bgep->status_block; 5207 break; 5208 case BGE_PP_SPACE_STATISTICS: 5209 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5210 areap = &bgep->statistics; 5211 break; 5212 } 5213 5214 sizemask = 8|4|2|1; 5215 mem_va = (uintptr_t)areap->mem_va; 5216 maxoff = areap->alength; 5217 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5218 break; 5219 } 5220 5221 switch (ppd->pp_acc_size) { 5222 default: 5223 return (IOC_INVAL); 5224 5225 case 8: 5226 case 4: 5227 case 2: 5228 case 1: 5229 if ((ppd->pp_acc_size & sizemask) == 0) 5230 return (IOC_INVAL); 5231 break; 5232 } 5233 5234 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5235 return (IOC_INVAL); 5236 5237 if (ppd->pp_acc_offset >= maxoff) 5238 return (IOC_INVAL); 5239 5240 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5241 return (IOC_INVAL); 5242 5243 /* 5244 * All OK - go do it! 5245 */ 5246 ppd->pp_acc_offset += mem_va; 5247 (*ppfn)(bgep, ppd); 5248 return (peek ? IOC_REPLY : IOC_ACK); 5249 } 5250 5251 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5252 struct iocblk *iocp); 5253 #pragma no_inline(bge_diag_ioctl) 5254 5255 static enum ioc_reply 5256 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5257 { 5258 ASSERT(mutex_owned(bgep->genlock)); 5259 5260 switch (cmd) { 5261 default: 5262 /* NOTREACHED */ 5263 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5264 return (IOC_INVAL); 5265 5266 case BGE_DIAG: 5267 /* 5268 * Currently a no-op 5269 */ 5270 return (IOC_ACK); 5271 5272 case BGE_PEEK: 5273 case BGE_POKE: 5274 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5275 5276 case BGE_PHY_RESET: 5277 return (IOC_RESTART_ACK); 5278 5279 case BGE_SOFT_RESET: 5280 case BGE_HARD_RESET: 5281 /* 5282 * Reset and reinitialise the 570x hardware 5283 */ 5284 bgep->bge_chip_state = BGE_CHIP_FAULT; 5285 ddi_trigger_softintr(bgep->factotum_id); 5286 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5287 return (IOC_ACK); 5288 } 5289 5290 /* NOTREACHED */ 5291 } 5292 5293 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5294 5295 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5296 struct iocblk *iocp); 5297 #pragma no_inline(bge_mii_ioctl) 5298 5299 static enum ioc_reply 5300 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5301 { 5302 struct bge_mii_rw *miirwp; 5303 5304 /* 5305 * Validate format of ioctl 5306 */ 5307 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5308 return (IOC_INVAL); 5309 if (mp->b_cont == NULL) 5310 return (IOC_INVAL); 5311 miirwp = (void *)mp->b_cont->b_rptr; 5312 5313 /* 5314 * Validate request parameters ... 5315 */ 5316 if (miirwp->mii_reg > MII_MAXREG) 5317 return (IOC_INVAL); 5318 5319 switch (cmd) { 5320 default: 5321 /* NOTREACHED */ 5322 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5323 return (IOC_INVAL); 5324 5325 case BGE_MII_READ: 5326 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5327 return (IOC_REPLY); 5328 5329 case BGE_MII_WRITE: 5330 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5331 return (IOC_ACK); 5332 } 5333 5334 /* NOTREACHED */ 5335 } 5336 5337 #if BGE_SEE_IO32 5338 5339 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5340 struct iocblk *iocp); 5341 #pragma no_inline(bge_see_ioctl) 5342 5343 static enum ioc_reply 5344 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5345 { 5346 struct bge_see_rw *seerwp; 5347 5348 /* 5349 * Validate format of ioctl 5350 */ 5351 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5352 return (IOC_INVAL); 5353 if (mp->b_cont == NULL) 5354 return (IOC_INVAL); 5355 seerwp = (void *)mp->b_cont->b_rptr; 5356 5357 /* 5358 * Validate request parameters ... 5359 */ 5360 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5361 return (IOC_INVAL); 5362 5363 switch (cmd) { 5364 default: 5365 /* NOTREACHED */ 5366 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5367 return (IOC_INVAL); 5368 5369 case BGE_SEE_READ: 5370 case BGE_SEE_WRITE: 5371 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5372 seerwp->see_addr, &seerwp->see_data); 5373 return (IOC_REPLY); 5374 } 5375 5376 /* NOTREACHED */ 5377 } 5378 5379 #endif /* BGE_SEE_IO32 */ 5380 5381 #if BGE_FLASH_IO32 5382 5383 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5384 struct iocblk *iocp); 5385 #pragma no_inline(bge_flash_ioctl) 5386 5387 static enum ioc_reply 5388 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5389 { 5390 struct bge_flash_rw *flashrwp; 5391 5392 /* 5393 * Validate format of ioctl 5394 */ 5395 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5396 return (IOC_INVAL); 5397 if (mp->b_cont == NULL) 5398 return (IOC_INVAL); 5399 flashrwp = (void *)mp->b_cont->b_rptr; 5400 5401 /* 5402 * Validate request parameters ... 5403 */ 5404 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5405 return (IOC_INVAL); 5406 5407 switch (cmd) { 5408 default: 5409 /* NOTREACHED */ 5410 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5411 return (IOC_INVAL); 5412 5413 case BGE_FLASH_READ: 5414 case BGE_FLASH_WRITE: 5415 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5416 flashrwp->flash_addr, &flashrwp->flash_data); 5417 return (IOC_REPLY); 5418 } 5419 5420 /* NOTREACHED */ 5421 } 5422 5423 #endif /* BGE_FLASH_IO32 */ 5424 5425 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5426 struct iocblk *iocp); 5427 #pragma no_inline(bge_chip_ioctl) 5428 5429 enum ioc_reply 5430 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5431 { 5432 int cmd; 5433 5434 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5435 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5436 5437 ASSERT(mutex_owned(bgep->genlock)); 5438 5439 cmd = iocp->ioc_cmd; 5440 switch (cmd) { 5441 default: 5442 /* NOTREACHED */ 5443 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5444 return (IOC_INVAL); 5445 5446 case BGE_DIAG: 5447 case BGE_PEEK: 5448 case BGE_POKE: 5449 case BGE_PHY_RESET: 5450 case BGE_SOFT_RESET: 5451 case BGE_HARD_RESET: 5452 #if BGE_DEBUGGING || BGE_DO_PPIO 5453 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5454 #else 5455 return (IOC_INVAL); 5456 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5457 5458 case BGE_MII_READ: 5459 case BGE_MII_WRITE: 5460 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5461 5462 #if BGE_SEE_IO32 5463 case BGE_SEE_READ: 5464 case BGE_SEE_WRITE: 5465 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5466 #endif /* BGE_SEE_IO32 */ 5467 5468 #if BGE_FLASH_IO32 5469 case BGE_FLASH_READ: 5470 case BGE_FLASH_WRITE: 5471 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5472 #endif /* BGE_FLASH_IO32 */ 5473 } 5474 5475 /* NOTREACHED */ 5476 } 5477 5478 void 5479 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5480 { 5481 bge_t *bgep = arg; 5482 5483 mutex_enter(bgep->genlock); 5484 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5485 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5486 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5487 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5488 mutex_exit(bgep->genlock); 5489 } 5490 5491 #ifdef BGE_IPMI_ASF 5492 5493 uint32_t 5494 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5495 { 5496 uint32_t data; 5497 5498 #ifndef __sparc 5499 if (!bgep->asf_wordswapped) { 5500 /* a workaround word swap error */ 5501 if (addr & 4) 5502 addr = addr - 4; 5503 else 5504 addr = addr + 4; 5505 } 5506 #endif 5507 5508 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5509 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5510 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5511 5512 data = LE_32(data); 5513 return (data); 5514 } 5515 5516 void 5517 bge_asf_update_status(bge_t *bgep) 5518 { 5519 uint32_t event; 5520 5521 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5522 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5523 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5524 5525 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5526 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5527 } 5528 5529 5530 /* 5531 * The driver is supposed to notify ASF that the OS is still running 5532 * every three seconds, otherwise the management server may attempt 5533 * to reboot the machine. If it hasn't actually failed, this is 5534 * not a desirable result. However, this isn't running as a real-time 5535 * thread, and even if it were, it might not be able to generate the 5536 * heartbeat in a timely manner due to system load. As it isn't a 5537 * significant strain on the machine, we will set the interval to half 5538 * of the required value. 5539 */ 5540 void 5541 bge_asf_heartbeat(void *arg) 5542 { 5543 bge_t *bgep = (bge_t *)arg; 5544 5545 mutex_enter(bgep->genlock); 5546 bge_asf_update_status((bge_t *)bgep); 5547 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5548 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5549 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5550 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5551 mutex_exit(bgep->genlock); 5552 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5553 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5554 } 5555 5556 5557 void 5558 bge_asf_stop_timer(bge_t *bgep) 5559 { 5560 timeout_id_t tmp_id = 0; 5561 5562 while ((bgep->asf_timeout_id != 0) && 5563 (tmp_id != bgep->asf_timeout_id)) { 5564 tmp_id = bgep->asf_timeout_id; 5565 (void) untimeout(tmp_id); 5566 } 5567 bgep->asf_timeout_id = 0; 5568 } 5569 5570 5571 5572 /* 5573 * This function should be placed at the earliest position of bge_attach(). 5574 */ 5575 void 5576 bge_asf_get_config(bge_t *bgep) 5577 { 5578 uint32_t nicsig; 5579 uint32_t niccfg; 5580 5581 bgep->asf_enabled = B_FALSE; 5582 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5583 if (nicsig == BGE_NIC_DATA_SIG) { 5584 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5585 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5586 /* 5587 * Here, we don't consider BAXTER, because BGE haven't 5588 * supported BAXTER (that is 5752). Also, as I know, 5589 * BAXTER doesn't support ASF feature. 5590 */ 5591 bgep->asf_enabled = B_TRUE; 5592 else 5593 bgep->asf_enabled = B_FALSE; 5594 } else 5595 bgep->asf_enabled = B_FALSE; 5596 } 5597 5598 5599 void 5600 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5601 { 5602 uint32_t tries; 5603 uint32_t event; 5604 5605 ASSERT(bgep->asf_enabled); 5606 5607 /* Issues "pause firmware" command and wait for ACK */ 5608 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5609 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5610 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5611 5612 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5613 tries = 0; 5614 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5615 drv_usecwait(1); 5616 tries ++; 5617 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5618 } 5619 5620 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5621 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5622 5623 if (bgep->asf_newhandshake) { 5624 switch (mode) { 5625 case BGE_INIT_RESET: 5626 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5627 BGE_DRV_STATE_START); 5628 break; 5629 case BGE_SHUTDOWN_RESET: 5630 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5631 BGE_DRV_STATE_UNLOAD); 5632 break; 5633 case BGE_SUSPEND_RESET: 5634 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5635 BGE_DRV_STATE_SUSPEND); 5636 break; 5637 default: 5638 break; 5639 } 5640 } 5641 } 5642 5643 5644 void 5645 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5646 { 5647 switch (mode) { 5648 case BGE_INIT_RESET: 5649 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5650 BGE_DRV_STATE_START); 5651 break; 5652 case BGE_SHUTDOWN_RESET: 5653 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5654 BGE_DRV_STATE_UNLOAD); 5655 break; 5656 case BGE_SUSPEND_RESET: 5657 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5658 BGE_DRV_STATE_SUSPEND); 5659 break; 5660 default: 5661 break; 5662 } 5663 } 5664 5665 5666 void 5667 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5668 { 5669 switch (mode) { 5670 case BGE_INIT_RESET: 5671 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5672 BGE_DRV_STATE_START_DONE); 5673 break; 5674 case BGE_SHUTDOWN_RESET: 5675 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5676 BGE_DRV_STATE_UNLOAD_DONE); 5677 break; 5678 default: 5679 break; 5680 } 5681 } 5682 5683 #endif /* BGE_IPMI_ASF */ 5684