1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 boolean_t bge_jumbo_enable = B_TRUE; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 245 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 246 247 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 248 (void *)bgep, regno, val)); 249 250 val = LE_32(val); 251 252 return (val); 253 } 254 255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 256 #pragma inline(bge_ind_put32) 257 258 void 259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 260 { 261 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 262 (void *)bgep, regno, val)); 263 264 val = LE_32(val); 265 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 267 } 268 269 #endif /* BGE_IND_IO32 */ 270 271 #if BGE_DEBUGGING 272 273 static void bge_pci_check(bge_t *bgep); 274 #pragma no_inline(bge_pci_check) 275 276 static void 277 bge_pci_check(bge_t *bgep) 278 { 279 uint16_t pcistatus; 280 281 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 282 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 283 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 284 (void *)bgep, pcistatus)); 285 } 286 287 #endif /* BGE_DEBUGGING */ 288 289 /* 290 * Perform first-stage chip (re-)initialisation, using only config-space 291 * accesses: 292 * 293 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 294 * returning the data in the structure pointed to by <idp>. 295 * + Configure the target-mode endianness (swap) options. 296 * + Disable interrupts and enable Memory Space accesses. 297 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 298 * 299 * This sequence is adapted from Broadcom document 570X-PG102-R, 300 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 301 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 302 * 303 * This function MUST be called before any non-config-space accesses 304 * are made; on this first call <enable_dma> is B_FALSE, and it 305 * effectively performs steps 3-1(!) of the initialisation sequence 306 * (the rest are not required but should be harmless). 307 * 308 * It MUST also be called after a chip reset, as this disables 309 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 310 * it is effectively performing steps 6-8. 311 */ 312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 313 #pragma no_inline(bge_chip_cfg_init) 314 315 void 316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 317 { 318 ddi_acc_handle_t handle; 319 uint16_t command; 320 uint32_t mhcr; 321 uint16_t value16; 322 int i; 323 324 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 325 (void *)bgep, (void *)cidp, enable_dma)); 326 327 /* 328 * Step 3: save PCI cache line size and subsystem vendor ID 329 * 330 * Read all the config-space registers that characterise the 331 * chip, specifically vendor/device/revision/subsystem vendor 332 * and subsystem device id. We expect (but don't check) that 333 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 334 * 335 * Also save all bus-transaction related registers (cache-line 336 * size, bus-grant/latency parameters, etc). Some of these are 337 * cleared by reset, so we'll have to restore them later. This 338 * comes from the Broadcom document 570X-PG102-R ... 339 * 340 * Note: Broadcom document 570X-PG102-R seems to be in error 341 * here w.r.t. the offsets of the Subsystem Vendor ID and 342 * Subsystem (Device) ID registers, which are the opposite way 343 * round according to the PCI standard. For good measure, we 344 * save/restore both anyway. 345 */ 346 handle = bgep->cfg_handle; 347 348 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 349 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 350 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 351 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 352 353 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 354 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 355 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 356 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 357 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 358 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 359 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 360 361 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 362 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 363 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 364 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 365 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 366 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 367 cidp->vendor, cidp->device, cidp->revision)); 368 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 369 cidp->subven, cidp->subdev, cidp->asic_rev)); 370 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 371 cidp->clsize, cidp->latency, cidp->command)); 372 373 /* 374 * Step 2 (also step 6): disable and clear interrupts. 375 * Steps 11-13: configure PIO endianness options, and enable 376 * indirect register access. We'll also select any other 377 * options controlled by the MHCR (e.g. tagged status, mask 378 * interrupt mode) at this stage ... 379 * 380 * Note: internally, the chip is 64-bit and BIG-endian, but 381 * since it talks to the host over a (LITTLE-endian) PCI bus, 382 * it normally swaps bytes around at the PCI interface. 383 * However, the PCI host bridge on SPARC systems normally 384 * swaps the byte lanes around too, since SPARCs are also 385 * BIG-endian. So it turns out that on SPARC, the right 386 * option is to tell the chip to swap (and the host bridge 387 * will swap back again), whereas on x86 we ask the chip 388 * NOT to swap, so the natural little-endianness of the 389 * PCI bus is assumed. Then the only thing that doesn't 390 * automatically work right is access to an 8-byte register 391 * by a little-endian host; but we don't want to set the 392 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 393 * accesses don't go where expected ;-( So we live with 394 * that, and perform word-swaps in software in the few cases 395 * where a chip register is defined as an 8-byte value -- 396 * see the code below for details ... 397 * 398 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 399 * very clear in the register description in the PRM, but 400 * Broadcom document 570X-PG104-R page 248 explains a little 401 * more (under "Broadcom Mask Mode"). The bit changes the way 402 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 403 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 404 * way as the 5700 did, which isn't very convenient. Setting 405 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 406 * bit do just what its name says -- MASK the PCI #INTA output 407 * (i.e. deassert the signal at the pin) leaving all internal 408 * state unchanged. This is much more convenient for our 409 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 410 * 411 * Note: the inconvenient semantics of the interrupt mailbox 412 * (nonzero disables and acknowledges/clears the interrupt, 413 * zero enables AND CLEARS it) would make race conditions 414 * likely in the interrupt handler: 415 * 416 * (1) acknowledge & disable interrupts 417 * (2) while (more to do) 418 * process packets 419 * (3) enable interrupts -- also clears pending 420 * 421 * If the chip received more packets and internally generated 422 * an interrupt between the check at (2) and the mbox write 423 * at (3), this interrupt would be lost :-( 424 * 425 * The best way to avoid this is to use TAGGED STATUS mode, 426 * where the chip includes a unique tag in each status block 427 * update, and the host, when re-enabling interrupts, passes 428 * the last tag it saw back to the chip; then the chip can 429 * see whether the host is truly up to date, and regenerate 430 * its interrupt if not. 431 */ 432 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 433 MHCR_ENABLE_TAGGED_STATUS_MODE | 434 MHCR_MASK_INTERRUPT_MODE | 435 MHCR_CLEAR_INTERRUPT_INTA; 436 437 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 438 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 439 440 #ifdef _BIG_ENDIAN 441 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 442 #endif /* _BIG_ENDIAN */ 443 444 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 445 446 #ifdef BGE_IPMI_ASF 447 bgep->asf_wordswapped = B_FALSE; 448 #endif 449 /* 450 * Step 1 (also step 7): Enable PCI Memory Space accesses 451 * Disable Memory Write/Invalidate 452 * Enable or disable Bus Mastering 453 * 454 * Note that all other bits are taken from the original value saved 455 * the first time through here, rather than from the current register 456 * value, 'cos that will have been cleared by a soft RESET since. 457 * In this way we preserve the OBP/nexus-parent's preferred settings 458 * of the parity-error and system-error enable bits across multiple 459 * chip RESETs. 460 */ 461 command = bgep->chipid.command | PCI_COMM_MAE; 462 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 463 if (enable_dma) 464 command |= PCI_COMM_ME; 465 /* 466 * on BCM5714 revision A0, false parity error gets generated 467 * due to a logic bug. Provide a workaround by disabling parity 468 * error. 469 */ 470 if (((cidp->device == DEVICE_ID_5714C) || 471 (cidp->device == DEVICE_ID_5714S)) && 472 (cidp->revision == REVISION_ID_5714_A0)) { 473 command &= ~PCI_COMM_PARITY_DETECT; 474 } 475 pci_config_put16(handle, PCI_CONF_COMM, command); 476 477 /* 478 * On some PCI-E device, there were instances when 479 * the device was still link training. 480 */ 481 if (bgep->chipid.pci_type == BGE_PCI_E) { 482 i = 0; 483 value16 = pci_config_get16(handle, PCI_CONF_COMM); 484 while ((value16 != command) && (i < 100)) { 485 drv_usecwait(200); 486 value16 = pci_config_get16(handle, PCI_CONF_COMM); 487 ++i; 488 } 489 } 490 491 /* 492 * Clear any remaining error status bits 493 */ 494 pci_config_put16(handle, PCI_CONF_STAT, ~0); 495 496 /* 497 * Do following if and only if the device is NOT BCM5714C OR 498 * BCM5715C 499 */ 500 if (!((cidp->device == DEVICE_ID_5714C) || 501 (cidp->device == DEVICE_ID_5715C))) { 502 /* 503 * Make sure these indirect-access registers are sane 504 * rather than random after power-up or reset 505 */ 506 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 507 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 508 } 509 /* 510 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 511 */ 512 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 513 514 if (cidp->pci_type == BGE_PCI_E) 515 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 516 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 517 } 518 519 #ifdef __amd64 520 /* 521 * Distinguish CPU types 522 * 523 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 524 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 525 * for PCI-Express based network interface card. This is the work-around 526 * for those nics. 527 */ 528 static boolean_t bge_get_em64t_type(void); 529 #pragma inline(bge_get_em64t_type) 530 531 static boolean_t 532 bge_get_em64t_type(void) 533 { 534 535 return (x86_vendor == X86_VENDOR_Intel); 536 } 537 #endif 538 539 /* 540 * Operating register get/set access routines 541 */ 542 543 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 544 #pragma inline(bge_reg_get32) 545 546 uint32_t 547 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 548 { 549 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 550 (void *)bgep, regno)); 551 552 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 553 } 554 555 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 556 #pragma inline(bge_reg_put32) 557 558 void 559 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 560 { 561 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 562 (void *)bgep, regno, data)); 563 564 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 565 BGE_PCICHK(bgep); 566 } 567 568 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 569 #pragma inline(bge_reg_set32) 570 571 void 572 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 573 { 574 uint32_t regval; 575 576 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 577 (void *)bgep, regno, bits)); 578 579 regval = bge_reg_get32(bgep, regno); 580 regval |= bits; 581 bge_reg_put32(bgep, regno, regval); 582 } 583 584 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 585 #pragma inline(bge_reg_clr32) 586 587 void 588 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 589 { 590 uint32_t regval; 591 592 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 593 (void *)bgep, regno, bits)); 594 595 regval = bge_reg_get32(bgep, regno); 596 regval &= ~bits; 597 bge_reg_put32(bgep, regno, regval); 598 } 599 600 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 601 #pragma inline(bge_reg_get64) 602 603 static uint64_t 604 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 605 { 606 uint64_t regval; 607 608 #ifdef __amd64 609 if (bge_get_em64t_type()) { 610 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 611 regval <<= 32; 612 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 613 } else { 614 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 615 } 616 #else 617 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 #endif 619 620 #ifdef _LITTLE_ENDIAN 621 regval = (regval >> 32) | (regval << 32); 622 #endif /* _LITTLE_ENDIAN */ 623 624 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 625 (void *)bgep, regno, regval)); 626 627 return (regval); 628 } 629 630 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 631 #pragma inline(bge_reg_put64) 632 633 static void 634 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 635 { 636 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 637 (void *)bgep, regno, data)); 638 639 #ifdef _LITTLE_ENDIAN 640 data = ((data >> 32) | (data << 32)); 641 #endif /* _LITTLE_ENDIAN */ 642 643 #ifdef __amd64 644 if (bge_get_em64t_type()) { 645 ddi_put32(bgep->io_handle, 646 PIO_ADDR(bgep, regno), (uint32_t)data); 647 BGE_PCICHK(bgep); 648 ddi_put32(bgep->io_handle, 649 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 650 651 } else { 652 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 653 } 654 #else 655 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 656 #endif 657 658 BGE_PCICHK(bgep); 659 } 660 661 /* 662 * The DDI doesn't provide get/put functions for 128 bit data 663 * so we put RCBs out as two 64-bit chunks instead. 664 */ 665 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 666 #pragma inline(bge_reg_putrcb) 667 668 static void 669 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 670 { 671 uint64_t *p; 672 673 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 674 (void *)bgep, addr, rcbp->host_ring_addr, 675 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 676 677 ASSERT((addr % sizeof (*rcbp)) == 0); 678 679 p = (void *)rcbp; 680 bge_reg_put64(bgep, addr, *p++); 681 bge_reg_put64(bgep, addr+8, *p); 682 } 683 684 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 685 #pragma inline(bge_mbx_put) 686 687 void 688 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 689 { 690 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 691 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 692 693 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 694 (void *)bgep, regno, data)); 695 696 /* 697 * Mailbox registers are nominally 64 bits on the 5701, but 698 * the MSW isn't used. On the 5703, they're only 32 bits 699 * anyway. So here we just write the lower(!) 32 bits - 700 * remembering that the chip is big-endian, even though the 701 * PCI bus is little-endian ... 702 */ 703 #ifdef _BIG_ENDIAN 704 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 705 #else 706 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 707 #endif /* _BIG_ENDIAN */ 708 BGE_PCICHK(bgep); 709 } 710 711 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 712 #pragma inline(bge_mbx_get) 713 714 uint32_t 715 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 716 { 717 uint32_t val32; 718 719 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 720 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 721 722 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 723 (void *)bgep, regno)); 724 725 #ifdef _BIG_ENDIAN 726 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 727 #else 728 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 729 #endif /* _BIG_ENDIAN */ 730 BGE_PCICHK(bgep); 731 732 return (val32); 733 } 734 735 736 #if BGE_DEBUGGING 737 738 void bge_led_mark(bge_t *bgep); 739 #pragma no_inline(bge_led_mark) 740 741 void 742 bge_led_mark(bge_t *bgep) 743 { 744 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 745 LED_CONTROL_1000MBPS_LED | 746 LED_CONTROL_100MBPS_LED | 747 LED_CONTROL_10MBPS_LED; 748 749 /* 750 * Blink all three LINK LEDs on simultaneously, then all off, 751 * then restore to automatic hardware control. This is used 752 * in laboratory testing to trigger a logic analyser or scope. 753 */ 754 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 755 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 756 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 757 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 758 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 759 } 760 761 #endif /* BGE_DEBUGGING */ 762 763 /* 764 * NIC on-chip memory access routines 765 * 766 * Only 32K of NIC memory is visible at a time, controlled by the 767 * Memory Window Base Address Register (in PCI config space). Once 768 * this is set, the 32K region of NIC-local memory that it refers 769 * to can be directly addressed in the upper 32K of the 64K of PCI 770 * memory space used for the device. 771 */ 772 773 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 774 #pragma inline(bge_nic_setwin) 775 776 static void 777 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 778 { 779 chip_id_t *cidp; 780 781 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 782 (void *)bgep, base)); 783 784 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 785 786 /* 787 * Don't do repeated zero data writes, 788 * if the device is BCM5714C/15C. 789 */ 790 cidp = &bgep->chipid; 791 if ((cidp->device == DEVICE_ID_5714C) || 792 (cidp->device == DEVICE_ID_5715C)) { 793 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 794 return; 795 /* Adjust lastWriteZeroData */ 796 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 797 B_TRUE : B_FALSE); 798 } 799 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 800 } 801 802 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 803 #pragma inline(bge_nic_get32) 804 805 static uint32_t 806 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 807 { 808 uint32_t data; 809 810 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 811 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 812 /* workaround for word swap error */ 813 if (addr & 4) 814 addr = addr - 4; 815 else 816 addr = addr + 4; 817 } 818 #endif 819 820 #ifdef __sparc 821 data = bge_nic_read32(bgep, addr); 822 #else 823 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 824 addr &= MWBAR_GRANULE_MASK; 825 addr += NIC_MEM_WINDOW_OFFSET; 826 827 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 828 #endif 829 830 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 831 (void *)bgep, addr, data)); 832 833 return (data); 834 } 835 836 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 837 #pragma inline(bge_nic_put32) 838 839 void 840 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 841 { 842 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 843 (void *)bgep, addr, data)); 844 845 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 846 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 847 /* workaround for word swap error */ 848 if (addr & 4) 849 addr = addr - 4; 850 else 851 addr = addr + 4; 852 } 853 #endif 854 855 #ifdef __sparc 856 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 857 data = LE_32(data); 858 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 859 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 860 #else 861 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 862 addr &= MWBAR_GRANULE_MASK; 863 addr += NIC_MEM_WINDOW_OFFSET; 864 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 865 BGE_PCICHK(bgep); 866 #endif 867 } 868 869 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 870 #pragma inline(bge_nic_get64) 871 872 static uint64_t 873 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 874 { 875 uint64_t data; 876 877 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 878 addr &= MWBAR_GRANULE_MASK; 879 addr += NIC_MEM_WINDOW_OFFSET; 880 881 #ifdef __amd64 882 if (bge_get_em64t_type()) { 883 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 884 data <<= 32; 885 data |= ddi_get32(bgep->io_handle, 886 PIO_ADDR(bgep, addr + 4)); 887 } else { 888 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 889 } 890 #else 891 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 892 #endif 893 894 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 895 (void *)bgep, addr, data)); 896 897 return (data); 898 } 899 900 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 901 #pragma inline(bge_nic_put64) 902 903 static void 904 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 905 { 906 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 907 (void *)bgep, addr, data)); 908 909 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 910 addr &= MWBAR_GRANULE_MASK; 911 addr += NIC_MEM_WINDOW_OFFSET; 912 913 #ifdef __amd64 914 if (bge_get_em64t_type()) { 915 ddi_put32(bgep->io_handle, 916 PIO_ADDR(bgep, addr), (uint32_t)data); 917 BGE_PCICHK(bgep); 918 ddi_put32(bgep->io_handle, 919 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 920 } else { 921 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 922 } 923 #else 924 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 925 #endif 926 927 BGE_PCICHK(bgep); 928 } 929 930 /* 931 * The DDI doesn't provide get/put functions for 128 bit data 932 * so we put RCBs out as two 64-bit chunks instead. 933 */ 934 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 935 #pragma inline(bge_nic_putrcb) 936 937 static void 938 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 939 { 940 uint64_t *p; 941 942 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 943 (void *)bgep, addr, rcbp->host_ring_addr, 944 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 945 946 ASSERT((addr % sizeof (*rcbp)) == 0); 947 948 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 949 addr &= MWBAR_GRANULE_MASK; 950 addr += NIC_MEM_WINDOW_OFFSET; 951 952 p = (void *)rcbp; 953 #ifdef __amd64 954 if (bge_get_em64t_type()) { 955 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 956 (uint32_t)(*p)); 957 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 958 (uint32_t)(*p >> 32)); 959 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 960 (uint32_t)(*(p + 1))); 961 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 962 (uint32_t)(*p >> 32)); 963 964 } else { 965 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 966 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 967 } 968 #else 969 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 970 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 971 #endif 972 973 BGE_PCICHK(bgep); 974 } 975 976 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 977 #pragma inline(bge_nic_zero) 978 979 static void 980 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 981 { 982 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 983 (void *)bgep, addr, nbytes)); 984 985 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 986 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 987 988 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 989 addr &= MWBAR_GRANULE_MASK; 990 addr += NIC_MEM_WINDOW_OFFSET; 991 992 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 993 nbytes, 1, DDI_DATA_SZ08_ACC); 994 BGE_PCICHK(bgep); 995 } 996 997 /* 998 * MII (PHY) register get/set access routines 999 * 1000 * These use the chip's MII auto-access method, controlled by the 1001 * MII Communication register at 0x044c, so the CPU doesn't have 1002 * to fiddle with the individual bits. 1003 */ 1004 1005 #undef BGE_DBG 1006 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1007 1008 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1009 uint16_t data, uint32_t cmd); 1010 #pragma no_inline(bge_mii_access) 1011 1012 static uint16_t 1013 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1014 { 1015 uint32_t timeout; 1016 uint32_t regval1; 1017 uint32_t regval2; 1018 1019 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1020 (void *)bgep, regno, data, cmd)); 1021 1022 ASSERT(mutex_owned(bgep->genlock)); 1023 1024 /* 1025 * Assemble the command ... 1026 */ 1027 cmd |= data << MI_COMMS_DATA_SHIFT; 1028 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1029 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1030 cmd |= MI_COMMS_START; 1031 1032 /* 1033 * Wait for any command already in progress ... 1034 * 1035 * Note: this *shouldn't* ever find that there is a command 1036 * in progress, because we already hold the <genlock> mutex. 1037 * Nonetheless, we have sometimes seen the MI_COMMS_START 1038 * bit set here -- it seems that the chip can initiate MII 1039 * accesses internally, even with polling OFF. 1040 */ 1041 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1042 for (timeout = 100; ; ) { 1043 if ((regval2 & MI_COMMS_START) == 0) { 1044 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1045 break; 1046 } 1047 if (--timeout == 0) 1048 break; 1049 drv_usecwait(10); 1050 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1051 } 1052 1053 if (timeout == 0) 1054 return ((uint16_t)~0u); 1055 1056 if (timeout != 100) 1057 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1058 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1059 cmd, 10*(100-timeout), regval1, regval2)); 1060 1061 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1062 for (timeout = 1000; ; ) { 1063 if ((regval1 & MI_COMMS_START) == 0) 1064 break; 1065 if (--timeout == 0) 1066 break; 1067 drv_usecwait(10); 1068 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1069 } 1070 1071 /* 1072 * Drop out early if the READ FAILED bit is set -- this chip 1073 * could be a 5703/4S, with a SerDes instead of a PHY! 1074 */ 1075 if (regval2 & MI_COMMS_READ_FAILED) 1076 return ((uint16_t)~0u); 1077 1078 if (timeout == 0) 1079 return ((uint16_t)~0u); 1080 1081 /* 1082 * The PRM says to wait 5us after seeing the START bit clear 1083 * and then re-read the register to get the final value of the 1084 * data field, in order to avoid a race condition where the 1085 * START bit is clear but the data field isn't yet valid. 1086 * 1087 * Note: we don't actually seem to be encounter this race; 1088 * except when the START bit is seen set again (see below), 1089 * the data field doesn't change during this 5us interval. 1090 */ 1091 drv_usecwait(5); 1092 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1093 1094 /* 1095 * Unfortunately, when following the PRMs instructions above, 1096 * we have occasionally seen the START bit set again(!) in the 1097 * value read after the 5us delay. This seems to be due to the 1098 * chip autonomously starting another MII access internally. 1099 * In such cases, the command/data/etc fields relate to the 1100 * internal command, rather than the one that we thought had 1101 * just finished. So in this case, we fall back to returning 1102 * the data from the original read that showed START clear. 1103 */ 1104 if (regval2 & MI_COMMS_START) { 1105 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1106 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1107 cmd, regval1, regval2)); 1108 regval2 = regval1; 1109 } 1110 1111 if (regval2 & MI_COMMS_START) 1112 return ((uint16_t)~0u); 1113 1114 if (regval2 & MI_COMMS_READ_FAILED) 1115 return ((uint16_t)~0u); 1116 1117 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1118 } 1119 1120 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1121 #pragma no_inline(bge_mii_get16) 1122 1123 uint16_t 1124 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1125 { 1126 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1127 (void *)bgep, regno)); 1128 1129 ASSERT(mutex_owned(bgep->genlock)); 1130 1131 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1132 (regno == MII_1000BASE_T_CONTROL))) 1133 return (0); 1134 1135 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1136 } 1137 1138 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1139 #pragma no_inline(bge_mii_put16) 1140 1141 void 1142 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1143 { 1144 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1145 (void *)bgep, regno, data)); 1146 1147 ASSERT(mutex_owned(bgep->genlock)); 1148 1149 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1150 (regno == MII_1000BASE_T_CONTROL))) 1151 return; 1152 1153 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1154 } 1155 1156 #undef BGE_DBG 1157 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1158 1159 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1160 1161 /* 1162 * Basic SEEPROM get/set access routine 1163 * 1164 * This uses the chip's SEEPROM auto-access method, controlled by the 1165 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1166 * doesn't have to fiddle with the individual bits. 1167 * 1168 * The caller should hold <genlock> and *also* have already acquired 1169 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1170 * 1171 * Return value: 1172 * 0 on success, 1173 * ENODATA on access timeout (maybe retryable: device may just be busy) 1174 * EPROTO on other h/w or s/w errors. 1175 * 1176 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1177 * from a (successful) SEEPROM_ACCESS_READ. 1178 */ 1179 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1180 uint32_t *dp); 1181 #pragma no_inline(bge_seeprom_access) 1182 1183 static int 1184 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1185 { 1186 uint32_t tries; 1187 uint32_t regval; 1188 1189 ASSERT(mutex_owned(bgep->genlock)); 1190 1191 /* 1192 * On the newer chips that support both SEEPROM & Flash, we need 1193 * to specifically enable SEEPROM access (Flash is the default). 1194 * On older chips, we don't; SEEPROM is the only NVtype supported, 1195 * and the NVM control registers don't exist ... 1196 */ 1197 switch (bgep->chipid.nvtype) { 1198 case BGE_NVTYPE_NONE: 1199 case BGE_NVTYPE_UNKNOWN: 1200 _NOTE(NOTREACHED) 1201 case BGE_NVTYPE_SEEPROM: 1202 break; 1203 1204 case BGE_NVTYPE_LEGACY_SEEPROM: 1205 case BGE_NVTYPE_UNBUFFERED_FLASH: 1206 case BGE_NVTYPE_BUFFERED_FLASH: 1207 default: 1208 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1209 NVM_CFG1_LEGACY_SEEPROM_MODE); 1210 break; 1211 } 1212 1213 /* 1214 * Check there's no command in progress. 1215 * 1216 * Note: this *shouldn't* ever find that there is a command 1217 * in progress, because we already hold the <genlock> mutex. 1218 * Also, to ensure we don't have a conflict with the chip's 1219 * internal firmware or a process accessing the same (shared) 1220 * SEEPROM through the other port of a 5704, we've already 1221 * been through the "software arbitration" protocol. 1222 * So this is just a final consistency check: we shouldn't 1223 * see EITHER the START bit (command started but not complete) 1224 * OR the COMPLETE bit (command completed but not cleared). 1225 */ 1226 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1227 if (regval & SEEPROM_ACCESS_START) 1228 return (EPROTO); 1229 if (regval & SEEPROM_ACCESS_COMPLETE) 1230 return (EPROTO); 1231 1232 /* 1233 * Assemble the command ... 1234 */ 1235 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1236 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1237 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1238 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1239 cmd |= SEEPROM_ACCESS_START; 1240 cmd |= SEEPROM_ACCESS_COMPLETE; 1241 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1242 1243 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1244 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1245 1246 /* 1247 * By observation, a successful access takes ~20us on a 5703/4, 1248 * but apparently much longer (up to 1000us) on the obsolescent 1249 * BCM5700/BCM5701. We want to be sure we don't get any false 1250 * timeouts here; but OTOH, we don't want a bogus access to lock 1251 * out interrupts for longer than necessary. So we'll allow up 1252 * to 1000us ... 1253 */ 1254 for (tries = 0; tries < 1000; ++tries) { 1255 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1256 if (regval & SEEPROM_ACCESS_COMPLETE) 1257 break; 1258 drv_usecwait(1); 1259 } 1260 1261 if (regval & SEEPROM_ACCESS_COMPLETE) { 1262 /* 1263 * All OK; read the SEEPROM data register, then write back 1264 * the value read from the address register in order to 1265 * clear the <complete> bit and leave the SEEPROM access 1266 * state machine idle, ready for the next access ... 1267 */ 1268 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1269 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1270 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1271 return (0); 1272 } 1273 1274 /* 1275 * Hmm ... what happened here? 1276 * 1277 * Most likely, the user addressed a non-existent SEEPROM. Or 1278 * maybe the SEEPROM was busy internally (e.g. processing a write) 1279 * and didn't respond to being addressed. Either way, it's left 1280 * the SEEPROM access state machine wedged. So we'll reset it 1281 * before we leave, so it's ready for next time ... 1282 */ 1283 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1284 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1285 return (ENODATA); 1286 } 1287 1288 /* 1289 * Basic Flash get/set access routine 1290 * 1291 * These use the chip's Flash auto-access method, controlled by the 1292 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1293 * fiddle with the individual bits. 1294 * 1295 * The caller should hold <genlock> and *also* have already acquired 1296 * the right to access the Flash, via bge_nvmem_acquire() above. 1297 * 1298 * Return value: 1299 * 0 on success, 1300 * ENODATA on access timeout (maybe retryable: device may just be busy) 1301 * ENODEV if the NVmem device is missing or otherwise unusable 1302 * 1303 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1304 * from a (successful) NVM_FLASH_CMD_RD. 1305 */ 1306 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1307 uint32_t *dp); 1308 #pragma no_inline(bge_flash_access) 1309 1310 static int 1311 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1312 { 1313 uint32_t tries; 1314 uint32_t regval; 1315 1316 ASSERT(mutex_owned(bgep->genlock)); 1317 1318 /* 1319 * On the newer chips that support both SEEPROM & Flash, we need 1320 * to specifically disable SEEPROM access while accessing Flash. 1321 * The older chips don't support Flash, and the NVM registers don't 1322 * exist, so we shouldn't be here at all! 1323 */ 1324 switch (bgep->chipid.nvtype) { 1325 case BGE_NVTYPE_NONE: 1326 case BGE_NVTYPE_UNKNOWN: 1327 _NOTE(NOTREACHED) 1328 case BGE_NVTYPE_SEEPROM: 1329 return (ENODEV); 1330 1331 case BGE_NVTYPE_LEGACY_SEEPROM: 1332 case BGE_NVTYPE_UNBUFFERED_FLASH: 1333 case BGE_NVTYPE_BUFFERED_FLASH: 1334 default: 1335 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1336 NVM_CFG1_LEGACY_SEEPROM_MODE); 1337 break; 1338 } 1339 1340 /* 1341 * Assemble the command ... 1342 */ 1343 addr &= NVM_FLASH_ADDR_MASK; 1344 cmd |= NVM_FLASH_CMD_DOIT; 1345 cmd |= NVM_FLASH_CMD_FIRST; 1346 cmd |= NVM_FLASH_CMD_LAST; 1347 cmd |= NVM_FLASH_CMD_DONE; 1348 1349 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1350 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1351 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1352 1353 /* 1354 * Allow up to 1000ms ... 1355 */ 1356 for (tries = 0; tries < 1000; ++tries) { 1357 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1358 if (regval & NVM_FLASH_CMD_DONE) 1359 break; 1360 drv_usecwait(1); 1361 } 1362 1363 if (regval & NVM_FLASH_CMD_DONE) { 1364 /* 1365 * All OK; read the data from the Flash read register 1366 */ 1367 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1368 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1369 return (0); 1370 } 1371 1372 /* 1373 * Hmm ... what happened here? 1374 * 1375 * Most likely, the user addressed a non-existent Flash. Or 1376 * maybe the Flash was busy internally (e.g. processing a write) 1377 * and didn't respond to being addressed. Either way, there's 1378 * nothing we can here ... 1379 */ 1380 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1381 return (ENODATA); 1382 } 1383 1384 /* 1385 * The next two functions regulate access to the NVram (if fitted). 1386 * 1387 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1388 * (SPI) interface, but they can be accessed through either port. These 1389 * are managed by different instance of this driver and have no software 1390 * state in common. 1391 * 1392 * In addition (and even on a single core chip) the chip's internal 1393 * firmware can access the SEEPROM/Flash, most notably after a RESET 1394 * when it may download code to run internally. 1395 * 1396 * So we need to arbitrate between these various software agents. For 1397 * this purpose, the chip provides the Software Arbitration Register, 1398 * which implements hardware(!) arbitration. 1399 * 1400 * This functionality didn't exist on older (5700/5701) chips, so there's 1401 * nothing we can do by way of arbitration on those; also, if there's no 1402 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1403 * nothing to do. 1404 * 1405 * The internal firmware appears to use Request 0, which is the highest 1406 * priority. So we'd like to use Request 2, leaving one higher and one 1407 * lower for any future developments ... but apparently this doesn't 1408 * always work. So for now, the code uses Request 1 ;-( 1409 */ 1410 1411 #define NVM_READ_REQ NVM_READ_REQ1 1412 #define NVM_RESET_REQ NVM_RESET_REQ1 1413 #define NVM_SET_REQ NVM_SET_REQ1 1414 1415 static void bge_nvmem_relinquish(bge_t *bgep); 1416 #pragma no_inline(bge_nvmem_relinquish) 1417 1418 static void 1419 bge_nvmem_relinquish(bge_t *bgep) 1420 { 1421 ASSERT(mutex_owned(bgep->genlock)); 1422 1423 switch (bgep->chipid.nvtype) { 1424 case BGE_NVTYPE_NONE: 1425 case BGE_NVTYPE_UNKNOWN: 1426 _NOTE(NOTREACHED) 1427 return; 1428 1429 case BGE_NVTYPE_SEEPROM: 1430 /* 1431 * No arbitration performed, no release needed 1432 */ 1433 return; 1434 1435 case BGE_NVTYPE_LEGACY_SEEPROM: 1436 case BGE_NVTYPE_UNBUFFERED_FLASH: 1437 case BGE_NVTYPE_BUFFERED_FLASH: 1438 default: 1439 break; 1440 } 1441 1442 /* 1443 * Our own request should be present (whether or not granted) ... 1444 */ 1445 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1446 1447 /* 1448 * ... this will make it go away. 1449 */ 1450 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1451 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1452 } 1453 1454 /* 1455 * Arbitrate for access to the NVmem, if necessary 1456 * 1457 * Return value: 1458 * 0 on success 1459 * EAGAIN if the device is in use (retryable) 1460 * ENODEV if the NVmem device is missing or otherwise unusable 1461 */ 1462 static int bge_nvmem_acquire(bge_t *bgep); 1463 #pragma no_inline(bge_nvmem_acquire) 1464 1465 static int 1466 bge_nvmem_acquire(bge_t *bgep) 1467 { 1468 uint32_t regval; 1469 uint32_t tries; 1470 1471 ASSERT(mutex_owned(bgep->genlock)); 1472 1473 switch (bgep->chipid.nvtype) { 1474 case BGE_NVTYPE_NONE: 1475 case BGE_NVTYPE_UNKNOWN: 1476 /* 1477 * Access denied: no (recognisable) device fitted 1478 */ 1479 return (ENODEV); 1480 1481 case BGE_NVTYPE_SEEPROM: 1482 /* 1483 * Access granted: no arbitration needed (or possible) 1484 */ 1485 return (0); 1486 1487 case BGE_NVTYPE_LEGACY_SEEPROM: 1488 case BGE_NVTYPE_UNBUFFERED_FLASH: 1489 case BGE_NVTYPE_BUFFERED_FLASH: 1490 default: 1491 /* 1492 * Access conditional: conduct arbitration protocol 1493 */ 1494 break; 1495 } 1496 1497 /* 1498 * We're holding the per-port mutex <genlock>, so no-one other 1499 * thread can be attempting to access the NVmem through *this* 1500 * port. But it could be in use by the *other* port (of a 5704), 1501 * or by the chip's internal firmware, so we have to go through 1502 * the full (hardware) arbitration protocol ... 1503 * 1504 * Note that *because* we're holding <genlock>, the interrupt handler 1505 * won't be able to progress. So we're only willing to spin for a 1506 * fairly short time. Specifically: 1507 * 1508 * We *must* wait long enough for the hardware to resolve all 1509 * requests and determine the winner. Fortunately, this is 1510 * "almost instantaneous", even as observed by GHz CPUs. 1511 * 1512 * A successful access by another Solaris thread (via either 1513 * port) typically takes ~20us. So waiting a bit longer than 1514 * that will give a good chance of success, if the other user 1515 * *is* another thread on the other port. 1516 * 1517 * However, the internal firmware can hold on to the NVmem 1518 * for *much* longer: at least 10 milliseconds just after a 1519 * RESET, and maybe even longer if the NVmem actually contains 1520 * code to download and run on the internal CPUs. 1521 * 1522 * So, we'll allow 50us; if that's not enough then it's up to the 1523 * caller to retry later (hence the choice of return code EAGAIN). 1524 */ 1525 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1526 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1527 1528 for (tries = 0; tries < 50; ++tries) { 1529 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1530 if (regval & NVM_WON_REQ1) 1531 break; 1532 drv_usecwait(1); 1533 } 1534 1535 if (regval & NVM_WON_REQ1) { 1536 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1537 return (0); 1538 } 1539 1540 /* 1541 * Somebody else must be accessing the NVmem, so abandon our 1542 * attempt take control of it. The caller can try again later ... 1543 */ 1544 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1545 bge_nvmem_relinquish(bgep); 1546 return (EAGAIN); 1547 } 1548 1549 /* 1550 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1551 * write protect line in such a way that the NVmem is protected when 1552 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1553 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1554 * 1555 * Note: there's only one set of GPIO pins on a 5704, even though they 1556 * can be accessed through either port. So the chip has to resolve what 1557 * happens if the two ports program a single pin differently ... the rule 1558 * it uses is that if the ports disagree about the *direction* of a pin, 1559 * "output" wins over "input", but if they disagree about its *value* as 1560 * an output, then the pin is TRISTATED instead! In such a case, no-one 1561 * wins, and the external signal does whatever the external circuitry 1562 * defines as the default -- which we've assumed is the PROTECTED state. 1563 * So, we always change GPIO1 back to being an *input* whenever we're not 1564 * specifically using it to unprotect the NVmem. This allows either port 1565 * to update the NVmem, although obviously only one at a time! 1566 * 1567 * The caller should hold <genlock> and *also* have already acquired the 1568 * right to access the NVmem, via bge_nvmem_acquire() above. 1569 */ 1570 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1571 #pragma inline(bge_nvmem_protect) 1572 1573 static void 1574 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1575 { 1576 uint32_t regval; 1577 1578 ASSERT(mutex_owned(bgep->genlock)); 1579 1580 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1581 if (protect) { 1582 regval |= MLCR_MISC_PINS_OUTPUT_1; 1583 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1584 } else { 1585 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1586 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1587 } 1588 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1589 } 1590 1591 /* 1592 * Now put it all together ... 1593 * 1594 * Try to acquire control of the NVmem; if successful, then: 1595 * unprotect it (if we want to write to it) 1596 * perform the requested access 1597 * reprotect it (after a write) 1598 * relinquish control 1599 * 1600 * Return value: 1601 * 0 on success, 1602 * EAGAIN if the device is in use (retryable) 1603 * ENODATA on access timeout (maybe retryable: device may just be busy) 1604 * ENODEV if the NVmem device is missing or otherwise unusable 1605 * EPROTO on other h/w or s/w errors. 1606 */ 1607 static int 1608 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1609 { 1610 int err; 1611 1612 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1613 switch (cmd) { 1614 case BGE_SEE_READ: 1615 err = bge_seeprom_access(bgep, 1616 SEEPROM_ACCESS_READ, addr, dp); 1617 break; 1618 1619 case BGE_SEE_WRITE: 1620 bge_nvmem_protect(bgep, B_FALSE); 1621 err = bge_seeprom_access(bgep, 1622 SEEPROM_ACCESS_WRITE, addr, dp); 1623 bge_nvmem_protect(bgep, B_TRUE); 1624 break; 1625 1626 case BGE_FLASH_READ: 1627 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1628 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1629 bge_reg_set32(bgep, NVM_ACCESS_REG, 1630 NVM_ACCESS_ENABLE); 1631 } 1632 err = bge_flash_access(bgep, 1633 NVM_FLASH_CMD_RD, addr, dp); 1634 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1635 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1636 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1637 NVM_ACCESS_ENABLE); 1638 } 1639 break; 1640 1641 case BGE_FLASH_WRITE: 1642 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1643 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1644 bge_reg_set32(bgep, NVM_ACCESS_REG, 1645 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1646 } 1647 bge_nvmem_protect(bgep, B_FALSE); 1648 err = bge_flash_access(bgep, 1649 NVM_FLASH_CMD_WR, addr, dp); 1650 bge_nvmem_protect(bgep, B_TRUE); 1651 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1652 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1653 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1654 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1655 } 1656 1657 break; 1658 1659 default: 1660 _NOTE(NOTREACHED) 1661 break; 1662 } 1663 bge_nvmem_relinquish(bgep); 1664 } 1665 1666 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1667 return (err); 1668 } 1669 1670 /* 1671 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1672 */ 1673 static uint64_t bge_get_nvmac(bge_t *bgep); 1674 #pragma no_inline(bge_get_nvmac) 1675 1676 static uint64_t 1677 bge_get_nvmac(bge_t *bgep) 1678 { 1679 uint32_t mac_high; 1680 uint32_t mac_low; 1681 uint32_t addr; 1682 uint32_t cmd; 1683 uint64_t mac; 1684 1685 BGE_TRACE(("bge_get_nvmac($%p)", 1686 (void *)bgep)); 1687 1688 switch (bgep->chipid.nvtype) { 1689 case BGE_NVTYPE_NONE: 1690 case BGE_NVTYPE_UNKNOWN: 1691 default: 1692 return (0ULL); 1693 1694 case BGE_NVTYPE_SEEPROM: 1695 case BGE_NVTYPE_LEGACY_SEEPROM: 1696 cmd = BGE_SEE_READ; 1697 break; 1698 1699 case BGE_NVTYPE_UNBUFFERED_FLASH: 1700 case BGE_NVTYPE_BUFFERED_FLASH: 1701 cmd = BGE_FLASH_READ; 1702 break; 1703 } 1704 1705 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1706 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1707 else 1708 addr = NVMEM_DATA_MAC_ADDRESS; 1709 1710 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1711 return (0ULL); 1712 addr += 4; 1713 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1714 return (0ULL); 1715 1716 /* 1717 * The Broadcom chip is natively BIG-endian, so that's how the 1718 * MAC address is represented in NVmem. We may need to swap it 1719 * around on a little-endian host ... 1720 */ 1721 #ifdef _BIG_ENDIAN 1722 mac = mac_high; 1723 mac = mac << 32; 1724 mac |= mac_low; 1725 #else 1726 mac = BGE_BSWAP_32(mac_high); 1727 mac = mac << 32; 1728 mac |= BGE_BSWAP_32(mac_low); 1729 #endif /* _BIG_ENDIAN */ 1730 1731 return (mac); 1732 } 1733 1734 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1735 1736 /* 1737 * Dummy version for when we're not supporting NVmem access 1738 */ 1739 static uint64_t bge_get_nvmac(bge_t *bgep); 1740 #pragma inline(bge_get_nvmac) 1741 1742 static uint64_t 1743 bge_get_nvmac(bge_t *bgep) 1744 { 1745 _NOTE(ARGUNUSED(bgep)) 1746 return (0ULL); 1747 } 1748 1749 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1750 1751 /* 1752 * Determine the type of NVmem that is (or may be) attached to this chip, 1753 */ 1754 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1755 #pragma no_inline(bge_nvmem_id) 1756 1757 static enum bge_nvmem_type 1758 bge_nvmem_id(bge_t *bgep) 1759 { 1760 enum bge_nvmem_type nvtype; 1761 uint32_t config1; 1762 1763 BGE_TRACE(("bge_nvmem_id($%p)", 1764 (void *)bgep)); 1765 1766 switch (bgep->chipid.device) { 1767 default: 1768 /* 1769 * We shouldn't get here; it means we don't recognise 1770 * the chip, which means we don't know how to determine 1771 * what sort of NVmem (if any) it has. So we'll say 1772 * NONE, to disable the NVmem access code ... 1773 */ 1774 nvtype = BGE_NVTYPE_NONE; 1775 break; 1776 1777 case DEVICE_ID_5700: 1778 case DEVICE_ID_5700x: 1779 case DEVICE_ID_5701: 1780 /* 1781 * These devices support *only* SEEPROMs 1782 */ 1783 nvtype = BGE_NVTYPE_SEEPROM; 1784 break; 1785 1786 case DEVICE_ID_5702: 1787 case DEVICE_ID_5702fe: 1788 case DEVICE_ID_5703C: 1789 case DEVICE_ID_5703S: 1790 case DEVICE_ID_5704C: 1791 case DEVICE_ID_5704S: 1792 case DEVICE_ID_5704: 1793 case DEVICE_ID_5705M: 1794 case DEVICE_ID_5705C: 1795 case DEVICE_ID_5705_2: 1796 case DEVICE_ID_5706: 1797 case DEVICE_ID_5780: 1798 case DEVICE_ID_5782: 1799 case DEVICE_ID_5787: 1800 case DEVICE_ID_5787M: 1801 case DEVICE_ID_5788: 1802 case DEVICE_ID_5789: 1803 case DEVICE_ID_5751: 1804 case DEVICE_ID_5751M: 1805 case DEVICE_ID_5752: 1806 case DEVICE_ID_5752M: 1807 case DEVICE_ID_5754: 1808 case DEVICE_ID_5755: 1809 case DEVICE_ID_5755M: 1810 case DEVICE_ID_5721: 1811 case DEVICE_ID_5722: 1812 case DEVICE_ID_5714C: 1813 case DEVICE_ID_5714S: 1814 case DEVICE_ID_5715C: 1815 case DEVICE_ID_5715S: 1816 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1817 if (config1 & NVM_CFG1_FLASH_MODE) 1818 if (config1 & NVM_CFG1_BUFFERED_MODE) 1819 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1820 else 1821 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1822 else 1823 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1824 break; 1825 case DEVICE_ID_5906: 1826 case DEVICE_ID_5906M: 1827 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1828 break; 1829 } 1830 1831 return (nvtype); 1832 } 1833 1834 #undef BGE_DBG 1835 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1836 1837 static void 1838 bge_init_recv_rule(bge_t *bgep) 1839 { 1840 bge_recv_rule_t *rulep; 1841 uint32_t i; 1842 1843 /* 1844 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1845 * 1. to direct UDP traffic, set: 1846 * rulep->control = RULE_PROTO_CONTROL; 1847 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1848 * 2. to direct ICMP traffic, set: 1849 * rulep->control = RULE_PROTO_CONTROL; 1850 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1851 * 3. to direct traffic by source ip, set: 1852 * rulep->control = RULE_SIP_CONTROL; 1853 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1854 */ 1855 rulep = bgep->recv_rules; 1856 rulep->control = RULE_PROTO_CONTROL; 1857 rulep->mask_value = RULE_TCP_MASK_VALUE; 1858 1859 /* 1860 * set receive rule registers 1861 */ 1862 rulep = bgep->recv_rules; 1863 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1864 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1865 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1866 } 1867 } 1868 1869 /* 1870 * Using the values captured by bge_chip_cfg_init(), and additional probes 1871 * as required, characterise the chip fully: determine the label by which 1872 * to refer to this chip, the correct settings for various registers, and 1873 * of course whether the device and/or subsystem are supported! 1874 */ 1875 int bge_chip_id_init(bge_t *bgep); 1876 #pragma no_inline(bge_chip_id_init) 1877 1878 int 1879 bge_chip_id_init(bge_t *bgep) 1880 { 1881 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1882 boolean_t sys_ok; 1883 boolean_t dev_ok; 1884 chip_id_t *cidp; 1885 uint32_t subid; 1886 char *devname; 1887 char *sysname; 1888 int *ids; 1889 int err; 1890 uint_t i; 1891 1892 sys_ok = dev_ok = B_FALSE; 1893 cidp = &bgep->chipid; 1894 1895 /* 1896 * Check the PCI device ID to determine the generic chip type and 1897 * select parameters that depend on this. 1898 * 1899 * Note: because the SPARC platforms in general don't fit the 1900 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1901 * as zero - which is why we use <asic_rev> rather than <revision> 1902 * below ... 1903 * 1904 * Note: in general we can't distinguish between the Copper/SerDes 1905 * versions by ID alone, as some Copper devices (e.g. some but not 1906 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1907 * treat them the same here, and the MII code works out the media 1908 * type later on ... 1909 */ 1910 cidp->mbuf_base = bge_mbuf_pool_base; 1911 cidp->mbuf_length = bge_mbuf_pool_len; 1912 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1913 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1914 cidp->pci_type = BGE_PCI_X; 1915 cidp->statistic_type = BGE_STAT_BLK; 1916 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1917 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1918 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1919 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1920 cidp->rx_count_norm = bge_rx_count_norm; 1921 1922 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1923 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1924 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1925 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1926 1927 cidp->msi_enabled = B_FALSE; 1928 1929 switch (cidp->device) { 1930 case DEVICE_ID_5700: 1931 case DEVICE_ID_5700x: 1932 cidp->chip_label = 5700; 1933 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1934 break; 1935 1936 case DEVICE_ID_5701: 1937 cidp->chip_label = 5701; 1938 dev_ok = B_TRUE; 1939 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1940 break; 1941 1942 case DEVICE_ID_5702: 1943 case DEVICE_ID_5702fe: 1944 cidp->chip_label = 5702; 1945 dev_ok = B_TRUE; 1946 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1947 cidp->pci_type = BGE_PCI; 1948 break; 1949 1950 case DEVICE_ID_5703C: 1951 case DEVICE_ID_5703S: 1952 case DEVICE_ID_5703: 1953 /* 1954 * Revision A0 of the 5703/5793 had various errata 1955 * that we can't or don't work around, so it's not 1956 * supported, but all later versions are 1957 */ 1958 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1959 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1960 dev_ok = B_TRUE; 1961 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1962 break; 1963 1964 case DEVICE_ID_5704C: 1965 case DEVICE_ID_5704S: 1966 case DEVICE_ID_5704: 1967 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1968 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1969 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1970 dev_ok = B_TRUE; 1971 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1972 break; 1973 1974 case DEVICE_ID_5705C: 1975 case DEVICE_ID_5705M: 1976 case DEVICE_ID_5705MA3: 1977 case DEVICE_ID_5705F: 1978 case DEVICE_ID_5705_2: 1979 case DEVICE_ID_5754: 1980 if (cidp->device == DEVICE_ID_5754) { 1981 cidp->chip_label = 5754; 1982 cidp->pci_type = BGE_PCI_E; 1983 } else { 1984 cidp->chip_label = 5705; 1985 cidp->pci_type = BGE_PCI; 1986 } 1987 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 1988 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 1989 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 1990 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1991 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1992 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1993 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1994 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 1995 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1996 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1997 cidp->statistic_type = BGE_STAT_REG; 1998 dev_ok = B_TRUE; 1999 break; 2000 2001 case DEVICE_ID_5906: 2002 case DEVICE_ID_5906M: 2003 cidp->chip_label = 5906; 2004 cidp->pci_type = BGE_PCI_E; 2005 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2006 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2007 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2008 cidp->mbuf_base = bge_mbuf_pool_base; 2009 cidp->mbuf_length = bge_mbuf_pool_len; 2010 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2011 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2012 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2013 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2014 cidp->statistic_type = BGE_STAT_REG; 2015 dev_ok = B_TRUE; 2016 break; 2017 2018 case DEVICE_ID_5753: 2019 cidp->chip_label = 5753; 2020 cidp->pci_type = BGE_PCI_E; 2021 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2022 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2023 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2024 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2025 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2026 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2027 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2028 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2029 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2030 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2031 cidp->statistic_type = BGE_STAT_REG; 2032 dev_ok = B_TRUE; 2033 break; 2034 2035 case DEVICE_ID_5755: 2036 case DEVICE_ID_5755M: 2037 cidp->chip_label = 5755; 2038 cidp->pci_type = BGE_PCI_E; 2039 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2040 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2041 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2042 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2043 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2044 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2045 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2046 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2047 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2048 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2049 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2050 cidp->statistic_type = BGE_STAT_REG; 2051 dev_ok = B_TRUE; 2052 break; 2053 2054 case DEVICE_ID_5787: 2055 case DEVICE_ID_5787M: 2056 cidp->chip_label = 5787; 2057 cidp->pci_type = BGE_PCI_E; 2058 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2059 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2060 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2061 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2062 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2063 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2064 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2065 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2066 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2067 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2068 cidp->statistic_type = BGE_STAT_REG; 2069 dev_ok = B_TRUE; 2070 break; 2071 2072 case DEVICE_ID_5706: 2073 cidp->chip_label = 5706; 2074 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2075 break; 2076 2077 case DEVICE_ID_5780: 2078 cidp->chip_label = 5780; 2079 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2080 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2081 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2082 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2083 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2084 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2085 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2086 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2087 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2088 cidp->statistic_type = BGE_STAT_REG; 2089 cidp->pci_type = BGE_PCI; 2090 dev_ok = B_TRUE; 2091 break; 2092 2093 case DEVICE_ID_5782: 2094 /* 2095 * Apart from the label, we treat this as a 5705(?) 2096 */ 2097 cidp->chip_label = 5782; 2098 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2099 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2100 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2101 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2102 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2103 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2104 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2105 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2106 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2107 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2108 cidp->statistic_type = BGE_STAT_REG; 2109 dev_ok = B_TRUE; 2110 break; 2111 2112 case DEVICE_ID_5788: 2113 /* 2114 * Apart from the label, we treat this as a 5705(?) 2115 */ 2116 cidp->chip_label = 5788; 2117 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2118 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2119 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2120 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2121 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2122 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2123 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2124 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2125 cidp->statistic_type = BGE_STAT_REG; 2126 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2127 dev_ok = B_TRUE; 2128 break; 2129 2130 case DEVICE_ID_5714C: 2131 if (cidp->revision >= REVISION_ID_5714_A2) 2132 cidp->msi_enabled = bge_enable_msi; 2133 /* FALLTHRU */ 2134 case DEVICE_ID_5714S: 2135 cidp->chip_label = 5714; 2136 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2137 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2138 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2139 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2140 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2141 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2142 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2143 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2144 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2145 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2146 cidp->pci_type = BGE_PCI_E; 2147 cidp->statistic_type = BGE_STAT_REG; 2148 dev_ok = B_TRUE; 2149 break; 2150 2151 case DEVICE_ID_5715C: 2152 case DEVICE_ID_5715S: 2153 cidp->chip_label = 5715; 2154 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2155 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2156 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2157 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2158 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2159 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2160 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2161 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2162 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2163 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2164 cidp->pci_type = BGE_PCI_E; 2165 cidp->statistic_type = BGE_STAT_REG; 2166 if (cidp->revision >= REVISION_ID_5715_A2) 2167 cidp->msi_enabled = bge_enable_msi; 2168 dev_ok = B_TRUE; 2169 break; 2170 2171 case DEVICE_ID_5721: 2172 cidp->chip_label = 5721; 2173 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2174 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2175 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2176 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2177 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2178 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2179 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2180 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2181 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2182 cidp->pci_type = BGE_PCI_E; 2183 cidp->statistic_type = BGE_STAT_REG; 2184 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2185 dev_ok = B_TRUE; 2186 break; 2187 2188 case DEVICE_ID_5722: 2189 cidp->chip_label = 5722; 2190 cidp->pci_type = BGE_PCI_E; 2191 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2192 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2193 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2194 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2195 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2196 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2197 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2198 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2199 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2200 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2201 cidp->statistic_type = BGE_STAT_REG; 2202 dev_ok = B_TRUE; 2203 break; 2204 2205 case DEVICE_ID_5751: 2206 case DEVICE_ID_5751M: 2207 cidp->chip_label = 5751; 2208 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2209 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2210 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2211 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2212 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2213 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2214 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2215 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2216 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2217 cidp->pci_type = BGE_PCI_E; 2218 cidp->statistic_type = BGE_STAT_REG; 2219 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2220 dev_ok = B_TRUE; 2221 break; 2222 2223 case DEVICE_ID_5752: 2224 case DEVICE_ID_5752M: 2225 cidp->chip_label = 5752; 2226 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2227 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2228 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2229 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2230 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2231 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2232 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2233 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2234 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2235 cidp->pci_type = BGE_PCI_E; 2236 cidp->statistic_type = BGE_STAT_REG; 2237 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2238 dev_ok = B_TRUE; 2239 break; 2240 2241 case DEVICE_ID_5789: 2242 cidp->chip_label = 5789; 2243 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2244 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2245 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2246 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2247 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2248 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2249 cidp->pci_type = BGE_PCI_E; 2250 cidp->statistic_type = BGE_STAT_REG; 2251 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2252 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2253 cidp->msi_enabled = B_TRUE; 2254 dev_ok = B_TRUE; 2255 break; 2256 2257 } 2258 2259 /* 2260 * Setup the default jumbo parameter. 2261 */ 2262 cidp->ethmax_size = ETHERMAX; 2263 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2264 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2265 2266 /* 2267 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2268 * setup below jumbo specific parameters. 2269 * 2270 * For BCM5714/5715, there is only one standard receive ring. So the 2271 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2272 * feature is enabled. 2273 */ 2274 if (bge_jumbo_enable && 2275 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2276 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2277 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2278 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2279 cidp->mbuf_lo_water_rdma = 2280 RDMA_MBUF_LOWAT_5714_JUMBO; 2281 cidp->mbuf_lo_water_rmac = 2282 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2283 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2284 cidp->jumbo_slots = 0; 2285 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2286 } else { 2287 cidp->mbuf_lo_water_rdma = 2288 RDMA_MBUF_LOWAT_JUMBO; 2289 cidp->mbuf_lo_water_rmac = 2290 MAC_RX_MBUF_LOWAT_JUMBO; 2291 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2292 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2293 } 2294 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2295 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2296 cidp->ethmax_size = cidp->default_mtu + 2297 sizeof (struct ether_header); 2298 } 2299 2300 /* 2301 * Identify the NV memory type: SEEPROM or Flash? 2302 */ 2303 cidp->nvtype = bge_nvmem_id(bgep); 2304 2305 /* 2306 * Now, we want to check whether this device is part of a 2307 * supported subsystem (e.g., on the motherboard of a Sun 2308 * branded platform). 2309 * 2310 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2311 */ 2312 if (cidp->subven == VENDOR_ID_SUN) 2313 sys_ok = B_TRUE; 2314 2315 /* 2316 * Rule 2: If it's on the list on known subsystems, then it's OK. 2317 * Note: 0x14e41647 should *not* appear in the list, but the code 2318 * doesn't enforce that. 2319 */ 2320 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2321 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2322 if (err == DDI_PROP_SUCCESS) { 2323 /* 2324 * Got the list; scan for a matching subsystem vendor/device 2325 */ 2326 subid = (cidp->subven << 16) | cidp->subdev; 2327 while (i--) 2328 if (ids[i] == subid) 2329 sys_ok = B_TRUE; 2330 ddi_prop_free(ids); 2331 } 2332 2333 /* 2334 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2335 * 2336 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2337 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2338 * we have to check specially for the exact device paths to the 2339 * motherboard devices on those platforms ;-( 2340 * 2341 * Note: we can't just use the "supported-subsystems" mechanism 2342 * above, because the entry would have to be 0x14e41647 -- which 2343 * would then accept *any* plugin card that *didn't* contain a 2344 * (valid) SEEPROM ;-( 2345 */ 2346 sysname = ddi_node_name(ddi_root_node()); 2347 devname = ddi_pathname(bgep->devinfo, buf); 2348 ASSERT(strlen(devname) > 0); 2349 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2350 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2351 sys_ok = B_TRUE; 2352 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2353 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2354 sys_ok = B_TRUE; 2355 2356 /* 2357 * Now check what we've discovered: is this truly a supported 2358 * chip on (the motherboard of) a supported platform? 2359 * 2360 * Possible problems here: 2361 * 1) it's a completely unheard-of chip (e.g. 5761) 2362 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2363 * 3) it's a chip we would support if it were on the motherboard 2364 * of a Sun platform, but this one isn't ;-( 2365 */ 2366 if (cidp->chip_label == 0) 2367 bge_problem(bgep, 2368 "Device 'pci%04x,%04x' not recognized (%d?)", 2369 cidp->vendor, cidp->device, cidp->device); 2370 else if (!dev_ok) 2371 bge_problem(bgep, 2372 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2373 cidp->vendor, cidp->device, cidp->chip_label, 2374 cidp->revision); 2375 #if BGE_DEBUGGING 2376 else if (!sys_ok) 2377 bge_problem(bgep, 2378 "%d-based subsystem 'pci%04x,%04x' not validated", 2379 cidp->chip_label, cidp->subven, cidp->subdev); 2380 #endif 2381 else 2382 cidp->flags |= CHIP_FLAG_SUPPORTED; 2383 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2384 return (EIO); 2385 return (0); 2386 } 2387 2388 void 2389 bge_chip_msi_trig(bge_t *bgep) 2390 { 2391 uint32_t regval; 2392 2393 regval = bgep->param_msi_cnt<<4; 2394 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2395 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2396 } 2397 2398 /* 2399 * Various registers that control the chip's internal engines (state 2400 * machines) have a <reset> and <enable> bits (fortunately, in the 2401 * same place in each such register :-). 2402 * 2403 * To reset the state machine, the <reset> bit must be written with 1; 2404 * it will then read back as 1 while the reset is in progress, but 2405 * self-clear to 0 when the reset completes. 2406 * 2407 * To enable a state machine, one must set the <enable> bit, which 2408 * will continue to read back as 0 until the state machine is running. 2409 * 2410 * To disable a state machine, the <enable> bit must be cleared, but 2411 * it will continue to read back as 1 until the state machine actually 2412 * stops. 2413 * 2414 * This routine implements polling for completion of a reset, enable 2415 * or disable operation, returning B_TRUE on success (bit reached the 2416 * required state) or B_FALSE on timeout (200*100us == 20ms). 2417 */ 2418 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2419 uint32_t mask, uint32_t val); 2420 #pragma no_inline(bge_chip_poll_engine) 2421 2422 static boolean_t 2423 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2424 uint32_t mask, uint32_t val) 2425 { 2426 uint32_t regval; 2427 uint32_t n; 2428 2429 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2430 (void *)bgep, regno, mask, val)); 2431 2432 for (n = 200; n; --n) { 2433 regval = bge_reg_get32(bgep, regno); 2434 if ((regval & mask) == val) 2435 return (B_TRUE); 2436 drv_usecwait(100); 2437 } 2438 2439 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2440 return (B_FALSE); 2441 } 2442 2443 /* 2444 * Various registers that control the chip's internal engines (state 2445 * machines) have a <reset> bit (fortunately, in the same place in 2446 * each such register :-). To reset the state machine, this bit must 2447 * be written with 1; it will then read back as 1 while the reset is 2448 * in progress, but self-clear to 0 when the reset completes. 2449 * 2450 * This code sets the bit, then polls for it to read back as zero. 2451 * The return value is B_TRUE on success (reset bit cleared itself), 2452 * or B_FALSE if the state machine didn't recover :( 2453 * 2454 * NOTE: the Core reset is similar to other resets, except that we 2455 * can't poll for completion, since the Core reset disables memory 2456 * access! So we just have to assume that it will all complete in 2457 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2458 */ 2459 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2460 #pragma no_inline(bge_chip_reset_engine) 2461 2462 static boolean_t 2463 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2464 { 2465 uint32_t regval; 2466 uint32_t val32; 2467 2468 regval = bge_reg_get32(bgep, regno); 2469 2470 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2471 (void *)bgep, regno)); 2472 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2473 regno, regval)); 2474 2475 regval |= STATE_MACHINE_RESET_BIT; 2476 2477 switch (regno) { 2478 case MISC_CONFIG_REG: 2479 /* 2480 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2481 * resetting PCIE block and bringing PCIE link down, bit 29 2482 * in the register needs to be set first, and then set it again 2483 * while the reset bit is written. 2484 * See:P500 of 57xx-PG102-RDS.pdf. 2485 */ 2486 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2487 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2488 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2489 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2490 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2491 if (bgep->chipid.pci_type == BGE_PCI_E) { 2492 if (bgep->chipid.asic_rev == 2493 MHCR_CHIP_REV_5751_A0 || 2494 bgep->chipid.asic_rev == 2495 MHCR_CHIP_REV_5721_A0 || 2496 bgep->chipid.asic_rev == 2497 MHCR_CHIP_REV_5755_A0) { 2498 val32 = bge_reg_get32(bgep, 2499 PHY_TEST_CTRL_REG); 2500 if (val32 == (PHY_PCIE_SCRAM_MODE | 2501 PHY_PCIE_LTASS_MODE)) 2502 bge_reg_put32(bgep, 2503 PHY_TEST_CTRL_REG, 2504 PHY_PCIE_SCRAM_MODE); 2505 val32 = pci_config_get32 2506 (bgep->cfg_handle, 2507 PCI_CONF_BGE_CLKCTL); 2508 val32 |= CLKCTL_PCIE_A0_FIX; 2509 pci_config_put32(bgep->cfg_handle, 2510 PCI_CONF_BGE_CLKCTL, val32); 2511 } 2512 bge_reg_set32(bgep, regno, 2513 MISC_CONFIG_GRC_RESET_DISABLE); 2514 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2515 } 2516 } 2517 2518 /* 2519 * Special case - causes Core reset 2520 * 2521 * On SPARC v9 we want to ensure that we don't start 2522 * timing until the I/O access has actually reached 2523 * the chip, otherwise we might make the next access 2524 * too early. And we can't just force the write out 2525 * by following it with a read (even to config space) 2526 * because that would cause the fault we're trying 2527 * to avoid. Hence the need for membar_sync() here. 2528 */ 2529 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2530 #ifdef __sparcv9 2531 membar_sync(); 2532 #endif /* __sparcv9 */ 2533 /* 2534 * On some platforms,system need about 300us for 2535 * link setup. 2536 */ 2537 drv_usecwait(300); 2538 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2539 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2540 bge_reg_clr32( 2541 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2542 } 2543 2544 if (bgep->chipid.pci_type == BGE_PCI_E) { 2545 /* PCI-E device need more reset time */ 2546 drv_usecwait(120000); 2547 2548 /* Set PCIE max payload size and clear error status. */ 2549 if ((bgep->chipid.chip_label == 5721) || 2550 (bgep->chipid.chip_label == 5751) || 2551 (bgep->chipid.chip_label == 5752) || 2552 (bgep->chipid.chip_label == 5789) || 2553 (bgep->chipid.chip_label == 5906)) { 2554 pci_config_put16(bgep->cfg_handle, 2555 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2556 pci_config_put16(bgep->cfg_handle, 2557 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2558 } 2559 } 2560 2561 BGE_PCICHK(bgep); 2562 return (B_TRUE); 2563 2564 default: 2565 bge_reg_put32(bgep, regno, regval); 2566 return (bge_chip_poll_engine(bgep, regno, 2567 STATE_MACHINE_RESET_BIT, 0)); 2568 } 2569 } 2570 2571 /* 2572 * Various registers that control the chip's internal engines (state 2573 * machines) have an <enable> bit (fortunately, in the same place in 2574 * each such register :-). To stop the state machine, this bit must 2575 * be written with 0, then polled to see when the state machine has 2576 * actually stopped. 2577 * 2578 * The return value is B_TRUE on success (enable bit cleared), or 2579 * B_FALSE if the state machine didn't stop :( 2580 */ 2581 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2582 uint32_t morebits); 2583 #pragma no_inline(bge_chip_disable_engine) 2584 2585 static boolean_t 2586 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2587 { 2588 uint32_t regval; 2589 2590 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2591 (void *)bgep, regno, morebits)); 2592 2593 switch (regno) { 2594 case FTQ_RESET_REG: 2595 /* 2596 * For Schumacher's bugfix CR6490108 2597 */ 2598 #ifdef BGE_IPMI_ASF 2599 #ifdef BGE_NETCONSOLE 2600 if (bgep->asf_enabled) 2601 return (B_TRUE); 2602 #endif 2603 #endif 2604 /* 2605 * Not quite like the others; it doesn't 2606 * have an <enable> bit, but instead we 2607 * have to set and then clear all the bits 2608 */ 2609 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2610 drv_usecwait(100); 2611 bge_reg_put32(bgep, regno, 0); 2612 return (B_TRUE); 2613 2614 default: 2615 regval = bge_reg_get32(bgep, regno); 2616 regval &= ~STATE_MACHINE_ENABLE_BIT; 2617 regval &= ~morebits; 2618 bge_reg_put32(bgep, regno, regval); 2619 return (bge_chip_poll_engine(bgep, regno, 2620 STATE_MACHINE_ENABLE_BIT, 0)); 2621 } 2622 } 2623 2624 /* 2625 * Various registers that control the chip's internal engines (state 2626 * machines) have an <enable> bit (fortunately, in the same place in 2627 * each such register :-). To start the state machine, this bit must 2628 * be written with 1, then polled to see when the state machine has 2629 * actually started. 2630 * 2631 * The return value is B_TRUE on success (enable bit set), or 2632 * B_FALSE if the state machine didn't start :( 2633 */ 2634 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2635 uint32_t morebits); 2636 #pragma no_inline(bge_chip_enable_engine) 2637 2638 static boolean_t 2639 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2640 { 2641 uint32_t regval; 2642 2643 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2644 (void *)bgep, regno, morebits)); 2645 2646 switch (regno) { 2647 case FTQ_RESET_REG: 2648 #ifdef BGE_IPMI_ASF 2649 #ifdef BGE_NETCONSOLE 2650 if (bgep->asf_enabled) 2651 return (B_TRUE); 2652 #endif 2653 #endif 2654 /* 2655 * Not quite like the others; it doesn't 2656 * have an <enable> bit, but instead we 2657 * have to set and then clear all the bits 2658 */ 2659 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2660 drv_usecwait(100); 2661 bge_reg_put32(bgep, regno, 0); 2662 return (B_TRUE); 2663 2664 default: 2665 regval = bge_reg_get32(bgep, regno); 2666 regval |= STATE_MACHINE_ENABLE_BIT; 2667 regval |= morebits; 2668 bge_reg_put32(bgep, regno, regval); 2669 return (bge_chip_poll_engine(bgep, regno, 2670 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2671 } 2672 } 2673 2674 /* 2675 * Reprogram the Ethernet, Transmit, and Receive MAC 2676 * modes to match the param_* variables 2677 */ 2678 void bge_sync_mac_modes(bge_t *bgep); 2679 #pragma no_inline(bge_sync_mac_modes) 2680 2681 void 2682 bge_sync_mac_modes(bge_t *bgep) 2683 { 2684 uint32_t macmode; 2685 uint32_t regval; 2686 2687 ASSERT(mutex_owned(bgep->genlock)); 2688 2689 /* 2690 * Reprogram the Ethernet MAC mode ... 2691 */ 2692 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2693 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2694 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2695 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2696 macmode |= ETHERNET_MODE_LINK_POLARITY; 2697 else 2698 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2699 else 2700 macmode |= ETHERNET_MODE_LINK_POLARITY; 2701 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2702 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2703 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2704 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2705 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2706 else 2707 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2708 } else if (bgep->param_link_speed == 10 || 2709 bgep->param_link_speed == 100) 2710 macmode |= ETHERNET_MODE_PORTMODE_MII; 2711 else 2712 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2713 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2714 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2715 else 2716 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2717 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2718 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2719 else 2720 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2721 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2722 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2723 (void *)bgep, regval, macmode)); 2724 2725 /* 2726 * ... the Transmit MAC mode ... 2727 */ 2728 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2729 if (bgep->param_link_tx_pause) 2730 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2731 else 2732 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2733 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2734 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2735 (void *)bgep, regval, macmode)); 2736 2737 /* 2738 * ... and the Receive MAC mode 2739 */ 2740 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2741 if (bgep->param_link_rx_pause) 2742 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2743 else 2744 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2745 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2746 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2747 (void *)bgep, regval, macmode)); 2748 } 2749 2750 /* 2751 * bge_chip_sync() -- program the chip with the unicast MAC address, 2752 * the multicast hash table, the required level of promiscuity, and 2753 * the current loopback mode ... 2754 */ 2755 #ifdef BGE_IPMI_ASF 2756 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2757 #else 2758 int bge_chip_sync(bge_t *bgep); 2759 #endif 2760 #pragma no_inline(bge_chip_sync) 2761 2762 int 2763 #ifdef BGE_IPMI_ASF 2764 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2765 #else 2766 bge_chip_sync(bge_t *bgep) 2767 #endif 2768 { 2769 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2770 boolean_t promisc; 2771 uint64_t macaddr; 2772 uint32_t fill; 2773 int i, j; 2774 int retval = DDI_SUCCESS; 2775 2776 BGE_TRACE(("bge_chip_sync($%p)", 2777 (void *)bgep)); 2778 2779 ASSERT(mutex_owned(bgep->genlock)); 2780 2781 promisc = B_FALSE; 2782 fill = ~(uint32_t)0; 2783 2784 if (bgep->promisc) 2785 promisc = B_TRUE; 2786 else 2787 fill = (uint32_t)0; 2788 2789 /* 2790 * If the TX/RX MAC engines are already running, we should stop 2791 * them (and reset the RX engine) before changing the parameters. 2792 * If they're not running, this will have no effect ... 2793 * 2794 * NOTE: this is currently disabled by default because stopping 2795 * and restarting the Tx engine may cause an outgoing packet in 2796 * transit to be truncated. Also, stopping and restarting the 2797 * Rx engine seems to not work correctly on the 5705. Testing 2798 * has not (yet!) revealed any problems with NOT stopping and 2799 * restarting these engines (and Broadcom say their drivers don't 2800 * do this), but if it is found to cause problems, this variable 2801 * can be patched to re-enable the old behaviour ... 2802 */ 2803 if (bge_stop_start_on_sync) { 2804 #ifdef BGE_IPMI_ASF 2805 if (!bgep->asf_enabled) { 2806 if (!bge_chip_disable_engine(bgep, 2807 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2808 retval = DDI_FAILURE; 2809 } else { 2810 if (!bge_chip_disable_engine(bgep, 2811 RECEIVE_MAC_MODE_REG, 0)) 2812 retval = DDI_FAILURE; 2813 } 2814 #else 2815 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2816 RECEIVE_MODE_KEEP_VLAN_TAG)) 2817 retval = DDI_FAILURE; 2818 #endif 2819 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2820 retval = DDI_FAILURE; 2821 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2822 retval = DDI_FAILURE; 2823 } 2824 2825 /* 2826 * Reprogram the hashed multicast address table ... 2827 */ 2828 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2829 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2830 2831 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2832 bge_reg_put32(bgep, MAC_HASH_REG(i), 2833 bgep->mcast_hash[i] | fill); 2834 2835 #ifdef BGE_IPMI_ASF 2836 if (!bgep->asf_enabled || !asf_keeplive) { 2837 #endif 2838 /* 2839 * Transform the MAC address(es) from host to chip format, then 2840 * reprogram the transmit random backoff seed and the unicast 2841 * MAC address(es) ... 2842 */ 2843 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2844 for (i = 0, fill = 0, macaddr = 0ull; 2845 i < ETHERADDRL; ++i) { 2846 macaddr <<= 8; 2847 macaddr |= bgep->curr_addr[j].addr[i]; 2848 fill += bgep->curr_addr[j].addr[i]; 2849 } 2850 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2851 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2852 } 2853 2854 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2855 (void *)bgep, macaddr)); 2856 #ifdef BGE_IPMI_ASF 2857 } 2858 #endif 2859 2860 /* 2861 * Set or clear the PROMISCUOUS mode bit 2862 */ 2863 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2864 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2865 2866 /* 2867 * Sync the rest of the MAC modes too ... 2868 */ 2869 bge_sync_mac_modes(bgep); 2870 2871 /* 2872 * Restart RX/TX MAC engines if required ... 2873 */ 2874 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2875 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2876 retval = DDI_FAILURE; 2877 #ifdef BGE_IPMI_ASF 2878 if (!bgep->asf_enabled) { 2879 if (!bge_chip_enable_engine(bgep, 2880 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2881 retval = DDI_FAILURE; 2882 } else { 2883 if (!bge_chip_enable_engine(bgep, 2884 RECEIVE_MAC_MODE_REG, 0)) 2885 retval = DDI_FAILURE; 2886 } 2887 #else 2888 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2889 RECEIVE_MODE_KEEP_VLAN_TAG)) 2890 retval = DDI_FAILURE; 2891 #endif 2892 } 2893 return (retval); 2894 } 2895 2896 /* 2897 * This array defines the sequence of state machine control registers 2898 * in which the <enable> bit must be cleared to bring the chip to a 2899 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2900 */ 2901 static bge_regno_t shutdown_engine_regs[] = { 2902 RECEIVE_MAC_MODE_REG, 2903 RCV_BD_INITIATOR_MODE_REG, 2904 RCV_LIST_PLACEMENT_MODE_REG, 2905 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2906 RCV_DATA_BD_INITIATOR_MODE_REG, 2907 RCV_DATA_COMPLETION_MODE_REG, 2908 RCV_BD_COMPLETION_MODE_REG, 2909 2910 SEND_BD_SELECTOR_MODE_REG, 2911 SEND_BD_INITIATOR_MODE_REG, 2912 SEND_DATA_INITIATOR_MODE_REG, 2913 READ_DMA_MODE_REG, 2914 SEND_DATA_COMPLETION_MODE_REG, 2915 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2916 SEND_BD_COMPLETION_MODE_REG, 2917 TRANSMIT_MAC_MODE_REG, 2918 2919 HOST_COALESCE_MODE_REG, 2920 WRITE_DMA_MODE_REG, 2921 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2922 FTQ_RESET_REG, /* special - see code */ 2923 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2924 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2925 BGE_REGNO_NONE /* terminator */ 2926 }; 2927 2928 #ifndef __sparc 2929 static bge_regno_t quiesce_regs[] = { 2930 READ_DMA_MODE_REG, 2931 DMA_COMPLETION_MODE_REG, 2932 WRITE_DMA_MODE_REG, 2933 BGE_REGNO_NONE 2934 }; 2935 2936 void bge_chip_stop_nonblocking(bge_t *bgep); 2937 #pragma no_inline(bge_chip_stop_nonblocking) 2938 2939 /* 2940 * This function is called by bge_quiesce(). We 2941 * turn off all the DMA engines here. 2942 */ 2943 void 2944 bge_chip_stop_nonblocking(bge_t *bgep) 2945 { 2946 bge_regno_t *rbp; 2947 2948 /* 2949 * Flag that no more activity may be initiated 2950 */ 2951 bgep->progress &= ~PROGRESS_READY; 2952 2953 rbp = quiesce_regs; 2954 while (*rbp != BGE_REGNO_NONE) { 2955 (void) bge_chip_disable_engine(bgep, *rbp, 0); 2956 ++rbp; 2957 } 2958 2959 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2960 } 2961 2962 #endif 2963 2964 /* 2965 * bge_chip_stop() -- stop all chip processing 2966 * 2967 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2968 * we've detected a problem internally; otherwise, this is a normal 2969 * (clean) stop (at user request i.e. the last STREAM has been closed). 2970 */ 2971 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2972 #pragma no_inline(bge_chip_stop) 2973 2974 void 2975 bge_chip_stop(bge_t *bgep, boolean_t fault) 2976 { 2977 bge_regno_t regno; 2978 bge_regno_t *rbp; 2979 boolean_t ok; 2980 2981 BGE_TRACE(("bge_chip_stop($%p)", 2982 (void *)bgep)); 2983 2984 ASSERT(mutex_owned(bgep->genlock)); 2985 2986 rbp = shutdown_engine_regs; 2987 /* 2988 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2989 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2990 * -ory arbiter should not be disabled. 2991 */ 2992 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2993 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2994 ok &= bge_chip_disable_engine(bgep, regno, 0); 2995 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2996 (regno != DMA_COMPLETION_MODE_REG) && 2997 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2998 (regno != BUFFER_MANAGER_MODE_REG) && 2999 (regno != MEMORY_ARBITER_MODE_REG)) 3000 ok &= bge_chip_disable_engine(bgep, 3001 regno, 0); 3002 } 3003 3004 if (!ok && !fault) 3005 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3006 3007 /* 3008 * Finally, disable (all) MAC events & clear the MAC status 3009 */ 3010 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3011 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3012 3013 /* 3014 * if we're stopping the chip because of a detected fault then do 3015 * appropriate actions 3016 */ 3017 if (fault) { 3018 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3019 bgep->bge_chip_state = BGE_CHIP_FAULT; 3020 if (!bgep->manual_reset) 3021 ddi_fm_service_impact(bgep->devinfo, 3022 DDI_SERVICE_LOST); 3023 if (bgep->bge_dma_error) { 3024 /* 3025 * need to free buffers in case the fault was 3026 * due to a memory error in a buffer - got to 3027 * do a fair bit of tidying first 3028 */ 3029 if (bgep->progress & PROGRESS_KSTATS) { 3030 bge_fini_kstats(bgep); 3031 bgep->progress &= ~PROGRESS_KSTATS; 3032 } 3033 if (bgep->progress & PROGRESS_INTR) { 3034 bge_intr_disable(bgep); 3035 rw_enter(bgep->errlock, RW_WRITER); 3036 bge_fini_rings(bgep); 3037 rw_exit(bgep->errlock); 3038 bgep->progress &= ~PROGRESS_INTR; 3039 } 3040 if (bgep->progress & PROGRESS_BUFS) { 3041 bge_free_bufs(bgep); 3042 bgep->progress &= ~PROGRESS_BUFS; 3043 } 3044 bgep->bge_dma_error = B_FALSE; 3045 } 3046 } 3047 } else 3048 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3049 } 3050 3051 /* 3052 * Poll for completion of chip's ROM firmware; also, at least on the 3053 * first time through, find and return the hardware MAC address, if any. 3054 */ 3055 static uint64_t bge_poll_firmware(bge_t *bgep); 3056 #pragma no_inline(bge_poll_firmware) 3057 3058 static uint64_t 3059 bge_poll_firmware(bge_t *bgep) 3060 { 3061 uint64_t magic; 3062 uint64_t mac; 3063 uint32_t gen, val; 3064 uint32_t i; 3065 3066 /* 3067 * Step 19: poll for firmware completion (GENCOMM port set 3068 * to the ones complement of T3_MAGIC_NUMBER). 3069 * 3070 * While we're at it, we also read the MAC address register; 3071 * at some stage the firmware will load this with the 3072 * factory-set value. 3073 * 3074 * When both the magic number and the MAC address are set, 3075 * we're done; but we impose a time limit of one second 3076 * (1000*1000us) in case the firmware fails in some fashion 3077 * or the SEEPROM that provides that MAC address isn't fitted. 3078 * 3079 * After the first time through (chip state != INITIAL), we 3080 * don't need the MAC address to be set (we've already got it 3081 * or not, from the first time), so we don't wait for it, but 3082 * we still have to wait for the T3_MAGIC_NUMBER. 3083 * 3084 * Note: the magic number is only a 32-bit quantity, but the NIC 3085 * memory is 64-bit (and big-endian) internally. Addressing the 3086 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3087 * it work correctly on both big- and little-endian hosts. 3088 */ 3089 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3090 MHCR_CHIP_ASIC_REV_5906) { 3091 for (i = 0; i < 1000; ++i) { 3092 drv_usecwait(1000); 3093 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3094 if (val & VCPU_INIT_DONE) 3095 break; 3096 } 3097 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3098 (void *)bgep, i)); 3099 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3100 } else { 3101 for (i = 0; i < 1000; ++i) { 3102 drv_usecwait(1000); 3103 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3104 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3105 drv_usecwait(100000); 3106 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3107 #ifdef BGE_IPMI_ASF 3108 if (!bgep->asf_enabled) { 3109 #endif 3110 if (gen != ~T3_MAGIC_NUMBER) 3111 continue; 3112 #ifdef BGE_IPMI_ASF 3113 } 3114 #endif 3115 if (mac != 0ULL) 3116 break; 3117 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3118 break; 3119 } 3120 } 3121 3122 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3123 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3124 (void *)bgep, gen, i)); 3125 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3126 mac, magic)); 3127 3128 return (mac); 3129 } 3130 3131 /* 3132 * Maximum times of trying to get the NVRAM access lock 3133 * by calling bge_nvmem_acquire() 3134 */ 3135 #define MAX_TRY_NVMEM_ACQUIRE 10000 3136 3137 #ifdef BGE_IPMI_ASF 3138 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3139 #else 3140 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3141 #endif 3142 #pragma no_inline(bge_chip_reset) 3143 3144 int 3145 #ifdef BGE_IPMI_ASF 3146 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3147 #else 3148 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3149 #endif 3150 { 3151 chip_id_t chipid; 3152 uint64_t mac; 3153 uint64_t magic; 3154 uint32_t modeflags; 3155 uint32_t mhcr; 3156 uint32_t sx0; 3157 uint32_t i, tries; 3158 #ifdef BGE_IPMI_ASF 3159 uint32_t mailbox; 3160 #endif 3161 int retval = DDI_SUCCESS; 3162 3163 BGE_TRACE(("bge_chip_reset($%p, %d)", 3164 (void *)bgep, enable_dma)); 3165 3166 ASSERT(mutex_owned(bgep->genlock)); 3167 3168 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3169 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3170 3171 /* 3172 * Do we need to stop the chip cleanly before resetting? 3173 */ 3174 switch (bgep->bge_chip_state) { 3175 default: 3176 _NOTE(NOTREACHED) 3177 return (DDI_FAILURE); 3178 3179 case BGE_CHIP_INITIAL: 3180 case BGE_CHIP_STOPPED: 3181 case BGE_CHIP_RESET: 3182 break; 3183 3184 case BGE_CHIP_RUNNING: 3185 case BGE_CHIP_ERROR: 3186 case BGE_CHIP_FAULT: 3187 bge_chip_stop(bgep, B_FALSE); 3188 break; 3189 } 3190 3191 #ifdef BGE_IPMI_ASF 3192 if (bgep->asf_enabled) { 3193 #ifdef __sparc 3194 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3195 MHCR_ENABLE_TAGGED_STATUS_MODE | 3196 MHCR_MASK_INTERRUPT_MODE | 3197 MHCR_MASK_PCI_INT_OUTPUT | 3198 MHCR_CLEAR_INTERRUPT_INTA | 3199 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3200 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3201 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3202 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3203 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3204 MEMORY_ARBITER_ENABLE); 3205 #endif 3206 if (asf_mode == ASF_MODE_INIT) { 3207 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3208 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3209 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3210 } 3211 } 3212 #endif 3213 /* 3214 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3215 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3216 * 3217 * Before reset Core clock,it is 3218 * also required to initialize the Memory Arbiter as specified in step9 3219 * and Misc Host Control Register as specified in step-13 3220 * Step 4-5: reset Core clock & wait for completion 3221 * Steps 6-8: are done by bge_chip_cfg_init() 3222 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3223 */ 3224 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3225 retval = DDI_FAILURE; 3226 3227 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3228 MHCR_ENABLE_TAGGED_STATUS_MODE | 3229 MHCR_MASK_INTERRUPT_MODE | 3230 MHCR_MASK_PCI_INT_OUTPUT | 3231 MHCR_CLEAR_INTERRUPT_INTA; 3232 #ifdef _BIG_ENDIAN 3233 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3234 #endif /* _BIG_ENDIAN */ 3235 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3236 #ifdef BGE_IPMI_ASF 3237 if (bgep->asf_enabled) 3238 bgep->asf_wordswapped = B_FALSE; 3239 #endif 3240 /* 3241 * NVRAM Corruption Workaround 3242 */ 3243 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3244 if (bge_nvmem_acquire(bgep) != EAGAIN) 3245 break; 3246 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3247 BGE_DEBUG(("%s: fail to acquire nvram lock", 3248 bgep->ifname)); 3249 3250 #ifdef BGE_IPMI_ASF 3251 if (!bgep->asf_enabled) { 3252 #endif 3253 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3254 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3255 #ifdef BGE_IPMI_ASF 3256 } 3257 #endif 3258 3259 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3260 retval = DDI_FAILURE; 3261 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3262 3263 /* 3264 * Step 8a: This may belong elsewhere, but BCM5721 needs 3265 * a bit set to avoid a fifo overflow/underflow bug. 3266 */ 3267 if ((bgep->chipid.chip_label == 5721) || 3268 (bgep->chipid.chip_label == 5751) || 3269 (bgep->chipid.chip_label == 5752) || 3270 (bgep->chipid.chip_label == 5755) || 3271 (bgep->chipid.chip_label == 5789) || 3272 (bgep->chipid.chip_label == 5906)) 3273 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3274 3275 3276 /* 3277 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3278 * not be changed. 3279 */ 3280 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3281 retval = DDI_FAILURE; 3282 3283 /* 3284 * Steps 10-11: configure PIO endianness options and 3285 * enable indirect register access -- already done 3286 * Steps 12-13: enable writing to the PCI state & clock 3287 * control registers -- not required; we aren't going to 3288 * use those features. 3289 * Steps 14-15: Configure DMA endianness options. See 3290 * the comments on the setting of the MHCR above. 3291 */ 3292 #ifdef _BIG_ENDIAN 3293 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3294 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3295 #else 3296 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3297 #endif /* _BIG_ENDIAN */ 3298 #ifdef BGE_IPMI_ASF 3299 if (bgep->asf_enabled) 3300 modeflags |= MODE_HOST_STACK_UP; 3301 #endif 3302 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3303 3304 #ifdef BGE_IPMI_ASF 3305 if (bgep->asf_enabled) { 3306 #ifdef __sparc 3307 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3308 MEMORY_ARBITER_ENABLE | 3309 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3310 #endif 3311 3312 #ifdef BGE_NETCONSOLE 3313 if (!bgep->asf_newhandshake) { 3314 if ((asf_mode == ASF_MODE_INIT) || 3315 (asf_mode == ASF_MODE_POST_INIT)) { 3316 bge_asf_post_reset_old_mode(bgep, 3317 BGE_INIT_RESET); 3318 } else { 3319 bge_asf_post_reset_old_mode(bgep, 3320 BGE_SHUTDOWN_RESET); 3321 } 3322 } 3323 #endif 3324 3325 /* Wait for NVRAM init */ 3326 i = 0; 3327 drv_usecwait(5000); 3328 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3329 3330 while ((mailbox != (uint32_t) 3331 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3332 (i < 10000)) { 3333 drv_usecwait(100); 3334 mailbox = bge_nic_get32(bgep, 3335 BGE_FIRMWARE_MAILBOX); 3336 i++; 3337 } 3338 3339 #ifndef BGE_NETCONSOLE 3340 if (!bgep->asf_newhandshake) { 3341 if ((asf_mode == ASF_MODE_INIT) || 3342 (asf_mode == ASF_MODE_POST_INIT)) { 3343 3344 bge_asf_post_reset_old_mode(bgep, 3345 BGE_INIT_RESET); 3346 } else { 3347 bge_asf_post_reset_old_mode(bgep, 3348 BGE_SHUTDOWN_RESET); 3349 } 3350 } 3351 #endif 3352 } 3353 #endif 3354 /* 3355 * Steps 16-17: poll for firmware completion 3356 */ 3357 mac = bge_poll_firmware(bgep); 3358 3359 /* 3360 * Step 18: enable external memory -- doesn't apply. 3361 * 3362 * However we take the opportunity to set the MLCR anyway, as 3363 * this register also controls the SEEPROM auto-access method 3364 * which we may want to use later ... 3365 * 3366 * The proper value here depends on the way the chip is wired 3367 * into the circuit board, as this register *also* controls which 3368 * of the "Miscellaneous I/O" pins are driven as outputs and the 3369 * values driven onto those pins! 3370 * 3371 * See also step 74 in the PRM ... 3372 */ 3373 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3374 bgep->chipid.bge_mlcr_default); 3375 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3376 3377 /* 3378 * Step 20: clear the Ethernet MAC mode register 3379 */ 3380 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3381 3382 /* 3383 * Step 21: restore cache-line-size, latency timer, and 3384 * subsystem ID registers to their original values (not 3385 * those read into the local structure <chipid>, 'cos 3386 * that was after they were cleared by the RESET). 3387 * 3388 * Note: the Subsystem Vendor/Device ID registers are not 3389 * directly writable in config space, so we use the shadow 3390 * copy in "Page Zero" of register space to restore them 3391 * both in one go ... 3392 */ 3393 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3394 bgep->chipid.clsize); 3395 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3396 bgep->chipid.latency); 3397 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3398 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3399 3400 /* 3401 * The SEND INDEX registers should be reset to zero by the 3402 * global chip reset; if they're not, there'll be trouble 3403 * later on. 3404 */ 3405 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3406 if (sx0 != 0) { 3407 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3408 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3409 retval = DDI_FAILURE; 3410 } 3411 3412 /* Enable MSI code */ 3413 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3414 bge_reg_set32(bgep, MSI_MODE_REG, 3415 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3416 3417 /* 3418 * On the first time through, save the factory-set MAC address 3419 * (if any). If bge_poll_firmware() above didn't return one 3420 * (from a chip register) consider looking in the attached NV 3421 * memory device, if any. Once we have it, we save it in both 3422 * register-image (64-bit) and byte-array forms. All-zero and 3423 * all-one addresses are not valid, and we refuse to stash those. 3424 */ 3425 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3426 if (mac == 0ULL) 3427 mac = bge_get_nvmac(bgep); 3428 if (mac != 0ULL && mac != ~0ULL) { 3429 bgep->chipid.hw_mac_addr = mac; 3430 for (i = ETHERADDRL; i-- != 0; ) { 3431 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3432 mac >>= 8; 3433 } 3434 bgep->chipid.vendor_addr.set = B_TRUE; 3435 } 3436 } 3437 3438 #ifdef BGE_IPMI_ASF 3439 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3440 if (asf_mode != ASF_MODE_NONE) { 3441 if ((asf_mode == ASF_MODE_INIT) || 3442 (asf_mode == ASF_MODE_POST_INIT)) { 3443 3444 bge_asf_post_reset_new_mode(bgep, 3445 BGE_INIT_RESET); 3446 } else { 3447 bge_asf_post_reset_new_mode(bgep, 3448 BGE_SHUTDOWN_RESET); 3449 } 3450 } 3451 } 3452 #endif 3453 3454 /* 3455 * Record the new state 3456 */ 3457 bgep->chip_resets += 1; 3458 bgep->bge_chip_state = BGE_CHIP_RESET; 3459 return (retval); 3460 } 3461 3462 /* 3463 * bge_chip_start() -- start the chip transmitting and/or receiving, 3464 * including enabling interrupts 3465 */ 3466 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3467 #pragma no_inline(bge_chip_start) 3468 3469 int 3470 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3471 { 3472 uint32_t coalmode; 3473 uint32_t ledctl; 3474 uint32_t mtu; 3475 uint32_t maxring; 3476 uint32_t stats_mask; 3477 uint32_t dma_wrprio; 3478 uint64_t ring; 3479 int retval = DDI_SUCCESS; 3480 3481 BGE_TRACE(("bge_chip_start($%p)", 3482 (void *)bgep)); 3483 3484 ASSERT(mutex_owned(bgep->genlock)); 3485 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3486 3487 /* 3488 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3489 * The document specifies 95 separate steps to fully 3490 * initialise the chip!!!! 3491 * 3492 * The reset code above has already got us as far as step 3493 * 21, so we continue with ... 3494 * 3495 * Step 22: clear the MAC statistics block 3496 * (0x0300-0x0aff in NIC-local memory) 3497 */ 3498 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3499 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3500 NIC_MEM_STATISTICS_SIZE); 3501 3502 /* 3503 * Step 23: clear the status block (in host memory) 3504 */ 3505 DMA_ZERO(bgep->status_block); 3506 3507 /* 3508 * Step 24: set DMA read/write control register 3509 */ 3510 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3511 bgep->chipid.bge_dma_rwctrl); 3512 3513 /* 3514 * Step 25: Configure DMA endianness -- already done (16/17) 3515 * Step 26: Configure Host-Based Send Rings 3516 * Step 27: Indicate Host Stack Up 3517 */ 3518 bge_reg_set32(bgep, MODE_CONTROL_REG, 3519 MODE_HOST_SEND_BDS | 3520 MODE_HOST_STACK_UP); 3521 3522 /* 3523 * Step 28: Configure checksum options: 3524 * Solaris supports the hardware default checksum options. 3525 * 3526 * Workaround for Incorrect pseudo-header checksum calculation. 3527 */ 3528 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3529 bge_reg_set32(bgep, MODE_CONTROL_REG, 3530 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3531 3532 /* 3533 * Step 29: configure Timer Prescaler. The value is always the 3534 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3535 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3536 * for the whole chip! 3537 */ 3538 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3539 3540 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3541 drv_usecwait(40); 3542 /* put PHY into ready state */ 3543 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3544 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3545 drv_usecwait(40); 3546 } 3547 3548 /* 3549 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3550 * 3551 * If the mbuf_length is specified as 0, we just leave these at 3552 * their hardware defaults, rather than explicitly setting them. 3553 * As the Broadcom HRM,driver better not change the parameters 3554 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3555 */ 3556 if ((bgep->chipid.mbuf_length != 0) && 3557 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3558 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3559 bgep->chipid.mbuf_base); 3560 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3561 bgep->chipid.mbuf_length); 3562 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3563 DMAD_POOL_BASE_DEFAULT); 3564 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3565 DMAD_POOL_LENGTH_DEFAULT); 3566 } 3567 3568 /* 3569 * Step 32: configure MAC memory pool watermarks 3570 */ 3571 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3572 bgep->chipid.mbuf_lo_water_rdma); 3573 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3574 bgep->chipid.mbuf_lo_water_rmac); 3575 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3576 bgep->chipid.mbuf_hi_water); 3577 3578 /* 3579 * Step 33: configure DMA resource watermarks 3580 */ 3581 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3582 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3583 bge_dmad_lo_water); 3584 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3585 bge_dmad_hi_water); 3586 } 3587 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3588 3589 /* 3590 * Steps 34-36: enable buffer manager & internal h/w queues 3591 */ 3592 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3593 STATE_MACHINE_ATTN_ENABLE_BIT)) 3594 retval = DDI_FAILURE; 3595 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3596 retval = DDI_FAILURE; 3597 3598 /* 3599 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3600 */ 3601 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3602 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3603 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3604 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3605 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3606 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3607 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3608 } 3609 3610 /* 3611 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3612 */ 3613 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3614 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3615 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3616 bge_replenish_jumbo); 3617 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3618 bge_replenish_mini); 3619 } 3620 3621 /* 3622 * Steps 41-43: clear Send Ring Producer Indices and initialise 3623 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3624 */ 3625 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3626 maxring = BGE_SEND_RINGS_MAX; 3627 else 3628 maxring = BGE_SEND_RINGS_MAX_5705; 3629 for (ring = 0; ring < maxring; ++ring) { 3630 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3631 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3632 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3633 &bgep->send[ring].hw_rcb); 3634 } 3635 3636 /* 3637 * Steps 44-45: initialise Receive Return Rings 3638 * (0x0200-0x02ff in NIC-local memory) 3639 */ 3640 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3641 maxring = BGE_RECV_RINGS_MAX; 3642 else 3643 maxring = BGE_RECV_RINGS_MAX_5705; 3644 for (ring = 0; ring < maxring; ++ring) 3645 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3646 &bgep->recv[ring].hw_rcb); 3647 3648 /* 3649 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3650 */ 3651 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3652 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3653 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3654 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3655 } 3656 /* 3657 * Step 47: configure the MAC unicast address 3658 * Step 48: configure the random backoff seed 3659 * Step 96: set up multicast filters 3660 */ 3661 #ifdef BGE_IPMI_ASF 3662 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3663 #else 3664 if (bge_chip_sync(bgep) == DDI_FAILURE) 3665 #endif 3666 retval = DDI_FAILURE; 3667 3668 /* 3669 * Step 49: configure the MTU 3670 */ 3671 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3672 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3673 3674 /* 3675 * Step 50: configure the IPG et al 3676 */ 3677 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3678 3679 /* 3680 * Step 51: configure the default Rx Return Ring 3681 */ 3682 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3683 3684 /* 3685 * Steps 52-54: configure Receive List Placement, 3686 * and enable Receive List Placement Statistics 3687 */ 3688 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3689 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3690 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3691 case MHCR_CHIP_ASIC_REV_5700: 3692 case MHCR_CHIP_ASIC_REV_5701: 3693 case MHCR_CHIP_ASIC_REV_5703: 3694 case MHCR_CHIP_ASIC_REV_5704: 3695 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3696 break; 3697 case MHCR_CHIP_ASIC_REV_5705: 3698 break; 3699 default: 3700 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3701 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3702 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3703 break; 3704 } 3705 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3706 3707 if (bgep->chipid.rx_rings > 1) 3708 bge_init_recv_rule(bgep); 3709 3710 /* 3711 * Steps 55-56: enable Send Data Initiator Statistics 3712 */ 3713 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3714 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3715 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3716 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3717 } else { 3718 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3719 SEND_INIT_STATS_ENABLE); 3720 } 3721 /* 3722 * Steps 57-58: stop (?) the Host Coalescing Engine 3723 */ 3724 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3725 retval = DDI_FAILURE; 3726 3727 /* 3728 * Steps 59-62: initialise Host Coalescing parameters 3729 */ 3730 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3731 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3732 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3733 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3734 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3735 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3736 bge_tx_count_intr); 3737 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3738 bge_tx_ticks_intr); 3739 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3740 bge_rx_count_intr); 3741 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3742 bge_rx_ticks_intr); 3743 } 3744 3745 /* 3746 * Steps 63-64: initialise status block & statistics 3747 * host memory addresses 3748 * The statistic block does not exist in some chipsets 3749 * Step 65: initialise Statistics Coalescing Tick Counter 3750 */ 3751 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3752 bgep->status_block.cookie.dmac_laddress); 3753 3754 /* 3755 * Steps 66-67: initialise status block & statistics 3756 * NIC-local memory addresses 3757 */ 3758 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3759 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3760 bgep->statistics.cookie.dmac_laddress); 3761 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3762 STATISTICS_TICKS_DEFAULT); 3763 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3764 NIC_MEM_STATUS_BLOCK); 3765 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3766 NIC_MEM_STATISTICS); 3767 } 3768 3769 /* 3770 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3771 * Completion Engine, the Receive List Placement Engine, and the 3772 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3773 * and BCM5715. 3774 */ 3775 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3776 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3777 coalmode = COALESCE_64_BYTE_STATUS; 3778 else 3779 coalmode = 0; 3780 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3781 retval = DDI_FAILURE; 3782 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3783 STATE_MACHINE_ATTN_ENABLE_BIT)) 3784 retval = DDI_FAILURE; 3785 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3786 retval = DDI_FAILURE; 3787 3788 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3789 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3790 STATE_MACHINE_ATTN_ENABLE_BIT)) 3791 retval = DDI_FAILURE; 3792 3793 /* 3794 * Step 72: Enable MAC DMA engines 3795 * Step 73: Clear & enable MAC statistics 3796 */ 3797 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3798 ETHERNET_MODE_ENABLE_FHDE | 3799 ETHERNET_MODE_ENABLE_RDE | 3800 ETHERNET_MODE_ENABLE_TDE); 3801 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3802 ETHERNET_MODE_ENABLE_TX_STATS | 3803 ETHERNET_MODE_ENABLE_RX_STATS | 3804 ETHERNET_MODE_CLEAR_TX_STATS | 3805 ETHERNET_MODE_CLEAR_RX_STATS); 3806 3807 /* 3808 * Step 74: configure the MLCR (Miscellaneous Local Control 3809 * Register); not required, as we set up the MLCR in step 10 3810 * (part of the reset code) above. 3811 * 3812 * Step 75: clear Interrupt Mailbox 0 3813 */ 3814 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3815 3816 /* 3817 * Steps 76-87: Gentlemen, start your engines ... 3818 * 3819 * Enable the DMA Completion Engine, the Write DMA Engine, 3820 * the Read DMA Engine, Receive Data Completion Engine, 3821 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3822 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3823 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3824 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3825 * 3826 * Beware exhaust fumes? 3827 */ 3828 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3829 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3830 retval = DDI_FAILURE; 3831 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3832 ALL_DMA_ATTN_BITS; 3833 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3834 MHCR_CHIP_ASIC_REV_5755) || 3835 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3836 MHCR_CHIP_ASIC_REV_5906)) { 3837 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3838 } 3839 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3840 dma_wrprio)) 3841 retval = DDI_FAILURE; 3842 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3843 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3844 retval = DDI_FAILURE; 3845 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3846 STATE_MACHINE_ATTN_ENABLE_BIT)) 3847 retval = DDI_FAILURE; 3848 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3849 if (!bge_chip_enable_engine(bgep, 3850 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3851 retval = DDI_FAILURE; 3852 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3853 retval = DDI_FAILURE; 3854 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3855 STATE_MACHINE_ATTN_ENABLE_BIT)) 3856 retval = DDI_FAILURE; 3857 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3858 RCV_BD_DISABLED_RING_ATTN)) 3859 retval = DDI_FAILURE; 3860 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3861 RCV_DATA_BD_ILL_RING_ATTN)) 3862 retval = DDI_FAILURE; 3863 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3864 retval = DDI_FAILURE; 3865 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3866 STATE_MACHINE_ATTN_ENABLE_BIT)) 3867 retval = DDI_FAILURE; 3868 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3869 STATE_MACHINE_ATTN_ENABLE_BIT)) 3870 retval = DDI_FAILURE; 3871 3872 /* 3873 * Step 88: download firmware -- doesn't apply 3874 * Steps 89-90: enable Transmit & Receive MAC Engines 3875 */ 3876 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3877 retval = DDI_FAILURE; 3878 #ifdef BGE_IPMI_ASF 3879 if (!bgep->asf_enabled) { 3880 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3881 RECEIVE_MODE_KEEP_VLAN_TAG)) 3882 retval = DDI_FAILURE; 3883 } else { 3884 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3885 retval = DDI_FAILURE; 3886 } 3887 #else 3888 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3889 RECEIVE_MODE_KEEP_VLAN_TAG)) 3890 retval = DDI_FAILURE; 3891 #endif 3892 3893 /* 3894 * Step 91: disable auto-polling of PHY status 3895 */ 3896 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3897 3898 /* 3899 * Step 92: configure D0 power state (not required) 3900 * Step 93: initialise LED control register () 3901 */ 3902 ledctl = LED_CONTROL_DEFAULT; 3903 switch (bgep->chipid.device) { 3904 case DEVICE_ID_5700: 3905 case DEVICE_ID_5700x: 3906 case DEVICE_ID_5701: 3907 /* 3908 * Switch to 5700 (MAC) mode on these older chips 3909 */ 3910 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3911 ledctl |= LED_CONTROL_LED_MODE_5700; 3912 break; 3913 3914 default: 3915 break; 3916 } 3917 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3918 3919 /* 3920 * Step 94: activate link 3921 */ 3922 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3923 3924 /* 3925 * Step 95: set up physical layer (PHY/SerDes) 3926 * restart autoneg (if required) 3927 */ 3928 if (reset_phys) 3929 if (bge_phys_update(bgep) == DDI_FAILURE) 3930 retval = DDI_FAILURE; 3931 3932 /* 3933 * Extra step (DSG): hand over all the Receive Buffers to the chip 3934 */ 3935 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3936 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3937 bgep->buff[ring].rf_next); 3938 3939 /* 3940 * MSI bits:The least significant MSI 16-bit word. 3941 * ISR will be triggered different. 3942 */ 3943 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3944 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3945 3946 /* 3947 * Extra step (DSG): select which interrupts are enabled 3948 * 3949 * Program the Ethernet MAC engine to signal attention on 3950 * Link Change events, then enable interrupts on MAC, DMA, 3951 * and FLOW attention signals. 3952 */ 3953 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3954 ETHERNET_EVENT_LINK_INT | 3955 ETHERNET_STATUS_PCS_ERROR_INT); 3956 #ifdef BGE_IPMI_ASF 3957 if (bgep->asf_enabled) { 3958 bge_reg_set32(bgep, MODE_CONTROL_REG, 3959 MODE_INT_ON_FLOW_ATTN | 3960 MODE_INT_ON_DMA_ATTN | 3961 MODE_HOST_STACK_UP| 3962 MODE_INT_ON_MAC_ATTN); 3963 } else { 3964 #endif 3965 bge_reg_set32(bgep, MODE_CONTROL_REG, 3966 MODE_INT_ON_FLOW_ATTN | 3967 MODE_INT_ON_DMA_ATTN | 3968 MODE_INT_ON_MAC_ATTN); 3969 #ifdef BGE_IPMI_ASF 3970 } 3971 #endif 3972 3973 /* 3974 * Step 97: enable PCI interrupts!!! 3975 */ 3976 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3977 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3978 MHCR_MASK_PCI_INT_OUTPUT); 3979 3980 /* 3981 * All done! 3982 */ 3983 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3984 return (retval); 3985 } 3986 3987 3988 /* 3989 * ========== Hardware interrupt handler ========== 3990 */ 3991 3992 #undef BGE_DBG 3993 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3994 3995 /* 3996 * Sync the status block, then atomically clear the specified bits in 3997 * the <flags-and-tag> field of the status block. 3998 * the <flags> word of the status block, returning the value of the 3999 * <tag> and the <flags> before the bits were cleared. 4000 */ 4001 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4002 #pragma inline(bge_status_sync) 4003 4004 static int 4005 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4006 { 4007 bge_status_t *bsp; 4008 int retval; 4009 4010 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4011 (void *)bgep, bits)); 4012 4013 ASSERT(bgep->bge_guard == BGE_GUARD); 4014 4015 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4016 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4017 if (retval != DDI_FM_OK) 4018 return (retval); 4019 4020 bsp = DMA_VPTR(bgep->status_block); 4021 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4022 4023 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4024 (void *)bgep, bits, *flags)); 4025 4026 return (retval); 4027 } 4028 4029 void bge_wake_factotum(bge_t *bgep); 4030 #pragma inline(bge_wake_factotum) 4031 4032 void 4033 bge_wake_factotum(bge_t *bgep) 4034 { 4035 mutex_enter(bgep->softintrlock); 4036 if (bgep->factotum_flag == 0) { 4037 bgep->factotum_flag = 1; 4038 ddi_trigger_softintr(bgep->factotum_id); 4039 } 4040 mutex_exit(bgep->softintrlock); 4041 } 4042 4043 /* 4044 * bge_intr() -- handle chip interrupts 4045 */ 4046 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4047 #pragma no_inline(bge_intr) 4048 4049 uint_t 4050 bge_intr(caddr_t arg1, caddr_t arg2) 4051 { 4052 bge_t *bgep = (void *)arg1; /* private device info */ 4053 bge_status_t *bsp; 4054 uint64_t flags; 4055 uint32_t regval; 4056 uint_t result; 4057 int retval, loop_cnt = 0; 4058 4059 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4060 4061 /* 4062 * GLD v2 checks that s/w setup is complete before passing 4063 * interrupts to this routine, thus eliminating the old 4064 * (and well-known) race condition around ddi_add_intr() 4065 */ 4066 ASSERT(bgep->progress & PROGRESS_HWINT); 4067 4068 result = DDI_INTR_UNCLAIMED; 4069 mutex_enter(bgep->genlock); 4070 4071 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4072 /* 4073 * Check whether chip's says it's asserting #INTA; 4074 * if not, don't process or claim the interrupt. 4075 * 4076 * Note that the PCI signal is active low, so the 4077 * bit is *zero* when the interrupt is asserted. 4078 */ 4079 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4080 if (regval & MLCR_INTA_STATE) { 4081 if (bge_check_acc_handle(bgep, bgep->io_handle) 4082 != DDI_FM_OK) 4083 goto chip_stop; 4084 mutex_exit(bgep->genlock); 4085 return (result); 4086 } 4087 4088 /* 4089 * Block further PCI interrupts ... 4090 */ 4091 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4092 MHCR_MASK_PCI_INT_OUTPUT); 4093 4094 } else { 4095 /* 4096 * Check MSI status 4097 */ 4098 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4099 if (regval & MSI_ERROR_ATTENTION) { 4100 BGE_REPORT((bgep, "msi error attention," 4101 " status=0x%x", regval)); 4102 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4103 } 4104 } 4105 4106 result = DDI_INTR_CLAIMED; 4107 4108 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4109 4110 /* 4111 * Sync the status block and grab the flags-n-tag from it. 4112 * We count the number of interrupts where there doesn't 4113 * seem to have been a DMA update of the status block; if 4114 * it *has* been updated, the counter will be cleared in 4115 * the while() loop below ... 4116 */ 4117 bgep->missed_dmas += 1; 4118 bsp = DMA_VPTR(bgep->status_block); 4119 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4120 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4121 /* 4122 * bge_chip_stop() may have freed dma area etc 4123 * while we were in this interrupt handler - 4124 * better not call bge_status_sync() 4125 */ 4126 (void) bge_check_acc_handle(bgep, 4127 bgep->io_handle); 4128 mutex_exit(bgep->genlock); 4129 return (DDI_INTR_CLAIMED); 4130 } 4131 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4132 &flags); 4133 if (retval != DDI_FM_OK) { 4134 bgep->bge_dma_error = B_TRUE; 4135 goto chip_stop; 4136 } 4137 4138 if (!(flags & STATUS_FLAG_UPDATED)) 4139 break; 4140 4141 /* 4142 * Tell the chip that we're processing the interrupt 4143 */ 4144 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4145 INTERRUPT_MBOX_DISABLE(flags)); 4146 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4147 DDI_FM_OK) 4148 goto chip_stop; 4149 4150 /* 4151 * Drop the mutex while we: 4152 * Receive any newly-arrived packets 4153 * Recycle any newly-finished send buffers 4154 */ 4155 bgep->bge_intr_running = B_TRUE; 4156 mutex_exit(bgep->genlock); 4157 bge_receive(bgep, bsp); 4158 bge_recycle(bgep, bsp); 4159 mutex_enter(bgep->genlock); 4160 bgep->bge_intr_running = B_FALSE; 4161 4162 /* 4163 * Tell the chip we've finished processing, and 4164 * give it the tag that we got from the status 4165 * block earlier, so that it knows just how far 4166 * we've gone. If it's got more for us to do, 4167 * it will now update the status block and try 4168 * to assert an interrupt (but we've got the 4169 * #INTA blocked at present). If we see the 4170 * update, we'll loop around to do some more. 4171 * Eventually we'll get out of here ... 4172 */ 4173 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4174 INTERRUPT_MBOX_ENABLE(flags)); 4175 if (bgep->chipid.pci_type == BGE_PCI_E) 4176 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4177 bgep->missed_dmas = 0; 4178 } 4179 4180 /* 4181 * Check for exceptional conditions that we need to handle 4182 * 4183 * Link status changed 4184 * Status block not updated 4185 */ 4186 if (flags & STATUS_FLAG_LINK_CHANGED) 4187 bge_wake_factotum(bgep); 4188 4189 if (bgep->missed_dmas) { 4190 /* 4191 * Probably due to the internal status tag not 4192 * being reset. Force a status block update now; 4193 * this should ensure that we get an update and 4194 * a new interrupt. After that, we should be in 4195 * sync again ... 4196 */ 4197 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4198 "not updated?", flags)); 4199 bgep->missed_updates++; 4200 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4201 COALESCE_NOW); 4202 4203 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4204 /* 4205 * If this happens multiple times in a row, 4206 * it means DMA is just not working. Maybe 4207 * the chip's failed, or maybe there's a 4208 * problem on the PCI bus or in the host-PCI 4209 * bridge (Tomatillo). 4210 * 4211 * At all events, we want to stop further 4212 * interrupts and let the recovery code take 4213 * over to see whether anything can be done 4214 * about it ... 4215 */ 4216 bge_fm_ereport(bgep, 4217 DDI_FM_DEVICE_BADINT_LIMIT); 4218 goto chip_stop; 4219 } 4220 } 4221 4222 /* 4223 * Reenable assertion of #INTA, unless there's a DMA fault 4224 */ 4225 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4226 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4227 MHCR_MASK_PCI_INT_OUTPUT); 4228 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4229 DDI_FM_OK) 4230 goto chip_stop; 4231 } 4232 4233 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4234 goto chip_stop; 4235 4236 mutex_exit(bgep->genlock); 4237 return (result); 4238 4239 chip_stop: 4240 #ifdef BGE_IPMI_ASF 4241 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4242 /* 4243 * We must stop ASF heart beat before 4244 * bge_chip_stop(), otherwise some 4245 * computers (ex. IBM HS20 blade 4246 * server) may crash. 4247 */ 4248 bge_asf_update_status(bgep); 4249 bge_asf_stop_timer(bgep); 4250 bgep->asf_status = ASF_STAT_STOP; 4251 4252 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4253 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4254 } 4255 #endif 4256 bge_chip_stop(bgep, B_TRUE); 4257 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4258 mutex_exit(bgep->genlock); 4259 return (result); 4260 } 4261 4262 /* 4263 * ========== Factotum, implemented as a softint handler ========== 4264 */ 4265 4266 #undef BGE_DBG 4267 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4268 4269 static void bge_factotum_error_handler(bge_t *bgep); 4270 #pragma no_inline(bge_factotum_error_handler) 4271 4272 static void 4273 bge_factotum_error_handler(bge_t *bgep) 4274 { 4275 uint32_t flow; 4276 uint32_t rdma; 4277 uint32_t wdma; 4278 uint32_t tmac; 4279 uint32_t rmac; 4280 uint32_t rxrs; 4281 uint32_t txrs = 0; 4282 4283 ASSERT(mutex_owned(bgep->genlock)); 4284 4285 /* 4286 * Read all the registers that show the possible 4287 * reasons for the ERROR bit to be asserted 4288 */ 4289 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4290 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4291 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4292 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4293 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4294 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4295 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4296 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4297 4298 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4299 (void *)bgep, flow, rdma, wdma)); 4300 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4301 (void *)bgep, tmac, rmac, rxrs, txrs)); 4302 4303 /* 4304 * For now, just clear all the errors ... 4305 */ 4306 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4307 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4308 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4309 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4310 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4311 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4312 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4313 } 4314 4315 /* 4316 * Handler for hardware link state change. 4317 * 4318 * When this routine is called, the hardware link state has changed 4319 * and the new state is reflected in the param_* variables. Here 4320 * we must update the softstate and reprogram the MAC to match. 4321 */ 4322 static void bge_factotum_link_handler(bge_t *bgep); 4323 #pragma no_inline(bge_factotum_link_handler) 4324 4325 static void 4326 bge_factotum_link_handler(bge_t *bgep) 4327 { 4328 ASSERT(mutex_owned(bgep->genlock)); 4329 4330 /* 4331 * Update the s/w link_state 4332 */ 4333 if (bgep->param_link_up) 4334 bgep->link_state = LINK_STATE_UP; 4335 else 4336 bgep->link_state = LINK_STATE_DOWN; 4337 4338 /* 4339 * Reprogram the MAC modes to match 4340 */ 4341 bge_sync_mac_modes(bgep); 4342 } 4343 4344 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4345 #pragma no_inline(bge_factotum_link_check) 4346 4347 static boolean_t 4348 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4349 { 4350 boolean_t check; 4351 uint64_t flags; 4352 uint32_t tmac_status; 4353 4354 ASSERT(mutex_owned(bgep->genlock)); 4355 4356 /* 4357 * Get & clear the writable status bits in the Tx status register 4358 * (some bits are write-1-to-clear, others are just readonly). 4359 */ 4360 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4361 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4362 4363 /* 4364 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4365 */ 4366 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4367 STATUS_FLAG_LINK_CHANGED, &flags); 4368 if (*dma_state != DDI_FM_OK) 4369 return (B_FALSE); 4370 4371 /* 4372 * Clear any errors flagged in the status block ... 4373 */ 4374 if (flags & STATUS_FLAG_ERROR) 4375 bge_factotum_error_handler(bgep); 4376 4377 /* 4378 * We need to check the link status if: 4379 * the status block says there's been a link change 4380 * or there's any discrepancy between the various 4381 * flags indicating the link state (link_state, 4382 * param_link_up, and the LINK STATE bit in the 4383 * Transmit MAC status register). 4384 */ 4385 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4386 switch (bgep->link_state) { 4387 case LINK_STATE_UP: 4388 check |= (bgep->param_link_up == B_FALSE); 4389 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4390 break; 4391 4392 case LINK_STATE_DOWN: 4393 check |= (bgep->param_link_up != B_FALSE); 4394 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4395 break; 4396 4397 default: 4398 check = B_TRUE; 4399 break; 4400 } 4401 4402 /* 4403 * If <check> is false, we're sure the link hasn't changed. 4404 * If true, however, it's not yet definitive; we have to call 4405 * bge_phys_check() to determine whether the link has settled 4406 * into a new state yet ... and if it has, then call the link 4407 * state change handler.But when the chip is 5700 in Dell 6650 4408 * ,even if check is false, the link may have changed.So we 4409 * have to call bge_phys_check() to determine the link state. 4410 */ 4411 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4412 check = bge_phys_check(bgep); 4413 if (check) 4414 bge_factotum_link_handler(bgep); 4415 } 4416 4417 return (check); 4418 } 4419 4420 /* 4421 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4422 */ 4423 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4424 #pragma no_inline(bge_factotum_stall_check) 4425 4426 static boolean_t 4427 bge_factotum_stall_check(bge_t *bgep) 4428 { 4429 uint32_t dogval; 4430 4431 ASSERT(mutex_owned(bgep->genlock)); 4432 4433 /* 4434 * Specific check for Tx stall ... 4435 * 4436 * The 'watchdog' counter is incremented whenever a packet 4437 * is queued, reset to 1 when some (but not all) buffers 4438 * are reclaimed, reset to 0 (disabled) when all buffers 4439 * are reclaimed, and shifted left here. If it exceeds the 4440 * threshold value, the chip is assumed to have stalled and 4441 * is put into the ERROR state. The factotum will then reset 4442 * it on the next pass. 4443 * 4444 * All of which should ensure that we don't get into a state 4445 * where packets are left pending indefinitely! 4446 */ 4447 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4448 if (dogval < bge_watchdog_count) 4449 return (B_FALSE); 4450 4451 #if !defined(BGE_NETCONSOLE) 4452 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4453 #endif 4454 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4455 return (B_TRUE); 4456 } 4457 4458 /* 4459 * The factotum is woken up when there's something to do that we'd rather 4460 * not do from inside a hardware interrupt handler or high-level cyclic. 4461 * Its two main tasks are: 4462 * reset & restart the chip after an error 4463 * check the link status whenever necessary 4464 */ 4465 uint_t bge_chip_factotum(caddr_t arg); 4466 #pragma no_inline(bge_chip_factotum) 4467 4468 uint_t 4469 bge_chip_factotum(caddr_t arg) 4470 { 4471 bge_t *bgep; 4472 uint_t result; 4473 boolean_t error; 4474 boolean_t linkchg; 4475 int dma_state; 4476 4477 bgep = (void *)arg; 4478 4479 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4480 4481 mutex_enter(bgep->softintrlock); 4482 if (bgep->factotum_flag == 0) { 4483 mutex_exit(bgep->softintrlock); 4484 return (DDI_INTR_UNCLAIMED); 4485 } 4486 bgep->factotum_flag = 0; 4487 mutex_exit(bgep->softintrlock); 4488 4489 result = DDI_INTR_CLAIMED; 4490 error = B_FALSE; 4491 linkchg = B_FALSE; 4492 4493 mutex_enter(bgep->genlock); 4494 switch (bgep->bge_chip_state) { 4495 default: 4496 break; 4497 4498 case BGE_CHIP_RUNNING: 4499 linkchg = bge_factotum_link_check(bgep, &dma_state); 4500 error = bge_factotum_stall_check(bgep); 4501 if (dma_state != DDI_FM_OK) { 4502 bgep->bge_dma_error = B_TRUE; 4503 error = B_TRUE; 4504 } 4505 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4506 error = B_TRUE; 4507 if (error) 4508 bgep->bge_chip_state = BGE_CHIP_ERROR; 4509 break; 4510 4511 case BGE_CHIP_ERROR: 4512 error = B_TRUE; 4513 break; 4514 4515 case BGE_CHIP_FAULT: 4516 /* 4517 * Fault detected, time to reset ... 4518 */ 4519 if (bge_autorecover) { 4520 if (!(bgep->progress & PROGRESS_BUFS)) { 4521 /* 4522 * if we can't allocate the ring buffers, 4523 * try later 4524 */ 4525 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4526 mutex_exit(bgep->genlock); 4527 return (result); 4528 } 4529 bgep->progress |= PROGRESS_BUFS; 4530 } 4531 if (!(bgep->progress & PROGRESS_INTR)) { 4532 bge_init_rings(bgep); 4533 bge_intr_enable(bgep); 4534 bgep->progress |= PROGRESS_INTR; 4535 } 4536 if (!(bgep->progress & PROGRESS_KSTATS)) { 4537 bge_init_kstats(bgep, 4538 ddi_get_instance(bgep->devinfo)); 4539 bgep->progress |= PROGRESS_KSTATS; 4540 } 4541 4542 BGE_REPORT((bgep, "automatic recovery activated")); 4543 4544 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4545 bgep->bge_chip_state = BGE_CHIP_ERROR; 4546 error = B_TRUE; 4547 } 4548 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4549 DDI_FM_OK) { 4550 bgep->bge_chip_state = BGE_CHIP_ERROR; 4551 error = B_TRUE; 4552 } 4553 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4554 DDI_FM_OK) { 4555 bgep->bge_chip_state = BGE_CHIP_ERROR; 4556 error = B_TRUE; 4557 } 4558 if (error == B_FALSE) { 4559 #ifdef BGE_IPMI_ASF 4560 if (bgep->asf_enabled && 4561 bgep->asf_status != ASF_STAT_RUN) { 4562 bgep->asf_timeout_id = timeout( 4563 bge_asf_heartbeat, (void *)bgep, 4564 drv_usectohz( 4565 BGE_ASF_HEARTBEAT_INTERVAL)); 4566 bgep->asf_status = ASF_STAT_RUN; 4567 } 4568 #endif 4569 if (!bgep->manual_reset) { 4570 ddi_fm_service_impact(bgep->devinfo, 4571 DDI_SERVICE_RESTORED); 4572 } 4573 } 4574 } 4575 break; 4576 } 4577 4578 4579 /* 4580 * If an error is detected, stop the chip now, marking it as 4581 * faulty, so that it will be reset next time through ... 4582 * 4583 * Note that if intr_running is set, then bge_intr() has dropped 4584 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4585 * this point so have to wait until the next time the factotum runs. 4586 */ 4587 if (error && !bgep->bge_intr_running) { 4588 #ifdef BGE_IPMI_ASF 4589 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4590 /* 4591 * We must stop ASF heart beat before bge_chip_stop(), 4592 * otherwise some computers (ex. IBM HS20 blade server) 4593 * may crash. 4594 */ 4595 bge_asf_update_status(bgep); 4596 bge_asf_stop_timer(bgep); 4597 bgep->asf_status = ASF_STAT_STOP; 4598 4599 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4600 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4601 } 4602 #endif 4603 bge_chip_stop(bgep, B_TRUE); 4604 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4605 } 4606 mutex_exit(bgep->genlock); 4607 4608 /* 4609 * If the link state changed, tell the world about it. 4610 * Note: can't do this while still holding the mutex. 4611 */ 4612 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4613 bgep->link_state != LINK_STATE_UNKNOWN) 4614 linkchg = B_TRUE; 4615 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4616 bgep->link_state == LINK_STATE_DOWN) 4617 linkchg = B_FALSE; 4618 4619 if (linkchg) { 4620 mac_link_update(bgep->mh, bgep->link_state); 4621 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4622 } 4623 if (bgep->manual_reset) { 4624 bgep->manual_reset = B_FALSE; 4625 } 4626 4627 return (result); 4628 } 4629 4630 /* 4631 * High-level cyclic handler 4632 * 4633 * This routine schedules a (low-level) softint callback to the 4634 * factotum, and prods the chip to update the status block (which 4635 * will cause a hardware interrupt when complete). 4636 */ 4637 void bge_chip_cyclic(void *arg); 4638 #pragma no_inline(bge_chip_cyclic) 4639 4640 void 4641 bge_chip_cyclic(void *arg) 4642 { 4643 bge_t *bgep; 4644 4645 bgep = arg; 4646 4647 switch (bgep->bge_chip_state) { 4648 default: 4649 return; 4650 4651 case BGE_CHIP_RUNNING: 4652 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4653 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4654 ddi_fm_service_impact(bgep->devinfo, 4655 DDI_SERVICE_UNAFFECTED); 4656 4657 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4658 bgep->link_update_timer++; 4659 4660 break; 4661 4662 case BGE_CHIP_FAULT: 4663 case BGE_CHIP_ERROR: 4664 break; 4665 } 4666 4667 bge_wake_factotum(bgep); 4668 } 4669 4670 4671 /* 4672 * ========== Ioctl subfunctions ========== 4673 */ 4674 4675 #undef BGE_DBG 4676 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4677 4678 #if BGE_DEBUGGING || BGE_DO_PPIO 4679 4680 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4681 #pragma no_inline(bge_chip_peek_cfg) 4682 4683 static void 4684 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4685 { 4686 uint64_t regval; 4687 uint64_t regno; 4688 4689 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4690 (void *)bgep, (void *)ppd)); 4691 4692 regno = ppd->pp_acc_offset; 4693 4694 switch (ppd->pp_acc_size) { 4695 case 1: 4696 regval = pci_config_get8(bgep->cfg_handle, regno); 4697 break; 4698 4699 case 2: 4700 regval = pci_config_get16(bgep->cfg_handle, regno); 4701 break; 4702 4703 case 4: 4704 regval = pci_config_get32(bgep->cfg_handle, regno); 4705 break; 4706 4707 case 8: 4708 regval = pci_config_get64(bgep->cfg_handle, regno); 4709 break; 4710 } 4711 4712 ppd->pp_acc_data = regval; 4713 } 4714 4715 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4716 #pragma no_inline(bge_chip_poke_cfg) 4717 4718 static void 4719 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4720 { 4721 uint64_t regval; 4722 uint64_t regno; 4723 4724 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4725 (void *)bgep, (void *)ppd)); 4726 4727 regno = ppd->pp_acc_offset; 4728 regval = ppd->pp_acc_data; 4729 4730 switch (ppd->pp_acc_size) { 4731 case 1: 4732 pci_config_put8(bgep->cfg_handle, regno, regval); 4733 break; 4734 4735 case 2: 4736 pci_config_put16(bgep->cfg_handle, regno, regval); 4737 break; 4738 4739 case 4: 4740 pci_config_put32(bgep->cfg_handle, regno, regval); 4741 break; 4742 4743 case 8: 4744 pci_config_put64(bgep->cfg_handle, regno, regval); 4745 break; 4746 } 4747 } 4748 4749 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4750 #pragma no_inline(bge_chip_peek_reg) 4751 4752 static void 4753 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4754 { 4755 uint64_t regval; 4756 void *regaddr; 4757 4758 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4759 (void *)bgep, (void *)ppd)); 4760 4761 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4762 4763 switch (ppd->pp_acc_size) { 4764 case 1: 4765 regval = ddi_get8(bgep->io_handle, regaddr); 4766 break; 4767 4768 case 2: 4769 regval = ddi_get16(bgep->io_handle, regaddr); 4770 break; 4771 4772 case 4: 4773 regval = ddi_get32(bgep->io_handle, regaddr); 4774 break; 4775 4776 case 8: 4777 regval = ddi_get64(bgep->io_handle, regaddr); 4778 break; 4779 } 4780 4781 ppd->pp_acc_data = regval; 4782 } 4783 4784 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4785 #pragma no_inline(bge_chip_peek_reg) 4786 4787 static void 4788 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4789 { 4790 uint64_t regval; 4791 void *regaddr; 4792 4793 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4794 (void *)bgep, (void *)ppd)); 4795 4796 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4797 regval = ppd->pp_acc_data; 4798 4799 switch (ppd->pp_acc_size) { 4800 case 1: 4801 ddi_put8(bgep->io_handle, regaddr, regval); 4802 break; 4803 4804 case 2: 4805 ddi_put16(bgep->io_handle, regaddr, regval); 4806 break; 4807 4808 case 4: 4809 ddi_put32(bgep->io_handle, regaddr, regval); 4810 break; 4811 4812 case 8: 4813 ddi_put64(bgep->io_handle, regaddr, regval); 4814 break; 4815 } 4816 BGE_PCICHK(bgep); 4817 } 4818 4819 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4820 #pragma no_inline(bge_chip_peek_nic) 4821 4822 static void 4823 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4824 { 4825 uint64_t regoff; 4826 uint64_t regval; 4827 void *regaddr; 4828 4829 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4830 (void *)bgep, (void *)ppd)); 4831 4832 regoff = ppd->pp_acc_offset; 4833 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4834 regoff &= MWBAR_GRANULE_MASK; 4835 regoff += NIC_MEM_WINDOW_OFFSET; 4836 regaddr = PIO_ADDR(bgep, regoff); 4837 4838 switch (ppd->pp_acc_size) { 4839 case 1: 4840 regval = ddi_get8(bgep->io_handle, regaddr); 4841 break; 4842 4843 case 2: 4844 regval = ddi_get16(bgep->io_handle, regaddr); 4845 break; 4846 4847 case 4: 4848 regval = ddi_get32(bgep->io_handle, regaddr); 4849 break; 4850 4851 case 8: 4852 regval = ddi_get64(bgep->io_handle, regaddr); 4853 break; 4854 } 4855 4856 ppd->pp_acc_data = regval; 4857 } 4858 4859 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4860 #pragma no_inline(bge_chip_poke_nic) 4861 4862 static void 4863 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4864 { 4865 uint64_t regoff; 4866 uint64_t regval; 4867 void *regaddr; 4868 4869 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4870 (void *)bgep, (void *)ppd)); 4871 4872 regoff = ppd->pp_acc_offset; 4873 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4874 regoff &= MWBAR_GRANULE_MASK; 4875 regoff += NIC_MEM_WINDOW_OFFSET; 4876 regaddr = PIO_ADDR(bgep, regoff); 4877 regval = ppd->pp_acc_data; 4878 4879 switch (ppd->pp_acc_size) { 4880 case 1: 4881 ddi_put8(bgep->io_handle, regaddr, regval); 4882 break; 4883 4884 case 2: 4885 ddi_put16(bgep->io_handle, regaddr, regval); 4886 break; 4887 4888 case 4: 4889 ddi_put32(bgep->io_handle, regaddr, regval); 4890 break; 4891 4892 case 8: 4893 ddi_put64(bgep->io_handle, regaddr, regval); 4894 break; 4895 } 4896 BGE_PCICHK(bgep); 4897 } 4898 4899 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4900 #pragma no_inline(bge_chip_peek_mii) 4901 4902 static void 4903 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4904 { 4905 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4906 (void *)bgep, (void *)ppd)); 4907 4908 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4909 } 4910 4911 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4912 #pragma no_inline(bge_chip_poke_mii) 4913 4914 static void 4915 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4916 { 4917 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4918 (void *)bgep, (void *)ppd)); 4919 4920 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4921 } 4922 4923 #if BGE_SEE_IO32 4924 4925 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4926 #pragma no_inline(bge_chip_peek_seeprom) 4927 4928 static void 4929 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4930 { 4931 uint32_t data; 4932 int err; 4933 4934 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4935 (void *)bgep, (void *)ppd)); 4936 4937 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4938 ppd->pp_acc_data = err ? ~0ull : data; 4939 } 4940 4941 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4942 #pragma no_inline(bge_chip_poke_seeprom) 4943 4944 static void 4945 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4946 { 4947 uint32_t data; 4948 4949 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4950 (void *)bgep, (void *)ppd)); 4951 4952 data = ppd->pp_acc_data; 4953 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4954 } 4955 #endif /* BGE_SEE_IO32 */ 4956 4957 #if BGE_FLASH_IO32 4958 4959 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4960 #pragma no_inline(bge_chip_peek_flash) 4961 4962 static void 4963 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4964 { 4965 uint32_t data; 4966 int err; 4967 4968 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4969 (void *)bgep, (void *)ppd)); 4970 4971 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4972 ppd->pp_acc_data = err ? ~0ull : data; 4973 } 4974 4975 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4976 #pragma no_inline(bge_chip_poke_flash) 4977 4978 static void 4979 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4980 { 4981 uint32_t data; 4982 4983 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4984 (void *)bgep, (void *)ppd)); 4985 4986 data = ppd->pp_acc_data; 4987 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4988 ppd->pp_acc_offset, &data); 4989 } 4990 #endif /* BGE_FLASH_IO32 */ 4991 4992 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4993 #pragma no_inline(bge_chip_peek_mem) 4994 4995 static void 4996 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4997 { 4998 uint64_t regval; 4999 void *vaddr; 5000 5001 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5002 (void *)bgep, (void *)ppd)); 5003 5004 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5005 5006 switch (ppd->pp_acc_size) { 5007 case 1: 5008 regval = *(uint8_t *)vaddr; 5009 break; 5010 5011 case 2: 5012 regval = *(uint16_t *)vaddr; 5013 break; 5014 5015 case 4: 5016 regval = *(uint32_t *)vaddr; 5017 break; 5018 5019 case 8: 5020 regval = *(uint64_t *)vaddr; 5021 break; 5022 } 5023 5024 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5025 (void *)bgep, (void *)ppd, regval, vaddr)); 5026 5027 ppd->pp_acc_data = regval; 5028 } 5029 5030 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5031 #pragma no_inline(bge_chip_poke_mem) 5032 5033 static void 5034 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5035 { 5036 uint64_t regval; 5037 void *vaddr; 5038 5039 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5040 (void *)bgep, (void *)ppd)); 5041 5042 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5043 regval = ppd->pp_acc_data; 5044 5045 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5046 (void *)bgep, (void *)ppd, regval, vaddr)); 5047 5048 switch (ppd->pp_acc_size) { 5049 case 1: 5050 *(uint8_t *)vaddr = (uint8_t)regval; 5051 break; 5052 5053 case 2: 5054 *(uint16_t *)vaddr = (uint16_t)regval; 5055 break; 5056 5057 case 4: 5058 *(uint32_t *)vaddr = (uint32_t)regval; 5059 break; 5060 5061 case 8: 5062 *(uint64_t *)vaddr = (uint64_t)regval; 5063 break; 5064 } 5065 } 5066 5067 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5068 struct iocblk *iocp); 5069 #pragma no_inline(bge_pp_ioctl) 5070 5071 static enum ioc_reply 5072 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5073 { 5074 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5075 bge_peekpoke_t *ppd; 5076 dma_area_t *areap; 5077 uint64_t sizemask; 5078 uint64_t mem_va; 5079 uint64_t maxoff; 5080 boolean_t peek; 5081 5082 switch (cmd) { 5083 default: 5084 /* NOTREACHED */ 5085 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5086 return (IOC_INVAL); 5087 5088 case BGE_PEEK: 5089 peek = B_TRUE; 5090 break; 5091 5092 case BGE_POKE: 5093 peek = B_FALSE; 5094 break; 5095 } 5096 5097 /* 5098 * Validate format of ioctl 5099 */ 5100 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5101 return (IOC_INVAL); 5102 if (mp->b_cont == NULL) 5103 return (IOC_INVAL); 5104 ppd = (void *)mp->b_cont->b_rptr; 5105 5106 /* 5107 * Validate request parameters 5108 */ 5109 switch (ppd->pp_acc_space) { 5110 default: 5111 return (IOC_INVAL); 5112 5113 case BGE_PP_SPACE_CFG: 5114 /* 5115 * Config space 5116 */ 5117 sizemask = 8|4|2|1; 5118 mem_va = 0; 5119 maxoff = PCI_CONF_HDR_SIZE; 5120 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5121 break; 5122 5123 case BGE_PP_SPACE_REG: 5124 /* 5125 * Memory-mapped I/O space 5126 */ 5127 sizemask = 8|4|2|1; 5128 mem_va = 0; 5129 maxoff = RIAAR_REGISTER_MAX; 5130 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5131 break; 5132 5133 case BGE_PP_SPACE_NIC: 5134 /* 5135 * NIC on-chip memory 5136 */ 5137 sizemask = 8|4|2|1; 5138 mem_va = 0; 5139 maxoff = MWBAR_ONCHIP_MAX; 5140 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5141 break; 5142 5143 case BGE_PP_SPACE_MII: 5144 /* 5145 * PHY's MII registers 5146 * NB: all PHY registers are two bytes, but the 5147 * addresses increment in ones (word addressing). 5148 * So we scale the address here, then undo the 5149 * transformation inside the peek/poke functions. 5150 */ 5151 ppd->pp_acc_offset *= 2; 5152 sizemask = 2; 5153 mem_va = 0; 5154 maxoff = (MII_MAXREG+1)*2; 5155 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5156 break; 5157 5158 #if BGE_SEE_IO32 5159 case BGE_PP_SPACE_SEEPROM: 5160 /* 5161 * Attached SEEPROM(s), if any. 5162 * NB: we use the high-order bits of the 'address' as 5163 * a device select to accommodate multiple SEEPROMS, 5164 * If each one is the maximum size (64kbytes), this 5165 * makes them appear contiguous. Otherwise, there may 5166 * be holes in the mapping. ENxS doesn't have any 5167 * SEEPROMs anyway ... 5168 */ 5169 sizemask = 4; 5170 mem_va = 0; 5171 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5172 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5173 break; 5174 #endif /* BGE_SEE_IO32 */ 5175 5176 #if BGE_FLASH_IO32 5177 case BGE_PP_SPACE_FLASH: 5178 /* 5179 * Attached Flash device (if any); a maximum of one device 5180 * is currently supported. But it can be up to 1MB (unlike 5181 * the 64k limit on SEEPROMs) so why would you need more ;-) 5182 */ 5183 sizemask = 4; 5184 mem_va = 0; 5185 maxoff = NVM_FLASH_ADDR_MASK; 5186 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5187 break; 5188 #endif /* BGE_FLASH_IO32 */ 5189 5190 case BGE_PP_SPACE_BGE: 5191 /* 5192 * BGE data structure! 5193 */ 5194 sizemask = 8|4|2|1; 5195 mem_va = (uintptr_t)bgep; 5196 maxoff = sizeof (*bgep); 5197 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5198 break; 5199 5200 case BGE_PP_SPACE_STATUS: 5201 case BGE_PP_SPACE_STATISTICS: 5202 case BGE_PP_SPACE_TXDESC: 5203 case BGE_PP_SPACE_TXBUFF: 5204 case BGE_PP_SPACE_RXDESC: 5205 case BGE_PP_SPACE_RXBUFF: 5206 /* 5207 * Various DMA_AREAs 5208 */ 5209 switch (ppd->pp_acc_space) { 5210 case BGE_PP_SPACE_TXDESC: 5211 areap = &bgep->tx_desc; 5212 break; 5213 case BGE_PP_SPACE_TXBUFF: 5214 areap = &bgep->tx_buff[0]; 5215 break; 5216 case BGE_PP_SPACE_RXDESC: 5217 areap = &bgep->rx_desc[0]; 5218 break; 5219 case BGE_PP_SPACE_RXBUFF: 5220 areap = &bgep->rx_buff[0]; 5221 break; 5222 case BGE_PP_SPACE_STATUS: 5223 areap = &bgep->status_block; 5224 break; 5225 case BGE_PP_SPACE_STATISTICS: 5226 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5227 areap = &bgep->statistics; 5228 break; 5229 } 5230 5231 sizemask = 8|4|2|1; 5232 mem_va = (uintptr_t)areap->mem_va; 5233 maxoff = areap->alength; 5234 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5235 break; 5236 } 5237 5238 switch (ppd->pp_acc_size) { 5239 default: 5240 return (IOC_INVAL); 5241 5242 case 8: 5243 case 4: 5244 case 2: 5245 case 1: 5246 if ((ppd->pp_acc_size & sizemask) == 0) 5247 return (IOC_INVAL); 5248 break; 5249 } 5250 5251 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5252 return (IOC_INVAL); 5253 5254 if (ppd->pp_acc_offset >= maxoff) 5255 return (IOC_INVAL); 5256 5257 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5258 return (IOC_INVAL); 5259 5260 /* 5261 * All OK - go do it! 5262 */ 5263 ppd->pp_acc_offset += mem_va; 5264 (*ppfn)(bgep, ppd); 5265 return (peek ? IOC_REPLY : IOC_ACK); 5266 } 5267 5268 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5269 struct iocblk *iocp); 5270 #pragma no_inline(bge_diag_ioctl) 5271 5272 static enum ioc_reply 5273 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5274 { 5275 ASSERT(mutex_owned(bgep->genlock)); 5276 5277 switch (cmd) { 5278 default: 5279 /* NOTREACHED */ 5280 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5281 return (IOC_INVAL); 5282 5283 case BGE_DIAG: 5284 /* 5285 * Currently a no-op 5286 */ 5287 return (IOC_ACK); 5288 5289 case BGE_PEEK: 5290 case BGE_POKE: 5291 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5292 5293 case BGE_PHY_RESET: 5294 return (IOC_RESTART_ACK); 5295 5296 case BGE_SOFT_RESET: 5297 case BGE_HARD_RESET: 5298 /* 5299 * Reset and reinitialise the 570x hardware 5300 */ 5301 bgep->bge_chip_state = BGE_CHIP_FAULT; 5302 ddi_trigger_softintr(bgep->factotum_id); 5303 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5304 return (IOC_ACK); 5305 } 5306 5307 /* NOTREACHED */ 5308 } 5309 5310 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5311 5312 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5313 struct iocblk *iocp); 5314 #pragma no_inline(bge_mii_ioctl) 5315 5316 static enum ioc_reply 5317 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5318 { 5319 struct bge_mii_rw *miirwp; 5320 5321 /* 5322 * Validate format of ioctl 5323 */ 5324 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5325 return (IOC_INVAL); 5326 if (mp->b_cont == NULL) 5327 return (IOC_INVAL); 5328 miirwp = (void *)mp->b_cont->b_rptr; 5329 5330 /* 5331 * Validate request parameters ... 5332 */ 5333 if (miirwp->mii_reg > MII_MAXREG) 5334 return (IOC_INVAL); 5335 5336 switch (cmd) { 5337 default: 5338 /* NOTREACHED */ 5339 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5340 return (IOC_INVAL); 5341 5342 case BGE_MII_READ: 5343 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5344 return (IOC_REPLY); 5345 5346 case BGE_MII_WRITE: 5347 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5348 return (IOC_ACK); 5349 } 5350 5351 /* NOTREACHED */ 5352 } 5353 5354 #if BGE_SEE_IO32 5355 5356 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5357 struct iocblk *iocp); 5358 #pragma no_inline(bge_see_ioctl) 5359 5360 static enum ioc_reply 5361 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5362 { 5363 struct bge_see_rw *seerwp; 5364 5365 /* 5366 * Validate format of ioctl 5367 */ 5368 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5369 return (IOC_INVAL); 5370 if (mp->b_cont == NULL) 5371 return (IOC_INVAL); 5372 seerwp = (void *)mp->b_cont->b_rptr; 5373 5374 /* 5375 * Validate request parameters ... 5376 */ 5377 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5378 return (IOC_INVAL); 5379 5380 switch (cmd) { 5381 default: 5382 /* NOTREACHED */ 5383 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5384 return (IOC_INVAL); 5385 5386 case BGE_SEE_READ: 5387 case BGE_SEE_WRITE: 5388 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5389 seerwp->see_addr, &seerwp->see_data); 5390 return (IOC_REPLY); 5391 } 5392 5393 /* NOTREACHED */ 5394 } 5395 5396 #endif /* BGE_SEE_IO32 */ 5397 5398 #if BGE_FLASH_IO32 5399 5400 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5401 struct iocblk *iocp); 5402 #pragma no_inline(bge_flash_ioctl) 5403 5404 static enum ioc_reply 5405 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5406 { 5407 struct bge_flash_rw *flashrwp; 5408 5409 /* 5410 * Validate format of ioctl 5411 */ 5412 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5413 return (IOC_INVAL); 5414 if (mp->b_cont == NULL) 5415 return (IOC_INVAL); 5416 flashrwp = (void *)mp->b_cont->b_rptr; 5417 5418 /* 5419 * Validate request parameters ... 5420 */ 5421 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5422 return (IOC_INVAL); 5423 5424 switch (cmd) { 5425 default: 5426 /* NOTREACHED */ 5427 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5428 return (IOC_INVAL); 5429 5430 case BGE_FLASH_READ: 5431 case BGE_FLASH_WRITE: 5432 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5433 flashrwp->flash_addr, &flashrwp->flash_data); 5434 return (IOC_REPLY); 5435 } 5436 5437 /* NOTREACHED */ 5438 } 5439 5440 #endif /* BGE_FLASH_IO32 */ 5441 5442 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5443 struct iocblk *iocp); 5444 #pragma no_inline(bge_chip_ioctl) 5445 5446 enum ioc_reply 5447 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5448 { 5449 int cmd; 5450 5451 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5452 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5453 5454 ASSERT(mutex_owned(bgep->genlock)); 5455 5456 cmd = iocp->ioc_cmd; 5457 switch (cmd) { 5458 default: 5459 /* NOTREACHED */ 5460 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5461 return (IOC_INVAL); 5462 5463 case BGE_DIAG: 5464 case BGE_PEEK: 5465 case BGE_POKE: 5466 case BGE_PHY_RESET: 5467 case BGE_SOFT_RESET: 5468 case BGE_HARD_RESET: 5469 #if BGE_DEBUGGING || BGE_DO_PPIO 5470 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5471 #else 5472 return (IOC_INVAL); 5473 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5474 5475 case BGE_MII_READ: 5476 case BGE_MII_WRITE: 5477 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5478 5479 #if BGE_SEE_IO32 5480 case BGE_SEE_READ: 5481 case BGE_SEE_WRITE: 5482 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5483 #endif /* BGE_SEE_IO32 */ 5484 5485 #if BGE_FLASH_IO32 5486 case BGE_FLASH_READ: 5487 case BGE_FLASH_WRITE: 5488 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5489 #endif /* BGE_FLASH_IO32 */ 5490 } 5491 5492 /* NOTREACHED */ 5493 } 5494 5495 void 5496 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5497 { 5498 bge_t *bgep = arg; 5499 5500 mutex_enter(bgep->genlock); 5501 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5502 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5503 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5504 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5505 mutex_exit(bgep->genlock); 5506 } 5507 5508 #ifdef BGE_IPMI_ASF 5509 5510 uint32_t 5511 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5512 { 5513 uint32_t data; 5514 5515 #ifndef __sparc 5516 if (!bgep->asf_wordswapped) { 5517 /* a workaround word swap error */ 5518 if (addr & 4) 5519 addr = addr - 4; 5520 else 5521 addr = addr + 4; 5522 } 5523 #endif 5524 5525 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5526 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5527 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5528 5529 data = LE_32(data); 5530 return (data); 5531 } 5532 5533 void 5534 bge_asf_update_status(bge_t *bgep) 5535 { 5536 uint32_t event; 5537 5538 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5539 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5540 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5541 5542 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5543 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5544 } 5545 5546 5547 /* 5548 * The driver is supposed to notify ASF that the OS is still running 5549 * every three seconds, otherwise the management server may attempt 5550 * to reboot the machine. If it hasn't actually failed, this is 5551 * not a desirable result. However, this isn't running as a real-time 5552 * thread, and even if it were, it might not be able to generate the 5553 * heartbeat in a timely manner due to system load. As it isn't a 5554 * significant strain on the machine, we will set the interval to half 5555 * of the required value. 5556 */ 5557 void 5558 bge_asf_heartbeat(void *arg) 5559 { 5560 bge_t *bgep = (bge_t *)arg; 5561 5562 mutex_enter(bgep->genlock); 5563 bge_asf_update_status((bge_t *)bgep); 5564 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5565 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5566 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5567 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5568 mutex_exit(bgep->genlock); 5569 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5570 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5571 } 5572 5573 5574 void 5575 bge_asf_stop_timer(bge_t *bgep) 5576 { 5577 timeout_id_t tmp_id = 0; 5578 5579 while ((bgep->asf_timeout_id != 0) && 5580 (tmp_id != bgep->asf_timeout_id)) { 5581 tmp_id = bgep->asf_timeout_id; 5582 (void) untimeout(tmp_id); 5583 } 5584 bgep->asf_timeout_id = 0; 5585 } 5586 5587 5588 5589 /* 5590 * This function should be placed at the earliest position of bge_attach(). 5591 */ 5592 void 5593 bge_asf_get_config(bge_t *bgep) 5594 { 5595 uint32_t nicsig; 5596 uint32_t niccfg; 5597 5598 bgep->asf_enabled = B_FALSE; 5599 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5600 if (nicsig == BGE_NIC_DATA_SIG) { 5601 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5602 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5603 /* 5604 * Here, we don't consider BAXTER, because BGE haven't 5605 * supported BAXTER (that is 5752). Also, as I know, 5606 * BAXTER doesn't support ASF feature. 5607 */ 5608 bgep->asf_enabled = B_TRUE; 5609 else 5610 bgep->asf_enabled = B_FALSE; 5611 } else 5612 bgep->asf_enabled = B_FALSE; 5613 } 5614 5615 5616 void 5617 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5618 { 5619 uint32_t tries; 5620 uint32_t event; 5621 5622 ASSERT(bgep->asf_enabled); 5623 5624 /* Issues "pause firmware" command and wait for ACK */ 5625 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5626 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5627 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5628 5629 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5630 tries = 0; 5631 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5632 drv_usecwait(1); 5633 tries ++; 5634 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5635 } 5636 5637 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5638 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5639 5640 if (bgep->asf_newhandshake) { 5641 switch (mode) { 5642 case BGE_INIT_RESET: 5643 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5644 BGE_DRV_STATE_START); 5645 break; 5646 case BGE_SHUTDOWN_RESET: 5647 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5648 BGE_DRV_STATE_UNLOAD); 5649 break; 5650 case BGE_SUSPEND_RESET: 5651 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5652 BGE_DRV_STATE_SUSPEND); 5653 break; 5654 default: 5655 break; 5656 } 5657 } 5658 } 5659 5660 5661 void 5662 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5663 { 5664 switch (mode) { 5665 case BGE_INIT_RESET: 5666 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5667 BGE_DRV_STATE_START); 5668 break; 5669 case BGE_SHUTDOWN_RESET: 5670 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5671 BGE_DRV_STATE_UNLOAD); 5672 break; 5673 case BGE_SUSPEND_RESET: 5674 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5675 BGE_DRV_STATE_SUSPEND); 5676 break; 5677 default: 5678 break; 5679 } 5680 } 5681 5682 5683 void 5684 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5685 { 5686 switch (mode) { 5687 case BGE_INIT_RESET: 5688 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5689 BGE_DRV_STATE_START_DONE); 5690 break; 5691 case BGE_SHUTDOWN_RESET: 5692 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5693 BGE_DRV_STATE_UNLOAD_DONE); 5694 break; 5695 default: 5696 break; 5697 } 5698 } 5699 5700 #endif /* BGE_IPMI_ASF */ 5701