1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 1 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 boolean_t bge_enable_msi = B_TRUE; 49 50 /* 51 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 52 */ 53 boolean_t bge_relaxed_ordering = B_TRUE; 54 55 /* 56 * Property names 57 */ 58 static char knownids_propname[] = "bge-known-subsystems"; 59 60 /* 61 * Patchable globals: 62 * 63 * bge_autorecover 64 * Enables/disables automatic recovery after fault detection 65 * 66 * bge_mlcr_default 67 * Value to program into the MLCR; controls the chip's GPIO pins 68 * 69 * bge_dma_{rd,wr}prio 70 * Relative priorities of DMA reads & DMA writes respectively. 71 * These may each be patched to any value 0-3. Equal values 72 * will give "fair" (round-robin) arbitration for PCI access. 73 * Unequal values will give one or the other function priority. 74 * 75 * bge_dma_rwctrl 76 * Value to put in the Read/Write DMA control register. See 77 * the Broadcom PRM for things you can fiddle with in this 78 * register ... 79 * 80 * bge_{tx,rx}_{count,ticks}_{norm,intr} 81 * Send/receive interrupt coalescing parameters. Counts are 82 * #s of descriptors, ticks are in microseconds. *norm* values 83 * apply between status updates/interrupts; the *intr* values 84 * refer to the 'during-interrupt' versions - see the PRM. 85 * 86 * NOTE: these values have been determined by measurement. They 87 * differ significantly from the values recommended in the PRM. 88 */ 89 static uint32_t bge_autorecover = 1; 90 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 91 92 static uint32_t bge_dma_rdprio = 1; 93 static uint32_t bge_dma_wrprio = 0; 94 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 95 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 96 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 97 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 98 99 uint32_t bge_rx_ticks_norm = 128; 100 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 101 uint32_t bge_rx_count_norm = 8; 102 uint32_t bge_tx_count_norm = 128; 103 104 static uint32_t bge_rx_ticks_intr = 128; 105 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 106 static uint32_t bge_rx_count_intr = 2; 107 static uint32_t bge_tx_count_intr = 0; 108 109 /* 110 * Memory pool configuration parameters. 111 * 112 * These are generally specific to each member of the chip family, since 113 * each one may have a different memory size/configuration. 114 * 115 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 116 * the driver from programming the various registers; instead they are left 117 * at their hardware defaults. This is the preferred option for later chips 118 * (5705+), whereas the older chips *required* these registers to be set, 119 * since the h/w default was 0 ;-( 120 */ 121 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 122 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 123 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 124 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 125 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 126 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 127 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 128 static uint32_t bge_mbuf_pool_len_5721 = 0; 129 130 /* 131 * Various high and low water marks, thresholds, etc ... 132 * 133 * Note: these are taken from revision 7 of the PRM, and some are different 134 * from both the values in earlier PRMs *and* those determined experimentally 135 * and used in earlier versions of this driver ... 136 */ 137 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 138 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 139 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 140 141 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 142 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 143 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 144 145 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 146 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 147 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 148 149 static uint32_t bge_watchdog_count = 1 << 16; 150 static uint16_t bge_dma_miss_limit = 20; 151 152 static uint32_t bge_stop_start_on_sync = 0; 153 154 boolean_t bge_jumbo_enable = B_TRUE; 155 156 /* 157 * bge_intr_max_loop controls the maximum loop number within bge_intr. 158 * When loading NIC with heavy network traffic, it is useful. 159 * Increasing this value could have positive effect to throughput, 160 * but it might also increase ticks of a bge ISR stick on CPU, which might 161 * lead to bad UI interactive experience. So tune this with caution. 162 */ 163 static int bge_intr_max_loop = 1; 164 165 /* 166 * ========== Low-level chip & ring buffer manipulation ========== 167 */ 168 169 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 170 171 172 /* 173 * Config space read-modify-write routines 174 */ 175 176 #if BGE_CFG_IO8 177 178 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 179 #pragma inline(bge_cfg_clr16) 180 181 static void 182 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 183 { 184 uint16_t regval; 185 186 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 187 (void *)bgep, regno, bits)); 188 189 regval = pci_config_get16(bgep->cfg_handle, regno); 190 191 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 192 (void *)bgep, regno, bits, regval, regval & ~bits)); 193 194 regval &= ~bits; 195 pci_config_put16(bgep->cfg_handle, regno, regval); 196 } 197 198 #endif /* BGE_CFG_IO8 */ 199 200 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 201 #pragma inline(bge_cfg_clr32) 202 203 static void 204 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 205 { 206 uint32_t regval; 207 208 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 209 (void *)bgep, regno, bits)); 210 211 regval = pci_config_get32(bgep->cfg_handle, regno); 212 213 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 214 (void *)bgep, regno, bits, regval, regval & ~bits)); 215 216 regval &= ~bits; 217 pci_config_put32(bgep->cfg_handle, regno, regval); 218 } 219 220 #if BGE_IND_IO32 221 222 /* 223 * Indirect access to registers & RISC scratchpads, using config space 224 * accesses only. 225 * 226 * This isn't currently used, but someday we might want to use it for 227 * restoring the Subsystem Device/Vendor registers (which aren't directly 228 * writable in Config Space), or for downloading firmware into the RISCs 229 * 230 * In any case there are endian issues to be resolved before this code is 231 * enabled; the bizarre way that bytes get twisted by this chip AND by 232 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 233 * it's been thoroughly tested for all access sizes on all supported 234 * architectures (SPARC *and* x86!). 235 */ 236 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 237 #pragma inline(bge_ind_get32) 238 239 uint32_t 240 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 241 { 242 uint32_t val; 243 244 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 245 246 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 247 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 248 249 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 250 (void *)bgep, regno, val)); 251 252 val = LE_32(val); 253 254 return (val); 255 } 256 257 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 258 #pragma inline(bge_ind_put32) 259 260 void 261 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 262 { 263 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 264 (void *)bgep, regno, val)); 265 266 val = LE_32(val); 267 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 268 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 269 } 270 271 #endif /* BGE_IND_IO32 */ 272 273 #if BGE_DEBUGGING 274 275 static void bge_pci_check(bge_t *bgep); 276 #pragma no_inline(bge_pci_check) 277 278 static void 279 bge_pci_check(bge_t *bgep) 280 { 281 uint16_t pcistatus; 282 283 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 284 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 285 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 286 (void *)bgep, pcistatus)); 287 } 288 289 #endif /* BGE_DEBUGGING */ 290 291 /* 292 * Perform first-stage chip (re-)initialisation, using only config-space 293 * accesses: 294 * 295 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 296 * returning the data in the structure pointed to by <idp>. 297 * + Configure the target-mode endianness (swap) options. 298 * + Disable interrupts and enable Memory Space accesses. 299 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 300 * 301 * This sequence is adapted from Broadcom document 570X-PG102-R, 302 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 303 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 304 * 305 * This function MUST be called before any non-config-space accesses 306 * are made; on this first call <enable_dma> is B_FALSE, and it 307 * effectively performs steps 3-1(!) of the initialisation sequence 308 * (the rest are not required but should be harmless). 309 * 310 * It MUST also be called after a chip reset, as this disables 311 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 312 * it is effectively performing steps 6-8. 313 */ 314 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 315 #pragma no_inline(bge_chip_cfg_init) 316 317 void 318 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 319 { 320 ddi_acc_handle_t handle; 321 uint16_t command; 322 uint32_t mhcr; 323 uint16_t value16; 324 int i; 325 326 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 327 (void *)bgep, (void *)cidp, enable_dma)); 328 329 /* 330 * Step 3: save PCI cache line size and subsystem vendor ID 331 * 332 * Read all the config-space registers that characterise the 333 * chip, specifically vendor/device/revision/subsystem vendor 334 * and subsystem device id. We expect (but don't check) that 335 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 336 * 337 * Also save all bus-transaction related registers (cache-line 338 * size, bus-grant/latency parameters, etc). Some of these are 339 * cleared by reset, so we'll have to restore them later. This 340 * comes from the Broadcom document 570X-PG102-R ... 341 * 342 * Note: Broadcom document 570X-PG102-R seems to be in error 343 * here w.r.t. the offsets of the Subsystem Vendor ID and 344 * Subsystem (Device) ID registers, which are the opposite way 345 * round according to the PCI standard. For good measure, we 346 * save/restore both anyway. 347 */ 348 handle = bgep->cfg_handle; 349 350 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 351 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 352 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 353 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 354 355 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 356 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 357 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 358 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 359 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 360 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 361 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 362 363 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 364 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 365 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 366 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 367 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 368 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 369 cidp->vendor, cidp->device, cidp->revision)); 370 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 371 cidp->subven, cidp->subdev, cidp->asic_rev)); 372 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 373 cidp->clsize, cidp->latency, cidp->command)); 374 375 /* 376 * Step 2 (also step 6): disable and clear interrupts. 377 * Steps 11-13: configure PIO endianness options, and enable 378 * indirect register access. We'll also select any other 379 * options controlled by the MHCR (e.g. tagged status, mask 380 * interrupt mode) at this stage ... 381 * 382 * Note: internally, the chip is 64-bit and BIG-endian, but 383 * since it talks to the host over a (LITTLE-endian) PCI bus, 384 * it normally swaps bytes around at the PCI interface. 385 * However, the PCI host bridge on SPARC systems normally 386 * swaps the byte lanes around too, since SPARCs are also 387 * BIG-endian. So it turns out that on SPARC, the right 388 * option is to tell the chip to swap (and the host bridge 389 * will swap back again), whereas on x86 we ask the chip 390 * NOT to swap, so the natural little-endianness of the 391 * PCI bus is assumed. Then the only thing that doesn't 392 * automatically work right is access to an 8-byte register 393 * by a little-endian host; but we don't want to set the 394 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 395 * accesses don't go where expected ;-( So we live with 396 * that, and perform word-swaps in software in the few cases 397 * where a chip register is defined as an 8-byte value -- 398 * see the code below for details ... 399 * 400 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 401 * very clear in the register description in the PRM, but 402 * Broadcom document 570X-PG104-R page 248 explains a little 403 * more (under "Broadcom Mask Mode"). The bit changes the way 404 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 405 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 406 * way as the 5700 did, which isn't very convenient. Setting 407 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 408 * bit do just what its name says -- MASK the PCI #INTA output 409 * (i.e. deassert the signal at the pin) leaving all internal 410 * state unchanged. This is much more convenient for our 411 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 412 * 413 * Note: the inconvenient semantics of the interrupt mailbox 414 * (nonzero disables and acknowledges/clears the interrupt, 415 * zero enables AND CLEARS it) would make race conditions 416 * likely in the interrupt handler: 417 * 418 * (1) acknowledge & disable interrupts 419 * (2) while (more to do) 420 * process packets 421 * (3) enable interrupts -- also clears pending 422 * 423 * If the chip received more packets and internally generated 424 * an interrupt between the check at (2) and the mbox write 425 * at (3), this interrupt would be lost :-( 426 * 427 * The best way to avoid this is to use TAGGED STATUS mode, 428 * where the chip includes a unique tag in each status block 429 * update, and the host, when re-enabling interrupts, passes 430 * the last tag it saw back to the chip; then the chip can 431 * see whether the host is truly up to date, and regenerate 432 * its interrupt if not. 433 */ 434 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 435 MHCR_ENABLE_TAGGED_STATUS_MODE | 436 MHCR_MASK_INTERRUPT_MODE | 437 MHCR_CLEAR_INTERRUPT_INTA; 438 439 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 440 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 441 442 #ifdef _BIG_ENDIAN 443 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 444 #endif /* _BIG_ENDIAN */ 445 446 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 447 448 #ifdef BGE_IPMI_ASF 449 bgep->asf_wordswapped = B_FALSE; 450 #endif 451 /* 452 * Step 1 (also step 7): Enable PCI Memory Space accesses 453 * Disable Memory Write/Invalidate 454 * Enable or disable Bus Mastering 455 * 456 * Note that all other bits are taken from the original value saved 457 * the first time through here, rather than from the current register 458 * value, 'cos that will have been cleared by a soft RESET since. 459 * In this way we preserve the OBP/nexus-parent's preferred settings 460 * of the parity-error and system-error enable bits across multiple 461 * chip RESETs. 462 */ 463 command = bgep->chipid.command | PCI_COMM_MAE; 464 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 465 if (enable_dma) 466 command |= PCI_COMM_ME; 467 /* 468 * on BCM5714 revision A0, false parity error gets generated 469 * due to a logic bug. Provide a workaround by disabling parity 470 * error. 471 */ 472 if (((cidp->device == DEVICE_ID_5714C) || 473 (cidp->device == DEVICE_ID_5714S)) && 474 (cidp->revision == REVISION_ID_5714_A0)) { 475 command &= ~PCI_COMM_PARITY_DETECT; 476 } 477 pci_config_put16(handle, PCI_CONF_COMM, command); 478 479 /* 480 * On some PCI-E device, there were instances when 481 * the device was still link training. 482 */ 483 if (bgep->chipid.pci_type == BGE_PCI_E) { 484 i = 0; 485 value16 = pci_config_get16(handle, PCI_CONF_COMM); 486 while ((value16 != command) && (i < 100)) { 487 drv_usecwait(200); 488 value16 = pci_config_get16(handle, PCI_CONF_COMM); 489 ++i; 490 } 491 } 492 493 /* 494 * Clear any remaining error status bits 495 */ 496 pci_config_put16(handle, PCI_CONF_STAT, ~0); 497 498 /* 499 * Do following if and only if the device is NOT BCM5714C OR 500 * BCM5715C 501 */ 502 if (!((cidp->device == DEVICE_ID_5714C) || 503 (cidp->device == DEVICE_ID_5715C))) { 504 /* 505 * Make sure these indirect-access registers are sane 506 * rather than random after power-up or reset 507 */ 508 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 509 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 510 } 511 /* 512 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 513 */ 514 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 515 516 if (cidp->pci_type == BGE_PCI_E) 517 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 518 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 519 } 520 521 #ifdef __amd64 522 /* 523 * Distinguish CPU types 524 * 525 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 526 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 527 * for PCI-Express based network interface card. This is the work-around 528 * for those nics. 529 */ 530 static boolean_t bge_get_em64t_type(void); 531 #pragma inline(bge_get_em64t_type) 532 533 static boolean_t 534 bge_get_em64t_type(void) 535 { 536 537 return (x86_vendor == X86_VENDOR_Intel); 538 } 539 #endif 540 541 /* 542 * Operating register get/set access routines 543 */ 544 545 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 546 #pragma inline(bge_reg_get32) 547 548 uint32_t 549 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 550 { 551 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 552 (void *)bgep, regno)); 553 554 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 555 } 556 557 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 558 #pragma inline(bge_reg_put32) 559 560 void 561 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 562 { 563 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 564 (void *)bgep, regno, data)); 565 566 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 567 BGE_PCICHK(bgep); 568 } 569 570 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 571 #pragma inline(bge_reg_set32) 572 573 void 574 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 575 { 576 uint32_t regval; 577 578 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 579 (void *)bgep, regno, bits)); 580 581 regval = bge_reg_get32(bgep, regno); 582 regval |= bits; 583 bge_reg_put32(bgep, regno, regval); 584 } 585 586 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 587 #pragma inline(bge_reg_clr32) 588 589 void 590 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 591 { 592 uint32_t regval; 593 594 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 595 (void *)bgep, regno, bits)); 596 597 regval = bge_reg_get32(bgep, regno); 598 regval &= ~bits; 599 bge_reg_put32(bgep, regno, regval); 600 } 601 602 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 603 #pragma inline(bge_reg_get64) 604 605 static uint64_t 606 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 607 { 608 uint64_t regval; 609 610 #ifdef __amd64 611 if (bge_get_em64t_type()) { 612 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 613 regval <<= 32; 614 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 615 } else { 616 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 617 } 618 #else 619 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 620 #endif 621 622 #ifdef _LITTLE_ENDIAN 623 regval = (regval >> 32) | (regval << 32); 624 #endif /* _LITTLE_ENDIAN */ 625 626 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 627 (void *)bgep, regno, regval)); 628 629 return (regval); 630 } 631 632 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 633 #pragma inline(bge_reg_put64) 634 635 static void 636 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 637 { 638 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 639 (void *)bgep, regno, data)); 640 641 #ifdef _LITTLE_ENDIAN 642 data = ((data >> 32) | (data << 32)); 643 #endif /* _LITTLE_ENDIAN */ 644 645 #ifdef __amd64 646 if (bge_get_em64t_type()) { 647 ddi_put32(bgep->io_handle, 648 PIO_ADDR(bgep, regno), (uint32_t)data); 649 BGE_PCICHK(bgep); 650 ddi_put32(bgep->io_handle, 651 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 652 653 } else { 654 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 655 } 656 #else 657 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 658 #endif 659 660 BGE_PCICHK(bgep); 661 } 662 663 /* 664 * The DDI doesn't provide get/put functions for 128 bit data 665 * so we put RCBs out as two 64-bit chunks instead. 666 */ 667 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 668 #pragma inline(bge_reg_putrcb) 669 670 static void 671 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 672 { 673 uint64_t *p; 674 675 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 676 (void *)bgep, addr, rcbp->host_ring_addr, 677 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 678 679 ASSERT((addr % sizeof (*rcbp)) == 0); 680 681 p = (void *)rcbp; 682 bge_reg_put64(bgep, addr, *p++); 683 bge_reg_put64(bgep, addr+8, *p); 684 } 685 686 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 687 #pragma inline(bge_mbx_put) 688 689 void 690 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 691 { 692 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 693 (void *)bgep, regno, data)); 694 695 /* 696 * Mailbox registers are nominally 64 bits on the 5701, but 697 * the MSW isn't used. On the 5703, they're only 32 bits 698 * anyway. So here we just write the lower(!) 32 bits - 699 * remembering that the chip is big-endian, even though the 700 * PCI bus is little-endian ... 701 */ 702 #ifdef _BIG_ENDIAN 703 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 704 #else 705 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 706 #endif /* _BIG_ENDIAN */ 707 BGE_PCICHK(bgep); 708 } 709 710 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 711 #pragma inline(bge_mbx_get) 712 713 uint32_t 714 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 715 { 716 uint32_t val32; 717 718 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 719 (void *)bgep, regno)); 720 721 #ifdef _BIG_ENDIAN 722 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 723 #else 724 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 725 #endif /* _BIG_ENDIAN */ 726 BGE_PCICHK(bgep); 727 728 return (val32); 729 } 730 731 732 #if BGE_DEBUGGING 733 734 void bge_led_mark(bge_t *bgep); 735 #pragma no_inline(bge_led_mark) 736 737 void 738 bge_led_mark(bge_t *bgep) 739 { 740 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 741 LED_CONTROL_1000MBPS_LED | 742 LED_CONTROL_100MBPS_LED | 743 LED_CONTROL_10MBPS_LED; 744 745 /* 746 * Blink all three LINK LEDs on simultaneously, then all off, 747 * then restore to automatic hardware control. This is used 748 * in laboratory testing to trigger a logic analyser or scope. 749 */ 750 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 751 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 752 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 753 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 754 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 755 } 756 757 #endif /* BGE_DEBUGGING */ 758 759 /* 760 * NIC on-chip memory access routines 761 * 762 * Only 32K of NIC memory is visible at a time, controlled by the 763 * Memory Window Base Address Register (in PCI config space). Once 764 * this is set, the 32K region of NIC-local memory that it refers 765 * to can be directly addressed in the upper 32K of the 64K of PCI 766 * memory space used for the device. 767 */ 768 769 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 770 #pragma inline(bge_nic_setwin) 771 772 static void 773 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 774 { 775 chip_id_t *cidp; 776 777 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 778 (void *)bgep, base)); 779 780 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 781 782 /* 783 * Don't do repeated zero data writes, 784 * if the device is BCM5714C/15C. 785 */ 786 cidp = &bgep->chipid; 787 if ((cidp->device == DEVICE_ID_5714C) || 788 (cidp->device == DEVICE_ID_5715C)) { 789 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 790 return; 791 /* Adjust lastWriteZeroData */ 792 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 793 B_TRUE : B_FALSE); 794 } 795 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 796 } 797 798 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 799 #pragma inline(bge_nic_get32) 800 801 static uint32_t 802 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 803 { 804 uint32_t data; 805 806 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 807 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 808 /* workaround for word swap error */ 809 if (addr & 4) 810 addr = addr - 4; 811 else 812 addr = addr + 4; 813 } 814 #endif 815 816 #ifdef __sparc 817 data = bge_nic_read32(bgep, addr); 818 #else 819 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 820 addr &= MWBAR_GRANULE_MASK; 821 addr += NIC_MEM_WINDOW_OFFSET; 822 823 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 824 #endif 825 826 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 827 (void *)bgep, addr, data)); 828 829 return (data); 830 } 831 832 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 833 #pragma inline(bge_nic_put32) 834 835 void 836 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 837 { 838 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 839 (void *)bgep, addr, data)); 840 841 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 842 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 843 /* workaround for word swap error */ 844 if (addr & 4) 845 addr = addr - 4; 846 else 847 addr = addr + 4; 848 } 849 #endif 850 851 #ifdef __sparc 852 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 853 data = LE_32(data); 854 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 855 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 856 #else 857 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 858 addr &= MWBAR_GRANULE_MASK; 859 addr += NIC_MEM_WINDOW_OFFSET; 860 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 861 BGE_PCICHK(bgep); 862 #endif 863 } 864 865 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 866 #pragma inline(bge_nic_get64) 867 868 static uint64_t 869 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 870 { 871 uint64_t data; 872 873 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 874 addr &= MWBAR_GRANULE_MASK; 875 addr += NIC_MEM_WINDOW_OFFSET; 876 877 #ifdef __amd64 878 if (bge_get_em64t_type()) { 879 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 880 data <<= 32; 881 data |= ddi_get32(bgep->io_handle, 882 PIO_ADDR(bgep, addr + 4)); 883 } else { 884 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 885 } 886 #else 887 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 888 #endif 889 890 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 891 (void *)bgep, addr, data)); 892 893 return (data); 894 } 895 896 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 897 #pragma inline(bge_nic_put64) 898 899 static void 900 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 901 { 902 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 903 (void *)bgep, addr, data)); 904 905 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 906 addr &= MWBAR_GRANULE_MASK; 907 addr += NIC_MEM_WINDOW_OFFSET; 908 909 #ifdef __amd64 910 if (bge_get_em64t_type()) { 911 ddi_put32(bgep->io_handle, 912 PIO_ADDR(bgep, addr), (uint32_t)data); 913 BGE_PCICHK(bgep); 914 ddi_put32(bgep->io_handle, 915 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 916 } else { 917 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 918 } 919 #else 920 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 921 #endif 922 923 BGE_PCICHK(bgep); 924 } 925 926 /* 927 * The DDI doesn't provide get/put functions for 128 bit data 928 * so we put RCBs out as two 64-bit chunks instead. 929 */ 930 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 931 #pragma inline(bge_nic_putrcb) 932 933 static void 934 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 935 { 936 uint64_t *p; 937 938 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 939 (void *)bgep, addr, rcbp->host_ring_addr, 940 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 941 942 ASSERT((addr % sizeof (*rcbp)) == 0); 943 944 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 945 addr &= MWBAR_GRANULE_MASK; 946 addr += NIC_MEM_WINDOW_OFFSET; 947 948 p = (void *)rcbp; 949 #ifdef __amd64 950 if (bge_get_em64t_type()) { 951 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 952 (uint32_t)(*p)); 953 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 954 (uint32_t)(*p >> 32)); 955 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 956 (uint32_t)(*(p + 1))); 957 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 958 (uint32_t)(*p >> 32)); 959 960 } else { 961 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 962 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 963 } 964 #else 965 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 966 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 967 #endif 968 969 BGE_PCICHK(bgep); 970 } 971 972 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 973 #pragma inline(bge_nic_zero) 974 975 static void 976 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 977 { 978 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 979 (void *)bgep, addr, nbytes)); 980 981 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 982 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 983 984 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 985 addr &= MWBAR_GRANULE_MASK; 986 addr += NIC_MEM_WINDOW_OFFSET; 987 988 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 989 nbytes, 1, DDI_DATA_SZ08_ACC); 990 BGE_PCICHK(bgep); 991 } 992 993 /* 994 * MII (PHY) register get/set access routines 995 * 996 * These use the chip's MII auto-access method, controlled by the 997 * MII Communication register at 0x044c, so the CPU doesn't have 998 * to fiddle with the individual bits. 999 */ 1000 1001 #undef BGE_DBG 1002 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1003 1004 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1005 uint16_t data, uint32_t cmd); 1006 #pragma no_inline(bge_mii_access) 1007 1008 static uint16_t 1009 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1010 { 1011 uint32_t timeout; 1012 uint32_t regval1; 1013 uint32_t regval2; 1014 1015 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1016 (void *)bgep, regno, data, cmd)); 1017 1018 ASSERT(mutex_owned(bgep->genlock)); 1019 1020 /* 1021 * Assemble the command ... 1022 */ 1023 cmd |= data << MI_COMMS_DATA_SHIFT; 1024 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1025 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1026 cmd |= MI_COMMS_START; 1027 1028 /* 1029 * Wait for any command already in progress ... 1030 * 1031 * Note: this *shouldn't* ever find that there is a command 1032 * in progress, because we already hold the <genlock> mutex. 1033 * Nonetheless, we have sometimes seen the MI_COMMS_START 1034 * bit set here -- it seems that the chip can initiate MII 1035 * accesses internally, even with polling OFF. 1036 */ 1037 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1038 for (timeout = 100; ; ) { 1039 if ((regval2 & MI_COMMS_START) == 0) { 1040 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1041 break; 1042 } 1043 if (--timeout == 0) 1044 break; 1045 drv_usecwait(10); 1046 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1047 } 1048 1049 if (timeout == 0) 1050 return ((uint16_t)~0u); 1051 1052 if (timeout != 100) 1053 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1054 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1055 cmd, 10*(100-timeout), regval1, regval2)); 1056 1057 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1058 for (timeout = 1000; ; ) { 1059 if ((regval1 & MI_COMMS_START) == 0) 1060 break; 1061 if (--timeout == 0) 1062 break; 1063 drv_usecwait(10); 1064 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1065 } 1066 1067 /* 1068 * Drop out early if the READ FAILED bit is set -- this chip 1069 * could be a 5703/4S, with a SerDes instead of a PHY! 1070 */ 1071 if (regval2 & MI_COMMS_READ_FAILED) 1072 return ((uint16_t)~0u); 1073 1074 if (timeout == 0) 1075 return ((uint16_t)~0u); 1076 1077 /* 1078 * The PRM says to wait 5us after seeing the START bit clear 1079 * and then re-read the register to get the final value of the 1080 * data field, in order to avoid a race condition where the 1081 * START bit is clear but the data field isn't yet valid. 1082 * 1083 * Note: we don't actually seem to be encounter this race; 1084 * except when the START bit is seen set again (see below), 1085 * the data field doesn't change during this 5us interval. 1086 */ 1087 drv_usecwait(5); 1088 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1089 1090 /* 1091 * Unfortunately, when following the PRMs instructions above, 1092 * we have occasionally seen the START bit set again(!) in the 1093 * value read after the 5us delay. This seems to be due to the 1094 * chip autonomously starting another MII access internally. 1095 * In such cases, the command/data/etc fields relate to the 1096 * internal command, rather than the one that we thought had 1097 * just finished. So in this case, we fall back to returning 1098 * the data from the original read that showed START clear. 1099 */ 1100 if (regval2 & MI_COMMS_START) { 1101 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1102 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1103 cmd, regval1, regval2)); 1104 regval2 = regval1; 1105 } 1106 1107 if (regval2 & MI_COMMS_START) 1108 return ((uint16_t)~0u); 1109 1110 if (regval2 & MI_COMMS_READ_FAILED) 1111 return ((uint16_t)~0u); 1112 1113 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1114 } 1115 1116 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1117 #pragma no_inline(bge_mii_get16) 1118 1119 uint16_t 1120 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1121 { 1122 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1123 (void *)bgep, regno)); 1124 1125 ASSERT(mutex_owned(bgep->genlock)); 1126 1127 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1128 } 1129 1130 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1131 #pragma no_inline(bge_mii_put16) 1132 1133 void 1134 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1135 { 1136 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1137 (void *)bgep, regno, data)); 1138 1139 ASSERT(mutex_owned(bgep->genlock)); 1140 1141 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1142 } 1143 1144 #undef BGE_DBG 1145 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1146 1147 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1148 1149 /* 1150 * Basic SEEPROM get/set access routine 1151 * 1152 * This uses the chip's SEEPROM auto-access method, controlled by the 1153 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1154 * doesn't have to fiddle with the individual bits. 1155 * 1156 * The caller should hold <genlock> and *also* have already acquired 1157 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1158 * 1159 * Return value: 1160 * 0 on success, 1161 * ENODATA on access timeout (maybe retryable: device may just be busy) 1162 * EPROTO on other h/w or s/w errors. 1163 * 1164 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1165 * from a (successful) SEEPROM_ACCESS_READ. 1166 */ 1167 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1168 uint32_t *dp); 1169 #pragma no_inline(bge_seeprom_access) 1170 1171 static int 1172 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1173 { 1174 uint32_t tries; 1175 uint32_t regval; 1176 1177 ASSERT(mutex_owned(bgep->genlock)); 1178 1179 /* 1180 * On the newer chips that support both SEEPROM & Flash, we need 1181 * to specifically enable SEEPROM access (Flash is the default). 1182 * On older chips, we don't; SEEPROM is the only NVtype supported, 1183 * and the NVM control registers don't exist ... 1184 */ 1185 switch (bgep->chipid.nvtype) { 1186 case BGE_NVTYPE_NONE: 1187 case BGE_NVTYPE_UNKNOWN: 1188 _NOTE(NOTREACHED) 1189 case BGE_NVTYPE_SEEPROM: 1190 break; 1191 1192 case BGE_NVTYPE_LEGACY_SEEPROM: 1193 case BGE_NVTYPE_UNBUFFERED_FLASH: 1194 case BGE_NVTYPE_BUFFERED_FLASH: 1195 default: 1196 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1197 NVM_CFG1_LEGACY_SEEPROM_MODE); 1198 break; 1199 } 1200 1201 /* 1202 * Check there's no command in progress. 1203 * 1204 * Note: this *shouldn't* ever find that there is a command 1205 * in progress, because we already hold the <genlock> mutex. 1206 * Also, to ensure we don't have a conflict with the chip's 1207 * internal firmware or a process accessing the same (shared) 1208 * SEEPROM through the other port of a 5704, we've already 1209 * been through the "software arbitration" protocol. 1210 * So this is just a final consistency check: we shouldn't 1211 * see EITHER the START bit (command started but not complete) 1212 * OR the COMPLETE bit (command completed but not cleared). 1213 */ 1214 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1215 if (regval & SEEPROM_ACCESS_START) 1216 return (EPROTO); 1217 if (regval & SEEPROM_ACCESS_COMPLETE) 1218 return (EPROTO); 1219 1220 /* 1221 * Assemble the command ... 1222 */ 1223 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1224 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1225 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1226 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1227 cmd |= SEEPROM_ACCESS_START; 1228 cmd |= SEEPROM_ACCESS_COMPLETE; 1229 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1230 1231 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1232 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1233 1234 /* 1235 * By observation, a successful access takes ~20us on a 5703/4, 1236 * but apparently much longer (up to 1000us) on the obsolescent 1237 * BCM5700/BCM5701. We want to be sure we don't get any false 1238 * timeouts here; but OTOH, we don't want a bogus access to lock 1239 * out interrupts for longer than necessary. So we'll allow up 1240 * to 1000us ... 1241 */ 1242 for (tries = 0; tries < 1000; ++tries) { 1243 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1244 if (regval & SEEPROM_ACCESS_COMPLETE) 1245 break; 1246 drv_usecwait(1); 1247 } 1248 1249 if (regval & SEEPROM_ACCESS_COMPLETE) { 1250 /* 1251 * All OK; read the SEEPROM data register, then write back 1252 * the value read from the address register in order to 1253 * clear the <complete> bit and leave the SEEPROM access 1254 * state machine idle, ready for the next access ... 1255 */ 1256 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1257 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1258 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1259 return (0); 1260 } 1261 1262 /* 1263 * Hmm ... what happened here? 1264 * 1265 * Most likely, the user addressed a non-existent SEEPROM. Or 1266 * maybe the SEEPROM was busy internally (e.g. processing a write) 1267 * and didn't respond to being addressed. Either way, it's left 1268 * the SEEPROM access state machine wedged. So we'll reset it 1269 * before we leave, so it's ready for next time ... 1270 */ 1271 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1272 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1273 return (ENODATA); 1274 } 1275 1276 /* 1277 * Basic Flash get/set access routine 1278 * 1279 * These use the chip's Flash auto-access method, controlled by the 1280 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1281 * fiddle with the individual bits. 1282 * 1283 * The caller should hold <genlock> and *also* have already acquired 1284 * the right to access the Flash, via bge_nvmem_acquire() above. 1285 * 1286 * Return value: 1287 * 0 on success, 1288 * ENODATA on access timeout (maybe retryable: device may just be busy) 1289 * ENODEV if the NVmem device is missing or otherwise unusable 1290 * 1291 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1292 * from a (successful) NVM_FLASH_CMD_RD. 1293 */ 1294 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1295 uint32_t *dp); 1296 #pragma no_inline(bge_flash_access) 1297 1298 static int 1299 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1300 { 1301 uint32_t tries; 1302 uint32_t regval; 1303 1304 ASSERT(mutex_owned(bgep->genlock)); 1305 1306 /* 1307 * On the newer chips that support both SEEPROM & Flash, we need 1308 * to specifically disable SEEPROM access while accessing Flash. 1309 * The older chips don't support Flash, and the NVM registers don't 1310 * exist, so we shouldn't be here at all! 1311 */ 1312 switch (bgep->chipid.nvtype) { 1313 case BGE_NVTYPE_NONE: 1314 case BGE_NVTYPE_UNKNOWN: 1315 _NOTE(NOTREACHED) 1316 case BGE_NVTYPE_SEEPROM: 1317 return (ENODEV); 1318 1319 case BGE_NVTYPE_LEGACY_SEEPROM: 1320 case BGE_NVTYPE_UNBUFFERED_FLASH: 1321 case BGE_NVTYPE_BUFFERED_FLASH: 1322 default: 1323 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1324 NVM_CFG1_LEGACY_SEEPROM_MODE); 1325 break; 1326 } 1327 1328 /* 1329 * Assemble the command ... 1330 */ 1331 addr &= NVM_FLASH_ADDR_MASK; 1332 cmd |= NVM_FLASH_CMD_DOIT; 1333 cmd |= NVM_FLASH_CMD_FIRST; 1334 cmd |= NVM_FLASH_CMD_LAST; 1335 cmd |= NVM_FLASH_CMD_DONE; 1336 1337 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1338 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1339 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1340 1341 /* 1342 * Allow up to 1000ms ... 1343 */ 1344 for (tries = 0; tries < 1000; ++tries) { 1345 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1346 if (regval & NVM_FLASH_CMD_DONE) 1347 break; 1348 drv_usecwait(1); 1349 } 1350 1351 if (regval & NVM_FLASH_CMD_DONE) { 1352 /* 1353 * All OK; read the data from the Flash read register 1354 */ 1355 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1356 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1357 return (0); 1358 } 1359 1360 /* 1361 * Hmm ... what happened here? 1362 * 1363 * Most likely, the user addressed a non-existent Flash. Or 1364 * maybe the Flash was busy internally (e.g. processing a write) 1365 * and didn't respond to being addressed. Either way, there's 1366 * nothing we can here ... 1367 */ 1368 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1369 return (ENODATA); 1370 } 1371 1372 /* 1373 * The next two functions regulate access to the NVram (if fitted). 1374 * 1375 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1376 * (SPI) interface, but they can be accessed through either port. These 1377 * are managed by different instance of this driver and have no software 1378 * state in common. 1379 * 1380 * In addition (and even on a single core chip) the chip's internal 1381 * firmware can access the SEEPROM/Flash, most notably after a RESET 1382 * when it may download code to run internally. 1383 * 1384 * So we need to arbitrate between these various software agents. For 1385 * this purpose, the chip provides the Software Arbitration Register, 1386 * which implements hardware(!) arbitration. 1387 * 1388 * This functionality didn't exist on older (5700/5701) chips, so there's 1389 * nothing we can do by way of arbitration on those; also, if there's no 1390 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1391 * nothing to do. 1392 * 1393 * The internal firmware appears to use Request 0, which is the highest 1394 * priority. So we'd like to use Request 2, leaving one higher and one 1395 * lower for any future developments ... but apparently this doesn't 1396 * always work. So for now, the code uses Request 1 ;-( 1397 */ 1398 1399 #define NVM_READ_REQ NVM_READ_REQ1 1400 #define NVM_RESET_REQ NVM_RESET_REQ1 1401 #define NVM_SET_REQ NVM_SET_REQ1 1402 1403 static void bge_nvmem_relinquish(bge_t *bgep); 1404 #pragma no_inline(bge_nvmem_relinquish) 1405 1406 static void 1407 bge_nvmem_relinquish(bge_t *bgep) 1408 { 1409 ASSERT(mutex_owned(bgep->genlock)); 1410 1411 switch (bgep->chipid.nvtype) { 1412 case BGE_NVTYPE_NONE: 1413 case BGE_NVTYPE_UNKNOWN: 1414 _NOTE(NOTREACHED) 1415 return; 1416 1417 case BGE_NVTYPE_SEEPROM: 1418 /* 1419 * No arbitration performed, no release needed 1420 */ 1421 return; 1422 1423 case BGE_NVTYPE_LEGACY_SEEPROM: 1424 case BGE_NVTYPE_UNBUFFERED_FLASH: 1425 case BGE_NVTYPE_BUFFERED_FLASH: 1426 default: 1427 break; 1428 } 1429 1430 /* 1431 * Our own request should be present (whether or not granted) ... 1432 */ 1433 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1434 1435 /* 1436 * ... this will make it go away. 1437 */ 1438 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1439 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1440 } 1441 1442 /* 1443 * Arbitrate for access to the NVmem, if necessary 1444 * 1445 * Return value: 1446 * 0 on success 1447 * EAGAIN if the device is in use (retryable) 1448 * ENODEV if the NVmem device is missing or otherwise unusable 1449 */ 1450 static int bge_nvmem_acquire(bge_t *bgep); 1451 #pragma no_inline(bge_nvmem_acquire) 1452 1453 static int 1454 bge_nvmem_acquire(bge_t *bgep) 1455 { 1456 uint32_t regval; 1457 uint32_t tries; 1458 1459 ASSERT(mutex_owned(bgep->genlock)); 1460 1461 switch (bgep->chipid.nvtype) { 1462 case BGE_NVTYPE_NONE: 1463 case BGE_NVTYPE_UNKNOWN: 1464 /* 1465 * Access denied: no (recognisable) device fitted 1466 */ 1467 return (ENODEV); 1468 1469 case BGE_NVTYPE_SEEPROM: 1470 /* 1471 * Access granted: no arbitration needed (or possible) 1472 */ 1473 return (0); 1474 1475 case BGE_NVTYPE_LEGACY_SEEPROM: 1476 case BGE_NVTYPE_UNBUFFERED_FLASH: 1477 case BGE_NVTYPE_BUFFERED_FLASH: 1478 default: 1479 /* 1480 * Access conditional: conduct arbitration protocol 1481 */ 1482 break; 1483 } 1484 1485 /* 1486 * We're holding the per-port mutex <genlock>, so no-one other 1487 * thread can be attempting to access the NVmem through *this* 1488 * port. But it could be in use by the *other* port (of a 5704), 1489 * or by the chip's internal firmware, so we have to go through 1490 * the full (hardware) arbitration protocol ... 1491 * 1492 * Note that *because* we're holding <genlock>, the interrupt handler 1493 * won't be able to progress. So we're only willing to spin for a 1494 * fairly short time. Specifically: 1495 * 1496 * We *must* wait long enough for the hardware to resolve all 1497 * requests and determine the winner. Fortunately, this is 1498 * "almost instantaneous", even as observed by GHz CPUs. 1499 * 1500 * A successful access by another Solaris thread (via either 1501 * port) typically takes ~20us. So waiting a bit longer than 1502 * that will give a good chance of success, if the other user 1503 * *is* another thread on the other port. 1504 * 1505 * However, the internal firmware can hold on to the NVmem 1506 * for *much* longer: at least 10 milliseconds just after a 1507 * RESET, and maybe even longer if the NVmem actually contains 1508 * code to download and run on the internal CPUs. 1509 * 1510 * So, we'll allow 50us; if that's not enough then it's up to the 1511 * caller to retry later (hence the choice of return code EAGAIN). 1512 */ 1513 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1514 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1515 1516 for (tries = 0; tries < 50; ++tries) { 1517 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1518 if (regval & NVM_WON_REQ1) 1519 break; 1520 drv_usecwait(1); 1521 } 1522 1523 if (regval & NVM_WON_REQ1) { 1524 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1525 return (0); 1526 } 1527 1528 /* 1529 * Somebody else must be accessing the NVmem, so abandon our 1530 * attempt take control of it. The caller can try again later ... 1531 */ 1532 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1533 bge_nvmem_relinquish(bgep); 1534 return (EAGAIN); 1535 } 1536 1537 /* 1538 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1539 * write protect line in such a way that the NVmem is protected when 1540 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1541 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1542 * 1543 * Note: there's only one set of GPIO pins on a 5704, even though they 1544 * can be accessed through either port. So the chip has to resolve what 1545 * happens if the two ports program a single pin differently ... the rule 1546 * it uses is that if the ports disagree about the *direction* of a pin, 1547 * "output" wins over "input", but if they disagree about its *value* as 1548 * an output, then the pin is TRISTATED instead! In such a case, no-one 1549 * wins, and the external signal does whatever the external circuitry 1550 * defines as the default -- which we've assumed is the PROTECTED state. 1551 * So, we always change GPIO1 back to being an *input* whenever we're not 1552 * specifically using it to unprotect the NVmem. This allows either port 1553 * to update the NVmem, although obviously only one at a time! 1554 * 1555 * The caller should hold <genlock> and *also* have already acquired the 1556 * right to access the NVmem, via bge_nvmem_acquire() above. 1557 */ 1558 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1559 #pragma inline(bge_nvmem_protect) 1560 1561 static void 1562 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1563 { 1564 uint32_t regval; 1565 1566 ASSERT(mutex_owned(bgep->genlock)); 1567 1568 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1569 if (protect) { 1570 regval |= MLCR_MISC_PINS_OUTPUT_1; 1571 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1572 } else { 1573 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1574 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1575 } 1576 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1577 } 1578 1579 /* 1580 * Now put it all together ... 1581 * 1582 * Try to acquire control of the NVmem; if successful, then: 1583 * unprotect it (if we want to write to it) 1584 * perform the requested access 1585 * reprotect it (after a write) 1586 * relinquish control 1587 * 1588 * Return value: 1589 * 0 on success, 1590 * EAGAIN if the device is in use (retryable) 1591 * ENODATA on access timeout (maybe retryable: device may just be busy) 1592 * ENODEV if the NVmem device is missing or otherwise unusable 1593 * EPROTO on other h/w or s/w errors. 1594 */ 1595 static int 1596 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1597 { 1598 int err; 1599 1600 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1601 switch (cmd) { 1602 case BGE_SEE_READ: 1603 err = bge_seeprom_access(bgep, 1604 SEEPROM_ACCESS_READ, addr, dp); 1605 break; 1606 1607 case BGE_SEE_WRITE: 1608 bge_nvmem_protect(bgep, B_FALSE); 1609 err = bge_seeprom_access(bgep, 1610 SEEPROM_ACCESS_WRITE, addr, dp); 1611 bge_nvmem_protect(bgep, B_TRUE); 1612 break; 1613 1614 case BGE_FLASH_READ: 1615 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1616 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1617 bge_reg_set32(bgep, NVM_ACCESS_REG, 1618 NVM_ACCESS_ENABLE); 1619 } 1620 err = bge_flash_access(bgep, 1621 NVM_FLASH_CMD_RD, addr, dp); 1622 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1623 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1624 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1625 NVM_ACCESS_ENABLE); 1626 } 1627 break; 1628 1629 case BGE_FLASH_WRITE: 1630 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1631 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1632 bge_reg_set32(bgep, NVM_ACCESS_REG, 1633 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1634 } 1635 bge_nvmem_protect(bgep, B_FALSE); 1636 err = bge_flash_access(bgep, 1637 NVM_FLASH_CMD_WR, addr, dp); 1638 bge_nvmem_protect(bgep, B_TRUE); 1639 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1640 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1641 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1642 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1643 } 1644 1645 break; 1646 1647 default: 1648 _NOTE(NOTREACHED) 1649 break; 1650 } 1651 bge_nvmem_relinquish(bgep); 1652 } 1653 1654 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1655 return (err); 1656 } 1657 1658 /* 1659 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1660 */ 1661 static uint64_t bge_get_nvmac(bge_t *bgep); 1662 #pragma no_inline(bge_get_nvmac) 1663 1664 static uint64_t 1665 bge_get_nvmac(bge_t *bgep) 1666 { 1667 uint32_t mac_high; 1668 uint32_t mac_low; 1669 uint32_t addr; 1670 uint32_t cmd; 1671 uint64_t mac; 1672 1673 BGE_TRACE(("bge_get_nvmac($%p)", 1674 (void *)bgep)); 1675 1676 switch (bgep->chipid.nvtype) { 1677 case BGE_NVTYPE_NONE: 1678 case BGE_NVTYPE_UNKNOWN: 1679 default: 1680 return (0ULL); 1681 1682 case BGE_NVTYPE_SEEPROM: 1683 case BGE_NVTYPE_LEGACY_SEEPROM: 1684 cmd = BGE_SEE_READ; 1685 break; 1686 1687 case BGE_NVTYPE_UNBUFFERED_FLASH: 1688 case BGE_NVTYPE_BUFFERED_FLASH: 1689 cmd = BGE_FLASH_READ; 1690 break; 1691 } 1692 1693 addr = NVMEM_DATA_MAC_ADDRESS; 1694 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1695 return (0ULL); 1696 addr += 4; 1697 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1698 return (0ULL); 1699 1700 /* 1701 * The Broadcom chip is natively BIG-endian, so that's how the 1702 * MAC address is represented in NVmem. We may need to swap it 1703 * around on a little-endian host ... 1704 */ 1705 #ifdef _BIG_ENDIAN 1706 mac = mac_high; 1707 mac = mac << 32; 1708 mac |= mac_low; 1709 #else 1710 mac = BGE_BSWAP_32(mac_high); 1711 mac = mac << 32; 1712 mac |= BGE_BSWAP_32(mac_low); 1713 #endif /* _BIG_ENDIAN */ 1714 1715 return (mac); 1716 } 1717 1718 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1719 1720 /* 1721 * Dummy version for when we're not supporting NVmem access 1722 */ 1723 static uint64_t bge_get_nvmac(bge_t *bgep); 1724 #pragma inline(bge_get_nvmac) 1725 1726 static uint64_t 1727 bge_get_nvmac(bge_t *bgep) 1728 { 1729 _NOTE(ARGUNUSED(bgep)) 1730 return (0ULL); 1731 } 1732 1733 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1734 1735 /* 1736 * Determine the type of NVmem that is (or may be) attached to this chip, 1737 */ 1738 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1739 #pragma no_inline(bge_nvmem_id) 1740 1741 static enum bge_nvmem_type 1742 bge_nvmem_id(bge_t *bgep) 1743 { 1744 enum bge_nvmem_type nvtype; 1745 uint32_t config1; 1746 1747 BGE_TRACE(("bge_nvmem_id($%p)", 1748 (void *)bgep)); 1749 1750 switch (bgep->chipid.device) { 1751 default: 1752 /* 1753 * We shouldn't get here; it means we don't recognise 1754 * the chip, which means we don't know how to determine 1755 * what sort of NVmem (if any) it has. So we'll say 1756 * NONE, to disable the NVmem access code ... 1757 */ 1758 nvtype = BGE_NVTYPE_NONE; 1759 break; 1760 1761 case DEVICE_ID_5700: 1762 case DEVICE_ID_5700x: 1763 case DEVICE_ID_5701: 1764 /* 1765 * These devices support *only* SEEPROMs 1766 */ 1767 nvtype = BGE_NVTYPE_SEEPROM; 1768 break; 1769 1770 case DEVICE_ID_5702: 1771 case DEVICE_ID_5702fe: 1772 case DEVICE_ID_5703C: 1773 case DEVICE_ID_5703S: 1774 case DEVICE_ID_5704C: 1775 case DEVICE_ID_5704S: 1776 case DEVICE_ID_5704: 1777 case DEVICE_ID_5705M: 1778 case DEVICE_ID_5705C: 1779 case DEVICE_ID_5705_2: 1780 case DEVICE_ID_5706: 1781 case DEVICE_ID_5782: 1782 case DEVICE_ID_5787: 1783 case DEVICE_ID_5787M: 1784 case DEVICE_ID_5788: 1785 case DEVICE_ID_5789: 1786 case DEVICE_ID_5751: 1787 case DEVICE_ID_5751M: 1788 case DEVICE_ID_5752: 1789 case DEVICE_ID_5752M: 1790 case DEVICE_ID_5754: 1791 case DEVICE_ID_5755: 1792 case DEVICE_ID_5755M: 1793 case DEVICE_ID_5721: 1794 case DEVICE_ID_5714C: 1795 case DEVICE_ID_5714S: 1796 case DEVICE_ID_5715C: 1797 case DEVICE_ID_5715S: 1798 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1799 if (config1 & NVM_CFG1_FLASH_MODE) 1800 if (config1 & NVM_CFG1_BUFFERED_MODE) 1801 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1802 else 1803 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1804 else 1805 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1806 break; 1807 } 1808 1809 return (nvtype); 1810 } 1811 1812 #undef BGE_DBG 1813 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1814 1815 static void 1816 bge_init_recv_rule(bge_t *bgep) 1817 { 1818 bge_recv_rule_t *rulep; 1819 uint32_t i; 1820 1821 /* 1822 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1823 * 1. to direct UDP traffic, set: 1824 * rulep->control = RULE_PROTO_CONTROL; 1825 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1826 * 2. to direct ICMP traffic, set: 1827 * rulep->control = RULE_PROTO_CONTROL; 1828 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1829 * 3. to direct traffic by source ip, set: 1830 * rulep->control = RULE_SIP_CONTROL; 1831 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1832 */ 1833 rulep = bgep->recv_rules; 1834 rulep->control = RULE_PROTO_CONTROL; 1835 rulep->mask_value = RULE_TCP_MASK_VALUE; 1836 1837 /* 1838 * set receive rule registers 1839 */ 1840 rulep = bgep->recv_rules; 1841 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1842 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1843 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1844 } 1845 } 1846 1847 /* 1848 * Using the values captured by bge_chip_cfg_init(), and additional probes 1849 * as required, characterise the chip fully: determine the label by which 1850 * to refer to this chip, the correct settings for various registers, and 1851 * of course whether the device and/or subsystem are supported! 1852 */ 1853 int bge_chip_id_init(bge_t *bgep); 1854 #pragma no_inline(bge_chip_id_init) 1855 1856 int 1857 bge_chip_id_init(bge_t *bgep) 1858 { 1859 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1860 boolean_t sys_ok; 1861 boolean_t dev_ok; 1862 chip_id_t *cidp; 1863 uint32_t subid; 1864 char *devname; 1865 char *sysname; 1866 int *ids; 1867 int err; 1868 uint_t i; 1869 1870 sys_ok = dev_ok = B_FALSE; 1871 cidp = &bgep->chipid; 1872 1873 /* 1874 * Check the PCI device ID to determine the generic chip type and 1875 * select parameters that depend on this. 1876 * 1877 * Note: because the SPARC platforms in general don't fit the 1878 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1879 * as zero - which is why we use <asic_rev> rather than <revision> 1880 * below ... 1881 * 1882 * Note: in general we can't distinguish between the Copper/SerDes 1883 * versions by ID alone, as some Copper devices (e.g. some but not 1884 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1885 * treat them the same here, and the MII code works out the media 1886 * type later on ... 1887 */ 1888 cidp->mbuf_base = bge_mbuf_pool_base; 1889 cidp->mbuf_length = bge_mbuf_pool_len; 1890 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1891 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1892 cidp->pci_type = BGE_PCI_X; 1893 cidp->statistic_type = BGE_STAT_BLK; 1894 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1895 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1896 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1897 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1898 cidp->rx_count_norm = bge_rx_count_norm; 1899 1900 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1901 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1902 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1903 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1904 1905 cidp->msi_enabled = B_FALSE; 1906 1907 switch (cidp->device) { 1908 case DEVICE_ID_5700: 1909 case DEVICE_ID_5700x: 1910 cidp->chip_label = 5700; 1911 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1912 break; 1913 1914 case DEVICE_ID_5701: 1915 cidp->chip_label = 5701; 1916 dev_ok = B_TRUE; 1917 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1918 break; 1919 1920 case DEVICE_ID_5702: 1921 case DEVICE_ID_5702fe: 1922 cidp->chip_label = 5702; 1923 dev_ok = B_TRUE; 1924 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1925 cidp->pci_type = BGE_PCI; 1926 break; 1927 1928 case DEVICE_ID_5703C: 1929 case DEVICE_ID_5703S: 1930 case DEVICE_ID_5703: 1931 /* 1932 * Revision A0 of the 5703/5793 had various errata 1933 * that we can't or don't work around, so it's not 1934 * supported, but all later versions are 1935 */ 1936 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1937 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1938 dev_ok = B_TRUE; 1939 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1940 break; 1941 1942 case DEVICE_ID_5704C: 1943 case DEVICE_ID_5704S: 1944 case DEVICE_ID_5704: 1945 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1946 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1947 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1948 dev_ok = B_TRUE; 1949 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1950 break; 1951 1952 case DEVICE_ID_5705C: 1953 case DEVICE_ID_5705M: 1954 case DEVICE_ID_5705MA3: 1955 case DEVICE_ID_5705F: 1956 case DEVICE_ID_5705_2: 1957 case DEVICE_ID_5754: 1958 if (cidp->device == DEVICE_ID_5754) { 1959 cidp->chip_label = 5754; 1960 cidp->pci_type = BGE_PCI_E; 1961 } else { 1962 cidp->chip_label = 5705; 1963 cidp->pci_type = BGE_PCI; 1964 } 1965 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 1966 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 1967 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 1968 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1969 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1970 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1971 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1972 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 1973 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1974 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1975 cidp->statistic_type = BGE_STAT_REG; 1976 dev_ok = B_TRUE; 1977 break; 1978 1979 case DEVICE_ID_5753: 1980 cidp->chip_label = 5753; 1981 cidp->pci_type = BGE_PCI_E; 1982 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 1983 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 1984 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 1985 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1986 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1987 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1988 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1989 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1990 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 1991 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1992 cidp->statistic_type = BGE_STAT_REG; 1993 dev_ok = B_TRUE; 1994 break; 1995 1996 case DEVICE_ID_5755: 1997 case DEVICE_ID_5755M: 1998 cidp->chip_label = 5755; 1999 cidp->pci_type = BGE_PCI_E; 2000 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2001 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2002 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2003 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2004 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2005 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2006 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2007 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2008 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2009 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2010 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2011 cidp->statistic_type = BGE_STAT_REG; 2012 dev_ok = B_TRUE; 2013 break; 2014 2015 case DEVICE_ID_5787: 2016 case DEVICE_ID_5787M: 2017 cidp->chip_label = 5787; 2018 cidp->pci_type = BGE_PCI_E; 2019 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2020 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2021 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2022 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2023 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2024 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2025 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2026 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2027 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2028 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2029 cidp->statistic_type = BGE_STAT_REG; 2030 dev_ok = B_TRUE; 2031 break; 2032 2033 case DEVICE_ID_5706: 2034 cidp->chip_label = 5706; 2035 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2036 break; 2037 2038 case DEVICE_ID_5782: 2039 /* 2040 * Apart from the label, we treat this as a 5705(?) 2041 */ 2042 cidp->chip_label = 5782; 2043 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2044 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2045 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2046 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2047 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2048 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2049 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2050 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2051 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2052 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2053 cidp->statistic_type = BGE_STAT_REG; 2054 dev_ok = B_TRUE; 2055 break; 2056 2057 case DEVICE_ID_5788: 2058 /* 2059 * Apart from the label, we treat this as a 5705(?) 2060 */ 2061 cidp->chip_label = 5788; 2062 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2063 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2064 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2065 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2066 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2067 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2068 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2069 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2070 cidp->statistic_type = BGE_STAT_REG; 2071 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2072 dev_ok = B_TRUE; 2073 break; 2074 2075 case DEVICE_ID_5714C: 2076 if (cidp->revision >= REVISION_ID_5714_A2) 2077 cidp->msi_enabled = bge_enable_msi; 2078 /* FALLTHRU */ 2079 case DEVICE_ID_5714S: 2080 cidp->chip_label = 5714; 2081 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2082 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2083 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2084 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2085 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2086 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2087 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2088 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2089 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2090 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2091 cidp->pci_type = BGE_PCI_E; 2092 cidp->statistic_type = BGE_STAT_REG; 2093 dev_ok = B_TRUE; 2094 break; 2095 2096 case DEVICE_ID_5715C: 2097 case DEVICE_ID_5715S: 2098 cidp->chip_label = 5715; 2099 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2100 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2101 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2102 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2103 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2104 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2105 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2106 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2107 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2108 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2109 cidp->pci_type = BGE_PCI_E; 2110 cidp->statistic_type = BGE_STAT_REG; 2111 if (cidp->revision >= REVISION_ID_5715_A2) 2112 cidp->msi_enabled = bge_enable_msi; 2113 dev_ok = B_TRUE; 2114 break; 2115 2116 case DEVICE_ID_5721: 2117 cidp->chip_label = 5721; 2118 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2119 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2120 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2121 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2122 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2123 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2124 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2125 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2126 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2127 cidp->pci_type = BGE_PCI_E; 2128 cidp->statistic_type = BGE_STAT_REG; 2129 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2130 dev_ok = B_TRUE; 2131 break; 2132 2133 case DEVICE_ID_5751: 2134 case DEVICE_ID_5751M: 2135 cidp->chip_label = 5751; 2136 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2137 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2138 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2139 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2140 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2141 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2142 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2143 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2144 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2145 cidp->pci_type = BGE_PCI_E; 2146 cidp->statistic_type = BGE_STAT_REG; 2147 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2148 dev_ok = B_TRUE; 2149 break; 2150 2151 case DEVICE_ID_5752: 2152 case DEVICE_ID_5752M: 2153 cidp->chip_label = 5752; 2154 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2155 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2156 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2157 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2158 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2159 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2160 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2161 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2162 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2163 cidp->pci_type = BGE_PCI_E; 2164 cidp->statistic_type = BGE_STAT_REG; 2165 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2166 dev_ok = B_TRUE; 2167 break; 2168 2169 case DEVICE_ID_5789: 2170 cidp->chip_label = 5789; 2171 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2172 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2173 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2174 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2175 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2176 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2177 cidp->pci_type = BGE_PCI_E; 2178 cidp->statistic_type = BGE_STAT_REG; 2179 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2180 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2181 cidp->msi_enabled = B_TRUE; 2182 dev_ok = B_TRUE; 2183 break; 2184 2185 } 2186 2187 /* 2188 * Setup the default jumbo parameter. 2189 */ 2190 cidp->ethmax_size = ETHERMAX; 2191 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2192 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2193 2194 /* 2195 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2196 * setup below jumbo specific parameters. 2197 * 2198 * For BCM5714/5715, there is only one standard receive ring. So the 2199 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2200 * feature is enabled. 2201 */ 2202 if (bge_jumbo_enable && 2203 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2204 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2205 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2206 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2207 cidp->mbuf_lo_water_rdma = 2208 RDMA_MBUF_LOWAT_5714_JUMBO; 2209 cidp->mbuf_lo_water_rmac = 2210 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2211 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2212 cidp->jumbo_slots = 0; 2213 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2214 } else { 2215 cidp->mbuf_lo_water_rdma = 2216 RDMA_MBUF_LOWAT_JUMBO; 2217 cidp->mbuf_lo_water_rmac = 2218 MAC_RX_MBUF_LOWAT_JUMBO; 2219 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2220 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2221 } 2222 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2223 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2224 cidp->ethmax_size = cidp->default_mtu + 2225 sizeof (struct ether_header); 2226 } 2227 2228 /* 2229 * Identify the NV memory type: SEEPROM or Flash? 2230 */ 2231 cidp->nvtype = bge_nvmem_id(bgep); 2232 2233 /* 2234 * Now, we want to check whether this device is part of a 2235 * supported subsystem (e.g., on the motherboard of a Sun 2236 * branded platform). 2237 * 2238 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2239 */ 2240 if (cidp->subven == VENDOR_ID_SUN) 2241 sys_ok = B_TRUE; 2242 2243 /* 2244 * Rule 2: If it's on the list on known subsystems, then it's OK. 2245 * Note: 0x14e41647 should *not* appear in the list, but the code 2246 * doesn't enforce that. 2247 */ 2248 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2249 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2250 if (err == DDI_PROP_SUCCESS) { 2251 /* 2252 * Got the list; scan for a matching subsystem vendor/device 2253 */ 2254 subid = (cidp->subven << 16) | cidp->subdev; 2255 while (i--) 2256 if (ids[i] == subid) 2257 sys_ok = B_TRUE; 2258 ddi_prop_free(ids); 2259 } 2260 2261 /* 2262 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2263 * 2264 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2265 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2266 * we have to check specially for the exact device paths to the 2267 * motherboard devices on those platforms ;-( 2268 * 2269 * Note: we can't just use the "supported-subsystems" mechanism 2270 * above, because the entry would have to be 0x14e41647 -- which 2271 * would then accept *any* plugin card that *didn't* contain a 2272 * (valid) SEEPROM ;-( 2273 */ 2274 sysname = ddi_node_name(ddi_root_node()); 2275 devname = ddi_pathname(bgep->devinfo, buf); 2276 ASSERT(strlen(devname) > 0); 2277 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2278 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2279 sys_ok = B_TRUE; 2280 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2281 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2282 sys_ok = B_TRUE; 2283 2284 /* 2285 * Now check what we've discovered: is this truly a supported 2286 * chip on (the motherboard of) a supported platform? 2287 * 2288 * Possible problems here: 2289 * 1) it's a completely unheard-of chip (e.g. 5761) 2290 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2291 * 3) it's a chip we would support if it were on the motherboard 2292 * of a Sun platform, but this one isn't ;-( 2293 */ 2294 if (cidp->chip_label == 0) 2295 bge_problem(bgep, 2296 "Device 'pci%04x,%04x' not recognized (%d?)", 2297 cidp->vendor, cidp->device, cidp->device); 2298 else if (!dev_ok) 2299 bge_problem(bgep, 2300 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2301 cidp->vendor, cidp->device, cidp->chip_label, 2302 cidp->revision); 2303 #if BGE_DEBUGGING 2304 else if (!sys_ok) 2305 bge_problem(bgep, 2306 "%d-based subsystem 'pci%04x,%04x' not validated", 2307 cidp->chip_label, cidp->subven, cidp->subdev); 2308 #endif 2309 else 2310 cidp->flags |= CHIP_FLAG_SUPPORTED; 2311 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2312 return (EIO); 2313 return (0); 2314 } 2315 2316 void 2317 bge_chip_msi_trig(bge_t *bgep) 2318 { 2319 uint32_t regval; 2320 2321 regval = bgep->param_msi_cnt<<4; 2322 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2323 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2324 } 2325 2326 /* 2327 * Various registers that control the chip's internal engines (state 2328 * machines) have a <reset> and <enable> bits (fortunately, in the 2329 * same place in each such register :-). 2330 * 2331 * To reset the state machine, the <reset> bit must be written with 1; 2332 * it will then read back as 1 while the reset is in progress, but 2333 * self-clear to 0 when the reset completes. 2334 * 2335 * To enable a state machine, one must set the <enable> bit, which 2336 * will continue to read back as 0 until the state machine is running. 2337 * 2338 * To disable a state machine, the <enable> bit must be cleared, but 2339 * it will continue to read back as 1 until the state machine actually 2340 * stops. 2341 * 2342 * This routine implements polling for completion of a reset, enable 2343 * or disable operation, returning B_TRUE on success (bit reached the 2344 * required state) or B_FALSE on timeout (200*100us == 20ms). 2345 */ 2346 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2347 uint32_t mask, uint32_t val); 2348 #pragma no_inline(bge_chip_poll_engine) 2349 2350 static boolean_t 2351 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2352 uint32_t mask, uint32_t val) 2353 { 2354 uint32_t regval; 2355 uint32_t n; 2356 2357 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2358 (void *)bgep, regno, mask, val)); 2359 2360 for (n = 200; n; --n) { 2361 regval = bge_reg_get32(bgep, regno); 2362 if ((regval & mask) == val) 2363 return (B_TRUE); 2364 drv_usecwait(100); 2365 } 2366 2367 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2368 return (B_FALSE); 2369 } 2370 2371 /* 2372 * Various registers that control the chip's internal engines (state 2373 * machines) have a <reset> bit (fortunately, in the same place in 2374 * each such register :-). To reset the state machine, this bit must 2375 * be written with 1; it will then read back as 1 while the reset is 2376 * in progress, but self-clear to 0 when the reset completes. 2377 * 2378 * This code sets the bit, then polls for it to read back as zero. 2379 * The return value is B_TRUE on success (reset bit cleared itself), 2380 * or B_FALSE if the state machine didn't recover :( 2381 * 2382 * NOTE: the Core reset is similar to other resets, except that we 2383 * can't poll for completion, since the Core reset disables memory 2384 * access! So we just have to assume that it will all complete in 2385 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2386 */ 2387 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2388 #pragma no_inline(bge_chip_reset_engine) 2389 2390 static boolean_t 2391 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2392 { 2393 uint32_t regval; 2394 uint32_t val32; 2395 2396 regval = bge_reg_get32(bgep, regno); 2397 2398 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2399 (void *)bgep, regno)); 2400 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2401 regno, regval)); 2402 2403 regval |= STATE_MACHINE_RESET_BIT; 2404 2405 switch (regno) { 2406 case MISC_CONFIG_REG: 2407 /* 2408 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2409 * resetting PCIE block and bringing PCIE link down, bit 29 2410 * in the register needs to be set first, and then set it again 2411 * while the reset bit is written. 2412 * See:P500 of 57xx-PG102-RDS.pdf. 2413 */ 2414 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2415 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2416 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2417 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2418 if (bgep->chipid.pci_type == BGE_PCI_E) { 2419 if (bgep->chipid.asic_rev == 2420 MHCR_CHIP_REV_5751_A0 || 2421 bgep->chipid.asic_rev == 2422 MHCR_CHIP_REV_5721_A0 || 2423 bgep->chipid.asic_rev == 2424 MHCR_CHIP_REV_5755_A0) { 2425 val32 = bge_reg_get32(bgep, 2426 PHY_TEST_CTRL_REG); 2427 if (val32 == (PHY_PCIE_SCRAM_MODE | 2428 PHY_PCIE_LTASS_MODE)) 2429 bge_reg_put32(bgep, 2430 PHY_TEST_CTRL_REG, 2431 PHY_PCIE_SCRAM_MODE); 2432 val32 = pci_config_get32 2433 (bgep->cfg_handle, 2434 PCI_CONF_BGE_CLKCTL); 2435 val32 |= CLKCTL_PCIE_A0_FIX; 2436 pci_config_put32(bgep->cfg_handle, 2437 PCI_CONF_BGE_CLKCTL, val32); 2438 } 2439 bge_reg_set32(bgep, regno, 2440 MISC_CONFIG_GRC_RESET_DISABLE); 2441 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2442 } 2443 } 2444 2445 /* 2446 * Special case - causes Core reset 2447 * 2448 * On SPARC v9 we want to ensure that we don't start 2449 * timing until the I/O access has actually reached 2450 * the chip, otherwise we might make the next access 2451 * too early. And we can't just force the write out 2452 * by following it with a read (even to config space) 2453 * because that would cause the fault we're trying 2454 * to avoid. Hence the need for membar_sync() here. 2455 */ 2456 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2457 #ifdef __sparcv9 2458 membar_sync(); 2459 #endif /* __sparcv9 */ 2460 /* 2461 * On some platforms,system need about 300us for 2462 * link setup. 2463 */ 2464 drv_usecwait(300); 2465 2466 if (bgep->chipid.pci_type == BGE_PCI_E) { 2467 /* PCI-E device need more reset time */ 2468 drv_usecwait(120000); 2469 2470 /* Set PCIE max payload size and clear error status. */ 2471 if ((bgep->chipid.chip_label == 5721) || 2472 (bgep->chipid.chip_label == 5751) || 2473 (bgep->chipid.chip_label == 5752) || 2474 (bgep->chipid.chip_label == 5789)) { 2475 pci_config_put16(bgep->cfg_handle, 2476 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2477 pci_config_put16(bgep->cfg_handle, 2478 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2479 } 2480 } 2481 2482 BGE_PCICHK(bgep); 2483 return (B_TRUE); 2484 2485 default: 2486 bge_reg_put32(bgep, regno, regval); 2487 return (bge_chip_poll_engine(bgep, regno, 2488 STATE_MACHINE_RESET_BIT, 0)); 2489 } 2490 } 2491 2492 /* 2493 * Various registers that control the chip's internal engines (state 2494 * machines) have an <enable> bit (fortunately, in the same place in 2495 * each such register :-). To stop the state machine, this bit must 2496 * be written with 0, then polled to see when the state machine has 2497 * actually stopped. 2498 * 2499 * The return value is B_TRUE on success (enable bit cleared), or 2500 * B_FALSE if the state machine didn't stop :( 2501 */ 2502 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2503 uint32_t morebits); 2504 #pragma no_inline(bge_chip_disable_engine) 2505 2506 static boolean_t 2507 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2508 { 2509 uint32_t regval; 2510 2511 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2512 (void *)bgep, regno, morebits)); 2513 2514 switch (regno) { 2515 case FTQ_RESET_REG: 2516 /* 2517 * For Schumacher's bugfix CR6490108 2518 */ 2519 #ifdef BGE_IPMI_ASF 2520 #ifdef BGE_NETCONSOLE 2521 if (bgep->asf_enabled) 2522 return (B_TRUE); 2523 #endif 2524 #endif 2525 /* 2526 * Not quite like the others; it doesn't 2527 * have an <enable> bit, but instead we 2528 * have to set and then clear all the bits 2529 */ 2530 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2531 drv_usecwait(100); 2532 bge_reg_put32(bgep, regno, 0); 2533 return (B_TRUE); 2534 2535 default: 2536 regval = bge_reg_get32(bgep, regno); 2537 regval &= ~STATE_MACHINE_ENABLE_BIT; 2538 regval &= ~morebits; 2539 bge_reg_put32(bgep, regno, regval); 2540 return (bge_chip_poll_engine(bgep, regno, 2541 STATE_MACHINE_ENABLE_BIT, 0)); 2542 } 2543 } 2544 2545 /* 2546 * Various registers that control the chip's internal engines (state 2547 * machines) have an <enable> bit (fortunately, in the same place in 2548 * each such register :-). To start the state machine, this bit must 2549 * be written with 1, then polled to see when the state machine has 2550 * actually started. 2551 * 2552 * The return value is B_TRUE on success (enable bit set), or 2553 * B_FALSE if the state machine didn't start :( 2554 */ 2555 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2556 uint32_t morebits); 2557 #pragma no_inline(bge_chip_enable_engine) 2558 2559 static boolean_t 2560 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2561 { 2562 uint32_t regval; 2563 2564 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2565 (void *)bgep, regno, morebits)); 2566 2567 switch (regno) { 2568 case FTQ_RESET_REG: 2569 #ifdef BGE_IPMI_ASF 2570 #ifdef BGE_NETCONSOLE 2571 if (bgep->asf_enabled) 2572 return (B_TRUE); 2573 #endif 2574 #endif 2575 /* 2576 * Not quite like the others; it doesn't 2577 * have an <enable> bit, but instead we 2578 * have to set and then clear all the bits 2579 */ 2580 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2581 drv_usecwait(100); 2582 bge_reg_put32(bgep, regno, 0); 2583 return (B_TRUE); 2584 2585 default: 2586 regval = bge_reg_get32(bgep, regno); 2587 regval |= STATE_MACHINE_ENABLE_BIT; 2588 regval |= morebits; 2589 bge_reg_put32(bgep, regno, regval); 2590 return (bge_chip_poll_engine(bgep, regno, 2591 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2592 } 2593 } 2594 2595 /* 2596 * Reprogram the Ethernet, Transmit, and Receive MAC 2597 * modes to match the param_* variables 2598 */ 2599 void bge_sync_mac_modes(bge_t *bgep); 2600 #pragma no_inline(bge_sync_mac_modes) 2601 2602 void 2603 bge_sync_mac_modes(bge_t *bgep) 2604 { 2605 uint32_t macmode; 2606 uint32_t regval; 2607 2608 ASSERT(mutex_owned(bgep->genlock)); 2609 2610 /* 2611 * Reprogram the Ethernet MAC mode ... 2612 */ 2613 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2614 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2615 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2616 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2617 else 2618 macmode |= ETHERNET_MODE_LINK_POLARITY; 2619 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2620 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2621 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2622 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2623 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2624 macmode |= ETHERNET_MODE_PORTMODE_MII; 2625 else 2626 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2627 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2628 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2629 else 2630 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2631 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2632 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2633 else 2634 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2635 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2636 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2637 (void *)bgep, regval, macmode)); 2638 2639 /* 2640 * ... the Transmit MAC mode ... 2641 */ 2642 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2643 if (bgep->param_link_tx_pause) 2644 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2645 else 2646 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2647 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2648 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2649 (void *)bgep, regval, macmode)); 2650 2651 /* 2652 * ... and the Receive MAC mode 2653 */ 2654 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2655 if (bgep->param_link_rx_pause) 2656 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2657 else 2658 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2659 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2660 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2661 (void *)bgep, regval, macmode)); 2662 } 2663 2664 /* 2665 * bge_chip_sync() -- program the chip with the unicast MAC address, 2666 * the multicast hash table, the required level of promiscuity, and 2667 * the current loopback mode ... 2668 */ 2669 #ifdef BGE_IPMI_ASF 2670 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2671 #else 2672 int bge_chip_sync(bge_t *bgep); 2673 #endif 2674 #pragma no_inline(bge_chip_sync) 2675 2676 int 2677 #ifdef BGE_IPMI_ASF 2678 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2679 #else 2680 bge_chip_sync(bge_t *bgep) 2681 #endif 2682 { 2683 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2684 boolean_t promisc; 2685 uint64_t macaddr; 2686 uint32_t fill; 2687 int i, j; 2688 int retval = DDI_SUCCESS; 2689 2690 BGE_TRACE(("bge_chip_sync($%p)", 2691 (void *)bgep)); 2692 2693 ASSERT(mutex_owned(bgep->genlock)); 2694 2695 promisc = B_FALSE; 2696 fill = ~(uint32_t)0; 2697 2698 if (bgep->promisc) 2699 promisc = B_TRUE; 2700 else 2701 fill = (uint32_t)0; 2702 2703 /* 2704 * If the TX/RX MAC engines are already running, we should stop 2705 * them (and reset the RX engine) before changing the parameters. 2706 * If they're not running, this will have no effect ... 2707 * 2708 * NOTE: this is currently disabled by default because stopping 2709 * and restarting the Tx engine may cause an outgoing packet in 2710 * transit to be truncated. Also, stopping and restarting the 2711 * Rx engine seems to not work correctly on the 5705. Testing 2712 * has not (yet!) revealed any problems with NOT stopping and 2713 * restarting these engines (and Broadcom say their drivers don't 2714 * do this), but if it is found to cause problems, this variable 2715 * can be patched to re-enable the old behaviour ... 2716 */ 2717 if (bge_stop_start_on_sync) { 2718 #ifdef BGE_IPMI_ASF 2719 if (!bgep->asf_enabled) { 2720 if (!bge_chip_disable_engine(bgep, 2721 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2722 retval = DDI_FAILURE; 2723 } else { 2724 if (!bge_chip_disable_engine(bgep, 2725 RECEIVE_MAC_MODE_REG, 0)) 2726 retval = DDI_FAILURE; 2727 } 2728 #else 2729 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2730 RECEIVE_MODE_KEEP_VLAN_TAG)) 2731 retval = DDI_FAILURE; 2732 #endif 2733 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2734 retval = DDI_FAILURE; 2735 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2736 retval = DDI_FAILURE; 2737 } 2738 2739 /* 2740 * Reprogram the hashed multicast address table ... 2741 */ 2742 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2743 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2744 2745 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2746 bge_reg_put32(bgep, MAC_HASH_REG(i), 2747 bgep->mcast_hash[i] | fill); 2748 2749 #ifdef BGE_IPMI_ASF 2750 if (!bgep->asf_enabled || !asf_keeplive) { 2751 #endif 2752 /* 2753 * Transform the MAC address(es) from host to chip format, then 2754 * reprogram the transmit random backoff seed and the unicast 2755 * MAC address(es) ... 2756 */ 2757 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2758 for (i = 0, fill = 0, macaddr = 0ull; 2759 i < ETHERADDRL; ++i) { 2760 macaddr <<= 8; 2761 macaddr |= bgep->curr_addr[j].addr[i]; 2762 fill += bgep->curr_addr[j].addr[i]; 2763 } 2764 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2765 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2766 } 2767 2768 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2769 (void *)bgep, macaddr)); 2770 #ifdef BGE_IPMI_ASF 2771 } 2772 #endif 2773 2774 /* 2775 * Set or clear the PROMISCUOUS mode bit 2776 */ 2777 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2778 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2779 2780 /* 2781 * Sync the rest of the MAC modes too ... 2782 */ 2783 bge_sync_mac_modes(bgep); 2784 2785 /* 2786 * Restart RX/TX MAC engines if required ... 2787 */ 2788 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2789 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2790 retval = DDI_FAILURE; 2791 #ifdef BGE_IPMI_ASF 2792 if (!bgep->asf_enabled) { 2793 if (!bge_chip_enable_engine(bgep, 2794 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2795 retval = DDI_FAILURE; 2796 } else { 2797 if (!bge_chip_enable_engine(bgep, 2798 RECEIVE_MAC_MODE_REG, 0)) 2799 retval = DDI_FAILURE; 2800 } 2801 #else 2802 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2803 RECEIVE_MODE_KEEP_VLAN_TAG)) 2804 retval = DDI_FAILURE; 2805 #endif 2806 } 2807 return (retval); 2808 } 2809 2810 /* 2811 * This array defines the sequence of state machine control registers 2812 * in which the <enable> bit must be cleared to bring the chip to a 2813 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2814 */ 2815 static bge_regno_t shutdown_engine_regs[] = { 2816 RECEIVE_MAC_MODE_REG, 2817 RCV_BD_INITIATOR_MODE_REG, 2818 RCV_LIST_PLACEMENT_MODE_REG, 2819 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2820 RCV_DATA_BD_INITIATOR_MODE_REG, 2821 RCV_DATA_COMPLETION_MODE_REG, 2822 RCV_BD_COMPLETION_MODE_REG, 2823 2824 SEND_BD_SELECTOR_MODE_REG, 2825 SEND_BD_INITIATOR_MODE_REG, 2826 SEND_DATA_INITIATOR_MODE_REG, 2827 READ_DMA_MODE_REG, 2828 SEND_DATA_COMPLETION_MODE_REG, 2829 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2830 SEND_BD_COMPLETION_MODE_REG, 2831 TRANSMIT_MAC_MODE_REG, 2832 2833 HOST_COALESCE_MODE_REG, 2834 WRITE_DMA_MODE_REG, 2835 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2836 FTQ_RESET_REG, /* special - see code */ 2837 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2838 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2839 BGE_REGNO_NONE /* terminator */ 2840 }; 2841 2842 /* 2843 * bge_chip_stop() -- stop all chip processing 2844 * 2845 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2846 * we've detected a problem internally; otherwise, this is a normal 2847 * (clean) stop (at user request i.e. the last STREAM has been closed). 2848 */ 2849 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2850 #pragma no_inline(bge_chip_stop) 2851 2852 void 2853 bge_chip_stop(bge_t *bgep, boolean_t fault) 2854 { 2855 bge_regno_t regno; 2856 bge_regno_t *rbp; 2857 boolean_t ok; 2858 2859 BGE_TRACE(("bge_chip_stop($%p)", 2860 (void *)bgep)); 2861 2862 ASSERT(mutex_owned(bgep->genlock)); 2863 2864 rbp = shutdown_engine_regs; 2865 /* 2866 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2867 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2868 * -ory arbiter should not be disabled. 2869 */ 2870 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2871 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2872 ok &= bge_chip_disable_engine(bgep, regno, 0); 2873 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2874 (regno != DMA_COMPLETION_MODE_REG) && 2875 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2876 (regno != BUFFER_MANAGER_MODE_REG) && 2877 (regno != MEMORY_ARBITER_MODE_REG)) 2878 ok &= bge_chip_disable_engine(bgep, 2879 regno, 0); 2880 } 2881 2882 if (!ok && !fault) 2883 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2884 2885 /* 2886 * Finally, disable (all) MAC events & clear the MAC status 2887 */ 2888 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2889 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2890 2891 /* 2892 * if we're stopping the chip because of a detected fault then do 2893 * appropriate actions 2894 */ 2895 if (fault) { 2896 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2897 bgep->bge_chip_state = BGE_CHIP_FAULT; 2898 if (!bgep->manual_reset) 2899 ddi_fm_service_impact(bgep->devinfo, 2900 DDI_SERVICE_LOST); 2901 if (bgep->bge_dma_error) { 2902 /* 2903 * need to free buffers in case the fault was 2904 * due to a memory error in a buffer - got to 2905 * do a fair bit of tidying first 2906 */ 2907 if (bgep->progress & PROGRESS_KSTATS) { 2908 bge_fini_kstats(bgep); 2909 bgep->progress &= ~PROGRESS_KSTATS; 2910 } 2911 if (bgep->progress & PROGRESS_INTR) { 2912 bge_intr_disable(bgep); 2913 rw_enter(bgep->errlock, RW_WRITER); 2914 bge_fini_rings(bgep); 2915 rw_exit(bgep->errlock); 2916 bgep->progress &= ~PROGRESS_INTR; 2917 } 2918 if (bgep->progress & PROGRESS_BUFS) { 2919 bge_free_bufs(bgep); 2920 bgep->progress &= ~PROGRESS_BUFS; 2921 } 2922 bgep->bge_dma_error = B_FALSE; 2923 } 2924 } 2925 } else 2926 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2927 } 2928 2929 /* 2930 * Poll for completion of chip's ROM firmware; also, at least on the 2931 * first time through, find and return the hardware MAC address, if any. 2932 */ 2933 static uint64_t bge_poll_firmware(bge_t *bgep); 2934 #pragma no_inline(bge_poll_firmware) 2935 2936 static uint64_t 2937 bge_poll_firmware(bge_t *bgep) 2938 { 2939 uint64_t magic; 2940 uint64_t mac; 2941 uint32_t gen; 2942 uint32_t i; 2943 2944 /* 2945 * Step 19: poll for firmware completion (GENCOMM port set 2946 * to the ones complement of T3_MAGIC_NUMBER). 2947 * 2948 * While we're at it, we also read the MAC address register; 2949 * at some stage the firmware will load this with the 2950 * factory-set value. 2951 * 2952 * When both the magic number and the MAC address are set, 2953 * we're done; but we impose a time limit of one second 2954 * (1000*1000us) in case the firmware fails in some fashion 2955 * or the SEEPROM that provides that MAC address isn't fitted. 2956 * 2957 * After the first time through (chip state != INITIAL), we 2958 * don't need the MAC address to be set (we've already got it 2959 * or not, from the first time), so we don't wait for it, but 2960 * we still have to wait for the T3_MAGIC_NUMBER. 2961 * 2962 * Note: the magic number is only a 32-bit quantity, but the NIC 2963 * memory is 64-bit (and big-endian) internally. Addressing the 2964 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2965 * it work correctly on both big- and little-endian hosts. 2966 */ 2967 for (i = 0; i < 1000; ++i) { 2968 drv_usecwait(1000); 2969 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2970 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2971 drv_usecwait(100000); 2972 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2973 #ifdef BGE_IPMI_ASF 2974 if (!bgep->asf_enabled) { 2975 #endif 2976 if (gen != ~T3_MAGIC_NUMBER) 2977 continue; 2978 #ifdef BGE_IPMI_ASF 2979 } 2980 #endif 2981 if (mac != 0ULL) 2982 break; 2983 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2984 break; 2985 } 2986 2987 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2988 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2989 (void *)bgep, gen, i)); 2990 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2991 mac, magic)); 2992 2993 return (mac); 2994 } 2995 2996 /* 2997 * Maximum times of trying to get the NVRAM access lock 2998 * by calling bge_nvmem_acquire() 2999 */ 3000 #define MAX_TRY_NVMEM_ACQUIRE 10000 3001 3002 #ifdef BGE_IPMI_ASF 3003 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3004 #else 3005 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3006 #endif 3007 #pragma no_inline(bge_chip_reset) 3008 3009 int 3010 #ifdef BGE_IPMI_ASF 3011 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3012 #else 3013 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3014 #endif 3015 { 3016 chip_id_t chipid; 3017 uint64_t mac; 3018 uint64_t magic; 3019 uint32_t modeflags; 3020 uint32_t mhcr; 3021 uint32_t sx0; 3022 uint32_t i, tries; 3023 #ifdef BGE_IPMI_ASF 3024 uint32_t mailbox; 3025 #endif 3026 int retval = DDI_SUCCESS; 3027 3028 BGE_TRACE(("bge_chip_reset($%p, %d)", 3029 (void *)bgep, enable_dma)); 3030 3031 ASSERT(mutex_owned(bgep->genlock)); 3032 3033 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3034 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3035 3036 /* 3037 * Do we need to stop the chip cleanly before resetting? 3038 */ 3039 switch (bgep->bge_chip_state) { 3040 default: 3041 _NOTE(NOTREACHED) 3042 return (DDI_FAILURE); 3043 3044 case BGE_CHIP_INITIAL: 3045 case BGE_CHIP_STOPPED: 3046 case BGE_CHIP_RESET: 3047 break; 3048 3049 case BGE_CHIP_RUNNING: 3050 case BGE_CHIP_ERROR: 3051 case BGE_CHIP_FAULT: 3052 bge_chip_stop(bgep, B_FALSE); 3053 break; 3054 } 3055 3056 #ifdef BGE_IPMI_ASF 3057 if (bgep->asf_enabled) { 3058 #ifdef __sparc 3059 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3060 MHCR_ENABLE_TAGGED_STATUS_MODE | 3061 MHCR_MASK_INTERRUPT_MODE | 3062 MHCR_MASK_PCI_INT_OUTPUT | 3063 MHCR_CLEAR_INTERRUPT_INTA | 3064 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3065 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3066 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3067 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3068 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3069 MEMORY_ARBITER_ENABLE); 3070 #endif 3071 if (asf_mode == ASF_MODE_INIT) { 3072 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3073 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3074 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3075 } 3076 } 3077 #endif 3078 /* 3079 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3080 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3081 * 3082 * Before reset Core clock,it is 3083 * also required to initialize the Memory Arbiter as specified in step9 3084 * and Misc Host Control Register as specified in step-13 3085 * Step 4-5: reset Core clock & wait for completion 3086 * Steps 6-8: are done by bge_chip_cfg_init() 3087 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3088 */ 3089 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3090 retval = DDI_FAILURE; 3091 3092 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3093 MHCR_ENABLE_TAGGED_STATUS_MODE | 3094 MHCR_MASK_INTERRUPT_MODE | 3095 MHCR_MASK_PCI_INT_OUTPUT | 3096 MHCR_CLEAR_INTERRUPT_INTA; 3097 #ifdef _BIG_ENDIAN 3098 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3099 #endif /* _BIG_ENDIAN */ 3100 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3101 #ifdef BGE_IPMI_ASF 3102 if (bgep->asf_enabled) 3103 bgep->asf_wordswapped = B_FALSE; 3104 #endif 3105 /* 3106 * NVRAM Corruption Workaround 3107 */ 3108 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3109 if (bge_nvmem_acquire(bgep) != EAGAIN) 3110 break; 3111 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3112 BGE_DEBUG(("%s: fail to acquire nvram lock", 3113 bgep->ifname)); 3114 3115 #ifdef BGE_IPMI_ASF 3116 if (!bgep->asf_enabled) { 3117 #endif 3118 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3119 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3120 #ifdef BGE_IPMI_ASF 3121 } 3122 #endif 3123 3124 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3125 retval = DDI_FAILURE; 3126 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3127 3128 /* 3129 * Step 8a: This may belong elsewhere, but BCM5721 needs 3130 * a bit set to avoid a fifo overflow/underflow bug. 3131 */ 3132 if ((bgep->chipid.chip_label == 5721) || 3133 (bgep->chipid.chip_label == 5751) || 3134 (bgep->chipid.chip_label == 5752) || 3135 (bgep->chipid.chip_label == 5755) || 3136 (bgep->chipid.chip_label == 5789)) 3137 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3138 3139 3140 /* 3141 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3142 * not be changed. 3143 */ 3144 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3145 retval = DDI_FAILURE; 3146 3147 /* 3148 * Steps 10-11: configure PIO endianness options and 3149 * enable indirect register access -- already done 3150 * Steps 12-13: enable writing to the PCI state & clock 3151 * control registers -- not required; we aren't going to 3152 * use those features. 3153 * Steps 14-15: Configure DMA endianness options. See 3154 * the comments on the setting of the MHCR above. 3155 */ 3156 #ifdef _BIG_ENDIAN 3157 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3158 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3159 #else 3160 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3161 #endif /* _BIG_ENDIAN */ 3162 #ifdef BGE_IPMI_ASF 3163 if (bgep->asf_enabled) 3164 modeflags |= MODE_HOST_STACK_UP; 3165 #endif 3166 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3167 3168 #ifdef BGE_IPMI_ASF 3169 if (bgep->asf_enabled) { 3170 #ifdef __sparc 3171 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3172 MEMORY_ARBITER_ENABLE | 3173 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3174 #endif 3175 3176 #ifdef BGE_NETCONSOLE 3177 if (!bgep->asf_newhandshake) { 3178 if ((asf_mode == ASF_MODE_INIT) || 3179 (asf_mode == ASF_MODE_POST_INIT)) { 3180 bge_asf_post_reset_old_mode(bgep, 3181 BGE_INIT_RESET); 3182 } else { 3183 bge_asf_post_reset_old_mode(bgep, 3184 BGE_SHUTDOWN_RESET); 3185 } 3186 } 3187 #endif 3188 3189 /* Wait for NVRAM init */ 3190 i = 0; 3191 drv_usecwait(5000); 3192 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3193 3194 while ((mailbox != (uint32_t) 3195 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3196 (i < 10000)) { 3197 drv_usecwait(100); 3198 mailbox = bge_nic_get32(bgep, 3199 BGE_FIRMWARE_MAILBOX); 3200 i++; 3201 } 3202 3203 #ifndef BGE_NETCONSOLE 3204 if (!bgep->asf_newhandshake) { 3205 if ((asf_mode == ASF_MODE_INIT) || 3206 (asf_mode == ASF_MODE_POST_INIT)) { 3207 3208 bge_asf_post_reset_old_mode(bgep, 3209 BGE_INIT_RESET); 3210 } else { 3211 bge_asf_post_reset_old_mode(bgep, 3212 BGE_SHUTDOWN_RESET); 3213 } 3214 } 3215 #endif 3216 } 3217 #endif 3218 /* 3219 * Steps 16-17: poll for firmware completion 3220 */ 3221 mac = bge_poll_firmware(bgep); 3222 3223 /* 3224 * Step 18: enable external memory -- doesn't apply. 3225 * 3226 * However we take the opportunity to set the MLCR anyway, as 3227 * this register also controls the SEEPROM auto-access method 3228 * which we may want to use later ... 3229 * 3230 * The proper value here depends on the way the chip is wired 3231 * into the circuit board, as this register *also* controls which 3232 * of the "Miscellaneous I/O" pins are driven as outputs and the 3233 * values driven onto those pins! 3234 * 3235 * See also step 74 in the PRM ... 3236 */ 3237 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3238 bgep->chipid.bge_mlcr_default); 3239 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3240 3241 /* 3242 * Step 20: clear the Ethernet MAC mode register 3243 */ 3244 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3245 3246 /* 3247 * Step 21: restore cache-line-size, latency timer, and 3248 * subsystem ID registers to their original values (not 3249 * those read into the local structure <chipid>, 'cos 3250 * that was after they were cleared by the RESET). 3251 * 3252 * Note: the Subsystem Vendor/Device ID registers are not 3253 * directly writable in config space, so we use the shadow 3254 * copy in "Page Zero" of register space to restore them 3255 * both in one go ... 3256 */ 3257 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3258 bgep->chipid.clsize); 3259 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3260 bgep->chipid.latency); 3261 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3262 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3263 3264 /* 3265 * The SEND INDEX registers should be reset to zero by the 3266 * global chip reset; if they're not, there'll be trouble 3267 * later on. 3268 */ 3269 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3270 if (sx0 != 0) { 3271 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3272 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3273 retval = DDI_FAILURE; 3274 } 3275 3276 /* Enable MSI code */ 3277 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3278 bge_reg_set32(bgep, MSI_MODE_REG, 3279 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3280 3281 /* 3282 * On the first time through, save the factory-set MAC address 3283 * (if any). If bge_poll_firmware() above didn't return one 3284 * (from a chip register) consider looking in the attached NV 3285 * memory device, if any. Once we have it, we save it in both 3286 * register-image (64-bit) and byte-array forms. All-zero and 3287 * all-one addresses are not valid, and we refuse to stash those. 3288 */ 3289 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3290 if (mac == 0ULL) 3291 mac = bge_get_nvmac(bgep); 3292 if (mac != 0ULL && mac != ~0ULL) { 3293 bgep->chipid.hw_mac_addr = mac; 3294 for (i = ETHERADDRL; i-- != 0; ) { 3295 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3296 mac >>= 8; 3297 } 3298 bgep->chipid.vendor_addr.set = B_TRUE; 3299 } 3300 } 3301 3302 #ifdef BGE_IPMI_ASF 3303 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3304 if (asf_mode != ASF_MODE_NONE) { 3305 if ((asf_mode == ASF_MODE_INIT) || 3306 (asf_mode == ASF_MODE_POST_INIT)) { 3307 3308 bge_asf_post_reset_new_mode(bgep, 3309 BGE_INIT_RESET); 3310 } else { 3311 bge_asf_post_reset_new_mode(bgep, 3312 BGE_SHUTDOWN_RESET); 3313 } 3314 } 3315 } 3316 #endif 3317 3318 /* 3319 * Record the new state 3320 */ 3321 bgep->chip_resets += 1; 3322 bgep->bge_chip_state = BGE_CHIP_RESET; 3323 return (retval); 3324 } 3325 3326 /* 3327 * bge_chip_start() -- start the chip transmitting and/or receiving, 3328 * including enabling interrupts 3329 */ 3330 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3331 #pragma no_inline(bge_chip_start) 3332 3333 int 3334 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3335 { 3336 uint32_t coalmode; 3337 uint32_t ledctl; 3338 uint32_t mtu; 3339 uint32_t maxring; 3340 uint32_t stats_mask; 3341 uint32_t dma_wrprio; 3342 uint64_t ring; 3343 int retval = DDI_SUCCESS; 3344 3345 BGE_TRACE(("bge_chip_start($%p)", 3346 (void *)bgep)); 3347 3348 ASSERT(mutex_owned(bgep->genlock)); 3349 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3350 3351 /* 3352 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3353 * The document specifies 95 separate steps to fully 3354 * initialise the chip!!!! 3355 * 3356 * The reset code above has already got us as far as step 3357 * 21, so we continue with ... 3358 * 3359 * Step 22: clear the MAC statistics block 3360 * (0x0300-0x0aff in NIC-local memory) 3361 */ 3362 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3363 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3364 NIC_MEM_STATISTICS_SIZE); 3365 3366 /* 3367 * Step 23: clear the status block (in host memory) 3368 */ 3369 DMA_ZERO(bgep->status_block); 3370 3371 /* 3372 * Step 24: set DMA read/write control register 3373 */ 3374 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3375 bgep->chipid.bge_dma_rwctrl); 3376 3377 /* 3378 * Step 25: Configure DMA endianness -- already done (16/17) 3379 * Step 26: Configure Host-Based Send Rings 3380 * Step 27: Indicate Host Stack Up 3381 */ 3382 bge_reg_set32(bgep, MODE_CONTROL_REG, 3383 MODE_HOST_SEND_BDS | 3384 MODE_HOST_STACK_UP); 3385 3386 /* 3387 * Step 28: Configure checksum options: 3388 * Solaris supports the hardware default checksum options. 3389 * 3390 * Workaround for Incorrect pseudo-header checksum calculation. 3391 */ 3392 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3393 bge_reg_set32(bgep, MODE_CONTROL_REG, 3394 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3395 3396 /* 3397 * Step 29: configure Timer Prescaler. The value is always the 3398 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3399 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3400 * for the whole chip! 3401 */ 3402 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3403 3404 /* 3405 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3406 * 3407 * If the mbuf_length is specified as 0, we just leave these at 3408 * their hardware defaults, rather than explicitly setting them. 3409 * As the Broadcom HRM,driver better not change the parameters 3410 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3411 */ 3412 if ((bgep->chipid.mbuf_length != 0) && 3413 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3414 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3415 bgep->chipid.mbuf_base); 3416 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3417 bgep->chipid.mbuf_length); 3418 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3419 DMAD_POOL_BASE_DEFAULT); 3420 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3421 DMAD_POOL_LENGTH_DEFAULT); 3422 } 3423 3424 /* 3425 * Step 32: configure MAC memory pool watermarks 3426 */ 3427 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3428 bgep->chipid.mbuf_lo_water_rdma); 3429 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3430 bgep->chipid.mbuf_lo_water_rmac); 3431 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3432 bgep->chipid.mbuf_hi_water); 3433 3434 /* 3435 * Step 33: configure DMA resource watermarks 3436 */ 3437 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3438 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3439 bge_dmad_lo_water); 3440 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3441 bge_dmad_hi_water); 3442 } 3443 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3444 3445 /* 3446 * Steps 34-36: enable buffer manager & internal h/w queues 3447 */ 3448 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3449 STATE_MACHINE_ATTN_ENABLE_BIT)) 3450 retval = DDI_FAILURE; 3451 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3452 retval = DDI_FAILURE; 3453 3454 /* 3455 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3456 */ 3457 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3458 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3459 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3460 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3461 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3462 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3463 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3464 } 3465 3466 /* 3467 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3468 */ 3469 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3470 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3471 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3472 bge_replenish_jumbo); 3473 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3474 bge_replenish_mini); 3475 } 3476 3477 /* 3478 * Steps 41-43: clear Send Ring Producer Indices and initialise 3479 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3480 */ 3481 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3482 maxring = BGE_SEND_RINGS_MAX; 3483 else 3484 maxring = BGE_SEND_RINGS_MAX_5705; 3485 for (ring = 0; ring < maxring; ++ring) { 3486 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3487 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3488 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3489 &bgep->send[ring].hw_rcb); 3490 } 3491 3492 /* 3493 * Steps 44-45: initialise Receive Return Rings 3494 * (0x0200-0x02ff in NIC-local memory) 3495 */ 3496 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3497 maxring = BGE_RECV_RINGS_MAX; 3498 else 3499 maxring = BGE_RECV_RINGS_MAX_5705; 3500 for (ring = 0; ring < maxring; ++ring) 3501 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3502 &bgep->recv[ring].hw_rcb); 3503 3504 /* 3505 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3506 */ 3507 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3508 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3509 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3510 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3511 } 3512 /* 3513 * Step 47: configure the MAC unicast address 3514 * Step 48: configure the random backoff seed 3515 * Step 96: set up multicast filters 3516 */ 3517 #ifdef BGE_IPMI_ASF 3518 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3519 #else 3520 if (bge_chip_sync(bgep) == DDI_FAILURE) 3521 #endif 3522 retval = DDI_FAILURE; 3523 3524 /* 3525 * Step 49: configure the MTU 3526 */ 3527 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3528 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3529 3530 /* 3531 * Step 50: configure the IPG et al 3532 */ 3533 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3534 3535 /* 3536 * Step 51: configure the default Rx Return Ring 3537 */ 3538 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3539 3540 /* 3541 * Steps 52-54: configure Receive List Placement, 3542 * and enable Receive List Placement Statistics 3543 */ 3544 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3545 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3546 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3547 case MHCR_CHIP_ASIC_REV_5700: 3548 case MHCR_CHIP_ASIC_REV_5701: 3549 case MHCR_CHIP_ASIC_REV_5703: 3550 case MHCR_CHIP_ASIC_REV_5704: 3551 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3552 break; 3553 case MHCR_CHIP_ASIC_REV_5705: 3554 break; 3555 default: 3556 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3557 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3558 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3559 break; 3560 } 3561 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3562 3563 if (bgep->chipid.rx_rings > 1) 3564 bge_init_recv_rule(bgep); 3565 3566 /* 3567 * Steps 55-56: enable Send Data Initiator Statistics 3568 */ 3569 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3570 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3571 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3572 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3573 } else { 3574 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3575 SEND_INIT_STATS_ENABLE); 3576 } 3577 /* 3578 * Steps 57-58: stop (?) the Host Coalescing Engine 3579 */ 3580 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3581 retval = DDI_FAILURE; 3582 3583 /* 3584 * Steps 59-62: initialise Host Coalescing parameters 3585 */ 3586 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3587 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3588 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3589 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3590 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3591 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3592 bge_tx_count_intr); 3593 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3594 bge_tx_ticks_intr); 3595 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3596 bge_rx_count_intr); 3597 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3598 bge_rx_ticks_intr); 3599 } 3600 3601 /* 3602 * Steps 63-64: initialise status block & statistics 3603 * host memory addresses 3604 * The statistic block does not exist in some chipsets 3605 * Step 65: initialise Statistics Coalescing Tick Counter 3606 */ 3607 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3608 bgep->status_block.cookie.dmac_laddress); 3609 3610 /* 3611 * Steps 66-67: initialise status block & statistics 3612 * NIC-local memory addresses 3613 */ 3614 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3615 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3616 bgep->statistics.cookie.dmac_laddress); 3617 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3618 STATISTICS_TICKS_DEFAULT); 3619 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3620 NIC_MEM_STATUS_BLOCK); 3621 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3622 NIC_MEM_STATISTICS); 3623 } 3624 3625 /* 3626 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3627 * Completion Engine, the Receive List Placement Engine, and the 3628 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3629 * and BCM5715. 3630 */ 3631 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3632 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3633 coalmode = COALESCE_64_BYTE_STATUS; 3634 else 3635 coalmode = 0; 3636 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3637 retval = DDI_FAILURE; 3638 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3639 STATE_MACHINE_ATTN_ENABLE_BIT)) 3640 retval = DDI_FAILURE; 3641 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3642 retval = DDI_FAILURE; 3643 3644 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3645 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3646 STATE_MACHINE_ATTN_ENABLE_BIT)) 3647 retval = DDI_FAILURE; 3648 3649 /* 3650 * Step 72: Enable MAC DMA engines 3651 * Step 73: Clear & enable MAC statistics 3652 */ 3653 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3654 ETHERNET_MODE_ENABLE_FHDE | 3655 ETHERNET_MODE_ENABLE_RDE | 3656 ETHERNET_MODE_ENABLE_TDE); 3657 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3658 ETHERNET_MODE_ENABLE_TX_STATS | 3659 ETHERNET_MODE_ENABLE_RX_STATS | 3660 ETHERNET_MODE_CLEAR_TX_STATS | 3661 ETHERNET_MODE_CLEAR_RX_STATS); 3662 3663 /* 3664 * Step 74: configure the MLCR (Miscellaneous Local Control 3665 * Register); not required, as we set up the MLCR in step 10 3666 * (part of the reset code) above. 3667 * 3668 * Step 75: clear Interrupt Mailbox 0 3669 */ 3670 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3671 3672 /* 3673 * Steps 76-87: Gentlemen, start your engines ... 3674 * 3675 * Enable the DMA Completion Engine, the Write DMA Engine, 3676 * the Read DMA Engine, Receive Data Completion Engine, 3677 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3678 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3679 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3680 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3681 * 3682 * Beware exhaust fumes? 3683 */ 3684 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3685 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3686 retval = DDI_FAILURE; 3687 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3688 ALL_DMA_ATTN_BITS; 3689 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3690 MHCR_CHIP_ASIC_REV_5755) { 3691 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3692 } 3693 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3694 dma_wrprio)) 3695 retval = DDI_FAILURE; 3696 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3697 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3698 retval = DDI_FAILURE; 3699 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3700 STATE_MACHINE_ATTN_ENABLE_BIT)) 3701 retval = DDI_FAILURE; 3702 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3703 if (!bge_chip_enable_engine(bgep, 3704 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3705 retval = DDI_FAILURE; 3706 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3707 retval = DDI_FAILURE; 3708 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3709 STATE_MACHINE_ATTN_ENABLE_BIT)) 3710 retval = DDI_FAILURE; 3711 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3712 RCV_BD_DISABLED_RING_ATTN)) 3713 retval = DDI_FAILURE; 3714 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3715 RCV_DATA_BD_ILL_RING_ATTN)) 3716 retval = DDI_FAILURE; 3717 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3718 retval = DDI_FAILURE; 3719 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3720 STATE_MACHINE_ATTN_ENABLE_BIT)) 3721 retval = DDI_FAILURE; 3722 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3723 STATE_MACHINE_ATTN_ENABLE_BIT)) 3724 retval = DDI_FAILURE; 3725 3726 /* 3727 * Step 88: download firmware -- doesn't apply 3728 * Steps 89-90: enable Transmit & Receive MAC Engines 3729 */ 3730 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3731 retval = DDI_FAILURE; 3732 #ifdef BGE_IPMI_ASF 3733 if (!bgep->asf_enabled) { 3734 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3735 RECEIVE_MODE_KEEP_VLAN_TAG)) 3736 retval = DDI_FAILURE; 3737 } else { 3738 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3739 retval = DDI_FAILURE; 3740 } 3741 #else 3742 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3743 RECEIVE_MODE_KEEP_VLAN_TAG)) 3744 retval = DDI_FAILURE; 3745 #endif 3746 3747 /* 3748 * Step 91: disable auto-polling of PHY status 3749 */ 3750 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3751 3752 /* 3753 * Step 92: configure D0 power state (not required) 3754 * Step 93: initialise LED control register () 3755 */ 3756 ledctl = LED_CONTROL_DEFAULT; 3757 switch (bgep->chipid.device) { 3758 case DEVICE_ID_5700: 3759 case DEVICE_ID_5700x: 3760 case DEVICE_ID_5701: 3761 /* 3762 * Switch to 5700 (MAC) mode on these older chips 3763 */ 3764 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3765 ledctl |= LED_CONTROL_LED_MODE_5700; 3766 break; 3767 3768 default: 3769 break; 3770 } 3771 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3772 3773 /* 3774 * Step 94: activate link 3775 */ 3776 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3777 3778 /* 3779 * Step 95: set up physical layer (PHY/SerDes) 3780 * restart autoneg (if required) 3781 */ 3782 if (reset_phys) 3783 if (bge_phys_update(bgep) == DDI_FAILURE) 3784 retval = DDI_FAILURE; 3785 3786 /* 3787 * Extra step (DSG): hand over all the Receive Buffers to the chip 3788 */ 3789 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3790 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3791 bgep->buff[ring].rf_next); 3792 3793 /* 3794 * MSI bits:The least significant MSI 16-bit word. 3795 * ISR will be triggered different. 3796 */ 3797 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3798 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3799 3800 /* 3801 * Extra step (DSG): select which interrupts are enabled 3802 * 3803 * Program the Ethernet MAC engine to signal attention on 3804 * Link Change events, then enable interrupts on MAC, DMA, 3805 * and FLOW attention signals. 3806 */ 3807 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3808 ETHERNET_EVENT_LINK_INT | 3809 ETHERNET_STATUS_PCS_ERROR_INT); 3810 #ifdef BGE_IPMI_ASF 3811 if (bgep->asf_enabled) { 3812 bge_reg_set32(bgep, MODE_CONTROL_REG, 3813 MODE_INT_ON_FLOW_ATTN | 3814 MODE_INT_ON_DMA_ATTN | 3815 MODE_HOST_STACK_UP| 3816 MODE_INT_ON_MAC_ATTN); 3817 } else { 3818 #endif 3819 bge_reg_set32(bgep, MODE_CONTROL_REG, 3820 MODE_INT_ON_FLOW_ATTN | 3821 MODE_INT_ON_DMA_ATTN | 3822 MODE_INT_ON_MAC_ATTN); 3823 #ifdef BGE_IPMI_ASF 3824 } 3825 #endif 3826 3827 /* 3828 * Step 97: enable PCI interrupts!!! 3829 */ 3830 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3831 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3832 MHCR_MASK_PCI_INT_OUTPUT); 3833 3834 /* 3835 * All done! 3836 */ 3837 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3838 return (retval); 3839 } 3840 3841 3842 /* 3843 * ========== Hardware interrupt handler ========== 3844 */ 3845 3846 #undef BGE_DBG 3847 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3848 3849 /* 3850 * Sync the status block, then atomically clear the specified bits in 3851 * the <flags-and-tag> field of the status block. 3852 * the <flags> word of the status block, returning the value of the 3853 * <tag> and the <flags> before the bits were cleared. 3854 */ 3855 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3856 #pragma inline(bge_status_sync) 3857 3858 static int 3859 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3860 { 3861 bge_status_t *bsp; 3862 int retval; 3863 3864 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3865 (void *)bgep, bits)); 3866 3867 ASSERT(bgep->bge_guard == BGE_GUARD); 3868 3869 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3870 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3871 if (retval != DDI_FM_OK) 3872 return (retval); 3873 3874 bsp = DMA_VPTR(bgep->status_block); 3875 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3876 3877 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3878 (void *)bgep, bits, *flags)); 3879 3880 return (retval); 3881 } 3882 3883 void bge_wake_factotum(bge_t *bgep); 3884 #pragma inline(bge_wake_factotum) 3885 3886 void 3887 bge_wake_factotum(bge_t *bgep) 3888 { 3889 mutex_enter(bgep->softintrlock); 3890 if (bgep->factotum_flag == 0) { 3891 bgep->factotum_flag = 1; 3892 ddi_trigger_softintr(bgep->factotum_id); 3893 } 3894 mutex_exit(bgep->softintrlock); 3895 } 3896 3897 /* 3898 * bge_intr() -- handle chip interrupts 3899 */ 3900 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3901 #pragma no_inline(bge_intr) 3902 3903 uint_t 3904 bge_intr(caddr_t arg1, caddr_t arg2) 3905 { 3906 bge_t *bgep = (void *)arg1; /* private device info */ 3907 bge_status_t *bsp; 3908 uint64_t flags; 3909 uint32_t regval; 3910 uint_t result; 3911 int retval, loop_cnt = 0; 3912 3913 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3914 3915 /* 3916 * GLD v2 checks that s/w setup is complete before passing 3917 * interrupts to this routine, thus eliminating the old 3918 * (and well-known) race condition around ddi_add_intr() 3919 */ 3920 ASSERT(bgep->progress & PROGRESS_HWINT); 3921 3922 result = DDI_INTR_UNCLAIMED; 3923 mutex_enter(bgep->genlock); 3924 3925 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3926 /* 3927 * Check whether chip's says it's asserting #INTA; 3928 * if not, don't process or claim the interrupt. 3929 * 3930 * Note that the PCI signal is active low, so the 3931 * bit is *zero* when the interrupt is asserted. 3932 */ 3933 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3934 if (regval & MLCR_INTA_STATE) { 3935 if (bge_check_acc_handle(bgep, bgep->io_handle) 3936 != DDI_FM_OK) 3937 goto chip_stop; 3938 mutex_exit(bgep->genlock); 3939 return (result); 3940 } 3941 3942 /* 3943 * Block further PCI interrupts ... 3944 */ 3945 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3946 MHCR_MASK_PCI_INT_OUTPUT); 3947 3948 } else { 3949 /* 3950 * Check MSI status 3951 */ 3952 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 3953 if (regval & MSI_ERROR_ATTENTION) { 3954 BGE_REPORT((bgep, "msi error attention," 3955 " status=0x%x", regval)); 3956 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 3957 } 3958 } 3959 3960 result = DDI_INTR_CLAIMED; 3961 3962 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 3963 3964 /* 3965 * Sync the status block and grab the flags-n-tag from it. 3966 * We count the number of interrupts where there doesn't 3967 * seem to have been a DMA update of the status block; if 3968 * it *has* been updated, the counter will be cleared in 3969 * the while() loop below ... 3970 */ 3971 bgep->missed_dmas += 1; 3972 bsp = DMA_VPTR(bgep->status_block); 3973 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 3974 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 3975 /* 3976 * bge_chip_stop() may have freed dma area etc 3977 * while we were in this interrupt handler - 3978 * better not call bge_status_sync() 3979 */ 3980 (void) bge_check_acc_handle(bgep, 3981 bgep->io_handle); 3982 mutex_exit(bgep->genlock); 3983 return (DDI_INTR_CLAIMED); 3984 } 3985 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 3986 &flags); 3987 if (retval != DDI_FM_OK) { 3988 bgep->bge_dma_error = B_TRUE; 3989 goto chip_stop; 3990 } 3991 3992 if (!(flags & STATUS_FLAG_UPDATED)) 3993 break; 3994 3995 /* 3996 * Tell the chip that we're processing the interrupt 3997 */ 3998 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3999 INTERRUPT_MBOX_DISABLE(flags)); 4000 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4001 DDI_FM_OK) 4002 goto chip_stop; 4003 4004 /* 4005 * Drop the mutex while we: 4006 * Receive any newly-arrived packets 4007 * Recycle any newly-finished send buffers 4008 */ 4009 bgep->bge_intr_running = B_TRUE; 4010 mutex_exit(bgep->genlock); 4011 bge_receive(bgep, bsp); 4012 bge_recycle(bgep, bsp); 4013 mutex_enter(bgep->genlock); 4014 bgep->bge_intr_running = B_FALSE; 4015 4016 /* 4017 * Tell the chip we've finished processing, and 4018 * give it the tag that we got from the status 4019 * block earlier, so that it knows just how far 4020 * we've gone. If it's got more for us to do, 4021 * it will now update the status block and try 4022 * to assert an interrupt (but we've got the 4023 * #INTA blocked at present). If we see the 4024 * update, we'll loop around to do some more. 4025 * Eventually we'll get out of here ... 4026 */ 4027 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4028 INTERRUPT_MBOX_ENABLE(flags)); 4029 if (bgep->chipid.pci_type == BGE_PCI_E) 4030 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4031 bgep->missed_dmas = 0; 4032 } 4033 4034 /* 4035 * Check for exceptional conditions that we need to handle 4036 * 4037 * Link status changed 4038 * Status block not updated 4039 */ 4040 if (flags & STATUS_FLAG_LINK_CHANGED) 4041 bge_wake_factotum(bgep); 4042 4043 if (bgep->missed_dmas) { 4044 /* 4045 * Probably due to the internal status tag not 4046 * being reset. Force a status block update now; 4047 * this should ensure that we get an update and 4048 * a new interrupt. After that, we should be in 4049 * sync again ... 4050 */ 4051 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4052 "not updated?", flags)); 4053 bgep->missed_updates++; 4054 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4055 COALESCE_NOW); 4056 4057 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4058 /* 4059 * If this happens multiple times in a row, 4060 * it means DMA is just not working. Maybe 4061 * the chip's failed, or maybe there's a 4062 * problem on the PCI bus or in the host-PCI 4063 * bridge (Tomatillo). 4064 * 4065 * At all events, we want to stop further 4066 * interrupts and let the recovery code take 4067 * over to see whether anything can be done 4068 * about it ... 4069 */ 4070 bge_fm_ereport(bgep, 4071 DDI_FM_DEVICE_BADINT_LIMIT); 4072 goto chip_stop; 4073 } 4074 } 4075 4076 /* 4077 * Reenable assertion of #INTA, unless there's a DMA fault 4078 */ 4079 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4080 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4081 MHCR_MASK_PCI_INT_OUTPUT); 4082 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4083 DDI_FM_OK) 4084 goto chip_stop; 4085 } 4086 4087 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4088 goto chip_stop; 4089 4090 mutex_exit(bgep->genlock); 4091 return (result); 4092 4093 chip_stop: 4094 #ifdef BGE_IPMI_ASF 4095 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4096 /* 4097 * We must stop ASF heart beat before 4098 * bge_chip_stop(), otherwise some 4099 * computers (ex. IBM HS20 blade 4100 * server) may crash. 4101 */ 4102 bge_asf_update_status(bgep); 4103 bge_asf_stop_timer(bgep); 4104 bgep->asf_status = ASF_STAT_STOP; 4105 4106 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4107 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4108 } 4109 #endif 4110 bge_chip_stop(bgep, B_TRUE); 4111 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4112 mutex_exit(bgep->genlock); 4113 return (result); 4114 } 4115 4116 /* 4117 * ========== Factotum, implemented as a softint handler ========== 4118 */ 4119 4120 #undef BGE_DBG 4121 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4122 4123 static void bge_factotum_error_handler(bge_t *bgep); 4124 #pragma no_inline(bge_factotum_error_handler) 4125 4126 static void 4127 bge_factotum_error_handler(bge_t *bgep) 4128 { 4129 uint32_t flow; 4130 uint32_t rdma; 4131 uint32_t wdma; 4132 uint32_t tmac; 4133 uint32_t rmac; 4134 uint32_t rxrs; 4135 uint32_t txrs = 0; 4136 4137 ASSERT(mutex_owned(bgep->genlock)); 4138 4139 /* 4140 * Read all the registers that show the possible 4141 * reasons for the ERROR bit to be asserted 4142 */ 4143 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4144 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4145 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4146 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4147 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4148 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4149 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4150 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4151 4152 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4153 (void *)bgep, flow, rdma, wdma)); 4154 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4155 (void *)bgep, tmac, rmac, rxrs, txrs)); 4156 4157 /* 4158 * For now, just clear all the errors ... 4159 */ 4160 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4161 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4162 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4163 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4164 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4165 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4166 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4167 } 4168 4169 /* 4170 * Handler for hardware link state change. 4171 * 4172 * When this routine is called, the hardware link state has changed 4173 * and the new state is reflected in the param_* variables. Here 4174 * we must update the softstate and reprogram the MAC to match. 4175 */ 4176 static void bge_factotum_link_handler(bge_t *bgep); 4177 #pragma no_inline(bge_factotum_link_handler) 4178 4179 static void 4180 bge_factotum_link_handler(bge_t *bgep) 4181 { 4182 ASSERT(mutex_owned(bgep->genlock)); 4183 4184 /* 4185 * Update the s/w link_state 4186 */ 4187 if (bgep->param_link_up) 4188 bgep->link_state = LINK_STATE_UP; 4189 else 4190 bgep->link_state = LINK_STATE_DOWN; 4191 4192 /* 4193 * Reprogram the MAC modes to match 4194 */ 4195 bge_sync_mac_modes(bgep); 4196 } 4197 4198 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4199 #pragma no_inline(bge_factotum_link_check) 4200 4201 static boolean_t 4202 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4203 { 4204 boolean_t check; 4205 uint64_t flags; 4206 uint32_t tmac_status; 4207 4208 ASSERT(mutex_owned(bgep->genlock)); 4209 4210 /* 4211 * Get & clear the writable status bits in the Tx status register 4212 * (some bits are write-1-to-clear, others are just readonly). 4213 */ 4214 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4215 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4216 4217 /* 4218 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4219 */ 4220 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4221 STATUS_FLAG_LINK_CHANGED, &flags); 4222 if (*dma_state != DDI_FM_OK) 4223 return (B_FALSE); 4224 4225 /* 4226 * Clear any errors flagged in the status block ... 4227 */ 4228 if (flags & STATUS_FLAG_ERROR) 4229 bge_factotum_error_handler(bgep); 4230 4231 /* 4232 * We need to check the link status if: 4233 * the status block says there's been a link change 4234 * or there's any discrepancy between the various 4235 * flags indicating the link state (link_state, 4236 * param_link_up, and the LINK STATE bit in the 4237 * Transmit MAC status register). 4238 */ 4239 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4240 switch (bgep->link_state) { 4241 case LINK_STATE_UP: 4242 check |= (bgep->param_link_up == B_FALSE); 4243 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4244 break; 4245 4246 case LINK_STATE_DOWN: 4247 check |= (bgep->param_link_up != B_FALSE); 4248 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4249 break; 4250 4251 default: 4252 check = B_TRUE; 4253 break; 4254 } 4255 4256 /* 4257 * If <check> is false, we're sure the link hasn't changed. 4258 * If true, however, it's not yet definitive; we have to call 4259 * bge_phys_check() to determine whether the link has settled 4260 * into a new state yet ... and if it has, then call the link 4261 * state change handler.But when the chip is 5700 in Dell 6650 4262 * ,even if check is false, the link may have changed.So we 4263 * have to call bge_phys_check() to determine the link state. 4264 */ 4265 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4266 check = bge_phys_check(bgep); 4267 if (check) 4268 bge_factotum_link_handler(bgep); 4269 } 4270 4271 return (check); 4272 } 4273 4274 /* 4275 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4276 */ 4277 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4278 #pragma no_inline(bge_factotum_stall_check) 4279 4280 static boolean_t 4281 bge_factotum_stall_check(bge_t *bgep) 4282 { 4283 uint32_t dogval; 4284 4285 ASSERT(mutex_owned(bgep->genlock)); 4286 4287 /* 4288 * Specific check for Tx stall ... 4289 * 4290 * The 'watchdog' counter is incremented whenever a packet 4291 * is queued, reset to 1 when some (but not all) buffers 4292 * are reclaimed, reset to 0 (disabled) when all buffers 4293 * are reclaimed, and shifted left here. If it exceeds the 4294 * threshold value, the chip is assumed to have stalled and 4295 * is put into the ERROR state. The factotum will then reset 4296 * it on the next pass. 4297 * 4298 * All of which should ensure that we don't get into a state 4299 * where packets are left pending indefinitely! 4300 */ 4301 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4302 if (dogval < bge_watchdog_count) 4303 return (B_FALSE); 4304 4305 #if !defined(BGE_NETCONSOLE) 4306 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4307 #endif 4308 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4309 return (B_TRUE); 4310 } 4311 4312 /* 4313 * The factotum is woken up when there's something to do that we'd rather 4314 * not do from inside a hardware interrupt handler or high-level cyclic. 4315 * Its two main tasks are: 4316 * reset & restart the chip after an error 4317 * check the link status whenever necessary 4318 */ 4319 uint_t bge_chip_factotum(caddr_t arg); 4320 #pragma no_inline(bge_chip_factotum) 4321 4322 uint_t 4323 bge_chip_factotum(caddr_t arg) 4324 { 4325 bge_t *bgep; 4326 uint_t result; 4327 boolean_t error; 4328 boolean_t linkchg; 4329 int dma_state; 4330 4331 bgep = (void *)arg; 4332 4333 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4334 4335 mutex_enter(bgep->softintrlock); 4336 if (bgep->factotum_flag == 0) { 4337 mutex_exit(bgep->softintrlock); 4338 return (DDI_INTR_UNCLAIMED); 4339 } 4340 bgep->factotum_flag = 0; 4341 mutex_exit(bgep->softintrlock); 4342 4343 result = DDI_INTR_CLAIMED; 4344 error = B_FALSE; 4345 linkchg = B_FALSE; 4346 4347 mutex_enter(bgep->genlock); 4348 switch (bgep->bge_chip_state) { 4349 default: 4350 break; 4351 4352 case BGE_CHIP_RUNNING: 4353 linkchg = bge_factotum_link_check(bgep, &dma_state); 4354 error = bge_factotum_stall_check(bgep); 4355 if (dma_state != DDI_FM_OK) { 4356 bgep->bge_dma_error = B_TRUE; 4357 error = B_TRUE; 4358 } 4359 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4360 error = B_TRUE; 4361 if (error) 4362 bgep->bge_chip_state = BGE_CHIP_ERROR; 4363 break; 4364 4365 case BGE_CHIP_ERROR: 4366 error = B_TRUE; 4367 break; 4368 4369 case BGE_CHIP_FAULT: 4370 /* 4371 * Fault detected, time to reset ... 4372 */ 4373 if (bge_autorecover) { 4374 if (!(bgep->progress & PROGRESS_BUFS)) { 4375 /* 4376 * if we can't allocate the ring buffers, 4377 * try later 4378 */ 4379 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4380 mutex_exit(bgep->genlock); 4381 return (result); 4382 } 4383 bgep->progress |= PROGRESS_BUFS; 4384 } 4385 if (!(bgep->progress & PROGRESS_INTR)) { 4386 bge_init_rings(bgep); 4387 bge_intr_enable(bgep); 4388 bgep->progress |= PROGRESS_INTR; 4389 } 4390 if (!(bgep->progress & PROGRESS_KSTATS)) { 4391 bge_init_kstats(bgep, 4392 ddi_get_instance(bgep->devinfo)); 4393 bgep->progress |= PROGRESS_KSTATS; 4394 } 4395 4396 BGE_REPORT((bgep, "automatic recovery activated")); 4397 4398 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4399 bgep->bge_chip_state = BGE_CHIP_ERROR; 4400 error = B_TRUE; 4401 } 4402 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4403 DDI_FM_OK) { 4404 bgep->bge_chip_state = BGE_CHIP_ERROR; 4405 error = B_TRUE; 4406 } 4407 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4408 DDI_FM_OK) { 4409 bgep->bge_chip_state = BGE_CHIP_ERROR; 4410 error = B_TRUE; 4411 } 4412 if (error == B_FALSE) { 4413 #ifdef BGE_IPMI_ASF 4414 if (bgep->asf_enabled && 4415 bgep->asf_status != ASF_STAT_RUN) { 4416 bgep->asf_timeout_id = timeout( 4417 bge_asf_heartbeat, (void *)bgep, 4418 drv_usectohz( 4419 BGE_ASF_HEARTBEAT_INTERVAL)); 4420 bgep->asf_status = ASF_STAT_RUN; 4421 } 4422 #endif 4423 if (!bgep->manual_reset) { 4424 ddi_fm_service_impact(bgep->devinfo, 4425 DDI_SERVICE_RESTORED); 4426 } 4427 } 4428 } 4429 break; 4430 } 4431 4432 4433 /* 4434 * If an error is detected, stop the chip now, marking it as 4435 * faulty, so that it will be reset next time through ... 4436 * 4437 * Note that if intr_running is set, then bge_intr() has dropped 4438 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4439 * this point so have to wait until the next time the factotum runs. 4440 */ 4441 if (error && !bgep->bge_intr_running) { 4442 #ifdef BGE_IPMI_ASF 4443 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4444 /* 4445 * We must stop ASF heart beat before bge_chip_stop(), 4446 * otherwise some computers (ex. IBM HS20 blade server) 4447 * may crash. 4448 */ 4449 bge_asf_update_status(bgep); 4450 bge_asf_stop_timer(bgep); 4451 bgep->asf_status = ASF_STAT_STOP; 4452 4453 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4454 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4455 } 4456 #endif 4457 bge_chip_stop(bgep, B_TRUE); 4458 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4459 } 4460 mutex_exit(bgep->genlock); 4461 4462 /* 4463 * If the link state changed, tell the world about it. 4464 * Note: can't do this while still holding the mutex. 4465 */ 4466 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4467 bgep->link_state != LINK_STATE_UNKNOWN) 4468 linkchg = B_TRUE; 4469 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4470 bgep->link_state == LINK_STATE_DOWN) 4471 linkchg = B_FALSE; 4472 4473 if (linkchg) { 4474 mac_link_update(bgep->mh, bgep->link_state); 4475 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4476 } 4477 if (bgep->manual_reset) { 4478 bgep->manual_reset = B_FALSE; 4479 } 4480 4481 return (result); 4482 } 4483 4484 /* 4485 * High-level cyclic handler 4486 * 4487 * This routine schedules a (low-level) softint callback to the 4488 * factotum, and prods the chip to update the status block (which 4489 * will cause a hardware interrupt when complete). 4490 */ 4491 void bge_chip_cyclic(void *arg); 4492 #pragma no_inline(bge_chip_cyclic) 4493 4494 void 4495 bge_chip_cyclic(void *arg) 4496 { 4497 bge_t *bgep; 4498 4499 bgep = arg; 4500 4501 switch (bgep->bge_chip_state) { 4502 default: 4503 return; 4504 4505 case BGE_CHIP_RUNNING: 4506 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4507 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4508 ddi_fm_service_impact(bgep->devinfo, 4509 DDI_SERVICE_UNAFFECTED); 4510 4511 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4512 bgep->link_update_timer++; 4513 4514 break; 4515 4516 case BGE_CHIP_FAULT: 4517 case BGE_CHIP_ERROR: 4518 break; 4519 } 4520 4521 bge_wake_factotum(bgep); 4522 } 4523 4524 4525 /* 4526 * ========== Ioctl subfunctions ========== 4527 */ 4528 4529 #undef BGE_DBG 4530 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4531 4532 #if BGE_DEBUGGING || BGE_DO_PPIO 4533 4534 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4535 #pragma no_inline(bge_chip_peek_cfg) 4536 4537 static void 4538 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4539 { 4540 uint64_t regval; 4541 uint64_t regno; 4542 4543 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4544 (void *)bgep, (void *)ppd)); 4545 4546 regno = ppd->pp_acc_offset; 4547 4548 switch (ppd->pp_acc_size) { 4549 case 1: 4550 regval = pci_config_get8(bgep->cfg_handle, regno); 4551 break; 4552 4553 case 2: 4554 regval = pci_config_get16(bgep->cfg_handle, regno); 4555 break; 4556 4557 case 4: 4558 regval = pci_config_get32(bgep->cfg_handle, regno); 4559 break; 4560 4561 case 8: 4562 regval = pci_config_get64(bgep->cfg_handle, regno); 4563 break; 4564 } 4565 4566 ppd->pp_acc_data = regval; 4567 } 4568 4569 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4570 #pragma no_inline(bge_chip_poke_cfg) 4571 4572 static void 4573 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4574 { 4575 uint64_t regval; 4576 uint64_t regno; 4577 4578 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4579 (void *)bgep, (void *)ppd)); 4580 4581 regno = ppd->pp_acc_offset; 4582 regval = ppd->pp_acc_data; 4583 4584 switch (ppd->pp_acc_size) { 4585 case 1: 4586 pci_config_put8(bgep->cfg_handle, regno, regval); 4587 break; 4588 4589 case 2: 4590 pci_config_put16(bgep->cfg_handle, regno, regval); 4591 break; 4592 4593 case 4: 4594 pci_config_put32(bgep->cfg_handle, regno, regval); 4595 break; 4596 4597 case 8: 4598 pci_config_put64(bgep->cfg_handle, regno, regval); 4599 break; 4600 } 4601 } 4602 4603 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4604 #pragma no_inline(bge_chip_peek_reg) 4605 4606 static void 4607 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4608 { 4609 uint64_t regval; 4610 void *regaddr; 4611 4612 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4613 (void *)bgep, (void *)ppd)); 4614 4615 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4616 4617 switch (ppd->pp_acc_size) { 4618 case 1: 4619 regval = ddi_get8(bgep->io_handle, regaddr); 4620 break; 4621 4622 case 2: 4623 regval = ddi_get16(bgep->io_handle, regaddr); 4624 break; 4625 4626 case 4: 4627 regval = ddi_get32(bgep->io_handle, regaddr); 4628 break; 4629 4630 case 8: 4631 regval = ddi_get64(bgep->io_handle, regaddr); 4632 break; 4633 } 4634 4635 ppd->pp_acc_data = regval; 4636 } 4637 4638 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4639 #pragma no_inline(bge_chip_peek_reg) 4640 4641 static void 4642 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4643 { 4644 uint64_t regval; 4645 void *regaddr; 4646 4647 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4648 (void *)bgep, (void *)ppd)); 4649 4650 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4651 regval = ppd->pp_acc_data; 4652 4653 switch (ppd->pp_acc_size) { 4654 case 1: 4655 ddi_put8(bgep->io_handle, regaddr, regval); 4656 break; 4657 4658 case 2: 4659 ddi_put16(bgep->io_handle, regaddr, regval); 4660 break; 4661 4662 case 4: 4663 ddi_put32(bgep->io_handle, regaddr, regval); 4664 break; 4665 4666 case 8: 4667 ddi_put64(bgep->io_handle, regaddr, regval); 4668 break; 4669 } 4670 BGE_PCICHK(bgep); 4671 } 4672 4673 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4674 #pragma no_inline(bge_chip_peek_nic) 4675 4676 static void 4677 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4678 { 4679 uint64_t regoff; 4680 uint64_t regval; 4681 void *regaddr; 4682 4683 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4684 (void *)bgep, (void *)ppd)); 4685 4686 regoff = ppd->pp_acc_offset; 4687 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4688 regoff &= MWBAR_GRANULE_MASK; 4689 regoff += NIC_MEM_WINDOW_OFFSET; 4690 regaddr = PIO_ADDR(bgep, regoff); 4691 4692 switch (ppd->pp_acc_size) { 4693 case 1: 4694 regval = ddi_get8(bgep->io_handle, regaddr); 4695 break; 4696 4697 case 2: 4698 regval = ddi_get16(bgep->io_handle, regaddr); 4699 break; 4700 4701 case 4: 4702 regval = ddi_get32(bgep->io_handle, regaddr); 4703 break; 4704 4705 case 8: 4706 regval = ddi_get64(bgep->io_handle, regaddr); 4707 break; 4708 } 4709 4710 ppd->pp_acc_data = regval; 4711 } 4712 4713 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4714 #pragma no_inline(bge_chip_poke_nic) 4715 4716 static void 4717 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4718 { 4719 uint64_t regoff; 4720 uint64_t regval; 4721 void *regaddr; 4722 4723 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4724 (void *)bgep, (void *)ppd)); 4725 4726 regoff = ppd->pp_acc_offset; 4727 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4728 regoff &= MWBAR_GRANULE_MASK; 4729 regoff += NIC_MEM_WINDOW_OFFSET; 4730 regaddr = PIO_ADDR(bgep, regoff); 4731 regval = ppd->pp_acc_data; 4732 4733 switch (ppd->pp_acc_size) { 4734 case 1: 4735 ddi_put8(bgep->io_handle, regaddr, regval); 4736 break; 4737 4738 case 2: 4739 ddi_put16(bgep->io_handle, regaddr, regval); 4740 break; 4741 4742 case 4: 4743 ddi_put32(bgep->io_handle, regaddr, regval); 4744 break; 4745 4746 case 8: 4747 ddi_put64(bgep->io_handle, regaddr, regval); 4748 break; 4749 } 4750 BGE_PCICHK(bgep); 4751 } 4752 4753 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4754 #pragma no_inline(bge_chip_peek_mii) 4755 4756 static void 4757 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4758 { 4759 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4760 (void *)bgep, (void *)ppd)); 4761 4762 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4763 } 4764 4765 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4766 #pragma no_inline(bge_chip_poke_mii) 4767 4768 static void 4769 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4770 { 4771 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4772 (void *)bgep, (void *)ppd)); 4773 4774 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4775 } 4776 4777 #if BGE_SEE_IO32 4778 4779 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4780 #pragma no_inline(bge_chip_peek_seeprom) 4781 4782 static void 4783 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4784 { 4785 uint32_t data; 4786 int err; 4787 4788 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4789 (void *)bgep, (void *)ppd)); 4790 4791 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4792 ppd->pp_acc_data = err ? ~0ull : data; 4793 } 4794 4795 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4796 #pragma no_inline(bge_chip_poke_seeprom) 4797 4798 static void 4799 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4800 { 4801 uint32_t data; 4802 4803 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4804 (void *)bgep, (void *)ppd)); 4805 4806 data = ppd->pp_acc_data; 4807 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4808 } 4809 #endif /* BGE_SEE_IO32 */ 4810 4811 #if BGE_FLASH_IO32 4812 4813 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4814 #pragma no_inline(bge_chip_peek_flash) 4815 4816 static void 4817 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4818 { 4819 uint32_t data; 4820 int err; 4821 4822 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4823 (void *)bgep, (void *)ppd)); 4824 4825 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4826 ppd->pp_acc_data = err ? ~0ull : data; 4827 } 4828 4829 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4830 #pragma no_inline(bge_chip_poke_flash) 4831 4832 static void 4833 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4834 { 4835 uint32_t data; 4836 4837 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4838 (void *)bgep, (void *)ppd)); 4839 4840 data = ppd->pp_acc_data; 4841 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4842 ppd->pp_acc_offset, &data); 4843 } 4844 #endif /* BGE_FLASH_IO32 */ 4845 4846 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4847 #pragma no_inline(bge_chip_peek_mem) 4848 4849 static void 4850 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4851 { 4852 uint64_t regval; 4853 void *vaddr; 4854 4855 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4856 (void *)bgep, (void *)ppd)); 4857 4858 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4859 4860 switch (ppd->pp_acc_size) { 4861 case 1: 4862 regval = *(uint8_t *)vaddr; 4863 break; 4864 4865 case 2: 4866 regval = *(uint16_t *)vaddr; 4867 break; 4868 4869 case 4: 4870 regval = *(uint32_t *)vaddr; 4871 break; 4872 4873 case 8: 4874 regval = *(uint64_t *)vaddr; 4875 break; 4876 } 4877 4878 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4879 (void *)bgep, (void *)ppd, regval, vaddr)); 4880 4881 ppd->pp_acc_data = regval; 4882 } 4883 4884 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4885 #pragma no_inline(bge_chip_poke_mem) 4886 4887 static void 4888 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4889 { 4890 uint64_t regval; 4891 void *vaddr; 4892 4893 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4894 (void *)bgep, (void *)ppd)); 4895 4896 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4897 regval = ppd->pp_acc_data; 4898 4899 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4900 (void *)bgep, (void *)ppd, regval, vaddr)); 4901 4902 switch (ppd->pp_acc_size) { 4903 case 1: 4904 *(uint8_t *)vaddr = (uint8_t)regval; 4905 break; 4906 4907 case 2: 4908 *(uint16_t *)vaddr = (uint16_t)regval; 4909 break; 4910 4911 case 4: 4912 *(uint32_t *)vaddr = (uint32_t)regval; 4913 break; 4914 4915 case 8: 4916 *(uint64_t *)vaddr = (uint64_t)regval; 4917 break; 4918 } 4919 } 4920 4921 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4922 struct iocblk *iocp); 4923 #pragma no_inline(bge_pp_ioctl) 4924 4925 static enum ioc_reply 4926 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4927 { 4928 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4929 bge_peekpoke_t *ppd; 4930 dma_area_t *areap; 4931 uint64_t sizemask; 4932 uint64_t mem_va; 4933 uint64_t maxoff; 4934 boolean_t peek; 4935 4936 switch (cmd) { 4937 default: 4938 /* NOTREACHED */ 4939 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4940 return (IOC_INVAL); 4941 4942 case BGE_PEEK: 4943 peek = B_TRUE; 4944 break; 4945 4946 case BGE_POKE: 4947 peek = B_FALSE; 4948 break; 4949 } 4950 4951 /* 4952 * Validate format of ioctl 4953 */ 4954 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4955 return (IOC_INVAL); 4956 if (mp->b_cont == NULL) 4957 return (IOC_INVAL); 4958 ppd = (void *)mp->b_cont->b_rptr; 4959 4960 /* 4961 * Validate request parameters 4962 */ 4963 switch (ppd->pp_acc_space) { 4964 default: 4965 return (IOC_INVAL); 4966 4967 case BGE_PP_SPACE_CFG: 4968 /* 4969 * Config space 4970 */ 4971 sizemask = 8|4|2|1; 4972 mem_va = 0; 4973 maxoff = PCI_CONF_HDR_SIZE; 4974 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4975 break; 4976 4977 case BGE_PP_SPACE_REG: 4978 /* 4979 * Memory-mapped I/O space 4980 */ 4981 sizemask = 8|4|2|1; 4982 mem_va = 0; 4983 maxoff = RIAAR_REGISTER_MAX; 4984 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4985 break; 4986 4987 case BGE_PP_SPACE_NIC: 4988 /* 4989 * NIC on-chip memory 4990 */ 4991 sizemask = 8|4|2|1; 4992 mem_va = 0; 4993 maxoff = MWBAR_ONCHIP_MAX; 4994 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4995 break; 4996 4997 case BGE_PP_SPACE_MII: 4998 /* 4999 * PHY's MII registers 5000 * NB: all PHY registers are two bytes, but the 5001 * addresses increment in ones (word addressing). 5002 * So we scale the address here, then undo the 5003 * transformation inside the peek/poke functions. 5004 */ 5005 ppd->pp_acc_offset *= 2; 5006 sizemask = 2; 5007 mem_va = 0; 5008 maxoff = (MII_MAXREG+1)*2; 5009 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5010 break; 5011 5012 #if BGE_SEE_IO32 5013 case BGE_PP_SPACE_SEEPROM: 5014 /* 5015 * Attached SEEPROM(s), if any. 5016 * NB: we use the high-order bits of the 'address' as 5017 * a device select to accommodate multiple SEEPROMS, 5018 * If each one is the maximum size (64kbytes), this 5019 * makes them appear contiguous. Otherwise, there may 5020 * be holes in the mapping. ENxS doesn't have any 5021 * SEEPROMs anyway ... 5022 */ 5023 sizemask = 4; 5024 mem_va = 0; 5025 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5026 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5027 break; 5028 #endif /* BGE_SEE_IO32 */ 5029 5030 #if BGE_FLASH_IO32 5031 case BGE_PP_SPACE_FLASH: 5032 /* 5033 * Attached Flash device (if any); a maximum of one device 5034 * is currently supported. But it can be up to 1MB (unlike 5035 * the 64k limit on SEEPROMs) so why would you need more ;-) 5036 */ 5037 sizemask = 4; 5038 mem_va = 0; 5039 maxoff = NVM_FLASH_ADDR_MASK; 5040 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5041 break; 5042 #endif /* BGE_FLASH_IO32 */ 5043 5044 case BGE_PP_SPACE_BGE: 5045 /* 5046 * BGE data structure! 5047 */ 5048 sizemask = 8|4|2|1; 5049 mem_va = (uintptr_t)bgep; 5050 maxoff = sizeof (*bgep); 5051 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5052 break; 5053 5054 case BGE_PP_SPACE_STATUS: 5055 case BGE_PP_SPACE_STATISTICS: 5056 case BGE_PP_SPACE_TXDESC: 5057 case BGE_PP_SPACE_TXBUFF: 5058 case BGE_PP_SPACE_RXDESC: 5059 case BGE_PP_SPACE_RXBUFF: 5060 /* 5061 * Various DMA_AREAs 5062 */ 5063 switch (ppd->pp_acc_space) { 5064 case BGE_PP_SPACE_TXDESC: 5065 areap = &bgep->tx_desc; 5066 break; 5067 case BGE_PP_SPACE_TXBUFF: 5068 areap = &bgep->tx_buff[0]; 5069 break; 5070 case BGE_PP_SPACE_RXDESC: 5071 areap = &bgep->rx_desc[0]; 5072 break; 5073 case BGE_PP_SPACE_RXBUFF: 5074 areap = &bgep->rx_buff[0]; 5075 break; 5076 case BGE_PP_SPACE_STATUS: 5077 areap = &bgep->status_block; 5078 break; 5079 case BGE_PP_SPACE_STATISTICS: 5080 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5081 areap = &bgep->statistics; 5082 break; 5083 } 5084 5085 sizemask = 8|4|2|1; 5086 mem_va = (uintptr_t)areap->mem_va; 5087 maxoff = areap->alength; 5088 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5089 break; 5090 } 5091 5092 switch (ppd->pp_acc_size) { 5093 default: 5094 return (IOC_INVAL); 5095 5096 case 8: 5097 case 4: 5098 case 2: 5099 case 1: 5100 if ((ppd->pp_acc_size & sizemask) == 0) 5101 return (IOC_INVAL); 5102 break; 5103 } 5104 5105 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5106 return (IOC_INVAL); 5107 5108 if (ppd->pp_acc_offset >= maxoff) 5109 return (IOC_INVAL); 5110 5111 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5112 return (IOC_INVAL); 5113 5114 /* 5115 * All OK - go do it! 5116 */ 5117 ppd->pp_acc_offset += mem_va; 5118 (*ppfn)(bgep, ppd); 5119 return (peek ? IOC_REPLY : IOC_ACK); 5120 } 5121 5122 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5123 struct iocblk *iocp); 5124 #pragma no_inline(bge_diag_ioctl) 5125 5126 static enum ioc_reply 5127 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5128 { 5129 ASSERT(mutex_owned(bgep->genlock)); 5130 5131 switch (cmd) { 5132 default: 5133 /* NOTREACHED */ 5134 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5135 return (IOC_INVAL); 5136 5137 case BGE_DIAG: 5138 /* 5139 * Currently a no-op 5140 */ 5141 return (IOC_ACK); 5142 5143 case BGE_PEEK: 5144 case BGE_POKE: 5145 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5146 5147 case BGE_PHY_RESET: 5148 return (IOC_RESTART_ACK); 5149 5150 case BGE_SOFT_RESET: 5151 case BGE_HARD_RESET: 5152 /* 5153 * Reset and reinitialise the 570x hardware 5154 */ 5155 bgep->bge_chip_state = BGE_CHIP_FAULT; 5156 ddi_trigger_softintr(bgep->factotum_id); 5157 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5158 return (IOC_ACK); 5159 } 5160 5161 /* NOTREACHED */ 5162 } 5163 5164 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5165 5166 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5167 struct iocblk *iocp); 5168 #pragma no_inline(bge_mii_ioctl) 5169 5170 static enum ioc_reply 5171 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5172 { 5173 struct bge_mii_rw *miirwp; 5174 5175 /* 5176 * Validate format of ioctl 5177 */ 5178 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5179 return (IOC_INVAL); 5180 if (mp->b_cont == NULL) 5181 return (IOC_INVAL); 5182 miirwp = (void *)mp->b_cont->b_rptr; 5183 5184 /* 5185 * Validate request parameters ... 5186 */ 5187 if (miirwp->mii_reg > MII_MAXREG) 5188 return (IOC_INVAL); 5189 5190 switch (cmd) { 5191 default: 5192 /* NOTREACHED */ 5193 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5194 return (IOC_INVAL); 5195 5196 case BGE_MII_READ: 5197 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5198 return (IOC_REPLY); 5199 5200 case BGE_MII_WRITE: 5201 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5202 return (IOC_ACK); 5203 } 5204 5205 /* NOTREACHED */ 5206 } 5207 5208 #if BGE_SEE_IO32 5209 5210 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5211 struct iocblk *iocp); 5212 #pragma no_inline(bge_see_ioctl) 5213 5214 static enum ioc_reply 5215 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5216 { 5217 struct bge_see_rw *seerwp; 5218 5219 /* 5220 * Validate format of ioctl 5221 */ 5222 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5223 return (IOC_INVAL); 5224 if (mp->b_cont == NULL) 5225 return (IOC_INVAL); 5226 seerwp = (void *)mp->b_cont->b_rptr; 5227 5228 /* 5229 * Validate request parameters ... 5230 */ 5231 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5232 return (IOC_INVAL); 5233 5234 switch (cmd) { 5235 default: 5236 /* NOTREACHED */ 5237 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5238 return (IOC_INVAL); 5239 5240 case BGE_SEE_READ: 5241 case BGE_SEE_WRITE: 5242 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5243 seerwp->see_addr, &seerwp->see_data); 5244 return (IOC_REPLY); 5245 } 5246 5247 /* NOTREACHED */ 5248 } 5249 5250 #endif /* BGE_SEE_IO32 */ 5251 5252 #if BGE_FLASH_IO32 5253 5254 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5255 struct iocblk *iocp); 5256 #pragma no_inline(bge_flash_ioctl) 5257 5258 static enum ioc_reply 5259 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5260 { 5261 struct bge_flash_rw *flashrwp; 5262 5263 /* 5264 * Validate format of ioctl 5265 */ 5266 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5267 return (IOC_INVAL); 5268 if (mp->b_cont == NULL) 5269 return (IOC_INVAL); 5270 flashrwp = (void *)mp->b_cont->b_rptr; 5271 5272 /* 5273 * Validate request parameters ... 5274 */ 5275 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5276 return (IOC_INVAL); 5277 5278 switch (cmd) { 5279 default: 5280 /* NOTREACHED */ 5281 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5282 return (IOC_INVAL); 5283 5284 case BGE_FLASH_READ: 5285 case BGE_FLASH_WRITE: 5286 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5287 flashrwp->flash_addr, &flashrwp->flash_data); 5288 return (IOC_REPLY); 5289 } 5290 5291 /* NOTREACHED */ 5292 } 5293 5294 #endif /* BGE_FLASH_IO32 */ 5295 5296 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5297 struct iocblk *iocp); 5298 #pragma no_inline(bge_chip_ioctl) 5299 5300 enum ioc_reply 5301 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5302 { 5303 int cmd; 5304 5305 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5306 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5307 5308 ASSERT(mutex_owned(bgep->genlock)); 5309 5310 cmd = iocp->ioc_cmd; 5311 switch (cmd) { 5312 default: 5313 /* NOTREACHED */ 5314 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5315 return (IOC_INVAL); 5316 5317 case BGE_DIAG: 5318 case BGE_PEEK: 5319 case BGE_POKE: 5320 case BGE_PHY_RESET: 5321 case BGE_SOFT_RESET: 5322 case BGE_HARD_RESET: 5323 #if BGE_DEBUGGING || BGE_DO_PPIO 5324 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5325 #else 5326 return (IOC_INVAL); 5327 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5328 5329 case BGE_MII_READ: 5330 case BGE_MII_WRITE: 5331 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5332 5333 #if BGE_SEE_IO32 5334 case BGE_SEE_READ: 5335 case BGE_SEE_WRITE: 5336 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5337 #endif /* BGE_SEE_IO32 */ 5338 5339 #if BGE_FLASH_IO32 5340 case BGE_FLASH_READ: 5341 case BGE_FLASH_WRITE: 5342 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5343 #endif /* BGE_FLASH_IO32 */ 5344 } 5345 5346 /* NOTREACHED */ 5347 } 5348 5349 void 5350 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5351 { 5352 bge_t *bgep = arg; 5353 5354 mutex_enter(bgep->genlock); 5355 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5356 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5357 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5358 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5359 mutex_exit(bgep->genlock); 5360 } 5361 5362 #ifdef BGE_IPMI_ASF 5363 5364 uint32_t 5365 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5366 { 5367 uint32_t data; 5368 5369 #ifndef __sparc 5370 if (!bgep->asf_wordswapped) { 5371 /* a workaround word swap error */ 5372 if (addr & 4) 5373 addr = addr - 4; 5374 else 5375 addr = addr + 4; 5376 } 5377 #endif 5378 5379 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5380 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5381 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5382 5383 data = LE_32(data); 5384 return (data); 5385 } 5386 5387 void 5388 bge_asf_update_status(bge_t *bgep) 5389 { 5390 uint32_t event; 5391 5392 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5393 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5394 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5395 5396 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5397 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5398 } 5399 5400 5401 /* 5402 * The driver is supposed to notify ASF that the OS is still running 5403 * every three seconds, otherwise the management server may attempt 5404 * to reboot the machine. If it hasn't actually failed, this is 5405 * not a desirable result. However, this isn't running as a real-time 5406 * thread, and even if it were, it might not be able to generate the 5407 * heartbeat in a timely manner due to system load. As it isn't a 5408 * significant strain on the machine, we will set the interval to half 5409 * of the required value. 5410 */ 5411 void 5412 bge_asf_heartbeat(void *arg) 5413 { 5414 bge_t *bgep = (bge_t *)arg; 5415 5416 mutex_enter(bgep->genlock); 5417 bge_asf_update_status((bge_t *)bgep); 5418 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5419 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5420 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5421 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5422 mutex_exit(bgep->genlock); 5423 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5424 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5425 } 5426 5427 5428 void 5429 bge_asf_stop_timer(bge_t *bgep) 5430 { 5431 timeout_id_t tmp_id = 0; 5432 5433 while ((bgep->asf_timeout_id != 0) && 5434 (tmp_id != bgep->asf_timeout_id)) { 5435 tmp_id = bgep->asf_timeout_id; 5436 (void) untimeout(tmp_id); 5437 } 5438 bgep->asf_timeout_id = 0; 5439 } 5440 5441 5442 5443 /* 5444 * This function should be placed at the earliest position of bge_attach(). 5445 */ 5446 void 5447 bge_asf_get_config(bge_t *bgep) 5448 { 5449 uint32_t nicsig; 5450 uint32_t niccfg; 5451 5452 bgep->asf_enabled = B_FALSE; 5453 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5454 if (nicsig == BGE_NIC_DATA_SIG) { 5455 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5456 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5457 /* 5458 * Here, we don't consider BAXTER, because BGE haven't 5459 * supported BAXTER (that is 5752). Also, as I know, 5460 * BAXTER doesn't support ASF feature. 5461 */ 5462 bgep->asf_enabled = B_TRUE; 5463 else 5464 bgep->asf_enabled = B_FALSE; 5465 } else 5466 bgep->asf_enabled = B_FALSE; 5467 } 5468 5469 5470 void 5471 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5472 { 5473 uint32_t tries; 5474 uint32_t event; 5475 5476 ASSERT(bgep->asf_enabled); 5477 5478 /* Issues "pause firmware" command and wait for ACK */ 5479 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5480 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5481 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5482 5483 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5484 tries = 0; 5485 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5486 drv_usecwait(1); 5487 tries ++; 5488 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5489 } 5490 5491 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5492 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5493 5494 if (bgep->asf_newhandshake) { 5495 switch (mode) { 5496 case BGE_INIT_RESET: 5497 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5498 BGE_DRV_STATE_START); 5499 break; 5500 case BGE_SHUTDOWN_RESET: 5501 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5502 BGE_DRV_STATE_UNLOAD); 5503 break; 5504 case BGE_SUSPEND_RESET: 5505 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5506 BGE_DRV_STATE_SUSPEND); 5507 break; 5508 default: 5509 break; 5510 } 5511 } 5512 } 5513 5514 5515 void 5516 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5517 { 5518 switch (mode) { 5519 case BGE_INIT_RESET: 5520 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5521 BGE_DRV_STATE_START); 5522 break; 5523 case BGE_SHUTDOWN_RESET: 5524 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5525 BGE_DRV_STATE_UNLOAD); 5526 break; 5527 case BGE_SUSPEND_RESET: 5528 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5529 BGE_DRV_STATE_SUSPEND); 5530 break; 5531 default: 5532 break; 5533 } 5534 } 5535 5536 5537 void 5538 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5539 { 5540 switch (mode) { 5541 case BGE_INIT_RESET: 5542 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5543 BGE_DRV_STATE_START_DONE); 5544 break; 5545 case BGE_SHUTDOWN_RESET: 5546 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5547 BGE_DRV_STATE_UNLOAD_DONE); 5548 break; 5549 default: 5550 break; 5551 } 5552 } 5553 5554 #endif /* BGE_IPMI_ASF */ 5555