1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 boolean_t bge_jumbo_enable = B_TRUE; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 245 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 246 247 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 248 (void *)bgep, regno, val)); 249 250 val = LE_32(val); 251 252 return (val); 253 } 254 255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 256 #pragma inline(bge_ind_put32) 257 258 void 259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 260 { 261 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 262 (void *)bgep, regno, val)); 263 264 val = LE_32(val); 265 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 267 } 268 269 #endif /* BGE_IND_IO32 */ 270 271 #if BGE_DEBUGGING 272 273 static void bge_pci_check(bge_t *bgep); 274 #pragma no_inline(bge_pci_check) 275 276 static void 277 bge_pci_check(bge_t *bgep) 278 { 279 uint16_t pcistatus; 280 281 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 282 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 283 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 284 (void *)bgep, pcistatus)); 285 } 286 287 #endif /* BGE_DEBUGGING */ 288 289 /* 290 * Perform first-stage chip (re-)initialisation, using only config-space 291 * accesses: 292 * 293 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 294 * returning the data in the structure pointed to by <idp>. 295 * + Configure the target-mode endianness (swap) options. 296 * + Disable interrupts and enable Memory Space accesses. 297 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 298 * 299 * This sequence is adapted from Broadcom document 570X-PG102-R, 300 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 301 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 302 * 303 * This function MUST be called before any non-config-space accesses 304 * are made; on this first call <enable_dma> is B_FALSE, and it 305 * effectively performs steps 3-1(!) of the initialisation sequence 306 * (the rest are not required but should be harmless). 307 * 308 * It MUST also be called after a chip reset, as this disables 309 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 310 * it is effectively performing steps 6-8. 311 */ 312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 313 #pragma no_inline(bge_chip_cfg_init) 314 315 void 316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 317 { 318 ddi_acc_handle_t handle; 319 uint16_t command; 320 uint32_t mhcr; 321 uint16_t value16; 322 int i; 323 324 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 325 (void *)bgep, (void *)cidp, enable_dma)); 326 327 /* 328 * Step 3: save PCI cache line size and subsystem vendor ID 329 * 330 * Read all the config-space registers that characterise the 331 * chip, specifically vendor/device/revision/subsystem vendor 332 * and subsystem device id. We expect (but don't check) that 333 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 334 * 335 * Also save all bus-transaction related registers (cache-line 336 * size, bus-grant/latency parameters, etc). Some of these are 337 * cleared by reset, so we'll have to restore them later. This 338 * comes from the Broadcom document 570X-PG102-R ... 339 * 340 * Note: Broadcom document 570X-PG102-R seems to be in error 341 * here w.r.t. the offsets of the Subsystem Vendor ID and 342 * Subsystem (Device) ID registers, which are the opposite way 343 * round according to the PCI standard. For good measure, we 344 * save/restore both anyway. 345 */ 346 handle = bgep->cfg_handle; 347 348 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 349 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 350 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 351 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 352 353 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 354 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 355 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 356 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 357 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 358 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 359 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 360 361 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 362 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 363 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 364 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 365 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 366 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 367 cidp->vendor, cidp->device, cidp->revision)); 368 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 369 cidp->subven, cidp->subdev, cidp->asic_rev)); 370 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 371 cidp->clsize, cidp->latency, cidp->command)); 372 373 /* 374 * Step 2 (also step 6): disable and clear interrupts. 375 * Steps 11-13: configure PIO endianness options, and enable 376 * indirect register access. We'll also select any other 377 * options controlled by the MHCR (e.g. tagged status, mask 378 * interrupt mode) at this stage ... 379 * 380 * Note: internally, the chip is 64-bit and BIG-endian, but 381 * since it talks to the host over a (LITTLE-endian) PCI bus, 382 * it normally swaps bytes around at the PCI interface. 383 * However, the PCI host bridge on SPARC systems normally 384 * swaps the byte lanes around too, since SPARCs are also 385 * BIG-endian. So it turns out that on SPARC, the right 386 * option is to tell the chip to swap (and the host bridge 387 * will swap back again), whereas on x86 we ask the chip 388 * NOT to swap, so the natural little-endianness of the 389 * PCI bus is assumed. Then the only thing that doesn't 390 * automatically work right is access to an 8-byte register 391 * by a little-endian host; but we don't want to set the 392 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 393 * accesses don't go where expected ;-( So we live with 394 * that, and perform word-swaps in software in the few cases 395 * where a chip register is defined as an 8-byte value -- 396 * see the code below for details ... 397 * 398 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 399 * very clear in the register description in the PRM, but 400 * Broadcom document 570X-PG104-R page 248 explains a little 401 * more (under "Broadcom Mask Mode"). The bit changes the way 402 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 403 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 404 * way as the 5700 did, which isn't very convenient. Setting 405 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 406 * bit do just what its name says -- MASK the PCI #INTA output 407 * (i.e. deassert the signal at the pin) leaving all internal 408 * state unchanged. This is much more convenient for our 409 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 410 * 411 * Note: the inconvenient semantics of the interrupt mailbox 412 * (nonzero disables and acknowledges/clears the interrupt, 413 * zero enables AND CLEARS it) would make race conditions 414 * likely in the interrupt handler: 415 * 416 * (1) acknowledge & disable interrupts 417 * (2) while (more to do) 418 * process packets 419 * (3) enable interrupts -- also clears pending 420 * 421 * If the chip received more packets and internally generated 422 * an interrupt between the check at (2) and the mbox write 423 * at (3), this interrupt would be lost :-( 424 * 425 * The best way to avoid this is to use TAGGED STATUS mode, 426 * where the chip includes a unique tag in each status block 427 * update, and the host, when re-enabling interrupts, passes 428 * the last tag it saw back to the chip; then the chip can 429 * see whether the host is truly up to date, and regenerate 430 * its interrupt if not. 431 */ 432 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 433 MHCR_ENABLE_TAGGED_STATUS_MODE | 434 MHCR_MASK_INTERRUPT_MODE | 435 MHCR_CLEAR_INTERRUPT_INTA; 436 437 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 438 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 439 440 #ifdef _BIG_ENDIAN 441 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 442 #endif /* _BIG_ENDIAN */ 443 444 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 445 446 #ifdef BGE_IPMI_ASF 447 bgep->asf_wordswapped = B_FALSE; 448 #endif 449 /* 450 * Step 1 (also step 7): Enable PCI Memory Space accesses 451 * Disable Memory Write/Invalidate 452 * Enable or disable Bus Mastering 453 * 454 * Note that all other bits are taken from the original value saved 455 * the first time through here, rather than from the current register 456 * value, 'cos that will have been cleared by a soft RESET since. 457 * In this way we preserve the OBP/nexus-parent's preferred settings 458 * of the parity-error and system-error enable bits across multiple 459 * chip RESETs. 460 */ 461 command = bgep->chipid.command | PCI_COMM_MAE; 462 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 463 if (enable_dma) 464 command |= PCI_COMM_ME; 465 /* 466 * on BCM5714 revision A0, false parity error gets generated 467 * due to a logic bug. Provide a workaround by disabling parity 468 * error. 469 */ 470 if (((cidp->device == DEVICE_ID_5714C) || 471 (cidp->device == DEVICE_ID_5714S)) && 472 (cidp->revision == REVISION_ID_5714_A0)) { 473 command &= ~PCI_COMM_PARITY_DETECT; 474 } 475 pci_config_put16(handle, PCI_CONF_COMM, command); 476 477 /* 478 * On some PCI-E device, there were instances when 479 * the device was still link training. 480 */ 481 if (bgep->chipid.pci_type == BGE_PCI_E) { 482 i = 0; 483 value16 = pci_config_get16(handle, PCI_CONF_COMM); 484 while ((value16 != command) && (i < 100)) { 485 drv_usecwait(200); 486 value16 = pci_config_get16(handle, PCI_CONF_COMM); 487 ++i; 488 } 489 } 490 491 /* 492 * Clear any remaining error status bits 493 */ 494 pci_config_put16(handle, PCI_CONF_STAT, ~0); 495 496 /* 497 * Do following if and only if the device is NOT BCM5714C OR 498 * BCM5715C 499 */ 500 if (!((cidp->device == DEVICE_ID_5714C) || 501 (cidp->device == DEVICE_ID_5715C))) { 502 /* 503 * Make sure these indirect-access registers are sane 504 * rather than random after power-up or reset 505 */ 506 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 507 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 508 } 509 /* 510 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 511 */ 512 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 513 514 if (cidp->pci_type == BGE_PCI_E) { 515 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 516 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723, 517 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 518 } else 519 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 520 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 521 } 522 } 523 524 #ifdef __amd64 525 /* 526 * Distinguish CPU types 527 * 528 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 529 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 530 * for PCI-Express based network interface card. This is the work-around 531 * for those nics. 532 */ 533 static boolean_t bge_get_em64t_type(void); 534 #pragma inline(bge_get_em64t_type) 535 536 static boolean_t 537 bge_get_em64t_type(void) 538 { 539 540 return (x86_vendor == X86_VENDOR_Intel); 541 } 542 #endif 543 544 /* 545 * Operating register get/set access routines 546 */ 547 548 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 549 #pragma inline(bge_reg_get32) 550 551 uint32_t 552 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 553 { 554 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 555 (void *)bgep, regno)); 556 557 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 558 } 559 560 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 561 #pragma inline(bge_reg_put32) 562 563 void 564 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 565 { 566 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 567 (void *)bgep, regno, data)); 568 569 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 570 BGE_PCICHK(bgep); 571 } 572 573 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 574 #pragma inline(bge_reg_set32) 575 576 void 577 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 578 { 579 uint32_t regval; 580 581 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 582 (void *)bgep, regno, bits)); 583 584 regval = bge_reg_get32(bgep, regno); 585 regval |= bits; 586 bge_reg_put32(bgep, regno, regval); 587 } 588 589 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 590 #pragma inline(bge_reg_clr32) 591 592 void 593 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 594 { 595 uint32_t regval; 596 597 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 598 (void *)bgep, regno, bits)); 599 600 regval = bge_reg_get32(bgep, regno); 601 regval &= ~bits; 602 bge_reg_put32(bgep, regno, regval); 603 } 604 605 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 606 #pragma inline(bge_reg_get64) 607 608 static uint64_t 609 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 610 { 611 uint64_t regval; 612 613 #ifdef __amd64 614 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 615 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 616 regval <<= 32; 617 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 } else { 619 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 620 } 621 #elif defined(__sparc) 622 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 623 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 624 regval <<= 32; 625 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 626 } else { 627 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 628 } 629 #else 630 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 631 #endif 632 633 #ifdef _LITTLE_ENDIAN 634 regval = (regval >> 32) | (regval << 32); 635 #endif /* _LITTLE_ENDIAN */ 636 637 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 638 (void *)bgep, regno, regval)); 639 640 return (regval); 641 } 642 643 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 644 #pragma inline(bge_reg_put64) 645 646 static void 647 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 648 { 649 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 650 (void *)bgep, regno, data)); 651 652 #ifdef _LITTLE_ENDIAN 653 data = ((data >> 32) | (data << 32)); 654 #endif /* _LITTLE_ENDIAN */ 655 656 #ifdef __amd64 657 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 658 ddi_put32(bgep->io_handle, 659 PIO_ADDR(bgep, regno), (uint32_t)data); 660 BGE_PCICHK(bgep); 661 ddi_put32(bgep->io_handle, 662 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 663 664 } else { 665 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 666 } 667 #elif defined(__sparc) 668 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 669 ddi_put32(bgep->io_handle, 670 PIO_ADDR(bgep, regno + 4), (uint32_t)data); 671 BGE_PCICHK(bgep); 672 ddi_put32(bgep->io_handle, 673 PIO_ADDR(bgep, regno), (uint32_t)(data >> 32)); 674 } else { 675 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 676 } 677 #else 678 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 679 #endif 680 681 BGE_PCICHK(bgep); 682 } 683 684 /* 685 * The DDI doesn't provide get/put functions for 128 bit data 686 * so we put RCBs out as two 64-bit chunks instead. 687 */ 688 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 689 #pragma inline(bge_reg_putrcb) 690 691 static void 692 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 693 { 694 uint64_t *p; 695 696 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 697 (void *)bgep, addr, rcbp->host_ring_addr, 698 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 699 700 ASSERT((addr % sizeof (*rcbp)) == 0); 701 702 p = (void *)rcbp; 703 bge_reg_put64(bgep, addr, *p++); 704 bge_reg_put64(bgep, addr+8, *p); 705 } 706 707 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 708 #pragma inline(bge_mbx_put) 709 710 void 711 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 712 { 713 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 714 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 715 716 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 717 (void *)bgep, regno, data)); 718 719 /* 720 * Mailbox registers are nominally 64 bits on the 5701, but 721 * the MSW isn't used. On the 5703, they're only 32 bits 722 * anyway. So here we just write the lower(!) 32 bits - 723 * remembering that the chip is big-endian, even though the 724 * PCI bus is little-endian ... 725 */ 726 #ifdef _BIG_ENDIAN 727 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 728 #else 729 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 730 #endif /* _BIG_ENDIAN */ 731 BGE_PCICHK(bgep); 732 } 733 734 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 735 #pragma inline(bge_mbx_get) 736 737 uint32_t 738 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 739 { 740 uint32_t val32; 741 742 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 743 regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4; 744 745 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 746 (void *)bgep, regno)); 747 748 #ifdef _BIG_ENDIAN 749 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 750 #else 751 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 752 #endif /* _BIG_ENDIAN */ 753 BGE_PCICHK(bgep); 754 755 return (val32); 756 } 757 758 759 #if BGE_DEBUGGING 760 761 void bge_led_mark(bge_t *bgep); 762 #pragma no_inline(bge_led_mark) 763 764 void 765 bge_led_mark(bge_t *bgep) 766 { 767 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 768 LED_CONTROL_1000MBPS_LED | 769 LED_CONTROL_100MBPS_LED | 770 LED_CONTROL_10MBPS_LED; 771 772 /* 773 * Blink all three LINK LEDs on simultaneously, then all off, 774 * then restore to automatic hardware control. This is used 775 * in laboratory testing to trigger a logic analyser or scope. 776 */ 777 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 778 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 779 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 780 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 781 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 782 } 783 784 #endif /* BGE_DEBUGGING */ 785 786 /* 787 * NIC on-chip memory access routines 788 * 789 * Only 32K of NIC memory is visible at a time, controlled by the 790 * Memory Window Base Address Register (in PCI config space). Once 791 * this is set, the 32K region of NIC-local memory that it refers 792 * to can be directly addressed in the upper 32K of the 64K of PCI 793 * memory space used for the device. 794 */ 795 796 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 797 #pragma inline(bge_nic_setwin) 798 799 static void 800 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 801 { 802 chip_id_t *cidp; 803 804 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 805 (void *)bgep, base)); 806 807 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 808 809 /* 810 * Don't do repeated zero data writes, 811 * if the device is BCM5714C/15C. 812 */ 813 cidp = &bgep->chipid; 814 if ((cidp->device == DEVICE_ID_5714C) || 815 (cidp->device == DEVICE_ID_5715C)) { 816 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 817 return; 818 /* Adjust lastWriteZeroData */ 819 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 820 B_TRUE : B_FALSE); 821 } 822 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 823 } 824 825 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 826 #pragma inline(bge_nic_get32) 827 828 static uint32_t 829 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 830 { 831 uint32_t data; 832 833 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 834 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 835 /* workaround for word swap error */ 836 if (addr & 4) 837 addr = addr - 4; 838 else 839 addr = addr + 4; 840 } 841 #endif 842 843 #ifdef __sparc 844 data = bge_nic_read32(bgep, addr); 845 #else 846 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 847 addr &= MWBAR_GRANULE_MASK; 848 addr += NIC_MEM_WINDOW_OFFSET; 849 850 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 851 #endif 852 853 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 854 (void *)bgep, addr, data)); 855 856 return (data); 857 } 858 859 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 860 #pragma inline(bge_nic_put32) 861 862 void 863 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 864 { 865 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 866 (void *)bgep, addr, data)); 867 868 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 869 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 870 /* workaround for word swap error */ 871 if (addr & 4) 872 addr = addr - 4; 873 else 874 addr = addr + 4; 875 } 876 #endif 877 878 #ifdef __sparc 879 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 880 data = LE_32(data); 881 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 882 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 883 #else 884 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 885 addr &= MWBAR_GRANULE_MASK; 886 addr += NIC_MEM_WINDOW_OFFSET; 887 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 888 BGE_PCICHK(bgep); 889 #endif 890 } 891 892 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 893 #pragma inline(bge_nic_get64) 894 895 static uint64_t 896 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 897 { 898 uint64_t data; 899 900 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 901 addr &= MWBAR_GRANULE_MASK; 902 addr += NIC_MEM_WINDOW_OFFSET; 903 904 #ifdef __amd64 905 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 906 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 907 data <<= 32; 908 data |= ddi_get32(bgep->io_handle, 909 PIO_ADDR(bgep, addr + 4)); 910 } else { 911 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 912 } 913 #elif defined(__sparc) 914 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 915 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 916 data <<= 32; 917 data |= ddi_get32(bgep->io_handle, 918 PIO_ADDR(bgep, addr + 4)); 919 } else { 920 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 921 } 922 #else 923 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 924 #endif 925 926 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 927 (void *)bgep, addr, data)); 928 929 return (data); 930 } 931 932 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 933 #pragma inline(bge_nic_put64) 934 935 static void 936 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 937 { 938 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 939 (void *)bgep, addr, data)); 940 941 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 942 addr &= MWBAR_GRANULE_MASK; 943 addr += NIC_MEM_WINDOW_OFFSET; 944 945 #ifdef __amd64 946 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 947 ddi_put32(bgep->io_handle, 948 PIO_ADDR(bgep, addr), (uint32_t)data); 949 BGE_PCICHK(bgep); 950 ddi_put32(bgep->io_handle, 951 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 952 } else { 953 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 954 } 955 #elif defined(__sparc) 956 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 957 ddi_put32(bgep->io_handle, 958 PIO_ADDR(bgep, addr + 4), (uint32_t)data); 959 BGE_PCICHK(bgep); 960 ddi_put32(bgep->io_handle, 961 PIO_ADDR(bgep, addr), (uint32_t)(data >> 32)); 962 } else { 963 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 964 } 965 #else 966 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 967 #endif 968 969 BGE_PCICHK(bgep); 970 } 971 972 /* 973 * The DDI doesn't provide get/put functions for 128 bit data 974 * so we put RCBs out as two 64-bit chunks instead. 975 */ 976 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 977 #pragma inline(bge_nic_putrcb) 978 979 static void 980 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 981 { 982 uint64_t *p; 983 984 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 985 (void *)bgep, addr, rcbp->host_ring_addr, 986 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 987 988 ASSERT((addr % sizeof (*rcbp)) == 0); 989 990 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 991 addr &= MWBAR_GRANULE_MASK; 992 addr += NIC_MEM_WINDOW_OFFSET; 993 994 p = (void *)rcbp; 995 #ifdef __amd64 996 if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) { 997 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 998 (uint32_t)(*p)); 999 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1000 (uint32_t)(*p >> 32)); 1001 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1002 (uint32_t)(*(p + 1))); 1003 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1004 (uint32_t)(*p >> 32)); 1005 1006 } else { 1007 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1008 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1009 } 1010 #elif defined(__sparc) 1011 if (DEVICE_5723_SERIES_CHIPSETS(bgep)) { 1012 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1013 (uint32_t)(*p)); 1014 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1015 (uint32_t)(*p >> 32)); 1016 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1017 (uint32_t)(*(p + 1))); 1018 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1019 (uint32_t)(*p >> 32)); 1020 } else { 1021 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1022 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1023 } 1024 #else 1025 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1026 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1027 #endif 1028 1029 BGE_PCICHK(bgep); 1030 } 1031 1032 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1033 #pragma inline(bge_nic_zero) 1034 1035 static void 1036 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1037 { 1038 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1039 (void *)bgep, addr, nbytes)); 1040 1041 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1042 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1043 1044 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1045 addr &= MWBAR_GRANULE_MASK; 1046 addr += NIC_MEM_WINDOW_OFFSET; 1047 1048 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1049 nbytes, 1, DDI_DATA_SZ08_ACC); 1050 BGE_PCICHK(bgep); 1051 } 1052 1053 /* 1054 * MII (PHY) register get/set access routines 1055 * 1056 * These use the chip's MII auto-access method, controlled by the 1057 * MII Communication register at 0x044c, so the CPU doesn't have 1058 * to fiddle with the individual bits. 1059 */ 1060 1061 #undef BGE_DBG 1062 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1063 1064 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1065 uint16_t data, uint32_t cmd); 1066 #pragma no_inline(bge_mii_access) 1067 1068 static uint16_t 1069 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1070 { 1071 uint32_t timeout; 1072 uint32_t regval1; 1073 uint32_t regval2; 1074 1075 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1076 (void *)bgep, regno, data, cmd)); 1077 1078 ASSERT(mutex_owned(bgep->genlock)); 1079 1080 /* 1081 * Assemble the command ... 1082 */ 1083 cmd |= data << MI_COMMS_DATA_SHIFT; 1084 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1085 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1086 cmd |= MI_COMMS_START; 1087 1088 /* 1089 * Wait for any command already in progress ... 1090 * 1091 * Note: this *shouldn't* ever find that there is a command 1092 * in progress, because we already hold the <genlock> mutex. 1093 * Nonetheless, we have sometimes seen the MI_COMMS_START 1094 * bit set here -- it seems that the chip can initiate MII 1095 * accesses internally, even with polling OFF. 1096 */ 1097 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1098 for (timeout = 100; ; ) { 1099 if ((regval2 & MI_COMMS_START) == 0) { 1100 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1101 break; 1102 } 1103 if (--timeout == 0) 1104 break; 1105 drv_usecwait(10); 1106 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1107 } 1108 1109 if (timeout == 0) 1110 return ((uint16_t)~0u); 1111 1112 if (timeout != 100) 1113 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1114 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1115 cmd, 10*(100-timeout), regval1, regval2)); 1116 1117 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1118 for (timeout = 1000; ; ) { 1119 if ((regval1 & MI_COMMS_START) == 0) 1120 break; 1121 if (--timeout == 0) 1122 break; 1123 drv_usecwait(10); 1124 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1125 } 1126 1127 /* 1128 * Drop out early if the READ FAILED bit is set -- this chip 1129 * could be a 5703/4S, with a SerDes instead of a PHY! 1130 */ 1131 if (regval2 & MI_COMMS_READ_FAILED) 1132 return ((uint16_t)~0u); 1133 1134 if (timeout == 0) 1135 return ((uint16_t)~0u); 1136 1137 /* 1138 * The PRM says to wait 5us after seeing the START bit clear 1139 * and then re-read the register to get the final value of the 1140 * data field, in order to avoid a race condition where the 1141 * START bit is clear but the data field isn't yet valid. 1142 * 1143 * Note: we don't actually seem to be encounter this race; 1144 * except when the START bit is seen set again (see below), 1145 * the data field doesn't change during this 5us interval. 1146 */ 1147 drv_usecwait(5); 1148 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1149 1150 /* 1151 * Unfortunately, when following the PRMs instructions above, 1152 * we have occasionally seen the START bit set again(!) in the 1153 * value read after the 5us delay. This seems to be due to the 1154 * chip autonomously starting another MII access internally. 1155 * In such cases, the command/data/etc fields relate to the 1156 * internal command, rather than the one that we thought had 1157 * just finished. So in this case, we fall back to returning 1158 * the data from the original read that showed START clear. 1159 */ 1160 if (regval2 & MI_COMMS_START) { 1161 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1162 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1163 cmd, regval1, regval2)); 1164 regval2 = regval1; 1165 } 1166 1167 if (regval2 & MI_COMMS_START) 1168 return ((uint16_t)~0u); 1169 1170 if (regval2 & MI_COMMS_READ_FAILED) 1171 return ((uint16_t)~0u); 1172 1173 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1174 } 1175 1176 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1177 #pragma no_inline(bge_mii_get16) 1178 1179 uint16_t 1180 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1181 { 1182 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1183 (void *)bgep, regno)); 1184 1185 ASSERT(mutex_owned(bgep->genlock)); 1186 1187 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1188 (regno == MII_MSCONTROL))) 1189 return (0); 1190 1191 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1192 } 1193 1194 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1195 #pragma no_inline(bge_mii_put16) 1196 1197 void 1198 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1199 { 1200 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1201 (void *)bgep, regno, data)); 1202 1203 ASSERT(mutex_owned(bgep->genlock)); 1204 1205 if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) || 1206 (regno == MII_MSCONTROL))) 1207 return; 1208 1209 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1210 } 1211 1212 #undef BGE_DBG 1213 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1214 1215 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1216 1217 /* 1218 * Basic SEEPROM get/set access routine 1219 * 1220 * This uses the chip's SEEPROM auto-access method, controlled by the 1221 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1222 * doesn't have to fiddle with the individual bits. 1223 * 1224 * The caller should hold <genlock> and *also* have already acquired 1225 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1226 * 1227 * Return value: 1228 * 0 on success, 1229 * ENODATA on access timeout (maybe retryable: device may just be busy) 1230 * EPROTO on other h/w or s/w errors. 1231 * 1232 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1233 * from a (successful) SEEPROM_ACCESS_READ. 1234 */ 1235 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1236 uint32_t *dp); 1237 #pragma no_inline(bge_seeprom_access) 1238 1239 static int 1240 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1241 { 1242 uint32_t tries; 1243 uint32_t regval; 1244 1245 ASSERT(mutex_owned(bgep->genlock)); 1246 1247 /* 1248 * On the newer chips that support both SEEPROM & Flash, we need 1249 * to specifically enable SEEPROM access (Flash is the default). 1250 * On older chips, we don't; SEEPROM is the only NVtype supported, 1251 * and the NVM control registers don't exist ... 1252 */ 1253 switch (bgep->chipid.nvtype) { 1254 case BGE_NVTYPE_NONE: 1255 case BGE_NVTYPE_UNKNOWN: 1256 _NOTE(NOTREACHED) 1257 case BGE_NVTYPE_SEEPROM: 1258 break; 1259 1260 case BGE_NVTYPE_LEGACY_SEEPROM: 1261 case BGE_NVTYPE_UNBUFFERED_FLASH: 1262 case BGE_NVTYPE_BUFFERED_FLASH: 1263 default: 1264 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1265 NVM_CFG1_LEGACY_SEEPROM_MODE); 1266 break; 1267 } 1268 1269 /* 1270 * Check there's no command in progress. 1271 * 1272 * Note: this *shouldn't* ever find that there is a command 1273 * in progress, because we already hold the <genlock> mutex. 1274 * Also, to ensure we don't have a conflict with the chip's 1275 * internal firmware or a process accessing the same (shared) 1276 * SEEPROM through the other port of a 5704, we've already 1277 * been through the "software arbitration" protocol. 1278 * So this is just a final consistency check: we shouldn't 1279 * see EITHER the START bit (command started but not complete) 1280 * OR the COMPLETE bit (command completed but not cleared). 1281 */ 1282 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1283 if (regval & SEEPROM_ACCESS_START) 1284 return (EPROTO); 1285 if (regval & SEEPROM_ACCESS_COMPLETE) 1286 return (EPROTO); 1287 1288 /* 1289 * Assemble the command ... 1290 */ 1291 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1292 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1293 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1294 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1295 cmd |= SEEPROM_ACCESS_START; 1296 cmd |= SEEPROM_ACCESS_COMPLETE; 1297 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1298 1299 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1300 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1301 1302 /* 1303 * By observation, a successful access takes ~20us on a 5703/4, 1304 * but apparently much longer (up to 1000us) on the obsolescent 1305 * BCM5700/BCM5701. We want to be sure we don't get any false 1306 * timeouts here; but OTOH, we don't want a bogus access to lock 1307 * out interrupts for longer than necessary. So we'll allow up 1308 * to 1000us ... 1309 */ 1310 for (tries = 0; tries < 1000; ++tries) { 1311 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1312 if (regval & SEEPROM_ACCESS_COMPLETE) 1313 break; 1314 drv_usecwait(1); 1315 } 1316 1317 if (regval & SEEPROM_ACCESS_COMPLETE) { 1318 /* 1319 * All OK; read the SEEPROM data register, then write back 1320 * the value read from the address register in order to 1321 * clear the <complete> bit and leave the SEEPROM access 1322 * state machine idle, ready for the next access ... 1323 */ 1324 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1325 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1326 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1327 return (0); 1328 } 1329 1330 /* 1331 * Hmm ... what happened here? 1332 * 1333 * Most likely, the user addressed a non-existent SEEPROM. Or 1334 * maybe the SEEPROM was busy internally (e.g. processing a write) 1335 * and didn't respond to being addressed. Either way, it's left 1336 * the SEEPROM access state machine wedged. So we'll reset it 1337 * before we leave, so it's ready for next time ... 1338 */ 1339 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1340 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1341 return (ENODATA); 1342 } 1343 1344 /* 1345 * Basic Flash get/set access routine 1346 * 1347 * These use the chip's Flash auto-access method, controlled by the 1348 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1349 * fiddle with the individual bits. 1350 * 1351 * The caller should hold <genlock> and *also* have already acquired 1352 * the right to access the Flash, via bge_nvmem_acquire() above. 1353 * 1354 * Return value: 1355 * 0 on success, 1356 * ENODATA on access timeout (maybe retryable: device may just be busy) 1357 * ENODEV if the NVmem device is missing or otherwise unusable 1358 * 1359 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1360 * from a (successful) NVM_FLASH_CMD_RD. 1361 */ 1362 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1363 uint32_t *dp); 1364 #pragma no_inline(bge_flash_access) 1365 1366 static int 1367 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1368 { 1369 uint32_t tries; 1370 uint32_t regval; 1371 1372 ASSERT(mutex_owned(bgep->genlock)); 1373 1374 /* 1375 * On the newer chips that support both SEEPROM & Flash, we need 1376 * to specifically disable SEEPROM access while accessing Flash. 1377 * The older chips don't support Flash, and the NVM registers don't 1378 * exist, so we shouldn't be here at all! 1379 */ 1380 switch (bgep->chipid.nvtype) { 1381 case BGE_NVTYPE_NONE: 1382 case BGE_NVTYPE_UNKNOWN: 1383 _NOTE(NOTREACHED) 1384 case BGE_NVTYPE_SEEPROM: 1385 return (ENODEV); 1386 1387 case BGE_NVTYPE_LEGACY_SEEPROM: 1388 case BGE_NVTYPE_UNBUFFERED_FLASH: 1389 case BGE_NVTYPE_BUFFERED_FLASH: 1390 default: 1391 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1392 NVM_CFG1_LEGACY_SEEPROM_MODE); 1393 break; 1394 } 1395 1396 /* 1397 * Assemble the command ... 1398 */ 1399 addr &= NVM_FLASH_ADDR_MASK; 1400 cmd |= NVM_FLASH_CMD_DOIT; 1401 cmd |= NVM_FLASH_CMD_FIRST; 1402 cmd |= NVM_FLASH_CMD_LAST; 1403 cmd |= NVM_FLASH_CMD_DONE; 1404 1405 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1406 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1407 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1408 1409 /* 1410 * Allow up to 1000ms ... 1411 */ 1412 for (tries = 0; tries < 1000; ++tries) { 1413 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1414 if (regval & NVM_FLASH_CMD_DONE) 1415 break; 1416 drv_usecwait(1); 1417 } 1418 1419 if (regval & NVM_FLASH_CMD_DONE) { 1420 /* 1421 * All OK; read the data from the Flash read register 1422 */ 1423 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1424 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1425 return (0); 1426 } 1427 1428 /* 1429 * Hmm ... what happened here? 1430 * 1431 * Most likely, the user addressed a non-existent Flash. Or 1432 * maybe the Flash was busy internally (e.g. processing a write) 1433 * and didn't respond to being addressed. Either way, there's 1434 * nothing we can here ... 1435 */ 1436 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1437 return (ENODATA); 1438 } 1439 1440 /* 1441 * The next two functions regulate access to the NVram (if fitted). 1442 * 1443 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1444 * (SPI) interface, but they can be accessed through either port. These 1445 * are managed by different instance of this driver and have no software 1446 * state in common. 1447 * 1448 * In addition (and even on a single core chip) the chip's internal 1449 * firmware can access the SEEPROM/Flash, most notably after a RESET 1450 * when it may download code to run internally. 1451 * 1452 * So we need to arbitrate between these various software agents. For 1453 * this purpose, the chip provides the Software Arbitration Register, 1454 * which implements hardware(!) arbitration. 1455 * 1456 * This functionality didn't exist on older (5700/5701) chips, so there's 1457 * nothing we can do by way of arbitration on those; also, if there's no 1458 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1459 * nothing to do. 1460 * 1461 * The internal firmware appears to use Request 0, which is the highest 1462 * priority. So we'd like to use Request 2, leaving one higher and one 1463 * lower for any future developments ... but apparently this doesn't 1464 * always work. So for now, the code uses Request 1 ;-( 1465 */ 1466 1467 #define NVM_READ_REQ NVM_READ_REQ1 1468 #define NVM_RESET_REQ NVM_RESET_REQ1 1469 #define NVM_SET_REQ NVM_SET_REQ1 1470 1471 static void bge_nvmem_relinquish(bge_t *bgep); 1472 #pragma no_inline(bge_nvmem_relinquish) 1473 1474 static void 1475 bge_nvmem_relinquish(bge_t *bgep) 1476 { 1477 ASSERT(mutex_owned(bgep->genlock)); 1478 1479 switch (bgep->chipid.nvtype) { 1480 case BGE_NVTYPE_NONE: 1481 case BGE_NVTYPE_UNKNOWN: 1482 _NOTE(NOTREACHED) 1483 return; 1484 1485 case BGE_NVTYPE_SEEPROM: 1486 /* 1487 * No arbitration performed, no release needed 1488 */ 1489 return; 1490 1491 case BGE_NVTYPE_LEGACY_SEEPROM: 1492 case BGE_NVTYPE_UNBUFFERED_FLASH: 1493 case BGE_NVTYPE_BUFFERED_FLASH: 1494 default: 1495 break; 1496 } 1497 1498 /* 1499 * Our own request should be present (whether or not granted) ... 1500 */ 1501 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1502 1503 /* 1504 * ... this will make it go away. 1505 */ 1506 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1507 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1508 } 1509 1510 /* 1511 * Arbitrate for access to the NVmem, if necessary 1512 * 1513 * Return value: 1514 * 0 on success 1515 * EAGAIN if the device is in use (retryable) 1516 * ENODEV if the NVmem device is missing or otherwise unusable 1517 */ 1518 static int bge_nvmem_acquire(bge_t *bgep); 1519 #pragma no_inline(bge_nvmem_acquire) 1520 1521 static int 1522 bge_nvmem_acquire(bge_t *bgep) 1523 { 1524 uint32_t regval; 1525 uint32_t tries; 1526 1527 ASSERT(mutex_owned(bgep->genlock)); 1528 1529 switch (bgep->chipid.nvtype) { 1530 case BGE_NVTYPE_NONE: 1531 case BGE_NVTYPE_UNKNOWN: 1532 /* 1533 * Access denied: no (recognisable) device fitted 1534 */ 1535 return (ENODEV); 1536 1537 case BGE_NVTYPE_SEEPROM: 1538 /* 1539 * Access granted: no arbitration needed (or possible) 1540 */ 1541 return (0); 1542 1543 case BGE_NVTYPE_LEGACY_SEEPROM: 1544 case BGE_NVTYPE_UNBUFFERED_FLASH: 1545 case BGE_NVTYPE_BUFFERED_FLASH: 1546 default: 1547 /* 1548 * Access conditional: conduct arbitration protocol 1549 */ 1550 break; 1551 } 1552 1553 /* 1554 * We're holding the per-port mutex <genlock>, so no-one other 1555 * thread can be attempting to access the NVmem through *this* 1556 * port. But it could be in use by the *other* port (of a 5704), 1557 * or by the chip's internal firmware, so we have to go through 1558 * the full (hardware) arbitration protocol ... 1559 * 1560 * Note that *because* we're holding <genlock>, the interrupt handler 1561 * won't be able to progress. So we're only willing to spin for a 1562 * fairly short time. Specifically: 1563 * 1564 * We *must* wait long enough for the hardware to resolve all 1565 * requests and determine the winner. Fortunately, this is 1566 * "almost instantaneous", even as observed by GHz CPUs. 1567 * 1568 * A successful access by another Solaris thread (via either 1569 * port) typically takes ~20us. So waiting a bit longer than 1570 * that will give a good chance of success, if the other user 1571 * *is* another thread on the other port. 1572 * 1573 * However, the internal firmware can hold on to the NVmem 1574 * for *much* longer: at least 10 milliseconds just after a 1575 * RESET, and maybe even longer if the NVmem actually contains 1576 * code to download and run on the internal CPUs. 1577 * 1578 * So, we'll allow 50us; if that's not enough then it's up to the 1579 * caller to retry later (hence the choice of return code EAGAIN). 1580 */ 1581 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1582 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1583 1584 for (tries = 0; tries < 50; ++tries) { 1585 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1586 if (regval & NVM_WON_REQ1) 1587 break; 1588 drv_usecwait(1); 1589 } 1590 1591 if (regval & NVM_WON_REQ1) { 1592 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1593 return (0); 1594 } 1595 1596 /* 1597 * Somebody else must be accessing the NVmem, so abandon our 1598 * attempt take control of it. The caller can try again later ... 1599 */ 1600 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1601 bge_nvmem_relinquish(bgep); 1602 return (EAGAIN); 1603 } 1604 1605 /* 1606 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1607 * write protect line in such a way that the NVmem is protected when 1608 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1609 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1610 * 1611 * Note: there's only one set of GPIO pins on a 5704, even though they 1612 * can be accessed through either port. So the chip has to resolve what 1613 * happens if the two ports program a single pin differently ... the rule 1614 * it uses is that if the ports disagree about the *direction* of a pin, 1615 * "output" wins over "input", but if they disagree about its *value* as 1616 * an output, then the pin is TRISTATED instead! In such a case, no-one 1617 * wins, and the external signal does whatever the external circuitry 1618 * defines as the default -- which we've assumed is the PROTECTED state. 1619 * So, we always change GPIO1 back to being an *input* whenever we're not 1620 * specifically using it to unprotect the NVmem. This allows either port 1621 * to update the NVmem, although obviously only one at a time! 1622 * 1623 * The caller should hold <genlock> and *also* have already acquired the 1624 * right to access the NVmem, via bge_nvmem_acquire() above. 1625 */ 1626 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1627 #pragma inline(bge_nvmem_protect) 1628 1629 static void 1630 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1631 { 1632 uint32_t regval; 1633 1634 ASSERT(mutex_owned(bgep->genlock)); 1635 1636 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1637 if (protect) { 1638 regval |= MLCR_MISC_PINS_OUTPUT_1; 1639 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1640 } else { 1641 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1642 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1643 } 1644 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1645 } 1646 1647 /* 1648 * Now put it all together ... 1649 * 1650 * Try to acquire control of the NVmem; if successful, then: 1651 * unprotect it (if we want to write to it) 1652 * perform the requested access 1653 * reprotect it (after a write) 1654 * relinquish control 1655 * 1656 * Return value: 1657 * 0 on success, 1658 * EAGAIN if the device is in use (retryable) 1659 * ENODATA on access timeout (maybe retryable: device may just be busy) 1660 * ENODEV if the NVmem device is missing or otherwise unusable 1661 * EPROTO on other h/w or s/w errors. 1662 */ 1663 static int 1664 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1665 { 1666 int err; 1667 1668 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1669 switch (cmd) { 1670 case BGE_SEE_READ: 1671 err = bge_seeprom_access(bgep, 1672 SEEPROM_ACCESS_READ, addr, dp); 1673 break; 1674 1675 case BGE_SEE_WRITE: 1676 bge_nvmem_protect(bgep, B_FALSE); 1677 err = bge_seeprom_access(bgep, 1678 SEEPROM_ACCESS_WRITE, addr, dp); 1679 bge_nvmem_protect(bgep, B_TRUE); 1680 break; 1681 1682 case BGE_FLASH_READ: 1683 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1684 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1685 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1686 bge_reg_set32(bgep, NVM_ACCESS_REG, 1687 NVM_ACCESS_ENABLE); 1688 } 1689 err = bge_flash_access(bgep, 1690 NVM_FLASH_CMD_RD, addr, dp); 1691 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1692 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1693 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1694 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1695 NVM_ACCESS_ENABLE); 1696 } 1697 break; 1698 1699 case BGE_FLASH_WRITE: 1700 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1701 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1702 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1703 bge_reg_set32(bgep, NVM_ACCESS_REG, 1704 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1705 } 1706 bge_nvmem_protect(bgep, B_FALSE); 1707 err = bge_flash_access(bgep, 1708 NVM_FLASH_CMD_WR, addr, dp); 1709 bge_nvmem_protect(bgep, B_TRUE); 1710 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1711 DEVICE_5723_SERIES_CHIPSETS(bgep) || 1712 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1713 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1714 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1715 } 1716 1717 break; 1718 1719 default: 1720 _NOTE(NOTREACHED) 1721 break; 1722 } 1723 bge_nvmem_relinquish(bgep); 1724 } 1725 1726 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1727 return (err); 1728 } 1729 1730 /* 1731 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1732 */ 1733 static uint64_t bge_get_nvmac(bge_t *bgep); 1734 #pragma no_inline(bge_get_nvmac) 1735 1736 static uint64_t 1737 bge_get_nvmac(bge_t *bgep) 1738 { 1739 uint32_t mac_high; 1740 uint32_t mac_low; 1741 uint32_t addr; 1742 uint32_t cmd; 1743 uint64_t mac; 1744 1745 BGE_TRACE(("bge_get_nvmac($%p)", 1746 (void *)bgep)); 1747 1748 switch (bgep->chipid.nvtype) { 1749 case BGE_NVTYPE_NONE: 1750 case BGE_NVTYPE_UNKNOWN: 1751 default: 1752 return (0ULL); 1753 1754 case BGE_NVTYPE_SEEPROM: 1755 case BGE_NVTYPE_LEGACY_SEEPROM: 1756 cmd = BGE_SEE_READ; 1757 break; 1758 1759 case BGE_NVTYPE_UNBUFFERED_FLASH: 1760 case BGE_NVTYPE_BUFFERED_FLASH: 1761 cmd = BGE_FLASH_READ; 1762 break; 1763 } 1764 1765 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) 1766 addr = NVMEM_DATA_MAC_ADDRESS_5906; 1767 else 1768 addr = NVMEM_DATA_MAC_ADDRESS; 1769 1770 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1771 return (0ULL); 1772 addr += 4; 1773 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1774 return (0ULL); 1775 1776 /* 1777 * The Broadcom chip is natively BIG-endian, so that's how the 1778 * MAC address is represented in NVmem. We may need to swap it 1779 * around on a little-endian host ... 1780 */ 1781 #ifdef _BIG_ENDIAN 1782 mac = mac_high; 1783 mac = mac << 32; 1784 mac |= mac_low; 1785 #else 1786 mac = BGE_BSWAP_32(mac_high); 1787 mac = mac << 32; 1788 mac |= BGE_BSWAP_32(mac_low); 1789 #endif /* _BIG_ENDIAN */ 1790 1791 return (mac); 1792 } 1793 1794 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1795 1796 /* 1797 * Dummy version for when we're not supporting NVmem access 1798 */ 1799 static uint64_t bge_get_nvmac(bge_t *bgep); 1800 #pragma inline(bge_get_nvmac) 1801 1802 static uint64_t 1803 bge_get_nvmac(bge_t *bgep) 1804 { 1805 _NOTE(ARGUNUSED(bgep)) 1806 return (0ULL); 1807 } 1808 1809 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1810 1811 /* 1812 * Determine the type of NVmem that is (or may be) attached to this chip, 1813 */ 1814 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1815 #pragma no_inline(bge_nvmem_id) 1816 1817 static enum bge_nvmem_type 1818 bge_nvmem_id(bge_t *bgep) 1819 { 1820 enum bge_nvmem_type nvtype; 1821 uint32_t config1; 1822 1823 BGE_TRACE(("bge_nvmem_id($%p)", 1824 (void *)bgep)); 1825 1826 switch (bgep->chipid.device) { 1827 default: 1828 /* 1829 * We shouldn't get here; it means we don't recognise 1830 * the chip, which means we don't know how to determine 1831 * what sort of NVmem (if any) it has. So we'll say 1832 * NONE, to disable the NVmem access code ... 1833 */ 1834 nvtype = BGE_NVTYPE_NONE; 1835 break; 1836 1837 case DEVICE_ID_5700: 1838 case DEVICE_ID_5700x: 1839 case DEVICE_ID_5701: 1840 /* 1841 * These devices support *only* SEEPROMs 1842 */ 1843 nvtype = BGE_NVTYPE_SEEPROM; 1844 break; 1845 1846 case DEVICE_ID_5702: 1847 case DEVICE_ID_5702fe: 1848 case DEVICE_ID_5703C: 1849 case DEVICE_ID_5703S: 1850 case DEVICE_ID_5704C: 1851 case DEVICE_ID_5704S: 1852 case DEVICE_ID_5704: 1853 case DEVICE_ID_5705M: 1854 case DEVICE_ID_5705C: 1855 case DEVICE_ID_5705_2: 1856 case DEVICE_ID_5780: 1857 case DEVICE_ID_5782: 1858 case DEVICE_ID_5787: 1859 case DEVICE_ID_5787M: 1860 case DEVICE_ID_5788: 1861 case DEVICE_ID_5789: 1862 case DEVICE_ID_5751: 1863 case DEVICE_ID_5751M: 1864 case DEVICE_ID_5752: 1865 case DEVICE_ID_5752M: 1866 case DEVICE_ID_5754: 1867 case DEVICE_ID_5755: 1868 case DEVICE_ID_5755M: 1869 case DEVICE_ID_5756M: 1870 case DEVICE_ID_5721: 1871 case DEVICE_ID_5722: 1872 case DEVICE_ID_5723: 1873 case DEVICE_ID_5761: 1874 case DEVICE_ID_5761E: 1875 case DEVICE_ID_5714C: 1876 case DEVICE_ID_5714S: 1877 case DEVICE_ID_5715C: 1878 case DEVICE_ID_5715S: 1879 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1880 if (config1 & NVM_CFG1_FLASH_MODE) 1881 if (config1 & NVM_CFG1_BUFFERED_MODE) 1882 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1883 else 1884 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1885 else 1886 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1887 break; 1888 case DEVICE_ID_5906: 1889 case DEVICE_ID_5906M: 1890 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1891 break; 1892 } 1893 1894 return (nvtype); 1895 } 1896 1897 #undef BGE_DBG 1898 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1899 1900 static void 1901 bge_init_recv_rule(bge_t *bgep) 1902 { 1903 bge_recv_rule_t *rulep = bgep->recv_rules; 1904 uint32_t i; 1905 1906 /* 1907 * Initialize receive rule registers. 1908 * Note that rules may persist across each bge_m_start/stop() call. 1909 */ 1910 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1911 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1912 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1913 } 1914 } 1915 1916 /* 1917 * Using the values captured by bge_chip_cfg_init(), and additional probes 1918 * as required, characterise the chip fully: determine the label by which 1919 * to refer to this chip, the correct settings for various registers, and 1920 * of course whether the device and/or subsystem are supported! 1921 */ 1922 int bge_chip_id_init(bge_t *bgep); 1923 #pragma no_inline(bge_chip_id_init) 1924 1925 int 1926 bge_chip_id_init(bge_t *bgep) 1927 { 1928 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1929 boolean_t sys_ok; 1930 boolean_t dev_ok; 1931 chip_id_t *cidp; 1932 uint32_t subid; 1933 char *devname; 1934 char *sysname; 1935 int *ids; 1936 int err; 1937 uint_t i; 1938 1939 sys_ok = dev_ok = B_FALSE; 1940 cidp = &bgep->chipid; 1941 1942 /* 1943 * Check the PCI device ID to determine the generic chip type and 1944 * select parameters that depend on this. 1945 * 1946 * Note: because the SPARC platforms in general don't fit the 1947 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1948 * as zero - which is why we use <asic_rev> rather than <revision> 1949 * below ... 1950 * 1951 * Note: in general we can't distinguish between the Copper/SerDes 1952 * versions by ID alone, as some Copper devices (e.g. some but not 1953 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1954 * treat them the same here, and the MII code works out the media 1955 * type later on ... 1956 */ 1957 cidp->mbuf_base = bge_mbuf_pool_base; 1958 cidp->mbuf_length = bge_mbuf_pool_len; 1959 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1960 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1961 cidp->pci_type = BGE_PCI_X; 1962 cidp->statistic_type = BGE_STAT_BLK; 1963 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1964 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1965 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1966 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1967 cidp->rx_count_norm = bge_rx_count_norm; 1968 cidp->tx_ticks_norm = bge_tx_ticks_norm; 1969 cidp->tx_count_norm = bge_tx_count_norm; 1970 1971 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1972 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1973 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1974 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1975 1976 cidp->msi_enabled = B_FALSE; 1977 1978 switch (cidp->device) { 1979 case DEVICE_ID_5700: 1980 case DEVICE_ID_5700x: 1981 cidp->chip_label = 5700; 1982 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1983 break; 1984 1985 case DEVICE_ID_5701: 1986 cidp->chip_label = 5701; 1987 dev_ok = B_TRUE; 1988 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1989 break; 1990 1991 case DEVICE_ID_5702: 1992 case DEVICE_ID_5702fe: 1993 cidp->chip_label = 5702; 1994 dev_ok = B_TRUE; 1995 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1996 cidp->pci_type = BGE_PCI; 1997 break; 1998 1999 case DEVICE_ID_5703C: 2000 case DEVICE_ID_5703S: 2001 case DEVICE_ID_5703: 2002 /* 2003 * Revision A0 of the 5703/5793 had various errata 2004 * that we can't or don't work around, so it's not 2005 * supported, but all later versions are 2006 */ 2007 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2008 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2009 dev_ok = B_TRUE; 2010 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2011 break; 2012 2013 case DEVICE_ID_5704C: 2014 case DEVICE_ID_5704S: 2015 case DEVICE_ID_5704: 2016 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2017 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2018 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2019 dev_ok = B_TRUE; 2020 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2021 break; 2022 2023 case DEVICE_ID_5705C: 2024 case DEVICE_ID_5705M: 2025 case DEVICE_ID_5705MA3: 2026 case DEVICE_ID_5705F: 2027 case DEVICE_ID_5705_2: 2028 case DEVICE_ID_5754: 2029 if (cidp->device == DEVICE_ID_5754) { 2030 cidp->chip_label = 5754; 2031 cidp->pci_type = BGE_PCI_E; 2032 } else { 2033 cidp->chip_label = 5705; 2034 cidp->pci_type = BGE_PCI; 2035 } 2036 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2037 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2038 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2039 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2040 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2041 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2042 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2043 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2044 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2045 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2046 cidp->statistic_type = BGE_STAT_REG; 2047 dev_ok = B_TRUE; 2048 break; 2049 2050 case DEVICE_ID_5906: 2051 case DEVICE_ID_5906M: 2052 cidp->chip_label = 5906; 2053 cidp->pci_type = BGE_PCI_E; 2054 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906; 2055 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906; 2056 cidp->mbuf_hi_water = MBUF_HIWAT_5906; 2057 cidp->mbuf_base = bge_mbuf_pool_base; 2058 cidp->mbuf_length = bge_mbuf_pool_len; 2059 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2060 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2061 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2062 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2063 cidp->statistic_type = BGE_STAT_REG; 2064 dev_ok = B_TRUE; 2065 break; 2066 2067 case DEVICE_ID_5753: 2068 cidp->chip_label = 5753; 2069 cidp->pci_type = BGE_PCI_E; 2070 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2071 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2072 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2073 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2074 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2075 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2076 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2077 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2078 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2079 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2080 cidp->statistic_type = BGE_STAT_REG; 2081 dev_ok = B_TRUE; 2082 break; 2083 2084 case DEVICE_ID_5755: 2085 case DEVICE_ID_5755M: 2086 cidp->chip_label = 5755; 2087 cidp->pci_type = BGE_PCI_E; 2088 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2089 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2090 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2091 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2092 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2093 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2094 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2095 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2096 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2097 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2098 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2099 cidp->statistic_type = BGE_STAT_REG; 2100 dev_ok = B_TRUE; 2101 break; 2102 2103 case DEVICE_ID_5756M: 2104 /* 2105 * This is nearly identical to the 5755M. 2106 * (Actually reports the 5755 chip ID.) 2107 */ 2108 cidp->chip_label = 5756; 2109 cidp->pci_type = BGE_PCI_E; 2110 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2111 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2112 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2113 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2114 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2115 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2116 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2117 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2118 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2119 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2120 cidp->statistic_type = BGE_STAT_REG; 2121 dev_ok = B_TRUE; 2122 break; 2123 2124 case DEVICE_ID_5787: 2125 case DEVICE_ID_5787M: 2126 cidp->chip_label = 5787; 2127 cidp->pci_type = BGE_PCI_E; 2128 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2129 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2130 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2131 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2132 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2133 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2134 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2135 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2136 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2137 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2138 cidp->statistic_type = BGE_STAT_REG; 2139 dev_ok = B_TRUE; 2140 break; 2141 2142 case DEVICE_ID_5723: 2143 case DEVICE_ID_5761: 2144 case DEVICE_ID_5761E: 2145 cidp->chip_label = cidp->device == DEVICE_ID_5723 ? 5723: 5761; 2146 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2147 cidp->msi_enabled = bge_enable_msi; 2148 cidp->pci_type = BGE_PCI_E; 2149 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2150 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2151 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2152 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2153 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2154 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2155 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2156 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2157 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2158 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2159 cidp->statistic_type = BGE_STAT_REG; 2160 dev_ok = B_TRUE; 2161 break; 2162 2163 /* PCI-X device, identical to 5714 */ 2164 case DEVICE_ID_5780: 2165 cidp->chip_label = 5780; 2166 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2167 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2168 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2169 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2170 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2171 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2172 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2173 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2174 cidp->statistic_type = BGE_STAT_REG; 2175 dev_ok = B_TRUE; 2176 break; 2177 2178 case DEVICE_ID_5782: 2179 /* 2180 * Apart from the label, we treat this as a 5705(?) 2181 */ 2182 cidp->chip_label = 5782; 2183 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2184 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2185 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2186 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2187 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2188 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2189 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2190 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2191 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2192 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2193 cidp->statistic_type = BGE_STAT_REG; 2194 dev_ok = B_TRUE; 2195 break; 2196 2197 case DEVICE_ID_5788: 2198 /* 2199 * Apart from the label, we treat this as a 5705(?) 2200 */ 2201 cidp->chip_label = 5788; 2202 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2203 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2204 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2205 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2206 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2207 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2208 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2209 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2210 cidp->statistic_type = BGE_STAT_REG; 2211 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2212 dev_ok = B_TRUE; 2213 break; 2214 2215 case DEVICE_ID_5714C: 2216 if (cidp->revision >= REVISION_ID_5714_A2) 2217 cidp->msi_enabled = bge_enable_msi; 2218 /* FALLTHRU */ 2219 case DEVICE_ID_5714S: 2220 cidp->chip_label = 5714; 2221 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2222 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2223 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2224 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2225 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2226 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2227 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2228 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2229 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2230 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2231 cidp->pci_type = BGE_PCI_E; 2232 cidp->statistic_type = BGE_STAT_REG; 2233 dev_ok = B_TRUE; 2234 break; 2235 2236 case DEVICE_ID_5715C: 2237 case DEVICE_ID_5715S: 2238 cidp->chip_label = 5715; 2239 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2240 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2241 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2242 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2243 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2244 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2245 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2246 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2247 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2248 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2249 cidp->pci_type = BGE_PCI_E; 2250 cidp->statistic_type = BGE_STAT_REG; 2251 if (cidp->revision >= REVISION_ID_5715_A2) 2252 cidp->msi_enabled = bge_enable_msi; 2253 dev_ok = B_TRUE; 2254 break; 2255 2256 case DEVICE_ID_5721: 2257 cidp->chip_label = 5721; 2258 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2259 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2260 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2261 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2262 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2263 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2264 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2265 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2266 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2267 cidp->pci_type = BGE_PCI_E; 2268 cidp->statistic_type = BGE_STAT_REG; 2269 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2270 dev_ok = B_TRUE; 2271 break; 2272 2273 case DEVICE_ID_5722: 2274 cidp->chip_label = 5722; 2275 cidp->pci_type = BGE_PCI_E; 2276 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2277 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2278 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2279 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2280 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2281 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2282 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2283 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2284 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2285 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2286 cidp->statistic_type = BGE_STAT_REG; 2287 dev_ok = B_TRUE; 2288 break; 2289 2290 case DEVICE_ID_5751: 2291 case DEVICE_ID_5751M: 2292 cidp->chip_label = 5751; 2293 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2294 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2295 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2296 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2297 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2298 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2299 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2300 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2301 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2302 cidp->pci_type = BGE_PCI_E; 2303 cidp->statistic_type = BGE_STAT_REG; 2304 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2305 dev_ok = B_TRUE; 2306 break; 2307 2308 case DEVICE_ID_5752: 2309 case DEVICE_ID_5752M: 2310 cidp->chip_label = 5752; 2311 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2312 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2313 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2314 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2315 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2316 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2317 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2318 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2319 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2320 cidp->pci_type = BGE_PCI_E; 2321 cidp->statistic_type = BGE_STAT_REG; 2322 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2323 dev_ok = B_TRUE; 2324 break; 2325 2326 case DEVICE_ID_5789: 2327 cidp->chip_label = 5789; 2328 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2329 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2330 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2331 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2332 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2333 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2334 cidp->pci_type = BGE_PCI_E; 2335 cidp->statistic_type = BGE_STAT_REG; 2336 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2337 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2338 cidp->msi_enabled = B_TRUE; 2339 dev_ok = B_TRUE; 2340 break; 2341 2342 } 2343 2344 /* 2345 * Setup the default jumbo parameter. 2346 */ 2347 cidp->ethmax_size = ETHERMAX; 2348 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2349 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2350 2351 /* 2352 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2353 * setup below jumbo specific parameters. 2354 * 2355 * For BCM5714/5715, there is only one standard receive ring. So the 2356 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2357 * feature is enabled. 2358 */ 2359 if (bge_jumbo_enable && 2360 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2361 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2362 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2363 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2364 cidp->mbuf_lo_water_rdma = 2365 RDMA_MBUF_LOWAT_5714_JUMBO; 2366 cidp->mbuf_lo_water_rmac = 2367 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2368 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2369 cidp->jumbo_slots = 0; 2370 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2371 } else { 2372 cidp->mbuf_lo_water_rdma = 2373 RDMA_MBUF_LOWAT_JUMBO; 2374 cidp->mbuf_lo_water_rmac = 2375 MAC_RX_MBUF_LOWAT_JUMBO; 2376 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2377 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2378 } 2379 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2380 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2381 cidp->ethmax_size = cidp->default_mtu + 2382 sizeof (struct ether_header); 2383 } 2384 2385 /* 2386 * Identify the NV memory type: SEEPROM or Flash? 2387 */ 2388 cidp->nvtype = bge_nvmem_id(bgep); 2389 2390 /* 2391 * Now, we want to check whether this device is part of a 2392 * supported subsystem (e.g., on the motherboard of a Sun 2393 * branded platform). 2394 * 2395 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2396 */ 2397 if (cidp->subven == VENDOR_ID_SUN) 2398 sys_ok = B_TRUE; 2399 2400 /* 2401 * Rule 2: If it's on the list on known subsystems, then it's OK. 2402 * Note: 0x14e41647 should *not* appear in the list, but the code 2403 * doesn't enforce that. 2404 */ 2405 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2406 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2407 if (err == DDI_PROP_SUCCESS) { 2408 /* 2409 * Got the list; scan for a matching subsystem vendor/device 2410 */ 2411 subid = (cidp->subven << 16) | cidp->subdev; 2412 while (i--) 2413 if (ids[i] == subid) 2414 sys_ok = B_TRUE; 2415 ddi_prop_free(ids); 2416 } 2417 2418 /* 2419 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2420 * 2421 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2422 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2423 * we have to check specially for the exact device paths to the 2424 * motherboard devices on those platforms ;-( 2425 * 2426 * Note: we can't just use the "supported-subsystems" mechanism 2427 * above, because the entry would have to be 0x14e41647 -- which 2428 * would then accept *any* plugin card that *didn't* contain a 2429 * (valid) SEEPROM ;-( 2430 */ 2431 sysname = ddi_node_name(ddi_root_node()); 2432 devname = ddi_pathname(bgep->devinfo, buf); 2433 ASSERT(strlen(devname) > 0); 2434 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2435 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2436 sys_ok = B_TRUE; 2437 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2438 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2439 sys_ok = B_TRUE; 2440 2441 /* 2442 * Now check what we've discovered: is this truly a supported 2443 * chip on (the motherboard of) a supported platform? 2444 * 2445 * Possible problems here: 2446 * 1) it's a completely unheard-of chip 2447 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2448 * 3) it's a chip we would support if it were on the motherboard 2449 * of a Sun platform, but this one isn't ;-( 2450 */ 2451 if (cidp->chip_label == 0) 2452 bge_problem(bgep, 2453 "Device 'pci%04x,%04x' not recognized (%d?)", 2454 cidp->vendor, cidp->device, cidp->device); 2455 else if (!dev_ok) 2456 bge_problem(bgep, 2457 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2458 cidp->vendor, cidp->device, cidp->chip_label, 2459 cidp->revision); 2460 #if BGE_DEBUGGING 2461 else if (!sys_ok) 2462 bge_problem(bgep, 2463 "%d-based subsystem 'pci%04x,%04x' not validated", 2464 cidp->chip_label, cidp->subven, cidp->subdev); 2465 #endif 2466 else 2467 cidp->flags |= CHIP_FLAG_SUPPORTED; 2468 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2469 return (EIO); 2470 return (0); 2471 } 2472 2473 void 2474 bge_chip_msi_trig(bge_t *bgep) 2475 { 2476 uint32_t regval; 2477 2478 regval = bgep->param_msi_cnt<<4; 2479 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2480 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2481 } 2482 2483 /* 2484 * Various registers that control the chip's internal engines (state 2485 * machines) have a <reset> and <enable> bits (fortunately, in the 2486 * same place in each such register :-). 2487 * 2488 * To reset the state machine, the <reset> bit must be written with 1; 2489 * it will then read back as 1 while the reset is in progress, but 2490 * self-clear to 0 when the reset completes. 2491 * 2492 * To enable a state machine, one must set the <enable> bit, which 2493 * will continue to read back as 0 until the state machine is running. 2494 * 2495 * To disable a state machine, the <enable> bit must be cleared, but 2496 * it will continue to read back as 1 until the state machine actually 2497 * stops. 2498 * 2499 * This routine implements polling for completion of a reset, enable 2500 * or disable operation, returning B_TRUE on success (bit reached the 2501 * required state) or B_FALSE on timeout (200*100us == 20ms). 2502 */ 2503 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2504 uint32_t mask, uint32_t val); 2505 #pragma no_inline(bge_chip_poll_engine) 2506 2507 static boolean_t 2508 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2509 uint32_t mask, uint32_t val) 2510 { 2511 uint32_t regval; 2512 uint32_t n; 2513 2514 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2515 (void *)bgep, regno, mask, val)); 2516 2517 for (n = 200; n; --n) { 2518 regval = bge_reg_get32(bgep, regno); 2519 if ((regval & mask) == val) 2520 return (B_TRUE); 2521 drv_usecwait(100); 2522 } 2523 2524 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2525 return (B_FALSE); 2526 } 2527 2528 /* 2529 * Various registers that control the chip's internal engines (state 2530 * machines) have a <reset> bit (fortunately, in the same place in 2531 * each such register :-). To reset the state machine, this bit must 2532 * be written with 1; it will then read back as 1 while the reset is 2533 * in progress, but self-clear to 0 when the reset completes. 2534 * 2535 * This code sets the bit, then polls for it to read back as zero. 2536 * The return value is B_TRUE on success (reset bit cleared itself), 2537 * or B_FALSE if the state machine didn't recover :( 2538 * 2539 * NOTE: the Core reset is similar to other resets, except that we 2540 * can't poll for completion, since the Core reset disables memory 2541 * access! So we just have to assume that it will all complete in 2542 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2543 */ 2544 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2545 #pragma no_inline(bge_chip_reset_engine) 2546 2547 static boolean_t 2548 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2549 { 2550 uint32_t regval; 2551 uint32_t val32; 2552 2553 regval = bge_reg_get32(bgep, regno); 2554 2555 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2556 (void *)bgep, regno)); 2557 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2558 regno, regval)); 2559 2560 regval |= STATE_MACHINE_RESET_BIT; 2561 2562 switch (regno) { 2563 case MISC_CONFIG_REG: 2564 /* 2565 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2566 * resetting PCIE block and bringing PCIE link down, bit 29 2567 * in the register needs to be set first, and then set it again 2568 * while the reset bit is written. 2569 * See:P500 of 57xx-PG102-RDS.pdf. 2570 */ 2571 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2572 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2573 DEVICE_5723_SERIES_CHIPSETS(bgep)|| 2574 DEVICE_5714_SERIES_CHIPSETS(bgep)|| 2575 DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2576 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2577 if (bgep->chipid.pci_type == BGE_PCI_E) { 2578 if (bgep->chipid.asic_rev == 2579 MHCR_CHIP_REV_5751_A0 || 2580 bgep->chipid.asic_rev == 2581 MHCR_CHIP_REV_5721_A0 || 2582 bgep->chipid.asic_rev == 2583 MHCR_CHIP_REV_5755_A0) { 2584 val32 = bge_reg_get32(bgep, 2585 PHY_TEST_CTRL_REG); 2586 if (val32 == (PHY_PCIE_SCRAM_MODE | 2587 PHY_PCIE_LTASS_MODE)) 2588 bge_reg_put32(bgep, 2589 PHY_TEST_CTRL_REG, 2590 PHY_PCIE_SCRAM_MODE); 2591 val32 = pci_config_get32 2592 (bgep->cfg_handle, 2593 PCI_CONF_BGE_CLKCTL); 2594 val32 |= CLKCTL_PCIE_A0_FIX; 2595 pci_config_put32(bgep->cfg_handle, 2596 PCI_CONF_BGE_CLKCTL, val32); 2597 } 2598 bge_reg_set32(bgep, regno, 2599 MISC_CONFIG_GRC_RESET_DISABLE); 2600 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2601 } 2602 } 2603 2604 /* 2605 * Special case - causes Core reset 2606 * 2607 * On SPARC v9 we want to ensure that we don't start 2608 * timing until the I/O access has actually reached 2609 * the chip, otherwise we might make the next access 2610 * too early. And we can't just force the write out 2611 * by following it with a read (even to config space) 2612 * because that would cause the fault we're trying 2613 * to avoid. Hence the need for membar_sync() here. 2614 */ 2615 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2616 #ifdef __sparcv9 2617 membar_sync(); 2618 #endif /* __sparcv9 */ 2619 /* 2620 * On some platforms,system need about 300us for 2621 * link setup. 2622 */ 2623 drv_usecwait(300); 2624 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 2625 bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET); 2626 bge_reg_clr32( 2627 bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF); 2628 } 2629 2630 if (bgep->chipid.pci_type == BGE_PCI_E) { 2631 /* PCI-E device need more reset time */ 2632 drv_usecwait(120000); 2633 2634 /* Set PCIE max payload size and clear error status. */ 2635 if ((bgep->chipid.chip_label == 5721) || 2636 (bgep->chipid.chip_label == 5751) || 2637 (bgep->chipid.chip_label == 5752) || 2638 (bgep->chipid.chip_label == 5789) || 2639 (bgep->chipid.chip_label == 5906)) { 2640 pci_config_put16(bgep->cfg_handle, 2641 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2642 pci_config_put16(bgep->cfg_handle, 2643 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2644 } 2645 2646 if ((bgep->chipid.chip_label == 5723) || 2647 (bgep->chipid.chip_label == 5761)) { 2648 pci_config_put16(bgep->cfg_handle, 2649 PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX); 2650 pci_config_put16(bgep->cfg_handle, 2651 PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS); 2652 } 2653 } 2654 2655 BGE_PCICHK(bgep); 2656 return (B_TRUE); 2657 2658 default: 2659 bge_reg_put32(bgep, regno, regval); 2660 return (bge_chip_poll_engine(bgep, regno, 2661 STATE_MACHINE_RESET_BIT, 0)); 2662 } 2663 } 2664 2665 /* 2666 * Various registers that control the chip's internal engines (state 2667 * machines) have an <enable> bit (fortunately, in the same place in 2668 * each such register :-). To stop the state machine, this bit must 2669 * be written with 0, then polled to see when the state machine has 2670 * actually stopped. 2671 * 2672 * The return value is B_TRUE on success (enable bit cleared), or 2673 * B_FALSE if the state machine didn't stop :( 2674 */ 2675 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2676 uint32_t morebits); 2677 #pragma no_inline(bge_chip_disable_engine) 2678 2679 static boolean_t 2680 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2681 { 2682 uint32_t regval; 2683 2684 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2685 (void *)bgep, regno, morebits)); 2686 2687 switch (regno) { 2688 case FTQ_RESET_REG: 2689 /* 2690 * For Schumacher's bugfix CR6490108 2691 */ 2692 #ifdef BGE_IPMI_ASF 2693 #ifdef BGE_NETCONSOLE 2694 if (bgep->asf_enabled) 2695 return (B_TRUE); 2696 #endif 2697 #endif 2698 /* 2699 * Not quite like the others; it doesn't 2700 * have an <enable> bit, but instead we 2701 * have to set and then clear all the bits 2702 */ 2703 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2704 drv_usecwait(100); 2705 bge_reg_put32(bgep, regno, 0); 2706 return (B_TRUE); 2707 2708 default: 2709 regval = bge_reg_get32(bgep, regno); 2710 regval &= ~STATE_MACHINE_ENABLE_BIT; 2711 regval &= ~morebits; 2712 bge_reg_put32(bgep, regno, regval); 2713 return (bge_chip_poll_engine(bgep, regno, 2714 STATE_MACHINE_ENABLE_BIT, 0)); 2715 } 2716 } 2717 2718 /* 2719 * Various registers that control the chip's internal engines (state 2720 * machines) have an <enable> bit (fortunately, in the same place in 2721 * each such register :-). To start the state machine, this bit must 2722 * be written with 1, then polled to see when the state machine has 2723 * actually started. 2724 * 2725 * The return value is B_TRUE on success (enable bit set), or 2726 * B_FALSE if the state machine didn't start :( 2727 */ 2728 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2729 uint32_t morebits); 2730 #pragma no_inline(bge_chip_enable_engine) 2731 2732 static boolean_t 2733 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2734 { 2735 uint32_t regval; 2736 2737 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2738 (void *)bgep, regno, morebits)); 2739 2740 switch (regno) { 2741 case FTQ_RESET_REG: 2742 #ifdef BGE_IPMI_ASF 2743 #ifdef BGE_NETCONSOLE 2744 if (bgep->asf_enabled) 2745 return (B_TRUE); 2746 #endif 2747 #endif 2748 /* 2749 * Not quite like the others; it doesn't 2750 * have an <enable> bit, but instead we 2751 * have to set and then clear all the bits 2752 */ 2753 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2754 drv_usecwait(100); 2755 bge_reg_put32(bgep, regno, 0); 2756 return (B_TRUE); 2757 2758 default: 2759 regval = bge_reg_get32(bgep, regno); 2760 regval |= STATE_MACHINE_ENABLE_BIT; 2761 regval |= morebits; 2762 bge_reg_put32(bgep, regno, regval); 2763 return (bge_chip_poll_engine(bgep, regno, 2764 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2765 } 2766 } 2767 2768 /* 2769 * Reprogram the Ethernet, Transmit, and Receive MAC 2770 * modes to match the param_* variables 2771 */ 2772 void bge_sync_mac_modes(bge_t *bgep); 2773 #pragma no_inline(bge_sync_mac_modes) 2774 2775 void 2776 bge_sync_mac_modes(bge_t *bgep) 2777 { 2778 uint32_t macmode; 2779 uint32_t regval; 2780 2781 ASSERT(mutex_owned(bgep->genlock)); 2782 2783 /* 2784 * Reprogram the Ethernet MAC mode ... 2785 */ 2786 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2787 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2788 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2789 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2790 macmode |= ETHERNET_MODE_LINK_POLARITY; 2791 else 2792 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2793 else 2794 macmode |= ETHERNET_MODE_LINK_POLARITY; 2795 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2796 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2797 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) { 2798 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) 2799 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2800 else 2801 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2802 } else if (bgep->param_link_speed == 10 || 2803 bgep->param_link_speed == 100) 2804 macmode |= ETHERNET_MODE_PORTMODE_MII; 2805 else 2806 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2807 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2808 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2809 else 2810 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2811 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2812 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2813 else 2814 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2815 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2816 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2817 (void *)bgep, regval, macmode)); 2818 2819 /* 2820 * ... the Transmit MAC mode ... 2821 */ 2822 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2823 if (bgep->param_link_tx_pause) 2824 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2825 else 2826 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2827 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2828 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2829 (void *)bgep, regval, macmode)); 2830 2831 /* 2832 * ... and the Receive MAC mode 2833 */ 2834 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2835 if (bgep->param_link_rx_pause) 2836 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2837 else 2838 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2839 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2840 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2841 (void *)bgep, regval, macmode)); 2842 } 2843 2844 /* 2845 * bge_chip_sync() -- program the chip with the unicast MAC address, 2846 * the multicast hash table, the required level of promiscuity, and 2847 * the current loopback mode ... 2848 */ 2849 #ifdef BGE_IPMI_ASF 2850 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2851 #else 2852 int bge_chip_sync(bge_t *bgep); 2853 #endif 2854 #pragma no_inline(bge_chip_sync) 2855 2856 int 2857 #ifdef BGE_IPMI_ASF 2858 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2859 #else 2860 bge_chip_sync(bge_t *bgep) 2861 #endif 2862 { 2863 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2864 boolean_t promisc; 2865 uint64_t macaddr; 2866 uint32_t fill = 0; 2867 int i, j; 2868 int retval = DDI_SUCCESS; 2869 2870 BGE_TRACE(("bge_chip_sync($%p)", 2871 (void *)bgep)); 2872 2873 ASSERT(mutex_owned(bgep->genlock)); 2874 2875 promisc = B_FALSE; 2876 fill = ~(uint32_t)0; 2877 2878 if (bgep->promisc) 2879 promisc = B_TRUE; 2880 else 2881 fill = (uint32_t)0; 2882 2883 /* 2884 * If the TX/RX MAC engines are already running, we should stop 2885 * them (and reset the RX engine) before changing the parameters. 2886 * If they're not running, this will have no effect ... 2887 * 2888 * NOTE: this is currently disabled by default because stopping 2889 * and restarting the Tx engine may cause an outgoing packet in 2890 * transit to be truncated. Also, stopping and restarting the 2891 * Rx engine seems to not work correctly on the 5705. Testing 2892 * has not (yet!) revealed any problems with NOT stopping and 2893 * restarting these engines (and Broadcom say their drivers don't 2894 * do this), but if it is found to cause problems, this variable 2895 * can be patched to re-enable the old behaviour ... 2896 */ 2897 if (bge_stop_start_on_sync) { 2898 #ifdef BGE_IPMI_ASF 2899 if (!bgep->asf_enabled) { 2900 if (!bge_chip_disable_engine(bgep, 2901 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2902 retval = DDI_FAILURE; 2903 } else { 2904 if (!bge_chip_disable_engine(bgep, 2905 RECEIVE_MAC_MODE_REG, 0)) 2906 retval = DDI_FAILURE; 2907 } 2908 #else 2909 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2910 RECEIVE_MODE_KEEP_VLAN_TAG)) 2911 retval = DDI_FAILURE; 2912 #endif 2913 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2914 retval = DDI_FAILURE; 2915 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2916 retval = DDI_FAILURE; 2917 } 2918 2919 /* 2920 * Reprogram the hashed multicast address table ... 2921 */ 2922 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2923 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2924 2925 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2926 bge_reg_put32(bgep, MAC_HASH_REG(i), 2927 bgep->mcast_hash[i] | fill); 2928 2929 #ifdef BGE_IPMI_ASF 2930 if (!bgep->asf_enabled || !asf_keeplive) { 2931 #endif 2932 /* 2933 * Transform the MAC address(es) from host to chip format, then 2934 * reprogram the transmit random backoff seed and the unicast 2935 * MAC address(es) ... 2936 */ 2937 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2938 for (i = 0, macaddr = 0ull; 2939 i < ETHERADDRL; ++i) { 2940 macaddr <<= 8; 2941 macaddr |= bgep->curr_addr[j].addr[i]; 2942 } 2943 fill += (macaddr >> 16) + (macaddr & 0xffffffff); 2944 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2945 2946 BGE_DEBUG(("bge_chip_sync($%p) " 2947 "setting MAC address %012llx", 2948 (void *)bgep, macaddr)); 2949 } 2950 #ifdef BGE_IPMI_ASF 2951 } 2952 #endif 2953 /* 2954 * Set random seed of backoff interval 2955 * - Writing zero means no backoff interval 2956 */ 2957 fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff; 2958 if (fill == 0) 2959 fill = 1; 2960 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2961 2962 /* 2963 * Set or clear the PROMISCUOUS mode bit 2964 */ 2965 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2966 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2967 2968 /* 2969 * Sync the rest of the MAC modes too ... 2970 */ 2971 bge_sync_mac_modes(bgep); 2972 2973 /* 2974 * Restart RX/TX MAC engines if required ... 2975 */ 2976 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2977 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2978 retval = DDI_FAILURE; 2979 #ifdef BGE_IPMI_ASF 2980 if (!bgep->asf_enabled) { 2981 if (!bge_chip_enable_engine(bgep, 2982 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2983 retval = DDI_FAILURE; 2984 } else { 2985 if (!bge_chip_enable_engine(bgep, 2986 RECEIVE_MAC_MODE_REG, 0)) 2987 retval = DDI_FAILURE; 2988 } 2989 #else 2990 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2991 RECEIVE_MODE_KEEP_VLAN_TAG)) 2992 retval = DDI_FAILURE; 2993 #endif 2994 } 2995 return (retval); 2996 } 2997 2998 /* 2999 * This array defines the sequence of state machine control registers 3000 * in which the <enable> bit must be cleared to bring the chip to a 3001 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 3002 */ 3003 static bge_regno_t shutdown_engine_regs[] = { 3004 RECEIVE_MAC_MODE_REG, 3005 RCV_BD_INITIATOR_MODE_REG, 3006 RCV_LIST_PLACEMENT_MODE_REG, 3007 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 3008 RCV_DATA_BD_INITIATOR_MODE_REG, 3009 RCV_DATA_COMPLETION_MODE_REG, 3010 RCV_BD_COMPLETION_MODE_REG, 3011 3012 SEND_BD_SELECTOR_MODE_REG, 3013 SEND_BD_INITIATOR_MODE_REG, 3014 SEND_DATA_INITIATOR_MODE_REG, 3015 READ_DMA_MODE_REG, 3016 SEND_DATA_COMPLETION_MODE_REG, 3017 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 3018 SEND_BD_COMPLETION_MODE_REG, 3019 TRANSMIT_MAC_MODE_REG, 3020 3021 HOST_COALESCE_MODE_REG, 3022 WRITE_DMA_MODE_REG, 3023 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 3024 FTQ_RESET_REG, /* special - see code */ 3025 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 3026 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 3027 BGE_REGNO_NONE /* terminator */ 3028 }; 3029 3030 #ifndef __sparc 3031 static bge_regno_t quiesce_regs[] = { 3032 READ_DMA_MODE_REG, 3033 DMA_COMPLETION_MODE_REG, 3034 WRITE_DMA_MODE_REG, 3035 BGE_REGNO_NONE 3036 }; 3037 3038 void bge_chip_stop_nonblocking(bge_t *bgep); 3039 #pragma no_inline(bge_chip_stop_nonblocking) 3040 3041 /* 3042 * This function is called by bge_quiesce(). We 3043 * turn off all the DMA engines here. 3044 */ 3045 void 3046 bge_chip_stop_nonblocking(bge_t *bgep) 3047 { 3048 bge_regno_t *rbp; 3049 3050 /* 3051 * Flag that no more activity may be initiated 3052 */ 3053 bgep->progress &= ~PROGRESS_READY; 3054 3055 rbp = quiesce_regs; 3056 while (*rbp != BGE_REGNO_NONE) { 3057 (void) bge_chip_disable_engine(bgep, *rbp, 0); 3058 ++rbp; 3059 } 3060 3061 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3062 } 3063 3064 #endif 3065 3066 /* 3067 * bge_chip_stop() -- stop all chip processing 3068 * 3069 * If the <fault> parameter is B_TRUE, we're stopping the chip because 3070 * we've detected a problem internally; otherwise, this is a normal 3071 * (clean) stop (at user request i.e. the last STREAM has been closed). 3072 */ 3073 void bge_chip_stop(bge_t *bgep, boolean_t fault); 3074 #pragma no_inline(bge_chip_stop) 3075 3076 void 3077 bge_chip_stop(bge_t *bgep, boolean_t fault) 3078 { 3079 bge_regno_t regno; 3080 bge_regno_t *rbp; 3081 boolean_t ok; 3082 3083 BGE_TRACE(("bge_chip_stop($%p)", 3084 (void *)bgep)); 3085 3086 ASSERT(mutex_owned(bgep->genlock)); 3087 3088 rbp = shutdown_engine_regs; 3089 /* 3090 * When driver try to shutdown the BCM5705/5788/5721/5751/ 3091 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 3092 * -ory arbiter should not be disabled. 3093 */ 3094 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 3095 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3096 ok &= bge_chip_disable_engine(bgep, regno, 0); 3097 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 3098 (regno != DMA_COMPLETION_MODE_REG) && 3099 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 3100 (regno != BUFFER_MANAGER_MODE_REG) && 3101 (regno != MEMORY_ARBITER_MODE_REG)) 3102 ok &= bge_chip_disable_engine(bgep, 3103 regno, 0); 3104 } 3105 3106 if (!ok && !fault) 3107 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 3108 3109 /* 3110 * Finally, disable (all) MAC events & clear the MAC status 3111 */ 3112 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 3113 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 3114 3115 /* 3116 * if we're stopping the chip because of a detected fault then do 3117 * appropriate actions 3118 */ 3119 if (fault) { 3120 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 3121 bgep->bge_chip_state = BGE_CHIP_FAULT; 3122 if (!bgep->manual_reset) 3123 ddi_fm_service_impact(bgep->devinfo, 3124 DDI_SERVICE_LOST); 3125 if (bgep->bge_dma_error) { 3126 /* 3127 * need to free buffers in case the fault was 3128 * due to a memory error in a buffer - got to 3129 * do a fair bit of tidying first 3130 */ 3131 if (bgep->progress & PROGRESS_KSTATS) { 3132 bge_fini_kstats(bgep); 3133 bgep->progress &= ~PROGRESS_KSTATS; 3134 } 3135 if (bgep->progress & PROGRESS_INTR) { 3136 bge_intr_disable(bgep); 3137 rw_enter(bgep->errlock, RW_WRITER); 3138 bge_fini_rings(bgep); 3139 rw_exit(bgep->errlock); 3140 bgep->progress &= ~PROGRESS_INTR; 3141 } 3142 if (bgep->progress & PROGRESS_BUFS) { 3143 bge_free_bufs(bgep); 3144 bgep->progress &= ~PROGRESS_BUFS; 3145 } 3146 bgep->bge_dma_error = B_FALSE; 3147 } 3148 } 3149 } else 3150 bgep->bge_chip_state = BGE_CHIP_STOPPED; 3151 } 3152 3153 /* 3154 * Poll for completion of chip's ROM firmware; also, at least on the 3155 * first time through, find and return the hardware MAC address, if any. 3156 */ 3157 static uint64_t bge_poll_firmware(bge_t *bgep); 3158 #pragma no_inline(bge_poll_firmware) 3159 3160 static uint64_t 3161 bge_poll_firmware(bge_t *bgep) 3162 { 3163 uint64_t magic; 3164 uint64_t mac; 3165 uint32_t gen, val; 3166 uint32_t i; 3167 3168 /* 3169 * Step 19: poll for firmware completion (GENCOMM port set 3170 * to the ones complement of T3_MAGIC_NUMBER). 3171 * 3172 * While we're at it, we also read the MAC address register; 3173 * at some stage the firmware will load this with the 3174 * factory-set value. 3175 * 3176 * When both the magic number and the MAC address are set, 3177 * we're done; but we impose a time limit of one second 3178 * (1000*1000us) in case the firmware fails in some fashion 3179 * or the SEEPROM that provides that MAC address isn't fitted. 3180 * 3181 * After the first time through (chip state != INITIAL), we 3182 * don't need the MAC address to be set (we've already got it 3183 * or not, from the first time), so we don't wait for it, but 3184 * we still have to wait for the T3_MAGIC_NUMBER. 3185 * 3186 * Note: the magic number is only a 32-bit quantity, but the NIC 3187 * memory is 64-bit (and big-endian) internally. Addressing the 3188 * GENCOMM word as "the upper half of a 64-bit quantity" makes 3189 * it work correctly on both big- and little-endian hosts. 3190 */ 3191 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3192 MHCR_CHIP_ASIC_REV_5906) { 3193 for (i = 0; i < 1000; ++i) { 3194 drv_usecwait(1000); 3195 val = bge_reg_get32(bgep, VCPU_STATUS_REG); 3196 if (val & VCPU_INIT_DONE) 3197 break; 3198 } 3199 BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops", 3200 (void *)bgep, i)); 3201 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3202 } else { 3203 for (i = 0; i < 1000; ++i) { 3204 drv_usecwait(1000); 3205 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 3206 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 3207 drv_usecwait(100000); 3208 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 3209 #ifdef BGE_IPMI_ASF 3210 if (!bgep->asf_enabled) { 3211 #endif 3212 if (gen != ~T3_MAGIC_NUMBER) 3213 continue; 3214 #ifdef BGE_IPMI_ASF 3215 } 3216 #endif 3217 if (mac != 0ULL) 3218 break; 3219 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3220 break; 3221 } 3222 } 3223 3224 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3225 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3226 (void *)bgep, gen, i)); 3227 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3228 mac, magic)); 3229 3230 return (mac); 3231 } 3232 3233 /* 3234 * Maximum times of trying to get the NVRAM access lock 3235 * by calling bge_nvmem_acquire() 3236 */ 3237 #define MAX_TRY_NVMEM_ACQUIRE 10000 3238 3239 #ifdef BGE_IPMI_ASF 3240 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3241 #else 3242 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3243 #endif 3244 #pragma no_inline(bge_chip_reset) 3245 3246 int 3247 #ifdef BGE_IPMI_ASF 3248 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3249 #else 3250 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3251 #endif 3252 { 3253 chip_id_t chipid; 3254 uint64_t mac; 3255 uint64_t magic; 3256 uint32_t modeflags; 3257 uint32_t mhcr; 3258 uint32_t sx0; 3259 uint32_t i, tries; 3260 #ifdef BGE_IPMI_ASF 3261 uint32_t mailbox; 3262 #endif 3263 int retval = DDI_SUCCESS; 3264 3265 BGE_TRACE(("bge_chip_reset($%p, %d)", 3266 (void *)bgep, enable_dma)); 3267 3268 ASSERT(mutex_owned(bgep->genlock)); 3269 3270 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3271 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3272 3273 /* 3274 * Do we need to stop the chip cleanly before resetting? 3275 */ 3276 switch (bgep->bge_chip_state) { 3277 default: 3278 _NOTE(NOTREACHED) 3279 return (DDI_FAILURE); 3280 3281 case BGE_CHIP_INITIAL: 3282 case BGE_CHIP_STOPPED: 3283 case BGE_CHIP_RESET: 3284 break; 3285 3286 case BGE_CHIP_RUNNING: 3287 case BGE_CHIP_ERROR: 3288 case BGE_CHIP_FAULT: 3289 bge_chip_stop(bgep, B_FALSE); 3290 break; 3291 } 3292 3293 #ifdef BGE_IPMI_ASF 3294 if (bgep->asf_enabled) { 3295 #ifdef __sparc 3296 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3297 MHCR_ENABLE_TAGGED_STATUS_MODE | 3298 MHCR_MASK_INTERRUPT_MODE | 3299 MHCR_MASK_PCI_INT_OUTPUT | 3300 MHCR_CLEAR_INTERRUPT_INTA | 3301 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3302 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3303 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3304 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3305 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3306 MEMORY_ARBITER_ENABLE); 3307 #endif 3308 if (asf_mode == ASF_MODE_INIT) { 3309 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3310 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3311 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3312 } 3313 } 3314 #endif 3315 /* 3316 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3317 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3318 * 3319 * Before reset Core clock,it is 3320 * also required to initialize the Memory Arbiter as specified in step9 3321 * and Misc Host Control Register as specified in step-13 3322 * Step 4-5: reset Core clock & wait for completion 3323 * Steps 6-8: are done by bge_chip_cfg_init() 3324 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3325 */ 3326 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3327 retval = DDI_FAILURE; 3328 3329 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3330 MHCR_ENABLE_TAGGED_STATUS_MODE | 3331 MHCR_MASK_INTERRUPT_MODE | 3332 MHCR_MASK_PCI_INT_OUTPUT | 3333 MHCR_CLEAR_INTERRUPT_INTA; 3334 #ifdef _BIG_ENDIAN 3335 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3336 #endif /* _BIG_ENDIAN */ 3337 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3338 #ifdef BGE_IPMI_ASF 3339 if (bgep->asf_enabled) 3340 bgep->asf_wordswapped = B_FALSE; 3341 #endif 3342 /* 3343 * NVRAM Corruption Workaround 3344 */ 3345 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3346 if (bge_nvmem_acquire(bgep) != EAGAIN) 3347 break; 3348 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3349 BGE_DEBUG(("%s: fail to acquire nvram lock", 3350 bgep->ifname)); 3351 3352 #ifdef BGE_IPMI_ASF 3353 if (!bgep->asf_enabled) { 3354 #endif 3355 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3356 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3357 #ifdef BGE_IPMI_ASF 3358 } 3359 #endif 3360 3361 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3362 retval = DDI_FAILURE; 3363 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3364 3365 /* 3366 * Step 8a: This may belong elsewhere, but BCM5721 needs 3367 * a bit set to avoid a fifo overflow/underflow bug. 3368 */ 3369 if ((bgep->chipid.chip_label == 5721) || 3370 (bgep->chipid.chip_label == 5751) || 3371 (bgep->chipid.chip_label == 5752) || 3372 (bgep->chipid.chip_label == 5755) || 3373 (bgep->chipid.chip_label == 5756) || 3374 (bgep->chipid.chip_label == 5789) || 3375 (bgep->chipid.chip_label == 5906)) 3376 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3377 3378 3379 /* 3380 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3381 * not be changed. 3382 */ 3383 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3384 retval = DDI_FAILURE; 3385 3386 /* 3387 * Steps 10-11: configure PIO endianness options and 3388 * enable indirect register access -- already done 3389 * Steps 12-13: enable writing to the PCI state & clock 3390 * control registers -- not required; we aren't going to 3391 * use those features. 3392 * Steps 14-15: Configure DMA endianness options. See 3393 * the comments on the setting of the MHCR above. 3394 */ 3395 #ifdef _BIG_ENDIAN 3396 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3397 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3398 #else 3399 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3400 #endif /* _BIG_ENDIAN */ 3401 #ifdef BGE_IPMI_ASF 3402 if (bgep->asf_enabled) 3403 modeflags |= MODE_HOST_STACK_UP; 3404 #endif 3405 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3406 3407 #ifdef BGE_IPMI_ASF 3408 if (bgep->asf_enabled) { 3409 #ifdef __sparc 3410 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3411 MEMORY_ARBITER_ENABLE | 3412 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3413 #endif 3414 3415 #ifdef BGE_NETCONSOLE 3416 if (!bgep->asf_newhandshake) { 3417 if ((asf_mode == ASF_MODE_INIT) || 3418 (asf_mode == ASF_MODE_POST_INIT)) { 3419 bge_asf_post_reset_old_mode(bgep, 3420 BGE_INIT_RESET); 3421 } else { 3422 bge_asf_post_reset_old_mode(bgep, 3423 BGE_SHUTDOWN_RESET); 3424 } 3425 } 3426 #endif 3427 3428 /* Wait for NVRAM init */ 3429 i = 0; 3430 drv_usecwait(5000); 3431 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3432 3433 while ((mailbox != (uint32_t) 3434 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3435 (i < 10000)) { 3436 drv_usecwait(100); 3437 mailbox = bge_nic_get32(bgep, 3438 BGE_FIRMWARE_MAILBOX); 3439 i++; 3440 } 3441 3442 #ifndef BGE_NETCONSOLE 3443 if (!bgep->asf_newhandshake) { 3444 if ((asf_mode == ASF_MODE_INIT) || 3445 (asf_mode == ASF_MODE_POST_INIT)) { 3446 3447 bge_asf_post_reset_old_mode(bgep, 3448 BGE_INIT_RESET); 3449 } else { 3450 bge_asf_post_reset_old_mode(bgep, 3451 BGE_SHUTDOWN_RESET); 3452 } 3453 } 3454 #endif 3455 } 3456 #endif 3457 /* 3458 * Steps 16-17: poll for firmware completion 3459 */ 3460 mac = bge_poll_firmware(bgep); 3461 3462 /* 3463 * Step 18: enable external memory -- doesn't apply. 3464 * 3465 * However we take the opportunity to set the MLCR anyway, as 3466 * this register also controls the SEEPROM auto-access method 3467 * which we may want to use later ... 3468 * 3469 * The proper value here depends on the way the chip is wired 3470 * into the circuit board, as this register *also* controls which 3471 * of the "Miscellaneous I/O" pins are driven as outputs and the 3472 * values driven onto those pins! 3473 * 3474 * See also step 74 in the PRM ... 3475 */ 3476 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3477 bgep->chipid.bge_mlcr_default); 3478 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3479 3480 /* 3481 * Step 20: clear the Ethernet MAC mode register 3482 */ 3483 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3484 3485 /* 3486 * Step 21: restore cache-line-size, latency timer, and 3487 * subsystem ID registers to their original values (not 3488 * those read into the local structure <chipid>, 'cos 3489 * that was after they were cleared by the RESET). 3490 * 3491 * Note: the Subsystem Vendor/Device ID registers are not 3492 * directly writable in config space, so we use the shadow 3493 * copy in "Page Zero" of register space to restore them 3494 * both in one go ... 3495 */ 3496 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3497 bgep->chipid.clsize); 3498 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3499 bgep->chipid.latency); 3500 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3501 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3502 3503 /* 3504 * The SEND INDEX registers should be reset to zero by the 3505 * global chip reset; if they're not, there'll be trouble 3506 * later on. 3507 */ 3508 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3509 if (sx0 != 0) { 3510 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3511 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3512 retval = DDI_FAILURE; 3513 } 3514 3515 /* Enable MSI code */ 3516 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3517 bge_reg_set32(bgep, MSI_MODE_REG, 3518 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3519 3520 /* 3521 * On the first time through, save the factory-set MAC address 3522 * (if any). If bge_poll_firmware() above didn't return one 3523 * (from a chip register) consider looking in the attached NV 3524 * memory device, if any. Once we have it, we save it in both 3525 * register-image (64-bit) and byte-array forms. All-zero and 3526 * all-one addresses are not valid, and we refuse to stash those. 3527 */ 3528 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3529 if (mac == 0ULL) 3530 mac = bge_get_nvmac(bgep); 3531 if (mac != 0ULL && mac != ~0ULL) { 3532 bgep->chipid.hw_mac_addr = mac; 3533 for (i = ETHERADDRL; i-- != 0; ) { 3534 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3535 mac >>= 8; 3536 } 3537 bgep->chipid.vendor_addr.set = B_TRUE; 3538 } 3539 } 3540 3541 #ifdef BGE_IPMI_ASF 3542 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3543 if (asf_mode != ASF_MODE_NONE) { 3544 if ((asf_mode == ASF_MODE_INIT) || 3545 (asf_mode == ASF_MODE_POST_INIT)) { 3546 3547 bge_asf_post_reset_new_mode(bgep, 3548 BGE_INIT_RESET); 3549 } else { 3550 bge_asf_post_reset_new_mode(bgep, 3551 BGE_SHUTDOWN_RESET); 3552 } 3553 } 3554 } 3555 #endif 3556 3557 /* 3558 * Record the new state 3559 */ 3560 bgep->chip_resets += 1; 3561 bgep->bge_chip_state = BGE_CHIP_RESET; 3562 return (retval); 3563 } 3564 3565 /* 3566 * bge_chip_start() -- start the chip transmitting and/or receiving, 3567 * including enabling interrupts 3568 */ 3569 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3570 #pragma no_inline(bge_chip_start) 3571 3572 void 3573 bge_chip_coalesce_update(bge_t *bgep) 3574 { 3575 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, 3576 bgep->chipid.tx_count_norm); 3577 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, 3578 bgep->chipid.tx_ticks_norm); 3579 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, 3580 bgep->chipid.rx_count_norm); 3581 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, 3582 bgep->chipid.rx_ticks_norm); 3583 } 3584 3585 int 3586 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3587 { 3588 uint32_t coalmode; 3589 uint32_t ledctl; 3590 uint32_t mtu; 3591 uint32_t maxring; 3592 uint32_t stats_mask; 3593 uint32_t dma_wrprio; 3594 uint64_t ring; 3595 int retval = DDI_SUCCESS; 3596 3597 BGE_TRACE(("bge_chip_start($%p)", 3598 (void *)bgep)); 3599 3600 ASSERT(mutex_owned(bgep->genlock)); 3601 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3602 3603 /* 3604 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3605 * The document specifies 95 separate steps to fully 3606 * initialise the chip!!!! 3607 * 3608 * The reset code above has already got us as far as step 3609 * 21, so we continue with ... 3610 * 3611 * Step 22: clear the MAC statistics block 3612 * (0x0300-0x0aff in NIC-local memory) 3613 */ 3614 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3615 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3616 NIC_MEM_STATISTICS_SIZE); 3617 3618 /* 3619 * Step 23: clear the status block (in host memory) 3620 */ 3621 DMA_ZERO(bgep->status_block); 3622 3623 /* 3624 * Step 24: set DMA read/write control register 3625 */ 3626 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3627 bgep->chipid.bge_dma_rwctrl); 3628 3629 /* 3630 * Step 25: Configure DMA endianness -- already done (16/17) 3631 * Step 26: Configure Host-Based Send Rings 3632 * Step 27: Indicate Host Stack Up 3633 */ 3634 bge_reg_set32(bgep, MODE_CONTROL_REG, 3635 MODE_HOST_SEND_BDS | 3636 MODE_HOST_STACK_UP); 3637 3638 /* 3639 * Step 28: Configure checksum options: 3640 * Solaris supports the hardware default checksum options. 3641 * 3642 * Workaround for Incorrect pseudo-header checksum calculation. 3643 */ 3644 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3645 bge_reg_set32(bgep, MODE_CONTROL_REG, 3646 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3647 3648 /* 3649 * Step 29: configure Timer Prescaler. The value is always the 3650 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3651 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3652 * for the whole chip! 3653 */ 3654 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3655 3656 if (DEVICE_5906_SERIES_CHIPSETS(bgep)) { 3657 drv_usecwait(40); 3658 /* put PHY into ready state */ 3659 bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ); 3660 (void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */ 3661 drv_usecwait(40); 3662 } 3663 3664 /* 3665 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3666 * 3667 * If the mbuf_length is specified as 0, we just leave these at 3668 * their hardware defaults, rather than explicitly setting them. 3669 * As the Broadcom HRM,driver better not change the parameters 3670 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3671 */ 3672 if ((bgep->chipid.mbuf_length != 0) && 3673 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3674 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3675 bgep->chipid.mbuf_base); 3676 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3677 bgep->chipid.mbuf_length); 3678 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3679 DMAD_POOL_BASE_DEFAULT); 3680 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3681 DMAD_POOL_LENGTH_DEFAULT); 3682 } 3683 3684 /* 3685 * Step 32: configure MAC memory pool watermarks 3686 */ 3687 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3688 bgep->chipid.mbuf_lo_water_rdma); 3689 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3690 bgep->chipid.mbuf_lo_water_rmac); 3691 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3692 bgep->chipid.mbuf_hi_water); 3693 3694 /* 3695 * Step 33: configure DMA resource watermarks 3696 */ 3697 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3698 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3699 bge_dmad_lo_water); 3700 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3701 bge_dmad_hi_water); 3702 } 3703 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3704 3705 /* 3706 * Steps 34-36: enable buffer manager & internal h/w queues 3707 */ 3708 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3709 STATE_MACHINE_ATTN_ENABLE_BIT)) 3710 retval = DDI_FAILURE; 3711 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3712 retval = DDI_FAILURE; 3713 3714 /* 3715 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3716 */ 3717 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3718 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3719 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3720 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3721 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3722 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3723 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3724 } 3725 3726 /* 3727 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3728 */ 3729 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3730 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3731 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3732 bge_replenish_jumbo); 3733 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3734 bge_replenish_mini); 3735 } 3736 3737 /* 3738 * Steps 41-43: clear Send Ring Producer Indices and initialise 3739 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3740 */ 3741 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3742 maxring = BGE_SEND_RINGS_MAX; 3743 else 3744 maxring = BGE_SEND_RINGS_MAX_5705; 3745 for (ring = 0; ring < maxring; ++ring) { 3746 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3747 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3748 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3749 &bgep->send[ring].hw_rcb); 3750 } 3751 3752 /* 3753 * Steps 44-45: initialise Receive Return Rings 3754 * (0x0200-0x02ff in NIC-local memory) 3755 */ 3756 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3757 maxring = BGE_RECV_RINGS_MAX; 3758 else 3759 maxring = BGE_RECV_RINGS_MAX_5705; 3760 for (ring = 0; ring < maxring; ++ring) 3761 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3762 &bgep->recv[ring].hw_rcb); 3763 3764 /* 3765 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3766 */ 3767 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3768 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3769 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3770 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3771 } 3772 /* 3773 * Step 47: configure the MAC unicast address 3774 * Step 48: configure the random backoff seed 3775 * Step 96: set up multicast filters 3776 */ 3777 #ifdef BGE_IPMI_ASF 3778 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3779 #else 3780 if (bge_chip_sync(bgep) == DDI_FAILURE) 3781 #endif 3782 retval = DDI_FAILURE; 3783 3784 /* 3785 * Step 49: configure the MTU 3786 */ 3787 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3788 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3789 3790 /* 3791 * Step 50: configure the IPG et al 3792 */ 3793 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3794 3795 /* 3796 * Step 51: configure the default Rx Return Ring 3797 */ 3798 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3799 3800 /* 3801 * Steps 52-54: configure Receive List Placement, 3802 * and enable Receive List Placement Statistics 3803 */ 3804 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3805 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3806 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3807 case MHCR_CHIP_ASIC_REV_5700: 3808 case MHCR_CHIP_ASIC_REV_5701: 3809 case MHCR_CHIP_ASIC_REV_5703: 3810 case MHCR_CHIP_ASIC_REV_5704: 3811 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3812 break; 3813 case MHCR_CHIP_ASIC_REV_5705: 3814 break; 3815 default: 3816 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3817 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3818 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3819 break; 3820 } 3821 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3822 3823 if (bgep->chipid.rx_rings > 1) 3824 bge_init_recv_rule(bgep); 3825 3826 /* 3827 * Steps 55-56: enable Send Data Initiator Statistics 3828 */ 3829 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3830 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3831 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3832 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3833 } else { 3834 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3835 SEND_INIT_STATS_ENABLE); 3836 } 3837 /* 3838 * Steps 57-58: stop (?) the Host Coalescing Engine 3839 */ 3840 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3841 retval = DDI_FAILURE; 3842 3843 /* 3844 * Steps 59-62: initialise Host Coalescing parameters 3845 */ 3846 bge_chip_coalesce_update(bgep); 3847 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3848 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3849 bge_tx_count_intr); 3850 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3851 bge_tx_ticks_intr); 3852 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3853 bge_rx_count_intr); 3854 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3855 bge_rx_ticks_intr); 3856 } 3857 3858 /* 3859 * Steps 63-64: initialise status block & statistics 3860 * host memory addresses 3861 * The statistic block does not exist in some chipsets 3862 * Step 65: initialise Statistics Coalescing Tick Counter 3863 */ 3864 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3865 bgep->status_block.cookie.dmac_laddress); 3866 3867 /* 3868 * Steps 66-67: initialise status block & statistics 3869 * NIC-local memory addresses 3870 */ 3871 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3872 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3873 bgep->statistics.cookie.dmac_laddress); 3874 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3875 STATISTICS_TICKS_DEFAULT); 3876 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3877 NIC_MEM_STATUS_BLOCK); 3878 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3879 NIC_MEM_STATISTICS); 3880 } 3881 3882 /* 3883 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3884 * Completion Engine, the Receive List Placement Engine, and the 3885 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3886 * and BCM5715. 3887 */ 3888 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3889 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3890 coalmode = COALESCE_64_BYTE_STATUS; 3891 else 3892 coalmode = 0; 3893 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3894 retval = DDI_FAILURE; 3895 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3896 STATE_MACHINE_ATTN_ENABLE_BIT)) 3897 retval = DDI_FAILURE; 3898 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3899 retval = DDI_FAILURE; 3900 3901 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3902 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3903 STATE_MACHINE_ATTN_ENABLE_BIT)) 3904 retval = DDI_FAILURE; 3905 3906 /* 3907 * Step 72: Enable MAC DMA engines 3908 * Step 73: Clear & enable MAC statistics 3909 */ 3910 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3911 ETHERNET_MODE_ENABLE_FHDE | 3912 ETHERNET_MODE_ENABLE_RDE | 3913 ETHERNET_MODE_ENABLE_TDE); 3914 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3915 ETHERNET_MODE_ENABLE_TX_STATS | 3916 ETHERNET_MODE_ENABLE_RX_STATS | 3917 ETHERNET_MODE_CLEAR_TX_STATS | 3918 ETHERNET_MODE_CLEAR_RX_STATS); 3919 3920 /* 3921 * Step 74: configure the MLCR (Miscellaneous Local Control 3922 * Register); not required, as we set up the MLCR in step 10 3923 * (part of the reset code) above. 3924 * 3925 * Step 75: clear Interrupt Mailbox 0 3926 */ 3927 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3928 3929 /* 3930 * Steps 76-87: Gentlemen, start your engines ... 3931 * 3932 * Enable the DMA Completion Engine, the Write DMA Engine, 3933 * the Read DMA Engine, Receive Data Completion Engine, 3934 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3935 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3936 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3937 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3938 * 3939 * Beware exhaust fumes? 3940 */ 3941 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3942 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3943 retval = DDI_FAILURE; 3944 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3945 ALL_DMA_ATTN_BITS; 3946 if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3947 MHCR_CHIP_ASIC_REV_5755) || 3948 (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3949 MHCR_CHIP_ASIC_REV_5906)) { 3950 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3951 } 3952 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3953 dma_wrprio)) 3954 retval = DDI_FAILURE; 3955 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3956 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3957 retval = DDI_FAILURE; 3958 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3959 STATE_MACHINE_ATTN_ENABLE_BIT)) 3960 retval = DDI_FAILURE; 3961 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3962 if (!bge_chip_enable_engine(bgep, 3963 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3964 retval = DDI_FAILURE; 3965 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3966 retval = DDI_FAILURE; 3967 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3968 STATE_MACHINE_ATTN_ENABLE_BIT)) 3969 retval = DDI_FAILURE; 3970 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3971 RCV_BD_DISABLED_RING_ATTN)) 3972 retval = DDI_FAILURE; 3973 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3974 RCV_DATA_BD_ILL_RING_ATTN)) 3975 retval = DDI_FAILURE; 3976 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3977 retval = DDI_FAILURE; 3978 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3979 STATE_MACHINE_ATTN_ENABLE_BIT)) 3980 retval = DDI_FAILURE; 3981 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3982 STATE_MACHINE_ATTN_ENABLE_BIT)) 3983 retval = DDI_FAILURE; 3984 3985 /* 3986 * Step 88: download firmware -- doesn't apply 3987 * Steps 89-90: enable Transmit & Receive MAC Engines 3988 */ 3989 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3990 retval = DDI_FAILURE; 3991 #ifdef BGE_IPMI_ASF 3992 if (!bgep->asf_enabled) { 3993 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3994 RECEIVE_MODE_KEEP_VLAN_TAG)) 3995 retval = DDI_FAILURE; 3996 } else { 3997 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3998 retval = DDI_FAILURE; 3999 } 4000 #else 4001 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 4002 RECEIVE_MODE_KEEP_VLAN_TAG)) 4003 retval = DDI_FAILURE; 4004 #endif 4005 4006 /* 4007 * Step 91: disable auto-polling of PHY status 4008 */ 4009 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 4010 4011 /* 4012 * Step 92: configure D0 power state (not required) 4013 * Step 93: initialise LED control register () 4014 */ 4015 ledctl = LED_CONTROL_DEFAULT; 4016 switch (bgep->chipid.device) { 4017 case DEVICE_ID_5700: 4018 case DEVICE_ID_5700x: 4019 case DEVICE_ID_5701: 4020 /* 4021 * Switch to 5700 (MAC) mode on these older chips 4022 */ 4023 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 4024 ledctl |= LED_CONTROL_LED_MODE_5700; 4025 break; 4026 4027 default: 4028 break; 4029 } 4030 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 4031 4032 /* 4033 * Step 94: activate link 4034 */ 4035 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 4036 4037 /* 4038 * Step 95: set up physical layer (PHY/SerDes) 4039 * restart autoneg (if required) 4040 */ 4041 if (reset_phys) 4042 if (bge_phys_update(bgep) == DDI_FAILURE) 4043 retval = DDI_FAILURE; 4044 4045 /* 4046 * Extra step (DSG): hand over all the Receive Buffers to the chip 4047 */ 4048 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 4049 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 4050 bgep->buff[ring].rf_next); 4051 4052 /* 4053 * MSI bits:The least significant MSI 16-bit word. 4054 * ISR will be triggered different. 4055 */ 4056 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 4057 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 4058 4059 /* 4060 * Extra step (DSG): select which interrupts are enabled 4061 * 4062 * Program the Ethernet MAC engine to signal attention on 4063 * Link Change events, then enable interrupts on MAC, DMA, 4064 * and FLOW attention signals. 4065 */ 4066 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 4067 ETHERNET_EVENT_LINK_INT | 4068 ETHERNET_STATUS_PCS_ERROR_INT); 4069 #ifdef BGE_IPMI_ASF 4070 if (bgep->asf_enabled) { 4071 bge_reg_set32(bgep, MODE_CONTROL_REG, 4072 MODE_INT_ON_FLOW_ATTN | 4073 MODE_INT_ON_DMA_ATTN | 4074 MODE_HOST_STACK_UP| 4075 MODE_INT_ON_MAC_ATTN); 4076 } else { 4077 #endif 4078 bge_reg_set32(bgep, MODE_CONTROL_REG, 4079 MODE_INT_ON_FLOW_ATTN | 4080 MODE_INT_ON_DMA_ATTN | 4081 MODE_INT_ON_MAC_ATTN); 4082 #ifdef BGE_IPMI_ASF 4083 } 4084 #endif 4085 4086 /* 4087 * Step 97: enable PCI interrupts!!! 4088 */ 4089 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 4090 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 4091 MHCR_MASK_PCI_INT_OUTPUT); 4092 4093 /* 4094 * All done! 4095 */ 4096 bgep->bge_chip_state = BGE_CHIP_RUNNING; 4097 return (retval); 4098 } 4099 4100 4101 /* 4102 * ========== Hardware interrupt handler ========== 4103 */ 4104 4105 #undef BGE_DBG 4106 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 4107 4108 /* 4109 * Sync the status block, then atomically clear the specified bits in 4110 * the <flags-and-tag> field of the status block. 4111 * the <flags> word of the status block, returning the value of the 4112 * <tag> and the <flags> before the bits were cleared. 4113 */ 4114 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 4115 #pragma inline(bge_status_sync) 4116 4117 static int 4118 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 4119 { 4120 bge_status_t *bsp; 4121 int retval; 4122 4123 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 4124 (void *)bgep, bits)); 4125 4126 ASSERT(bgep->bge_guard == BGE_GUARD); 4127 4128 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 4129 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 4130 if (retval != DDI_FM_OK) 4131 return (retval); 4132 4133 bsp = DMA_VPTR(bgep->status_block); 4134 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 4135 4136 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 4137 (void *)bgep, bits, *flags)); 4138 4139 return (retval); 4140 } 4141 4142 void bge_wake_factotum(bge_t *bgep); 4143 #pragma inline(bge_wake_factotum) 4144 4145 void 4146 bge_wake_factotum(bge_t *bgep) 4147 { 4148 mutex_enter(bgep->softintrlock); 4149 if (bgep->factotum_flag == 0) { 4150 bgep->factotum_flag = 1; 4151 ddi_trigger_softintr(bgep->factotum_id); 4152 } 4153 mutex_exit(bgep->softintrlock); 4154 } 4155 4156 /* 4157 * bge_intr() -- handle chip interrupts 4158 */ 4159 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 4160 #pragma no_inline(bge_intr) 4161 4162 uint_t 4163 bge_intr(caddr_t arg1, caddr_t arg2) 4164 { 4165 bge_t *bgep = (void *)arg1; /* private device info */ 4166 bge_status_t *bsp; 4167 uint64_t flags; 4168 uint32_t regval; 4169 uint_t result; 4170 int retval, loop_cnt = 0; 4171 4172 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 4173 4174 /* 4175 * GLD v2 checks that s/w setup is complete before passing 4176 * interrupts to this routine, thus eliminating the old 4177 * (and well-known) race condition around ddi_add_intr() 4178 */ 4179 ASSERT(bgep->progress & PROGRESS_HWINT); 4180 4181 result = DDI_INTR_UNCLAIMED; 4182 mutex_enter(bgep->genlock); 4183 4184 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4185 /* 4186 * Check whether chip's says it's asserting #INTA; 4187 * if not, don't process or claim the interrupt. 4188 * 4189 * Note that the PCI signal is active low, so the 4190 * bit is *zero* when the interrupt is asserted. 4191 */ 4192 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 4193 if (regval & MLCR_INTA_STATE) { 4194 if (bge_check_acc_handle(bgep, bgep->io_handle) 4195 != DDI_FM_OK) 4196 goto chip_stop; 4197 mutex_exit(bgep->genlock); 4198 return (result); 4199 } 4200 4201 /* 4202 * Block further PCI interrupts ... 4203 */ 4204 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 4205 MHCR_MASK_PCI_INT_OUTPUT); 4206 4207 } else { 4208 /* 4209 * Check MSI status 4210 */ 4211 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 4212 if (regval & MSI_ERROR_ATTENTION) { 4213 BGE_REPORT((bgep, "msi error attention," 4214 " status=0x%x", regval)); 4215 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 4216 } 4217 } 4218 4219 result = DDI_INTR_CLAIMED; 4220 4221 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 4222 4223 /* 4224 * Sync the status block and grab the flags-n-tag from it. 4225 * We count the number of interrupts where there doesn't 4226 * seem to have been a DMA update of the status block; if 4227 * it *has* been updated, the counter will be cleared in 4228 * the while() loop below ... 4229 */ 4230 bgep->missed_dmas += 1; 4231 bsp = DMA_VPTR(bgep->status_block); 4232 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 4233 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 4234 /* 4235 * bge_chip_stop() may have freed dma area etc 4236 * while we were in this interrupt handler - 4237 * better not call bge_status_sync() 4238 */ 4239 (void) bge_check_acc_handle(bgep, 4240 bgep->io_handle); 4241 mutex_exit(bgep->genlock); 4242 return (DDI_INTR_CLAIMED); 4243 } 4244 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4245 &flags); 4246 if (retval != DDI_FM_OK) { 4247 bgep->bge_dma_error = B_TRUE; 4248 goto chip_stop; 4249 } 4250 4251 if (!(flags & STATUS_FLAG_UPDATED)) 4252 break; 4253 4254 /* 4255 * Tell the chip that we're processing the interrupt 4256 */ 4257 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4258 INTERRUPT_MBOX_DISABLE(flags)); 4259 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4260 DDI_FM_OK) 4261 goto chip_stop; 4262 4263 /* 4264 * Drop the mutex while we: 4265 * Receive any newly-arrived packets 4266 * Recycle any newly-finished send buffers 4267 */ 4268 bgep->bge_intr_running = B_TRUE; 4269 mutex_exit(bgep->genlock); 4270 bge_receive(bgep, bsp); 4271 bge_recycle(bgep, bsp); 4272 mutex_enter(bgep->genlock); 4273 bgep->bge_intr_running = B_FALSE; 4274 4275 /* 4276 * Tell the chip we've finished processing, and 4277 * give it the tag that we got from the status 4278 * block earlier, so that it knows just how far 4279 * we've gone. If it's got more for us to do, 4280 * it will now update the status block and try 4281 * to assert an interrupt (but we've got the 4282 * #INTA blocked at present). If we see the 4283 * update, we'll loop around to do some more. 4284 * Eventually we'll get out of here ... 4285 */ 4286 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4287 INTERRUPT_MBOX_ENABLE(flags)); 4288 if (bgep->chipid.pci_type == BGE_PCI_E) 4289 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4290 bgep->missed_dmas = 0; 4291 } 4292 4293 /* 4294 * Check for exceptional conditions that we need to handle 4295 * 4296 * Link status changed 4297 * Status block not updated 4298 */ 4299 if (flags & STATUS_FLAG_LINK_CHANGED) 4300 bge_wake_factotum(bgep); 4301 4302 if (bgep->missed_dmas) { 4303 /* 4304 * Probably due to the internal status tag not 4305 * being reset. Force a status block update now; 4306 * this should ensure that we get an update and 4307 * a new interrupt. After that, we should be in 4308 * sync again ... 4309 */ 4310 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4311 "not updated?", flags)); 4312 bgep->missed_updates++; 4313 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4314 COALESCE_NOW); 4315 4316 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4317 /* 4318 * If this happens multiple times in a row, 4319 * it means DMA is just not working. Maybe 4320 * the chip's failed, or maybe there's a 4321 * problem on the PCI bus or in the host-PCI 4322 * bridge (Tomatillo). 4323 * 4324 * At all events, we want to stop further 4325 * interrupts and let the recovery code take 4326 * over to see whether anything can be done 4327 * about it ... 4328 */ 4329 bge_fm_ereport(bgep, 4330 DDI_FM_DEVICE_BADINT_LIMIT); 4331 goto chip_stop; 4332 } 4333 } 4334 4335 /* 4336 * Reenable assertion of #INTA, unless there's a DMA fault 4337 */ 4338 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4339 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4340 MHCR_MASK_PCI_INT_OUTPUT); 4341 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4342 DDI_FM_OK) 4343 goto chip_stop; 4344 } 4345 4346 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4347 goto chip_stop; 4348 4349 mutex_exit(bgep->genlock); 4350 return (result); 4351 4352 chip_stop: 4353 #ifdef BGE_IPMI_ASF 4354 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4355 /* 4356 * We must stop ASF heart beat before 4357 * bge_chip_stop(), otherwise some 4358 * computers (ex. IBM HS20 blade 4359 * server) may crash. 4360 */ 4361 bge_asf_update_status(bgep); 4362 bge_asf_stop_timer(bgep); 4363 bgep->asf_status = ASF_STAT_STOP; 4364 4365 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4366 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4367 } 4368 #endif 4369 bge_chip_stop(bgep, B_TRUE); 4370 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4371 mutex_exit(bgep->genlock); 4372 return (result); 4373 } 4374 4375 /* 4376 * ========== Factotum, implemented as a softint handler ========== 4377 */ 4378 4379 #undef BGE_DBG 4380 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4381 4382 static void bge_factotum_error_handler(bge_t *bgep); 4383 #pragma no_inline(bge_factotum_error_handler) 4384 4385 static void 4386 bge_factotum_error_handler(bge_t *bgep) 4387 { 4388 uint32_t flow; 4389 uint32_t rdma; 4390 uint32_t wdma; 4391 uint32_t tmac; 4392 uint32_t rmac; 4393 uint32_t rxrs; 4394 uint32_t txrs = 0; 4395 4396 ASSERT(mutex_owned(bgep->genlock)); 4397 4398 /* 4399 * Read all the registers that show the possible 4400 * reasons for the ERROR bit to be asserted 4401 */ 4402 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4403 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4404 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4405 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4406 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4407 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4408 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4409 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4410 4411 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4412 (void *)bgep, flow, rdma, wdma)); 4413 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4414 (void *)bgep, tmac, rmac, rxrs, txrs)); 4415 4416 /* 4417 * For now, just clear all the errors ... 4418 */ 4419 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4420 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4421 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4422 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4423 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4424 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4425 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4426 } 4427 4428 /* 4429 * Handler for hardware link state change. 4430 * 4431 * When this routine is called, the hardware link state has changed 4432 * and the new state is reflected in the param_* variables. Here 4433 * we must update the softstate and reprogram the MAC to match. 4434 */ 4435 static void bge_factotum_link_handler(bge_t *bgep); 4436 #pragma no_inline(bge_factotum_link_handler) 4437 4438 static void 4439 bge_factotum_link_handler(bge_t *bgep) 4440 { 4441 ASSERT(mutex_owned(bgep->genlock)); 4442 4443 /* 4444 * Update the s/w link_state 4445 */ 4446 if (bgep->param_link_up) 4447 bgep->link_state = LINK_STATE_UP; 4448 else 4449 bgep->link_state = LINK_STATE_DOWN; 4450 4451 /* 4452 * Reprogram the MAC modes to match 4453 */ 4454 bge_sync_mac_modes(bgep); 4455 } 4456 4457 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4458 #pragma no_inline(bge_factotum_link_check) 4459 4460 static boolean_t 4461 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4462 { 4463 boolean_t check; 4464 uint64_t flags; 4465 uint32_t tmac_status; 4466 4467 ASSERT(mutex_owned(bgep->genlock)); 4468 4469 /* 4470 * Get & clear the writable status bits in the Tx status register 4471 * (some bits are write-1-to-clear, others are just readonly). 4472 */ 4473 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4474 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4475 4476 /* 4477 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4478 */ 4479 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4480 STATUS_FLAG_LINK_CHANGED, &flags); 4481 if (*dma_state != DDI_FM_OK) 4482 return (B_FALSE); 4483 4484 /* 4485 * Clear any errors flagged in the status block ... 4486 */ 4487 if (flags & STATUS_FLAG_ERROR) 4488 bge_factotum_error_handler(bgep); 4489 4490 /* 4491 * We need to check the link status if: 4492 * the status block says there's been a link change 4493 * or there's any discrepancy between the various 4494 * flags indicating the link state (link_state, 4495 * param_link_up, and the LINK STATE bit in the 4496 * Transmit MAC status register). 4497 */ 4498 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4499 switch (bgep->link_state) { 4500 case LINK_STATE_UP: 4501 check |= (bgep->param_link_up == B_FALSE); 4502 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4503 break; 4504 4505 case LINK_STATE_DOWN: 4506 check |= (bgep->param_link_up != B_FALSE); 4507 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4508 break; 4509 4510 default: 4511 check = B_TRUE; 4512 break; 4513 } 4514 4515 /* 4516 * If <check> is false, we're sure the link hasn't changed. 4517 * If true, however, it's not yet definitive; we have to call 4518 * bge_phys_check() to determine whether the link has settled 4519 * into a new state yet ... and if it has, then call the link 4520 * state change handler.But when the chip is 5700 in Dell 6650 4521 * ,even if check is false, the link may have changed.So we 4522 * have to call bge_phys_check() to determine the link state. 4523 */ 4524 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4525 check = bge_phys_check(bgep); 4526 if (check) 4527 bge_factotum_link_handler(bgep); 4528 } 4529 4530 return (check); 4531 } 4532 4533 /* 4534 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4535 */ 4536 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4537 #pragma no_inline(bge_factotum_stall_check) 4538 4539 static boolean_t 4540 bge_factotum_stall_check(bge_t *bgep) 4541 { 4542 uint32_t dogval; 4543 4544 ASSERT(mutex_owned(bgep->genlock)); 4545 4546 /* 4547 * Specific check for Tx stall ... 4548 * 4549 * The 'watchdog' counter is incremented whenever a packet 4550 * is queued, reset to 1 when some (but not all) buffers 4551 * are reclaimed, reset to 0 (disabled) when all buffers 4552 * are reclaimed, and shifted left here. If it exceeds the 4553 * threshold value, the chip is assumed to have stalled and 4554 * is put into the ERROR state. The factotum will then reset 4555 * it on the next pass. 4556 * 4557 * All of which should ensure that we don't get into a state 4558 * where packets are left pending indefinitely! 4559 */ 4560 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4561 if (dogval < bge_watchdog_count) 4562 return (B_FALSE); 4563 4564 #if !defined(BGE_NETCONSOLE) 4565 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4566 #endif 4567 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4568 return (B_TRUE); 4569 } 4570 4571 /* 4572 * The factotum is woken up when there's something to do that we'd rather 4573 * not do from inside a hardware interrupt handler or high-level cyclic. 4574 * Its two main tasks are: 4575 * reset & restart the chip after an error 4576 * check the link status whenever necessary 4577 */ 4578 uint_t bge_chip_factotum(caddr_t arg); 4579 #pragma no_inline(bge_chip_factotum) 4580 4581 uint_t 4582 bge_chip_factotum(caddr_t arg) 4583 { 4584 bge_t *bgep; 4585 uint_t result; 4586 boolean_t error; 4587 boolean_t linkchg; 4588 int dma_state; 4589 4590 bgep = (void *)arg; 4591 4592 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4593 4594 mutex_enter(bgep->softintrlock); 4595 if (bgep->factotum_flag == 0) { 4596 mutex_exit(bgep->softintrlock); 4597 return (DDI_INTR_UNCLAIMED); 4598 } 4599 bgep->factotum_flag = 0; 4600 mutex_exit(bgep->softintrlock); 4601 4602 result = DDI_INTR_CLAIMED; 4603 error = B_FALSE; 4604 linkchg = B_FALSE; 4605 4606 mutex_enter(bgep->genlock); 4607 switch (bgep->bge_chip_state) { 4608 default: 4609 break; 4610 4611 case BGE_CHIP_RUNNING: 4612 linkchg = bge_factotum_link_check(bgep, &dma_state); 4613 error = bge_factotum_stall_check(bgep); 4614 if (dma_state != DDI_FM_OK) { 4615 bgep->bge_dma_error = B_TRUE; 4616 error = B_TRUE; 4617 } 4618 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4619 error = B_TRUE; 4620 if (error) 4621 bgep->bge_chip_state = BGE_CHIP_ERROR; 4622 break; 4623 4624 case BGE_CHIP_ERROR: 4625 error = B_TRUE; 4626 break; 4627 4628 case BGE_CHIP_FAULT: 4629 /* 4630 * Fault detected, time to reset ... 4631 */ 4632 if (bge_autorecover) { 4633 if (!(bgep->progress & PROGRESS_BUFS)) { 4634 /* 4635 * if we can't allocate the ring buffers, 4636 * try later 4637 */ 4638 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4639 mutex_exit(bgep->genlock); 4640 return (result); 4641 } 4642 bgep->progress |= PROGRESS_BUFS; 4643 } 4644 if (!(bgep->progress & PROGRESS_INTR)) { 4645 bge_init_rings(bgep); 4646 bge_intr_enable(bgep); 4647 bgep->progress |= PROGRESS_INTR; 4648 } 4649 if (!(bgep->progress & PROGRESS_KSTATS)) { 4650 bge_init_kstats(bgep, 4651 ddi_get_instance(bgep->devinfo)); 4652 bgep->progress |= PROGRESS_KSTATS; 4653 } 4654 4655 BGE_REPORT((bgep, "automatic recovery activated")); 4656 4657 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4658 bgep->bge_chip_state = BGE_CHIP_ERROR; 4659 error = B_TRUE; 4660 } 4661 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4662 DDI_FM_OK) { 4663 bgep->bge_chip_state = BGE_CHIP_ERROR; 4664 error = B_TRUE; 4665 } 4666 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4667 DDI_FM_OK) { 4668 bgep->bge_chip_state = BGE_CHIP_ERROR; 4669 error = B_TRUE; 4670 } 4671 if (error == B_FALSE) { 4672 #ifdef BGE_IPMI_ASF 4673 if (bgep->asf_enabled && 4674 bgep->asf_status != ASF_STAT_RUN) { 4675 bgep->asf_timeout_id = timeout( 4676 bge_asf_heartbeat, (void *)bgep, 4677 drv_usectohz( 4678 BGE_ASF_HEARTBEAT_INTERVAL)); 4679 bgep->asf_status = ASF_STAT_RUN; 4680 } 4681 #endif 4682 if (!bgep->manual_reset) { 4683 ddi_fm_service_impact(bgep->devinfo, 4684 DDI_SERVICE_RESTORED); 4685 } 4686 } 4687 } 4688 break; 4689 } 4690 4691 4692 /* 4693 * If an error is detected, stop the chip now, marking it as 4694 * faulty, so that it will be reset next time through ... 4695 * 4696 * Note that if intr_running is set, then bge_intr() has dropped 4697 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4698 * this point so have to wait until the next time the factotum runs. 4699 */ 4700 if (error && !bgep->bge_intr_running) { 4701 #ifdef BGE_IPMI_ASF 4702 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4703 /* 4704 * We must stop ASF heart beat before bge_chip_stop(), 4705 * otherwise some computers (ex. IBM HS20 blade server) 4706 * may crash. 4707 */ 4708 bge_asf_update_status(bgep); 4709 bge_asf_stop_timer(bgep); 4710 bgep->asf_status = ASF_STAT_STOP; 4711 4712 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4713 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4714 } 4715 #endif 4716 bge_chip_stop(bgep, B_TRUE); 4717 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4718 } 4719 mutex_exit(bgep->genlock); 4720 4721 /* 4722 * If the link state changed, tell the world about it. 4723 * Note: can't do this while still holding the mutex. 4724 */ 4725 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4726 bgep->link_state != LINK_STATE_UNKNOWN) 4727 linkchg = B_TRUE; 4728 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4729 bgep->link_state == LINK_STATE_DOWN) 4730 linkchg = B_FALSE; 4731 4732 if (linkchg) { 4733 mac_link_update(bgep->mh, bgep->link_state); 4734 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4735 } 4736 if (bgep->manual_reset) { 4737 bgep->manual_reset = B_FALSE; 4738 } 4739 4740 return (result); 4741 } 4742 4743 /* 4744 * High-level cyclic handler 4745 * 4746 * This routine schedules a (low-level) softint callback to the 4747 * factotum, and prods the chip to update the status block (which 4748 * will cause a hardware interrupt when complete). 4749 */ 4750 void bge_chip_cyclic(void *arg); 4751 #pragma no_inline(bge_chip_cyclic) 4752 4753 void 4754 bge_chip_cyclic(void *arg) 4755 { 4756 bge_t *bgep; 4757 4758 bgep = arg; 4759 4760 switch (bgep->bge_chip_state) { 4761 default: 4762 return; 4763 4764 case BGE_CHIP_RUNNING: 4765 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4766 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4767 ddi_fm_service_impact(bgep->devinfo, 4768 DDI_SERVICE_UNAFFECTED); 4769 4770 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4771 bgep->link_update_timer++; 4772 4773 break; 4774 4775 case BGE_CHIP_FAULT: 4776 case BGE_CHIP_ERROR: 4777 break; 4778 } 4779 4780 bge_wake_factotum(bgep); 4781 } 4782 4783 4784 /* 4785 * ========== Ioctl subfunctions ========== 4786 */ 4787 4788 #undef BGE_DBG 4789 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4790 4791 #if BGE_DEBUGGING || BGE_DO_PPIO 4792 4793 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4794 #pragma no_inline(bge_chip_peek_cfg) 4795 4796 static void 4797 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4798 { 4799 uint64_t regval; 4800 uint64_t regno; 4801 4802 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4803 (void *)bgep, (void *)ppd)); 4804 4805 regno = ppd->pp_acc_offset; 4806 4807 switch (ppd->pp_acc_size) { 4808 case 1: 4809 regval = pci_config_get8(bgep->cfg_handle, regno); 4810 break; 4811 4812 case 2: 4813 regval = pci_config_get16(bgep->cfg_handle, regno); 4814 break; 4815 4816 case 4: 4817 regval = pci_config_get32(bgep->cfg_handle, regno); 4818 break; 4819 4820 case 8: 4821 regval = pci_config_get64(bgep->cfg_handle, regno); 4822 break; 4823 } 4824 4825 ppd->pp_acc_data = regval; 4826 } 4827 4828 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4829 #pragma no_inline(bge_chip_poke_cfg) 4830 4831 static void 4832 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4833 { 4834 uint64_t regval; 4835 uint64_t regno; 4836 4837 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4838 (void *)bgep, (void *)ppd)); 4839 4840 regno = ppd->pp_acc_offset; 4841 regval = ppd->pp_acc_data; 4842 4843 switch (ppd->pp_acc_size) { 4844 case 1: 4845 pci_config_put8(bgep->cfg_handle, regno, regval); 4846 break; 4847 4848 case 2: 4849 pci_config_put16(bgep->cfg_handle, regno, regval); 4850 break; 4851 4852 case 4: 4853 pci_config_put32(bgep->cfg_handle, regno, regval); 4854 break; 4855 4856 case 8: 4857 pci_config_put64(bgep->cfg_handle, regno, regval); 4858 break; 4859 } 4860 } 4861 4862 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4863 #pragma no_inline(bge_chip_peek_reg) 4864 4865 static void 4866 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4867 { 4868 uint64_t regval; 4869 void *regaddr; 4870 4871 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4872 (void *)bgep, (void *)ppd)); 4873 4874 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4875 4876 switch (ppd->pp_acc_size) { 4877 case 1: 4878 regval = ddi_get8(bgep->io_handle, regaddr); 4879 break; 4880 4881 case 2: 4882 regval = ddi_get16(bgep->io_handle, regaddr); 4883 break; 4884 4885 case 4: 4886 regval = ddi_get32(bgep->io_handle, regaddr); 4887 break; 4888 4889 case 8: 4890 regval = ddi_get64(bgep->io_handle, regaddr); 4891 break; 4892 } 4893 4894 ppd->pp_acc_data = regval; 4895 } 4896 4897 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4898 #pragma no_inline(bge_chip_peek_reg) 4899 4900 static void 4901 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4902 { 4903 uint64_t regval; 4904 void *regaddr; 4905 4906 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4907 (void *)bgep, (void *)ppd)); 4908 4909 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4910 regval = ppd->pp_acc_data; 4911 4912 switch (ppd->pp_acc_size) { 4913 case 1: 4914 ddi_put8(bgep->io_handle, regaddr, regval); 4915 break; 4916 4917 case 2: 4918 ddi_put16(bgep->io_handle, regaddr, regval); 4919 break; 4920 4921 case 4: 4922 ddi_put32(bgep->io_handle, regaddr, regval); 4923 break; 4924 4925 case 8: 4926 ddi_put64(bgep->io_handle, regaddr, regval); 4927 break; 4928 } 4929 BGE_PCICHK(bgep); 4930 } 4931 4932 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4933 #pragma no_inline(bge_chip_peek_nic) 4934 4935 static void 4936 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4937 { 4938 uint64_t regoff; 4939 uint64_t regval; 4940 void *regaddr; 4941 4942 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4943 (void *)bgep, (void *)ppd)); 4944 4945 regoff = ppd->pp_acc_offset; 4946 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4947 regoff &= MWBAR_GRANULE_MASK; 4948 regoff += NIC_MEM_WINDOW_OFFSET; 4949 regaddr = PIO_ADDR(bgep, regoff); 4950 4951 switch (ppd->pp_acc_size) { 4952 case 1: 4953 regval = ddi_get8(bgep->io_handle, regaddr); 4954 break; 4955 4956 case 2: 4957 regval = ddi_get16(bgep->io_handle, regaddr); 4958 break; 4959 4960 case 4: 4961 regval = ddi_get32(bgep->io_handle, regaddr); 4962 break; 4963 4964 case 8: 4965 regval = ddi_get64(bgep->io_handle, regaddr); 4966 break; 4967 } 4968 4969 ppd->pp_acc_data = regval; 4970 } 4971 4972 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4973 #pragma no_inline(bge_chip_poke_nic) 4974 4975 static void 4976 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4977 { 4978 uint64_t regoff; 4979 uint64_t regval; 4980 void *regaddr; 4981 4982 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4983 (void *)bgep, (void *)ppd)); 4984 4985 regoff = ppd->pp_acc_offset; 4986 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4987 regoff &= MWBAR_GRANULE_MASK; 4988 regoff += NIC_MEM_WINDOW_OFFSET; 4989 regaddr = PIO_ADDR(bgep, regoff); 4990 regval = ppd->pp_acc_data; 4991 4992 switch (ppd->pp_acc_size) { 4993 case 1: 4994 ddi_put8(bgep->io_handle, regaddr, regval); 4995 break; 4996 4997 case 2: 4998 ddi_put16(bgep->io_handle, regaddr, regval); 4999 break; 5000 5001 case 4: 5002 ddi_put32(bgep->io_handle, regaddr, regval); 5003 break; 5004 5005 case 8: 5006 ddi_put64(bgep->io_handle, regaddr, regval); 5007 break; 5008 } 5009 BGE_PCICHK(bgep); 5010 } 5011 5012 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5013 #pragma no_inline(bge_chip_peek_mii) 5014 5015 static void 5016 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5017 { 5018 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 5019 (void *)bgep, (void *)ppd)); 5020 5021 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 5022 } 5023 5024 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 5025 #pragma no_inline(bge_chip_poke_mii) 5026 5027 static void 5028 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 5029 { 5030 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 5031 (void *)bgep, (void *)ppd)); 5032 5033 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 5034 } 5035 5036 #if BGE_SEE_IO32 5037 5038 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5039 #pragma no_inline(bge_chip_peek_seeprom) 5040 5041 static void 5042 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5043 { 5044 uint32_t data; 5045 int err; 5046 5047 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 5048 (void *)bgep, (void *)ppd)); 5049 5050 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 5051 ppd->pp_acc_data = err ? ~0ull : data; 5052 } 5053 5054 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 5055 #pragma no_inline(bge_chip_poke_seeprom) 5056 5057 static void 5058 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 5059 { 5060 uint32_t data; 5061 5062 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 5063 (void *)bgep, (void *)ppd)); 5064 5065 data = ppd->pp_acc_data; 5066 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 5067 } 5068 #endif /* BGE_SEE_IO32 */ 5069 5070 #if BGE_FLASH_IO32 5071 5072 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5073 #pragma no_inline(bge_chip_peek_flash) 5074 5075 static void 5076 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5077 { 5078 uint32_t data; 5079 int err; 5080 5081 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 5082 (void *)bgep, (void *)ppd)); 5083 5084 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 5085 ppd->pp_acc_data = err ? ~0ull : data; 5086 } 5087 5088 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 5089 #pragma no_inline(bge_chip_poke_flash) 5090 5091 static void 5092 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 5093 { 5094 uint32_t data; 5095 5096 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 5097 (void *)bgep, (void *)ppd)); 5098 5099 data = ppd->pp_acc_data; 5100 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 5101 ppd->pp_acc_offset, &data); 5102 } 5103 #endif /* BGE_FLASH_IO32 */ 5104 5105 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5106 #pragma no_inline(bge_chip_peek_mem) 5107 5108 static void 5109 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5110 { 5111 uint64_t regval; 5112 void *vaddr; 5113 5114 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 5115 (void *)bgep, (void *)ppd)); 5116 5117 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5118 5119 switch (ppd->pp_acc_size) { 5120 case 1: 5121 regval = *(uint8_t *)vaddr; 5122 break; 5123 5124 case 2: 5125 regval = *(uint16_t *)vaddr; 5126 break; 5127 5128 case 4: 5129 regval = *(uint32_t *)vaddr; 5130 break; 5131 5132 case 8: 5133 regval = *(uint64_t *)vaddr; 5134 break; 5135 } 5136 5137 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 5138 (void *)bgep, (void *)ppd, regval, vaddr)); 5139 5140 ppd->pp_acc_data = regval; 5141 } 5142 5143 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 5144 #pragma no_inline(bge_chip_poke_mem) 5145 5146 static void 5147 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 5148 { 5149 uint64_t regval; 5150 void *vaddr; 5151 5152 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 5153 (void *)bgep, (void *)ppd)); 5154 5155 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 5156 regval = ppd->pp_acc_data; 5157 5158 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 5159 (void *)bgep, (void *)ppd, regval, vaddr)); 5160 5161 switch (ppd->pp_acc_size) { 5162 case 1: 5163 *(uint8_t *)vaddr = (uint8_t)regval; 5164 break; 5165 5166 case 2: 5167 *(uint16_t *)vaddr = (uint16_t)regval; 5168 break; 5169 5170 case 4: 5171 *(uint32_t *)vaddr = (uint32_t)regval; 5172 break; 5173 5174 case 8: 5175 *(uint64_t *)vaddr = (uint64_t)regval; 5176 break; 5177 } 5178 } 5179 5180 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5181 struct iocblk *iocp); 5182 #pragma no_inline(bge_pp_ioctl) 5183 5184 static enum ioc_reply 5185 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5186 { 5187 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 5188 bge_peekpoke_t *ppd; 5189 dma_area_t *areap; 5190 uint64_t sizemask; 5191 uint64_t mem_va; 5192 uint64_t maxoff; 5193 boolean_t peek; 5194 5195 switch (cmd) { 5196 default: 5197 /* NOTREACHED */ 5198 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 5199 return (IOC_INVAL); 5200 5201 case BGE_PEEK: 5202 peek = B_TRUE; 5203 break; 5204 5205 case BGE_POKE: 5206 peek = B_FALSE; 5207 break; 5208 } 5209 5210 /* 5211 * Validate format of ioctl 5212 */ 5213 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 5214 return (IOC_INVAL); 5215 if (mp->b_cont == NULL) 5216 return (IOC_INVAL); 5217 ppd = (void *)mp->b_cont->b_rptr; 5218 5219 /* 5220 * Validate request parameters 5221 */ 5222 switch (ppd->pp_acc_space) { 5223 default: 5224 return (IOC_INVAL); 5225 5226 case BGE_PP_SPACE_CFG: 5227 /* 5228 * Config space 5229 */ 5230 sizemask = 8|4|2|1; 5231 mem_va = 0; 5232 maxoff = PCI_CONF_HDR_SIZE; 5233 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 5234 break; 5235 5236 case BGE_PP_SPACE_REG: 5237 /* 5238 * Memory-mapped I/O space 5239 */ 5240 sizemask = 8|4|2|1; 5241 mem_va = 0; 5242 maxoff = RIAAR_REGISTER_MAX; 5243 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5244 break; 5245 5246 case BGE_PP_SPACE_NIC: 5247 /* 5248 * NIC on-chip memory 5249 */ 5250 sizemask = 8|4|2|1; 5251 mem_va = 0; 5252 maxoff = MWBAR_ONCHIP_MAX; 5253 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5254 break; 5255 5256 case BGE_PP_SPACE_MII: 5257 /* 5258 * PHY's MII registers 5259 * NB: all PHY registers are two bytes, but the 5260 * addresses increment in ones (word addressing). 5261 * So we scale the address here, then undo the 5262 * transformation inside the peek/poke functions. 5263 */ 5264 ppd->pp_acc_offset *= 2; 5265 sizemask = 2; 5266 mem_va = 0; 5267 maxoff = (MII_MAXREG+1)*2; 5268 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5269 break; 5270 5271 #if BGE_SEE_IO32 5272 case BGE_PP_SPACE_SEEPROM: 5273 /* 5274 * Attached SEEPROM(s), if any. 5275 * NB: we use the high-order bits of the 'address' as 5276 * a device select to accommodate multiple SEEPROMS, 5277 * If each one is the maximum size (64kbytes), this 5278 * makes them appear contiguous. Otherwise, there may 5279 * be holes in the mapping. ENxS doesn't have any 5280 * SEEPROMs anyway ... 5281 */ 5282 sizemask = 4; 5283 mem_va = 0; 5284 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5285 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5286 break; 5287 #endif /* BGE_SEE_IO32 */ 5288 5289 #if BGE_FLASH_IO32 5290 case BGE_PP_SPACE_FLASH: 5291 /* 5292 * Attached Flash device (if any); a maximum of one device 5293 * is currently supported. But it can be up to 1MB (unlike 5294 * the 64k limit on SEEPROMs) so why would you need more ;-) 5295 */ 5296 sizemask = 4; 5297 mem_va = 0; 5298 maxoff = NVM_FLASH_ADDR_MASK; 5299 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5300 break; 5301 #endif /* BGE_FLASH_IO32 */ 5302 5303 case BGE_PP_SPACE_BGE: 5304 /* 5305 * BGE data structure! 5306 */ 5307 sizemask = 8|4|2|1; 5308 mem_va = (uintptr_t)bgep; 5309 maxoff = sizeof (*bgep); 5310 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5311 break; 5312 5313 case BGE_PP_SPACE_STATUS: 5314 case BGE_PP_SPACE_STATISTICS: 5315 case BGE_PP_SPACE_TXDESC: 5316 case BGE_PP_SPACE_TXBUFF: 5317 case BGE_PP_SPACE_RXDESC: 5318 case BGE_PP_SPACE_RXBUFF: 5319 /* 5320 * Various DMA_AREAs 5321 */ 5322 switch (ppd->pp_acc_space) { 5323 case BGE_PP_SPACE_TXDESC: 5324 areap = &bgep->tx_desc; 5325 break; 5326 case BGE_PP_SPACE_TXBUFF: 5327 areap = &bgep->tx_buff[0]; 5328 break; 5329 case BGE_PP_SPACE_RXDESC: 5330 areap = &bgep->rx_desc[0]; 5331 break; 5332 case BGE_PP_SPACE_RXBUFF: 5333 areap = &bgep->rx_buff[0]; 5334 break; 5335 case BGE_PP_SPACE_STATUS: 5336 areap = &bgep->status_block; 5337 break; 5338 case BGE_PP_SPACE_STATISTICS: 5339 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5340 areap = &bgep->statistics; 5341 break; 5342 } 5343 5344 sizemask = 8|4|2|1; 5345 mem_va = (uintptr_t)areap->mem_va; 5346 maxoff = areap->alength; 5347 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5348 break; 5349 } 5350 5351 switch (ppd->pp_acc_size) { 5352 default: 5353 return (IOC_INVAL); 5354 5355 case 8: 5356 case 4: 5357 case 2: 5358 case 1: 5359 if ((ppd->pp_acc_size & sizemask) == 0) 5360 return (IOC_INVAL); 5361 break; 5362 } 5363 5364 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5365 return (IOC_INVAL); 5366 5367 if (ppd->pp_acc_offset >= maxoff) 5368 return (IOC_INVAL); 5369 5370 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5371 return (IOC_INVAL); 5372 5373 /* 5374 * All OK - go do it! 5375 */ 5376 ppd->pp_acc_offset += mem_va; 5377 (*ppfn)(bgep, ppd); 5378 return (peek ? IOC_REPLY : IOC_ACK); 5379 } 5380 5381 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5382 struct iocblk *iocp); 5383 #pragma no_inline(bge_diag_ioctl) 5384 5385 static enum ioc_reply 5386 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5387 { 5388 ASSERT(mutex_owned(bgep->genlock)); 5389 5390 switch (cmd) { 5391 default: 5392 /* NOTREACHED */ 5393 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5394 return (IOC_INVAL); 5395 5396 case BGE_DIAG: 5397 /* 5398 * Currently a no-op 5399 */ 5400 return (IOC_ACK); 5401 5402 case BGE_PEEK: 5403 case BGE_POKE: 5404 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5405 5406 case BGE_PHY_RESET: 5407 return (IOC_RESTART_ACK); 5408 5409 case BGE_SOFT_RESET: 5410 case BGE_HARD_RESET: 5411 /* 5412 * Reset and reinitialise the 570x hardware 5413 */ 5414 bgep->bge_chip_state = BGE_CHIP_FAULT; 5415 ddi_trigger_softintr(bgep->factotum_id); 5416 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5417 return (IOC_ACK); 5418 } 5419 5420 /* NOTREACHED */ 5421 } 5422 5423 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5424 5425 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5426 struct iocblk *iocp); 5427 #pragma no_inline(bge_mii_ioctl) 5428 5429 static enum ioc_reply 5430 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5431 { 5432 struct bge_mii_rw *miirwp; 5433 5434 /* 5435 * Validate format of ioctl 5436 */ 5437 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5438 return (IOC_INVAL); 5439 if (mp->b_cont == NULL) 5440 return (IOC_INVAL); 5441 miirwp = (void *)mp->b_cont->b_rptr; 5442 5443 /* 5444 * Validate request parameters ... 5445 */ 5446 if (miirwp->mii_reg > MII_MAXREG) 5447 return (IOC_INVAL); 5448 5449 switch (cmd) { 5450 default: 5451 /* NOTREACHED */ 5452 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5453 return (IOC_INVAL); 5454 5455 case BGE_MII_READ: 5456 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5457 return (IOC_REPLY); 5458 5459 case BGE_MII_WRITE: 5460 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5461 return (IOC_ACK); 5462 } 5463 5464 /* NOTREACHED */ 5465 } 5466 5467 #if BGE_SEE_IO32 5468 5469 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5470 struct iocblk *iocp); 5471 #pragma no_inline(bge_see_ioctl) 5472 5473 static enum ioc_reply 5474 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5475 { 5476 struct bge_see_rw *seerwp; 5477 5478 /* 5479 * Validate format of ioctl 5480 */ 5481 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5482 return (IOC_INVAL); 5483 if (mp->b_cont == NULL) 5484 return (IOC_INVAL); 5485 seerwp = (void *)mp->b_cont->b_rptr; 5486 5487 /* 5488 * Validate request parameters ... 5489 */ 5490 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5491 return (IOC_INVAL); 5492 5493 switch (cmd) { 5494 default: 5495 /* NOTREACHED */ 5496 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5497 return (IOC_INVAL); 5498 5499 case BGE_SEE_READ: 5500 case BGE_SEE_WRITE: 5501 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5502 seerwp->see_addr, &seerwp->see_data); 5503 return (IOC_REPLY); 5504 } 5505 5506 /* NOTREACHED */ 5507 } 5508 5509 #endif /* BGE_SEE_IO32 */ 5510 5511 #if BGE_FLASH_IO32 5512 5513 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5514 struct iocblk *iocp); 5515 #pragma no_inline(bge_flash_ioctl) 5516 5517 static enum ioc_reply 5518 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5519 { 5520 struct bge_flash_rw *flashrwp; 5521 5522 /* 5523 * Validate format of ioctl 5524 */ 5525 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5526 return (IOC_INVAL); 5527 if (mp->b_cont == NULL) 5528 return (IOC_INVAL); 5529 flashrwp = (void *)mp->b_cont->b_rptr; 5530 5531 /* 5532 * Validate request parameters ... 5533 */ 5534 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5535 return (IOC_INVAL); 5536 5537 switch (cmd) { 5538 default: 5539 /* NOTREACHED */ 5540 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5541 return (IOC_INVAL); 5542 5543 case BGE_FLASH_READ: 5544 case BGE_FLASH_WRITE: 5545 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5546 flashrwp->flash_addr, &flashrwp->flash_data); 5547 return (IOC_REPLY); 5548 } 5549 5550 /* NOTREACHED */ 5551 } 5552 5553 #endif /* BGE_FLASH_IO32 */ 5554 5555 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5556 struct iocblk *iocp); 5557 #pragma no_inline(bge_chip_ioctl) 5558 5559 enum ioc_reply 5560 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5561 { 5562 int cmd; 5563 5564 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5565 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5566 5567 ASSERT(mutex_owned(bgep->genlock)); 5568 5569 cmd = iocp->ioc_cmd; 5570 switch (cmd) { 5571 default: 5572 /* NOTREACHED */ 5573 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5574 return (IOC_INVAL); 5575 5576 case BGE_DIAG: 5577 case BGE_PEEK: 5578 case BGE_POKE: 5579 case BGE_PHY_RESET: 5580 case BGE_SOFT_RESET: 5581 case BGE_HARD_RESET: 5582 #if BGE_DEBUGGING || BGE_DO_PPIO 5583 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5584 #else 5585 return (IOC_INVAL); 5586 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5587 5588 case BGE_MII_READ: 5589 case BGE_MII_WRITE: 5590 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5591 5592 #if BGE_SEE_IO32 5593 case BGE_SEE_READ: 5594 case BGE_SEE_WRITE: 5595 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5596 #endif /* BGE_SEE_IO32 */ 5597 5598 #if BGE_FLASH_IO32 5599 case BGE_FLASH_READ: 5600 case BGE_FLASH_WRITE: 5601 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5602 #endif /* BGE_FLASH_IO32 */ 5603 } 5604 5605 /* NOTREACHED */ 5606 } 5607 5608 /* ARGSUSED */ 5609 void 5610 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 5611 { 5612 recv_ring_t *rrp = arg; 5613 bge_t *bgep = rrp->bgep; 5614 5615 mutex_enter(bgep->genlock); 5616 rrp->poll_flag = flag; 5617 #ifdef NOT_YET 5618 /* 5619 * XXX-Sunay: Since most broadcom cards support only one 5620 * interrupt but multiple rx rings, we can't disable the 5621 * physical interrupt. This need to be done via capability 5622 * negotiation depending on the NIC. 5623 */ 5624 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5625 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5626 #endif 5627 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5628 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5629 mutex_exit(bgep->genlock); 5630 } 5631 5632 #ifdef BGE_IPMI_ASF 5633 5634 uint32_t 5635 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5636 { 5637 uint32_t data; 5638 5639 #ifndef __sparc 5640 if (!bgep->asf_wordswapped) { 5641 /* a workaround word swap error */ 5642 if (addr & 4) 5643 addr = addr - 4; 5644 else 5645 addr = addr + 4; 5646 } 5647 #endif 5648 5649 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5650 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5651 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5652 5653 data = LE_32(data); 5654 return (data); 5655 } 5656 5657 void 5658 bge_asf_update_status(bge_t *bgep) 5659 { 5660 uint32_t event; 5661 5662 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5663 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5664 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5665 5666 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5667 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5668 } 5669 5670 5671 /* 5672 * The driver is supposed to notify ASF that the OS is still running 5673 * every three seconds, otherwise the management server may attempt 5674 * to reboot the machine. If it hasn't actually failed, this is 5675 * not a desirable result. However, this isn't running as a real-time 5676 * thread, and even if it were, it might not be able to generate the 5677 * heartbeat in a timely manner due to system load. As it isn't a 5678 * significant strain on the machine, we will set the interval to half 5679 * of the required value. 5680 */ 5681 void 5682 bge_asf_heartbeat(void *arg) 5683 { 5684 bge_t *bgep = (bge_t *)arg; 5685 5686 mutex_enter(bgep->genlock); 5687 bge_asf_update_status((bge_t *)bgep); 5688 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5689 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5690 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5691 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5692 mutex_exit(bgep->genlock); 5693 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5694 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5695 } 5696 5697 5698 void 5699 bge_asf_stop_timer(bge_t *bgep) 5700 { 5701 timeout_id_t tmp_id = 0; 5702 5703 while ((bgep->asf_timeout_id != 0) && 5704 (tmp_id != bgep->asf_timeout_id)) { 5705 tmp_id = bgep->asf_timeout_id; 5706 (void) untimeout(tmp_id); 5707 } 5708 bgep->asf_timeout_id = 0; 5709 } 5710 5711 5712 5713 /* 5714 * This function should be placed at the earliest position of bge_attach(). 5715 */ 5716 void 5717 bge_asf_get_config(bge_t *bgep) 5718 { 5719 uint32_t nicsig; 5720 uint32_t niccfg; 5721 5722 bgep->asf_enabled = B_FALSE; 5723 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5724 if (nicsig == BGE_NIC_DATA_SIG) { 5725 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5726 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5727 /* 5728 * Here, we don't consider BAXTER, because BGE haven't 5729 * supported BAXTER (that is 5752). Also, as I know, 5730 * BAXTER doesn't support ASF feature. 5731 */ 5732 bgep->asf_enabled = B_TRUE; 5733 else 5734 bgep->asf_enabled = B_FALSE; 5735 } else 5736 bgep->asf_enabled = B_FALSE; 5737 } 5738 5739 5740 void 5741 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5742 { 5743 uint32_t tries; 5744 uint32_t event; 5745 5746 ASSERT(bgep->asf_enabled); 5747 5748 /* Issues "pause firmware" command and wait for ACK */ 5749 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5750 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5751 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5752 5753 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5754 tries = 0; 5755 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5756 drv_usecwait(1); 5757 tries ++; 5758 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5759 } 5760 5761 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5762 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5763 5764 if (bgep->asf_newhandshake) { 5765 switch (mode) { 5766 case BGE_INIT_RESET: 5767 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5768 BGE_DRV_STATE_START); 5769 break; 5770 case BGE_SHUTDOWN_RESET: 5771 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5772 BGE_DRV_STATE_UNLOAD); 5773 break; 5774 case BGE_SUSPEND_RESET: 5775 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5776 BGE_DRV_STATE_SUSPEND); 5777 break; 5778 default: 5779 break; 5780 } 5781 } 5782 } 5783 5784 5785 void 5786 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5787 { 5788 switch (mode) { 5789 case BGE_INIT_RESET: 5790 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5791 BGE_DRV_STATE_START); 5792 break; 5793 case BGE_SHUTDOWN_RESET: 5794 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5795 BGE_DRV_STATE_UNLOAD); 5796 break; 5797 case BGE_SUSPEND_RESET: 5798 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5799 BGE_DRV_STATE_SUSPEND); 5800 break; 5801 default: 5802 break; 5803 } 5804 } 5805 5806 5807 void 5808 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5809 { 5810 switch (mode) { 5811 case BGE_INIT_RESET: 5812 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5813 BGE_DRV_STATE_START_DONE); 5814 break; 5815 case BGE_SHUTDOWN_RESET: 5816 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5817 BGE_DRV_STATE_UNLOAD_DONE); 5818 break; 5819 default: 5820 break; 5821 } 5822 } 5823 5824 #endif /* BGE_IPMI_ASF */ 5825