1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include "bge_impl.h" 28 29 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 30 31 /* 32 * Future features ... ? 33 */ 34 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 35 #define BGE_IND_IO32 1 /* indirect access code */ 36 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 37 #define BGE_FLASH_IO32 1 /* FLASH access code */ 38 39 /* 40 * BGE MSI tunable: 41 * 42 * By default MSI is enabled on all supported platforms but it is disabled 43 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 44 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 45 */ 46 boolean_t bge_enable_msi = B_TRUE; 47 48 /* 49 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 50 */ 51 boolean_t bge_relaxed_ordering = B_TRUE; 52 53 /* 54 * Property names 55 */ 56 static char knownids_propname[] = "bge-known-subsystems"; 57 58 /* 59 * Patchable globals: 60 * 61 * bge_autorecover 62 * Enables/disables automatic recovery after fault detection 63 * 64 * bge_mlcr_default 65 * Value to program into the MLCR; controls the chip's GPIO pins 66 * 67 * bge_dma_{rd,wr}prio 68 * Relative priorities of DMA reads & DMA writes respectively. 69 * These may each be patched to any value 0-3. Equal values 70 * will give "fair" (round-robin) arbitration for PCI access. 71 * Unequal values will give one or the other function priority. 72 * 73 * bge_dma_rwctrl 74 * Value to put in the Read/Write DMA control register. See 75 * the Broadcom PRM for things you can fiddle with in this 76 * register ... 77 * 78 * bge_{tx,rx}_{count,ticks}_{norm,intr} 79 * Send/receive interrupt coalescing parameters. Counts are 80 * #s of descriptors, ticks are in microseconds. *norm* values 81 * apply between status updates/interrupts; the *intr* values 82 * refer to the 'during-interrupt' versions - see the PRM. 83 * 84 * NOTE: these values have been determined by measurement. They 85 * differ significantly from the values recommended in the PRM. 86 */ 87 static uint32_t bge_autorecover = 1; 88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 89 90 static uint32_t bge_dma_rdprio = 1; 91 static uint32_t bge_dma_wrprio = 0; 92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 96 97 uint32_t bge_rx_ticks_norm = 128; 98 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 99 uint32_t bge_rx_count_norm = 8; 100 uint32_t bge_tx_count_norm = 128; 101 102 static uint32_t bge_rx_ticks_intr = 128; 103 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 104 static uint32_t bge_rx_count_intr = 2; 105 static uint32_t bge_tx_count_intr = 0; 106 107 /* 108 * Memory pool configuration parameters. 109 * 110 * These are generally specific to each member of the chip family, since 111 * each one may have a different memory size/configuration. 112 * 113 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 114 * the driver from programming the various registers; instead they are left 115 * at their hardware defaults. This is the preferred option for later chips 116 * (5705+), whereas the older chips *required* these registers to be set, 117 * since the h/w default was 0 ;-( 118 */ 119 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 120 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 121 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 123 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 124 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 125 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 126 static uint32_t bge_mbuf_pool_len_5721 = 0; 127 128 /* 129 * Various high and low water marks, thresholds, etc ... 130 * 131 * Note: these are taken from revision 7 of the PRM, and some are different 132 * from both the values in earlier PRMs *and* those determined experimentally 133 * and used in earlier versions of this driver ... 134 */ 135 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 136 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 137 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 138 139 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 140 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 141 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 142 143 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 144 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 145 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 146 147 static uint32_t bge_watchdog_count = 1 << 16; 148 static uint16_t bge_dma_miss_limit = 20; 149 150 static uint32_t bge_stop_start_on_sync = 0; 151 152 boolean_t bge_jumbo_enable = B_TRUE; 153 154 /* 155 * bge_intr_max_loop controls the maximum loop number within bge_intr. 156 * When loading NIC with heavy network traffic, it is useful. 157 * Increasing this value could have positive effect to throughput, 158 * but it might also increase ticks of a bge ISR stick on CPU, which might 159 * lead to bad UI interactive experience. So tune this with caution. 160 */ 161 static int bge_intr_max_loop = 1; 162 163 /* 164 * ========== Low-level chip & ring buffer manipulation ========== 165 */ 166 167 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 168 169 170 /* 171 * Config space read-modify-write routines 172 */ 173 174 #if BGE_CFG_IO8 175 176 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 177 #pragma inline(bge_cfg_clr16) 178 179 static void 180 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 181 { 182 uint16_t regval; 183 184 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 185 (void *)bgep, regno, bits)); 186 187 regval = pci_config_get16(bgep->cfg_handle, regno); 188 189 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 190 (void *)bgep, regno, bits, regval, regval & ~bits)); 191 192 regval &= ~bits; 193 pci_config_put16(bgep->cfg_handle, regno, regval); 194 } 195 196 #endif /* BGE_CFG_IO8 */ 197 198 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 199 #pragma inline(bge_cfg_clr32) 200 201 static void 202 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 203 { 204 uint32_t regval; 205 206 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 207 (void *)bgep, regno, bits)); 208 209 regval = pci_config_get32(bgep->cfg_handle, regno); 210 211 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 212 (void *)bgep, regno, bits, regval, regval & ~bits)); 213 214 regval &= ~bits; 215 pci_config_put32(bgep->cfg_handle, regno, regval); 216 } 217 218 #if BGE_IND_IO32 219 220 /* 221 * Indirect access to registers & RISC scratchpads, using config space 222 * accesses only. 223 * 224 * This isn't currently used, but someday we might want to use it for 225 * restoring the Subsystem Device/Vendor registers (which aren't directly 226 * writable in Config Space), or for downloading firmware into the RISCs 227 * 228 * In any case there are endian issues to be resolved before this code is 229 * enabled; the bizarre way that bytes get twisted by this chip AND by 230 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 231 * it's been thoroughly tested for all access sizes on all supported 232 * architectures (SPARC *and* x86!). 233 */ 234 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 235 #pragma inline(bge_ind_get32) 236 237 uint32_t 238 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 239 { 240 uint32_t val; 241 242 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 243 244 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 245 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 246 247 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 248 (void *)bgep, regno, val)); 249 250 val = LE_32(val); 251 252 return (val); 253 } 254 255 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 256 #pragma inline(bge_ind_put32) 257 258 void 259 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 260 { 261 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 262 (void *)bgep, regno, val)); 263 264 val = LE_32(val); 265 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 266 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 267 } 268 269 #endif /* BGE_IND_IO32 */ 270 271 #if BGE_DEBUGGING 272 273 static void bge_pci_check(bge_t *bgep); 274 #pragma no_inline(bge_pci_check) 275 276 static void 277 bge_pci_check(bge_t *bgep) 278 { 279 uint16_t pcistatus; 280 281 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 282 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 283 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 284 (void *)bgep, pcistatus)); 285 } 286 287 #endif /* BGE_DEBUGGING */ 288 289 /* 290 * Perform first-stage chip (re-)initialisation, using only config-space 291 * accesses: 292 * 293 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 294 * returning the data in the structure pointed to by <idp>. 295 * + Configure the target-mode endianness (swap) options. 296 * + Disable interrupts and enable Memory Space accesses. 297 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 298 * 299 * This sequence is adapted from Broadcom document 570X-PG102-R, 300 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 301 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 302 * 303 * This function MUST be called before any non-config-space accesses 304 * are made; on this first call <enable_dma> is B_FALSE, and it 305 * effectively performs steps 3-1(!) of the initialisation sequence 306 * (the rest are not required but should be harmless). 307 * 308 * It MUST also be called after a chip reset, as this disables 309 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 310 * it is effectively performing steps 6-8. 311 */ 312 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 313 #pragma no_inline(bge_chip_cfg_init) 314 315 void 316 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 317 { 318 ddi_acc_handle_t handle; 319 uint16_t command; 320 uint32_t mhcr; 321 uint16_t value16; 322 int i; 323 324 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 325 (void *)bgep, (void *)cidp, enable_dma)); 326 327 /* 328 * Step 3: save PCI cache line size and subsystem vendor ID 329 * 330 * Read all the config-space registers that characterise the 331 * chip, specifically vendor/device/revision/subsystem vendor 332 * and subsystem device id. We expect (but don't check) that 333 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 334 * 335 * Also save all bus-transaction related registers (cache-line 336 * size, bus-grant/latency parameters, etc). Some of these are 337 * cleared by reset, so we'll have to restore them later. This 338 * comes from the Broadcom document 570X-PG102-R ... 339 * 340 * Note: Broadcom document 570X-PG102-R seems to be in error 341 * here w.r.t. the offsets of the Subsystem Vendor ID and 342 * Subsystem (Device) ID registers, which are the opposite way 343 * round according to the PCI standard. For good measure, we 344 * save/restore both anyway. 345 */ 346 handle = bgep->cfg_handle; 347 348 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 349 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 350 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 351 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 352 353 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 354 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 355 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 356 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 357 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 358 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 359 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 360 361 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 362 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 363 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 364 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 365 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 366 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 367 cidp->vendor, cidp->device, cidp->revision)); 368 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 369 cidp->subven, cidp->subdev, cidp->asic_rev)); 370 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 371 cidp->clsize, cidp->latency, cidp->command)); 372 373 /* 374 * Step 2 (also step 6): disable and clear interrupts. 375 * Steps 11-13: configure PIO endianness options, and enable 376 * indirect register access. We'll also select any other 377 * options controlled by the MHCR (e.g. tagged status, mask 378 * interrupt mode) at this stage ... 379 * 380 * Note: internally, the chip is 64-bit and BIG-endian, but 381 * since it talks to the host over a (LITTLE-endian) PCI bus, 382 * it normally swaps bytes around at the PCI interface. 383 * However, the PCI host bridge on SPARC systems normally 384 * swaps the byte lanes around too, since SPARCs are also 385 * BIG-endian. So it turns out that on SPARC, the right 386 * option is to tell the chip to swap (and the host bridge 387 * will swap back again), whereas on x86 we ask the chip 388 * NOT to swap, so the natural little-endianness of the 389 * PCI bus is assumed. Then the only thing that doesn't 390 * automatically work right is access to an 8-byte register 391 * by a little-endian host; but we don't want to set the 392 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 393 * accesses don't go where expected ;-( So we live with 394 * that, and perform word-swaps in software in the few cases 395 * where a chip register is defined as an 8-byte value -- 396 * see the code below for details ... 397 * 398 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 399 * very clear in the register description in the PRM, but 400 * Broadcom document 570X-PG104-R page 248 explains a little 401 * more (under "Broadcom Mask Mode"). The bit changes the way 402 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 403 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 404 * way as the 5700 did, which isn't very convenient. Setting 405 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 406 * bit do just what its name says -- MASK the PCI #INTA output 407 * (i.e. deassert the signal at the pin) leaving all internal 408 * state unchanged. This is much more convenient for our 409 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 410 * 411 * Note: the inconvenient semantics of the interrupt mailbox 412 * (nonzero disables and acknowledges/clears the interrupt, 413 * zero enables AND CLEARS it) would make race conditions 414 * likely in the interrupt handler: 415 * 416 * (1) acknowledge & disable interrupts 417 * (2) while (more to do) 418 * process packets 419 * (3) enable interrupts -- also clears pending 420 * 421 * If the chip received more packets and internally generated 422 * an interrupt between the check at (2) and the mbox write 423 * at (3), this interrupt would be lost :-( 424 * 425 * The best way to avoid this is to use TAGGED STATUS mode, 426 * where the chip includes a unique tag in each status block 427 * update, and the host, when re-enabling interrupts, passes 428 * the last tag it saw back to the chip; then the chip can 429 * see whether the host is truly up to date, and regenerate 430 * its interrupt if not. 431 */ 432 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 433 MHCR_ENABLE_TAGGED_STATUS_MODE | 434 MHCR_MASK_INTERRUPT_MODE | 435 MHCR_CLEAR_INTERRUPT_INTA; 436 437 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 438 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 439 440 #ifdef _BIG_ENDIAN 441 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 442 #endif /* _BIG_ENDIAN */ 443 444 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 445 446 #ifdef BGE_IPMI_ASF 447 bgep->asf_wordswapped = B_FALSE; 448 #endif 449 /* 450 * Step 1 (also step 7): Enable PCI Memory Space accesses 451 * Disable Memory Write/Invalidate 452 * Enable or disable Bus Mastering 453 * 454 * Note that all other bits are taken from the original value saved 455 * the first time through here, rather than from the current register 456 * value, 'cos that will have been cleared by a soft RESET since. 457 * In this way we preserve the OBP/nexus-parent's preferred settings 458 * of the parity-error and system-error enable bits across multiple 459 * chip RESETs. 460 */ 461 command = bgep->chipid.command | PCI_COMM_MAE; 462 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 463 if (enable_dma) 464 command |= PCI_COMM_ME; 465 /* 466 * on BCM5714 revision A0, false parity error gets generated 467 * due to a logic bug. Provide a workaround by disabling parity 468 * error. 469 */ 470 if (((cidp->device == DEVICE_ID_5714C) || 471 (cidp->device == DEVICE_ID_5714S)) && 472 (cidp->revision == REVISION_ID_5714_A0)) { 473 command &= ~PCI_COMM_PARITY_DETECT; 474 } 475 pci_config_put16(handle, PCI_CONF_COMM, command); 476 477 /* 478 * On some PCI-E device, there were instances when 479 * the device was still link training. 480 */ 481 if (bgep->chipid.pci_type == BGE_PCI_E) { 482 i = 0; 483 value16 = pci_config_get16(handle, PCI_CONF_COMM); 484 while ((value16 != command) && (i < 100)) { 485 drv_usecwait(200); 486 value16 = pci_config_get16(handle, PCI_CONF_COMM); 487 ++i; 488 } 489 } 490 491 /* 492 * Clear any remaining error status bits 493 */ 494 pci_config_put16(handle, PCI_CONF_STAT, ~0); 495 496 /* 497 * Do following if and only if the device is NOT BCM5714C OR 498 * BCM5715C 499 */ 500 if (!((cidp->device == DEVICE_ID_5714C) || 501 (cidp->device == DEVICE_ID_5715C))) { 502 /* 503 * Make sure these indirect-access registers are sane 504 * rather than random after power-up or reset 505 */ 506 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 507 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 508 } 509 /* 510 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 511 */ 512 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 513 514 if (cidp->pci_type == BGE_PCI_E) 515 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 516 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 517 } 518 519 #ifdef __amd64 520 /* 521 * Distinguish CPU types 522 * 523 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 524 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 525 * for PCI-Express based network interface card. This is the work-around 526 * for those nics. 527 */ 528 static boolean_t bge_get_em64t_type(void); 529 #pragma inline(bge_get_em64t_type) 530 531 static boolean_t 532 bge_get_em64t_type(void) 533 { 534 535 return (x86_vendor == X86_VENDOR_Intel); 536 } 537 #endif 538 539 /* 540 * Operating register get/set access routines 541 */ 542 543 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 544 #pragma inline(bge_reg_get32) 545 546 uint32_t 547 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 548 { 549 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 550 (void *)bgep, regno)); 551 552 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 553 } 554 555 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 556 #pragma inline(bge_reg_put32) 557 558 void 559 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 560 { 561 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 562 (void *)bgep, regno, data)); 563 564 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 565 BGE_PCICHK(bgep); 566 } 567 568 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 569 #pragma inline(bge_reg_set32) 570 571 void 572 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 573 { 574 uint32_t regval; 575 576 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 577 (void *)bgep, regno, bits)); 578 579 regval = bge_reg_get32(bgep, regno); 580 regval |= bits; 581 bge_reg_put32(bgep, regno, regval); 582 } 583 584 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 585 #pragma inline(bge_reg_clr32) 586 587 void 588 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 589 { 590 uint32_t regval; 591 592 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 593 (void *)bgep, regno, bits)); 594 595 regval = bge_reg_get32(bgep, regno); 596 regval &= ~bits; 597 bge_reg_put32(bgep, regno, regval); 598 } 599 600 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 601 #pragma inline(bge_reg_get64) 602 603 static uint64_t 604 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 605 { 606 uint64_t regval; 607 608 #ifdef __amd64 609 if (bge_get_em64t_type()) { 610 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 611 regval <<= 32; 612 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 613 } else { 614 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 615 } 616 #else 617 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 618 #endif 619 620 #ifdef _LITTLE_ENDIAN 621 regval = (regval >> 32) | (regval << 32); 622 #endif /* _LITTLE_ENDIAN */ 623 624 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 625 (void *)bgep, regno, regval)); 626 627 return (regval); 628 } 629 630 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 631 #pragma inline(bge_reg_put64) 632 633 static void 634 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 635 { 636 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 637 (void *)bgep, regno, data)); 638 639 #ifdef _LITTLE_ENDIAN 640 data = ((data >> 32) | (data << 32)); 641 #endif /* _LITTLE_ENDIAN */ 642 643 #ifdef __amd64 644 if (bge_get_em64t_type()) { 645 ddi_put32(bgep->io_handle, 646 PIO_ADDR(bgep, regno), (uint32_t)data); 647 BGE_PCICHK(bgep); 648 ddi_put32(bgep->io_handle, 649 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 650 651 } else { 652 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 653 } 654 #else 655 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 656 #endif 657 658 BGE_PCICHK(bgep); 659 } 660 661 /* 662 * The DDI doesn't provide get/put functions for 128 bit data 663 * so we put RCBs out as two 64-bit chunks instead. 664 */ 665 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 666 #pragma inline(bge_reg_putrcb) 667 668 static void 669 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 670 { 671 uint64_t *p; 672 673 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 674 (void *)bgep, addr, rcbp->host_ring_addr, 675 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 676 677 ASSERT((addr % sizeof (*rcbp)) == 0); 678 679 p = (void *)rcbp; 680 bge_reg_put64(bgep, addr, *p++); 681 bge_reg_put64(bgep, addr+8, *p); 682 } 683 684 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 685 #pragma inline(bge_mbx_put) 686 687 void 688 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 689 { 690 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 691 (void *)bgep, regno, data)); 692 693 /* 694 * Mailbox registers are nominally 64 bits on the 5701, but 695 * the MSW isn't used. On the 5703, they're only 32 bits 696 * anyway. So here we just write the lower(!) 32 bits - 697 * remembering that the chip is big-endian, even though the 698 * PCI bus is little-endian ... 699 */ 700 #ifdef _BIG_ENDIAN 701 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 702 #else 703 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 704 #endif /* _BIG_ENDIAN */ 705 BGE_PCICHK(bgep); 706 } 707 708 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno); 709 #pragma inline(bge_mbx_get) 710 711 uint32_t 712 bge_mbx_get(bge_t *bgep, bge_regno_t regno) 713 { 714 uint32_t val32; 715 716 BGE_TRACE(("bge_mbx_get($%p, 0x%lx)", 717 (void *)bgep, regno)); 718 719 #ifdef _BIG_ENDIAN 720 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4)); 721 #else 722 val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 723 #endif /* _BIG_ENDIAN */ 724 BGE_PCICHK(bgep); 725 726 return (val32); 727 } 728 729 730 #if BGE_DEBUGGING 731 732 void bge_led_mark(bge_t *bgep); 733 #pragma no_inline(bge_led_mark) 734 735 void 736 bge_led_mark(bge_t *bgep) 737 { 738 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 739 LED_CONTROL_1000MBPS_LED | 740 LED_CONTROL_100MBPS_LED | 741 LED_CONTROL_10MBPS_LED; 742 743 /* 744 * Blink all three LINK LEDs on simultaneously, then all off, 745 * then restore to automatic hardware control. This is used 746 * in laboratory testing to trigger a logic analyser or scope. 747 */ 748 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 749 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 750 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 751 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 752 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 753 } 754 755 #endif /* BGE_DEBUGGING */ 756 757 /* 758 * NIC on-chip memory access routines 759 * 760 * Only 32K of NIC memory is visible at a time, controlled by the 761 * Memory Window Base Address Register (in PCI config space). Once 762 * this is set, the 32K region of NIC-local memory that it refers 763 * to can be directly addressed in the upper 32K of the 64K of PCI 764 * memory space used for the device. 765 */ 766 767 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 768 #pragma inline(bge_nic_setwin) 769 770 static void 771 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 772 { 773 chip_id_t *cidp; 774 775 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 776 (void *)bgep, base)); 777 778 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 779 780 /* 781 * Don't do repeated zero data writes, 782 * if the device is BCM5714C/15C. 783 */ 784 cidp = &bgep->chipid; 785 if ((cidp->device == DEVICE_ID_5714C) || 786 (cidp->device == DEVICE_ID_5715C)) { 787 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 788 return; 789 /* Adjust lastWriteZeroData */ 790 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 791 B_TRUE : B_FALSE); 792 } 793 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 794 } 795 796 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 797 #pragma inline(bge_nic_get32) 798 799 static uint32_t 800 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 801 { 802 uint32_t data; 803 804 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 805 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 806 /* workaround for word swap error */ 807 if (addr & 4) 808 addr = addr - 4; 809 else 810 addr = addr + 4; 811 } 812 #endif 813 814 #ifdef __sparc 815 data = bge_nic_read32(bgep, addr); 816 #else 817 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 818 addr &= MWBAR_GRANULE_MASK; 819 addr += NIC_MEM_WINDOW_OFFSET; 820 821 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 822 #endif 823 824 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 825 (void *)bgep, addr, data)); 826 827 return (data); 828 } 829 830 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 831 #pragma inline(bge_nic_put32) 832 833 void 834 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 835 { 836 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 837 (void *)bgep, addr, data)); 838 839 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 840 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 841 /* workaround for word swap error */ 842 if (addr & 4) 843 addr = addr - 4; 844 else 845 addr = addr + 4; 846 } 847 #endif 848 849 #ifdef __sparc 850 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 851 data = LE_32(data); 852 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 853 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 854 #else 855 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 856 addr &= MWBAR_GRANULE_MASK; 857 addr += NIC_MEM_WINDOW_OFFSET; 858 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 859 BGE_PCICHK(bgep); 860 #endif 861 } 862 863 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 864 #pragma inline(bge_nic_get64) 865 866 static uint64_t 867 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 868 { 869 uint64_t data; 870 871 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 872 addr &= MWBAR_GRANULE_MASK; 873 addr += NIC_MEM_WINDOW_OFFSET; 874 875 #ifdef __amd64 876 if (bge_get_em64t_type()) { 877 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 878 data <<= 32; 879 data |= ddi_get32(bgep->io_handle, 880 PIO_ADDR(bgep, addr + 4)); 881 } else { 882 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 883 } 884 #else 885 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 886 #endif 887 888 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 889 (void *)bgep, addr, data)); 890 891 return (data); 892 } 893 894 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 895 #pragma inline(bge_nic_put64) 896 897 static void 898 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 899 { 900 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 901 (void *)bgep, addr, data)); 902 903 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 904 addr &= MWBAR_GRANULE_MASK; 905 addr += NIC_MEM_WINDOW_OFFSET; 906 907 #ifdef __amd64 908 if (bge_get_em64t_type()) { 909 ddi_put32(bgep->io_handle, 910 PIO_ADDR(bgep, addr), (uint32_t)data); 911 BGE_PCICHK(bgep); 912 ddi_put32(bgep->io_handle, 913 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 914 } else { 915 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 916 } 917 #else 918 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 919 #endif 920 921 BGE_PCICHK(bgep); 922 } 923 924 /* 925 * The DDI doesn't provide get/put functions for 128 bit data 926 * so we put RCBs out as two 64-bit chunks instead. 927 */ 928 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 929 #pragma inline(bge_nic_putrcb) 930 931 static void 932 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 933 { 934 uint64_t *p; 935 936 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 937 (void *)bgep, addr, rcbp->host_ring_addr, 938 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 939 940 ASSERT((addr % sizeof (*rcbp)) == 0); 941 942 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 943 addr &= MWBAR_GRANULE_MASK; 944 addr += NIC_MEM_WINDOW_OFFSET; 945 946 p = (void *)rcbp; 947 #ifdef __amd64 948 if (bge_get_em64t_type()) { 949 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 950 (uint32_t)(*p)); 951 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 952 (uint32_t)(*p >> 32)); 953 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 954 (uint32_t)(*(p + 1))); 955 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 956 (uint32_t)(*p >> 32)); 957 958 } else { 959 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 960 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 961 } 962 #else 963 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 964 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 965 #endif 966 967 BGE_PCICHK(bgep); 968 } 969 970 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 971 #pragma inline(bge_nic_zero) 972 973 static void 974 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 975 { 976 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 977 (void *)bgep, addr, nbytes)); 978 979 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 980 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 981 982 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 983 addr &= MWBAR_GRANULE_MASK; 984 addr += NIC_MEM_WINDOW_OFFSET; 985 986 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 987 nbytes, 1, DDI_DATA_SZ08_ACC); 988 BGE_PCICHK(bgep); 989 } 990 991 /* 992 * MII (PHY) register get/set access routines 993 * 994 * These use the chip's MII auto-access method, controlled by the 995 * MII Communication register at 0x044c, so the CPU doesn't have 996 * to fiddle with the individual bits. 997 */ 998 999 #undef BGE_DBG 1000 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1001 1002 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1003 uint16_t data, uint32_t cmd); 1004 #pragma no_inline(bge_mii_access) 1005 1006 static uint16_t 1007 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1008 { 1009 uint32_t timeout; 1010 uint32_t regval1; 1011 uint32_t regval2; 1012 1013 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1014 (void *)bgep, regno, data, cmd)); 1015 1016 ASSERT(mutex_owned(bgep->genlock)); 1017 1018 /* 1019 * Assemble the command ... 1020 */ 1021 cmd |= data << MI_COMMS_DATA_SHIFT; 1022 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1023 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1024 cmd |= MI_COMMS_START; 1025 1026 /* 1027 * Wait for any command already in progress ... 1028 * 1029 * Note: this *shouldn't* ever find that there is a command 1030 * in progress, because we already hold the <genlock> mutex. 1031 * Nonetheless, we have sometimes seen the MI_COMMS_START 1032 * bit set here -- it seems that the chip can initiate MII 1033 * accesses internally, even with polling OFF. 1034 */ 1035 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1036 for (timeout = 100; ; ) { 1037 if ((regval2 & MI_COMMS_START) == 0) { 1038 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1039 break; 1040 } 1041 if (--timeout == 0) 1042 break; 1043 drv_usecwait(10); 1044 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1045 } 1046 1047 if (timeout == 0) 1048 return ((uint16_t)~0u); 1049 1050 if (timeout != 100) 1051 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1052 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1053 cmd, 10*(100-timeout), regval1, regval2)); 1054 1055 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1056 for (timeout = 1000; ; ) { 1057 if ((regval1 & MI_COMMS_START) == 0) 1058 break; 1059 if (--timeout == 0) 1060 break; 1061 drv_usecwait(10); 1062 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1063 } 1064 1065 /* 1066 * Drop out early if the READ FAILED bit is set -- this chip 1067 * could be a 5703/4S, with a SerDes instead of a PHY! 1068 */ 1069 if (regval2 & MI_COMMS_READ_FAILED) 1070 return ((uint16_t)~0u); 1071 1072 if (timeout == 0) 1073 return ((uint16_t)~0u); 1074 1075 /* 1076 * The PRM says to wait 5us after seeing the START bit clear 1077 * and then re-read the register to get the final value of the 1078 * data field, in order to avoid a race condition where the 1079 * START bit is clear but the data field isn't yet valid. 1080 * 1081 * Note: we don't actually seem to be encounter this race; 1082 * except when the START bit is seen set again (see below), 1083 * the data field doesn't change during this 5us interval. 1084 */ 1085 drv_usecwait(5); 1086 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1087 1088 /* 1089 * Unfortunately, when following the PRMs instructions above, 1090 * we have occasionally seen the START bit set again(!) in the 1091 * value read after the 5us delay. This seems to be due to the 1092 * chip autonomously starting another MII access internally. 1093 * In such cases, the command/data/etc fields relate to the 1094 * internal command, rather than the one that we thought had 1095 * just finished. So in this case, we fall back to returning 1096 * the data from the original read that showed START clear. 1097 */ 1098 if (regval2 & MI_COMMS_START) { 1099 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1100 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1101 cmd, regval1, regval2)); 1102 regval2 = regval1; 1103 } 1104 1105 if (regval2 & MI_COMMS_START) 1106 return ((uint16_t)~0u); 1107 1108 if (regval2 & MI_COMMS_READ_FAILED) 1109 return ((uint16_t)~0u); 1110 1111 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1112 } 1113 1114 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1115 #pragma no_inline(bge_mii_get16) 1116 1117 uint16_t 1118 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1119 { 1120 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1121 (void *)bgep, regno)); 1122 1123 ASSERT(mutex_owned(bgep->genlock)); 1124 1125 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1126 } 1127 1128 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1129 #pragma no_inline(bge_mii_put16) 1130 1131 void 1132 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1133 { 1134 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1135 (void *)bgep, regno, data)); 1136 1137 ASSERT(mutex_owned(bgep->genlock)); 1138 1139 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1140 } 1141 1142 #undef BGE_DBG 1143 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1144 1145 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1146 1147 /* 1148 * Basic SEEPROM get/set access routine 1149 * 1150 * This uses the chip's SEEPROM auto-access method, controlled by the 1151 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1152 * doesn't have to fiddle with the individual bits. 1153 * 1154 * The caller should hold <genlock> and *also* have already acquired 1155 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1156 * 1157 * Return value: 1158 * 0 on success, 1159 * ENODATA on access timeout (maybe retryable: device may just be busy) 1160 * EPROTO on other h/w or s/w errors. 1161 * 1162 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1163 * from a (successful) SEEPROM_ACCESS_READ. 1164 */ 1165 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1166 uint32_t *dp); 1167 #pragma no_inline(bge_seeprom_access) 1168 1169 static int 1170 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1171 { 1172 uint32_t tries; 1173 uint32_t regval; 1174 1175 ASSERT(mutex_owned(bgep->genlock)); 1176 1177 /* 1178 * On the newer chips that support both SEEPROM & Flash, we need 1179 * to specifically enable SEEPROM access (Flash is the default). 1180 * On older chips, we don't; SEEPROM is the only NVtype supported, 1181 * and the NVM control registers don't exist ... 1182 */ 1183 switch (bgep->chipid.nvtype) { 1184 case BGE_NVTYPE_NONE: 1185 case BGE_NVTYPE_UNKNOWN: 1186 _NOTE(NOTREACHED) 1187 case BGE_NVTYPE_SEEPROM: 1188 break; 1189 1190 case BGE_NVTYPE_LEGACY_SEEPROM: 1191 case BGE_NVTYPE_UNBUFFERED_FLASH: 1192 case BGE_NVTYPE_BUFFERED_FLASH: 1193 default: 1194 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1195 NVM_CFG1_LEGACY_SEEPROM_MODE); 1196 break; 1197 } 1198 1199 /* 1200 * Check there's no command in progress. 1201 * 1202 * Note: this *shouldn't* ever find that there is a command 1203 * in progress, because we already hold the <genlock> mutex. 1204 * Also, to ensure we don't have a conflict with the chip's 1205 * internal firmware or a process accessing the same (shared) 1206 * SEEPROM through the other port of a 5704, we've already 1207 * been through the "software arbitration" protocol. 1208 * So this is just a final consistency check: we shouldn't 1209 * see EITHER the START bit (command started but not complete) 1210 * OR the COMPLETE bit (command completed but not cleared). 1211 */ 1212 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1213 if (regval & SEEPROM_ACCESS_START) 1214 return (EPROTO); 1215 if (regval & SEEPROM_ACCESS_COMPLETE) 1216 return (EPROTO); 1217 1218 /* 1219 * Assemble the command ... 1220 */ 1221 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1222 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1223 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1224 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1225 cmd |= SEEPROM_ACCESS_START; 1226 cmd |= SEEPROM_ACCESS_COMPLETE; 1227 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1228 1229 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1230 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1231 1232 /* 1233 * By observation, a successful access takes ~20us on a 5703/4, 1234 * but apparently much longer (up to 1000us) on the obsolescent 1235 * BCM5700/BCM5701. We want to be sure we don't get any false 1236 * timeouts here; but OTOH, we don't want a bogus access to lock 1237 * out interrupts for longer than necessary. So we'll allow up 1238 * to 1000us ... 1239 */ 1240 for (tries = 0; tries < 1000; ++tries) { 1241 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1242 if (regval & SEEPROM_ACCESS_COMPLETE) 1243 break; 1244 drv_usecwait(1); 1245 } 1246 1247 if (regval & SEEPROM_ACCESS_COMPLETE) { 1248 /* 1249 * All OK; read the SEEPROM data register, then write back 1250 * the value read from the address register in order to 1251 * clear the <complete> bit and leave the SEEPROM access 1252 * state machine idle, ready for the next access ... 1253 */ 1254 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1255 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1256 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1257 return (0); 1258 } 1259 1260 /* 1261 * Hmm ... what happened here? 1262 * 1263 * Most likely, the user addressed a non-existent SEEPROM. Or 1264 * maybe the SEEPROM was busy internally (e.g. processing a write) 1265 * and didn't respond to being addressed. Either way, it's left 1266 * the SEEPROM access state machine wedged. So we'll reset it 1267 * before we leave, so it's ready for next time ... 1268 */ 1269 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1270 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1271 return (ENODATA); 1272 } 1273 1274 /* 1275 * Basic Flash get/set access routine 1276 * 1277 * These use the chip's Flash auto-access method, controlled by the 1278 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1279 * fiddle with the individual bits. 1280 * 1281 * The caller should hold <genlock> and *also* have already acquired 1282 * the right to access the Flash, via bge_nvmem_acquire() above. 1283 * 1284 * Return value: 1285 * 0 on success, 1286 * ENODATA on access timeout (maybe retryable: device may just be busy) 1287 * ENODEV if the NVmem device is missing or otherwise unusable 1288 * 1289 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1290 * from a (successful) NVM_FLASH_CMD_RD. 1291 */ 1292 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1293 uint32_t *dp); 1294 #pragma no_inline(bge_flash_access) 1295 1296 static int 1297 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1298 { 1299 uint32_t tries; 1300 uint32_t regval; 1301 1302 ASSERT(mutex_owned(bgep->genlock)); 1303 1304 /* 1305 * On the newer chips that support both SEEPROM & Flash, we need 1306 * to specifically disable SEEPROM access while accessing Flash. 1307 * The older chips don't support Flash, and the NVM registers don't 1308 * exist, so we shouldn't be here at all! 1309 */ 1310 switch (bgep->chipid.nvtype) { 1311 case BGE_NVTYPE_NONE: 1312 case BGE_NVTYPE_UNKNOWN: 1313 _NOTE(NOTREACHED) 1314 case BGE_NVTYPE_SEEPROM: 1315 return (ENODEV); 1316 1317 case BGE_NVTYPE_LEGACY_SEEPROM: 1318 case BGE_NVTYPE_UNBUFFERED_FLASH: 1319 case BGE_NVTYPE_BUFFERED_FLASH: 1320 default: 1321 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1322 NVM_CFG1_LEGACY_SEEPROM_MODE); 1323 break; 1324 } 1325 1326 /* 1327 * Assemble the command ... 1328 */ 1329 addr &= NVM_FLASH_ADDR_MASK; 1330 cmd |= NVM_FLASH_CMD_DOIT; 1331 cmd |= NVM_FLASH_CMD_FIRST; 1332 cmd |= NVM_FLASH_CMD_LAST; 1333 cmd |= NVM_FLASH_CMD_DONE; 1334 1335 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1336 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1337 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1338 1339 /* 1340 * Allow up to 1000ms ... 1341 */ 1342 for (tries = 0; tries < 1000; ++tries) { 1343 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1344 if (regval & NVM_FLASH_CMD_DONE) 1345 break; 1346 drv_usecwait(1); 1347 } 1348 1349 if (regval & NVM_FLASH_CMD_DONE) { 1350 /* 1351 * All OK; read the data from the Flash read register 1352 */ 1353 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1354 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1355 return (0); 1356 } 1357 1358 /* 1359 * Hmm ... what happened here? 1360 * 1361 * Most likely, the user addressed a non-existent Flash. Or 1362 * maybe the Flash was busy internally (e.g. processing a write) 1363 * and didn't respond to being addressed. Either way, there's 1364 * nothing we can here ... 1365 */ 1366 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1367 return (ENODATA); 1368 } 1369 1370 /* 1371 * The next two functions regulate access to the NVram (if fitted). 1372 * 1373 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1374 * (SPI) interface, but they can be accessed through either port. These 1375 * are managed by different instance of this driver and have no software 1376 * state in common. 1377 * 1378 * In addition (and even on a single core chip) the chip's internal 1379 * firmware can access the SEEPROM/Flash, most notably after a RESET 1380 * when it may download code to run internally. 1381 * 1382 * So we need to arbitrate between these various software agents. For 1383 * this purpose, the chip provides the Software Arbitration Register, 1384 * which implements hardware(!) arbitration. 1385 * 1386 * This functionality didn't exist on older (5700/5701) chips, so there's 1387 * nothing we can do by way of arbitration on those; also, if there's no 1388 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1389 * nothing to do. 1390 * 1391 * The internal firmware appears to use Request 0, which is the highest 1392 * priority. So we'd like to use Request 2, leaving one higher and one 1393 * lower for any future developments ... but apparently this doesn't 1394 * always work. So for now, the code uses Request 1 ;-( 1395 */ 1396 1397 #define NVM_READ_REQ NVM_READ_REQ1 1398 #define NVM_RESET_REQ NVM_RESET_REQ1 1399 #define NVM_SET_REQ NVM_SET_REQ1 1400 1401 static void bge_nvmem_relinquish(bge_t *bgep); 1402 #pragma no_inline(bge_nvmem_relinquish) 1403 1404 static void 1405 bge_nvmem_relinquish(bge_t *bgep) 1406 { 1407 ASSERT(mutex_owned(bgep->genlock)); 1408 1409 switch (bgep->chipid.nvtype) { 1410 case BGE_NVTYPE_NONE: 1411 case BGE_NVTYPE_UNKNOWN: 1412 _NOTE(NOTREACHED) 1413 return; 1414 1415 case BGE_NVTYPE_SEEPROM: 1416 /* 1417 * No arbitration performed, no release needed 1418 */ 1419 return; 1420 1421 case BGE_NVTYPE_LEGACY_SEEPROM: 1422 case BGE_NVTYPE_UNBUFFERED_FLASH: 1423 case BGE_NVTYPE_BUFFERED_FLASH: 1424 default: 1425 break; 1426 } 1427 1428 /* 1429 * Our own request should be present (whether or not granted) ... 1430 */ 1431 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1432 1433 /* 1434 * ... this will make it go away. 1435 */ 1436 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1437 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1438 } 1439 1440 /* 1441 * Arbitrate for access to the NVmem, if necessary 1442 * 1443 * Return value: 1444 * 0 on success 1445 * EAGAIN if the device is in use (retryable) 1446 * ENODEV if the NVmem device is missing or otherwise unusable 1447 */ 1448 static int bge_nvmem_acquire(bge_t *bgep); 1449 #pragma no_inline(bge_nvmem_acquire) 1450 1451 static int 1452 bge_nvmem_acquire(bge_t *bgep) 1453 { 1454 uint32_t regval; 1455 uint32_t tries; 1456 1457 ASSERT(mutex_owned(bgep->genlock)); 1458 1459 switch (bgep->chipid.nvtype) { 1460 case BGE_NVTYPE_NONE: 1461 case BGE_NVTYPE_UNKNOWN: 1462 /* 1463 * Access denied: no (recognisable) device fitted 1464 */ 1465 return (ENODEV); 1466 1467 case BGE_NVTYPE_SEEPROM: 1468 /* 1469 * Access granted: no arbitration needed (or possible) 1470 */ 1471 return (0); 1472 1473 case BGE_NVTYPE_LEGACY_SEEPROM: 1474 case BGE_NVTYPE_UNBUFFERED_FLASH: 1475 case BGE_NVTYPE_BUFFERED_FLASH: 1476 default: 1477 /* 1478 * Access conditional: conduct arbitration protocol 1479 */ 1480 break; 1481 } 1482 1483 /* 1484 * We're holding the per-port mutex <genlock>, so no-one other 1485 * thread can be attempting to access the NVmem through *this* 1486 * port. But it could be in use by the *other* port (of a 5704), 1487 * or by the chip's internal firmware, so we have to go through 1488 * the full (hardware) arbitration protocol ... 1489 * 1490 * Note that *because* we're holding <genlock>, the interrupt handler 1491 * won't be able to progress. So we're only willing to spin for a 1492 * fairly short time. Specifically: 1493 * 1494 * We *must* wait long enough for the hardware to resolve all 1495 * requests and determine the winner. Fortunately, this is 1496 * "almost instantaneous", even as observed by GHz CPUs. 1497 * 1498 * A successful access by another Solaris thread (via either 1499 * port) typically takes ~20us. So waiting a bit longer than 1500 * that will give a good chance of success, if the other user 1501 * *is* another thread on the other port. 1502 * 1503 * However, the internal firmware can hold on to the NVmem 1504 * for *much* longer: at least 10 milliseconds just after a 1505 * RESET, and maybe even longer if the NVmem actually contains 1506 * code to download and run on the internal CPUs. 1507 * 1508 * So, we'll allow 50us; if that's not enough then it's up to the 1509 * caller to retry later (hence the choice of return code EAGAIN). 1510 */ 1511 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1512 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1513 1514 for (tries = 0; tries < 50; ++tries) { 1515 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1516 if (regval & NVM_WON_REQ1) 1517 break; 1518 drv_usecwait(1); 1519 } 1520 1521 if (regval & NVM_WON_REQ1) { 1522 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1523 return (0); 1524 } 1525 1526 /* 1527 * Somebody else must be accessing the NVmem, so abandon our 1528 * attempt take control of it. The caller can try again later ... 1529 */ 1530 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1531 bge_nvmem_relinquish(bgep); 1532 return (EAGAIN); 1533 } 1534 1535 /* 1536 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1537 * write protect line in such a way that the NVmem is protected when 1538 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1539 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1540 * 1541 * Note: there's only one set of GPIO pins on a 5704, even though they 1542 * can be accessed through either port. So the chip has to resolve what 1543 * happens if the two ports program a single pin differently ... the rule 1544 * it uses is that if the ports disagree about the *direction* of a pin, 1545 * "output" wins over "input", but if they disagree about its *value* as 1546 * an output, then the pin is TRISTATED instead! In such a case, no-one 1547 * wins, and the external signal does whatever the external circuitry 1548 * defines as the default -- which we've assumed is the PROTECTED state. 1549 * So, we always change GPIO1 back to being an *input* whenever we're not 1550 * specifically using it to unprotect the NVmem. This allows either port 1551 * to update the NVmem, although obviously only one at a time! 1552 * 1553 * The caller should hold <genlock> and *also* have already acquired the 1554 * right to access the NVmem, via bge_nvmem_acquire() above. 1555 */ 1556 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1557 #pragma inline(bge_nvmem_protect) 1558 1559 static void 1560 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1561 { 1562 uint32_t regval; 1563 1564 ASSERT(mutex_owned(bgep->genlock)); 1565 1566 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1567 if (protect) { 1568 regval |= MLCR_MISC_PINS_OUTPUT_1; 1569 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1570 } else { 1571 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1572 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1573 } 1574 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1575 } 1576 1577 /* 1578 * Now put it all together ... 1579 * 1580 * Try to acquire control of the NVmem; if successful, then: 1581 * unprotect it (if we want to write to it) 1582 * perform the requested access 1583 * reprotect it (after a write) 1584 * relinquish control 1585 * 1586 * Return value: 1587 * 0 on success, 1588 * EAGAIN if the device is in use (retryable) 1589 * ENODATA on access timeout (maybe retryable: device may just be busy) 1590 * ENODEV if the NVmem device is missing or otherwise unusable 1591 * EPROTO on other h/w or s/w errors. 1592 */ 1593 static int 1594 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1595 { 1596 int err; 1597 1598 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1599 switch (cmd) { 1600 case BGE_SEE_READ: 1601 err = bge_seeprom_access(bgep, 1602 SEEPROM_ACCESS_READ, addr, dp); 1603 break; 1604 1605 case BGE_SEE_WRITE: 1606 bge_nvmem_protect(bgep, B_FALSE); 1607 err = bge_seeprom_access(bgep, 1608 SEEPROM_ACCESS_WRITE, addr, dp); 1609 bge_nvmem_protect(bgep, B_TRUE); 1610 break; 1611 1612 case BGE_FLASH_READ: 1613 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1614 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1615 bge_reg_set32(bgep, NVM_ACCESS_REG, 1616 NVM_ACCESS_ENABLE); 1617 } 1618 err = bge_flash_access(bgep, 1619 NVM_FLASH_CMD_RD, addr, dp); 1620 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1621 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1622 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1623 NVM_ACCESS_ENABLE); 1624 } 1625 break; 1626 1627 case BGE_FLASH_WRITE: 1628 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1629 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1630 bge_reg_set32(bgep, NVM_ACCESS_REG, 1631 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1632 } 1633 bge_nvmem_protect(bgep, B_FALSE); 1634 err = bge_flash_access(bgep, 1635 NVM_FLASH_CMD_WR, addr, dp); 1636 bge_nvmem_protect(bgep, B_TRUE); 1637 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1638 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1639 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1640 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1641 } 1642 1643 break; 1644 1645 default: 1646 _NOTE(NOTREACHED) 1647 break; 1648 } 1649 bge_nvmem_relinquish(bgep); 1650 } 1651 1652 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1653 return (err); 1654 } 1655 1656 /* 1657 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1658 */ 1659 static uint64_t bge_get_nvmac(bge_t *bgep); 1660 #pragma no_inline(bge_get_nvmac) 1661 1662 static uint64_t 1663 bge_get_nvmac(bge_t *bgep) 1664 { 1665 uint32_t mac_high; 1666 uint32_t mac_low; 1667 uint32_t addr; 1668 uint32_t cmd; 1669 uint64_t mac; 1670 1671 BGE_TRACE(("bge_get_nvmac($%p)", 1672 (void *)bgep)); 1673 1674 switch (bgep->chipid.nvtype) { 1675 case BGE_NVTYPE_NONE: 1676 case BGE_NVTYPE_UNKNOWN: 1677 default: 1678 return (0ULL); 1679 1680 case BGE_NVTYPE_SEEPROM: 1681 case BGE_NVTYPE_LEGACY_SEEPROM: 1682 cmd = BGE_SEE_READ; 1683 break; 1684 1685 case BGE_NVTYPE_UNBUFFERED_FLASH: 1686 case BGE_NVTYPE_BUFFERED_FLASH: 1687 cmd = BGE_FLASH_READ; 1688 break; 1689 } 1690 1691 addr = NVMEM_DATA_MAC_ADDRESS; 1692 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1693 return (0ULL); 1694 addr += 4; 1695 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1696 return (0ULL); 1697 1698 /* 1699 * The Broadcom chip is natively BIG-endian, so that's how the 1700 * MAC address is represented in NVmem. We may need to swap it 1701 * around on a little-endian host ... 1702 */ 1703 #ifdef _BIG_ENDIAN 1704 mac = mac_high; 1705 mac = mac << 32; 1706 mac |= mac_low; 1707 #else 1708 mac = BGE_BSWAP_32(mac_high); 1709 mac = mac << 32; 1710 mac |= BGE_BSWAP_32(mac_low); 1711 #endif /* _BIG_ENDIAN */ 1712 1713 return (mac); 1714 } 1715 1716 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1717 1718 /* 1719 * Dummy version for when we're not supporting NVmem access 1720 */ 1721 static uint64_t bge_get_nvmac(bge_t *bgep); 1722 #pragma inline(bge_get_nvmac) 1723 1724 static uint64_t 1725 bge_get_nvmac(bge_t *bgep) 1726 { 1727 _NOTE(ARGUNUSED(bgep)) 1728 return (0ULL); 1729 } 1730 1731 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1732 1733 /* 1734 * Determine the type of NVmem that is (or may be) attached to this chip, 1735 */ 1736 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1737 #pragma no_inline(bge_nvmem_id) 1738 1739 static enum bge_nvmem_type 1740 bge_nvmem_id(bge_t *bgep) 1741 { 1742 enum bge_nvmem_type nvtype; 1743 uint32_t config1; 1744 1745 BGE_TRACE(("bge_nvmem_id($%p)", 1746 (void *)bgep)); 1747 1748 switch (bgep->chipid.device) { 1749 default: 1750 /* 1751 * We shouldn't get here; it means we don't recognise 1752 * the chip, which means we don't know how to determine 1753 * what sort of NVmem (if any) it has. So we'll say 1754 * NONE, to disable the NVmem access code ... 1755 */ 1756 nvtype = BGE_NVTYPE_NONE; 1757 break; 1758 1759 case DEVICE_ID_5700: 1760 case DEVICE_ID_5700x: 1761 case DEVICE_ID_5701: 1762 /* 1763 * These devices support *only* SEEPROMs 1764 */ 1765 nvtype = BGE_NVTYPE_SEEPROM; 1766 break; 1767 1768 case DEVICE_ID_5702: 1769 case DEVICE_ID_5702fe: 1770 case DEVICE_ID_5703C: 1771 case DEVICE_ID_5703S: 1772 case DEVICE_ID_5704C: 1773 case DEVICE_ID_5704S: 1774 case DEVICE_ID_5704: 1775 case DEVICE_ID_5705M: 1776 case DEVICE_ID_5705C: 1777 case DEVICE_ID_5705_2: 1778 case DEVICE_ID_5706: 1779 case DEVICE_ID_5782: 1780 case DEVICE_ID_5787: 1781 case DEVICE_ID_5787M: 1782 case DEVICE_ID_5788: 1783 case DEVICE_ID_5789: 1784 case DEVICE_ID_5751: 1785 case DEVICE_ID_5751M: 1786 case DEVICE_ID_5752: 1787 case DEVICE_ID_5752M: 1788 case DEVICE_ID_5754: 1789 case DEVICE_ID_5755: 1790 case DEVICE_ID_5755M: 1791 case DEVICE_ID_5721: 1792 case DEVICE_ID_5722: 1793 case DEVICE_ID_5714C: 1794 case DEVICE_ID_5714S: 1795 case DEVICE_ID_5715C: 1796 case DEVICE_ID_5715S: 1797 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1798 if (config1 & NVM_CFG1_FLASH_MODE) 1799 if (config1 & NVM_CFG1_BUFFERED_MODE) 1800 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1801 else 1802 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1803 else 1804 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1805 break; 1806 } 1807 1808 return (nvtype); 1809 } 1810 1811 #undef BGE_DBG 1812 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1813 1814 static void 1815 bge_init_recv_rule(bge_t *bgep) 1816 { 1817 bge_recv_rule_t *rulep; 1818 uint32_t i; 1819 1820 /* 1821 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1822 * 1. to direct UDP traffic, set: 1823 * rulep->control = RULE_PROTO_CONTROL; 1824 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1825 * 2. to direct ICMP traffic, set: 1826 * rulep->control = RULE_PROTO_CONTROL; 1827 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1828 * 3. to direct traffic by source ip, set: 1829 * rulep->control = RULE_SIP_CONTROL; 1830 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1831 */ 1832 rulep = bgep->recv_rules; 1833 rulep->control = RULE_PROTO_CONTROL; 1834 rulep->mask_value = RULE_TCP_MASK_VALUE; 1835 1836 /* 1837 * set receive rule registers 1838 */ 1839 rulep = bgep->recv_rules; 1840 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1841 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1842 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1843 } 1844 } 1845 1846 /* 1847 * Using the values captured by bge_chip_cfg_init(), and additional probes 1848 * as required, characterise the chip fully: determine the label by which 1849 * to refer to this chip, the correct settings for various registers, and 1850 * of course whether the device and/or subsystem are supported! 1851 */ 1852 int bge_chip_id_init(bge_t *bgep); 1853 #pragma no_inline(bge_chip_id_init) 1854 1855 int 1856 bge_chip_id_init(bge_t *bgep) 1857 { 1858 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1859 boolean_t sys_ok; 1860 boolean_t dev_ok; 1861 chip_id_t *cidp; 1862 uint32_t subid; 1863 char *devname; 1864 char *sysname; 1865 int *ids; 1866 int err; 1867 uint_t i; 1868 1869 sys_ok = dev_ok = B_FALSE; 1870 cidp = &bgep->chipid; 1871 1872 /* 1873 * Check the PCI device ID to determine the generic chip type and 1874 * select parameters that depend on this. 1875 * 1876 * Note: because the SPARC platforms in general don't fit the 1877 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1878 * as zero - which is why we use <asic_rev> rather than <revision> 1879 * below ... 1880 * 1881 * Note: in general we can't distinguish between the Copper/SerDes 1882 * versions by ID alone, as some Copper devices (e.g. some but not 1883 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1884 * treat them the same here, and the MII code works out the media 1885 * type later on ... 1886 */ 1887 cidp->mbuf_base = bge_mbuf_pool_base; 1888 cidp->mbuf_length = bge_mbuf_pool_len; 1889 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1890 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1891 cidp->pci_type = BGE_PCI_X; 1892 cidp->statistic_type = BGE_STAT_BLK; 1893 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1894 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1895 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1896 cidp->rx_ticks_norm = bge_rx_ticks_norm; 1897 cidp->rx_count_norm = bge_rx_count_norm; 1898 1899 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1900 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1901 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1902 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1903 1904 cidp->msi_enabled = B_FALSE; 1905 1906 switch (cidp->device) { 1907 case DEVICE_ID_5700: 1908 case DEVICE_ID_5700x: 1909 cidp->chip_label = 5700; 1910 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1911 break; 1912 1913 case DEVICE_ID_5701: 1914 cidp->chip_label = 5701; 1915 dev_ok = B_TRUE; 1916 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1917 break; 1918 1919 case DEVICE_ID_5702: 1920 case DEVICE_ID_5702fe: 1921 cidp->chip_label = 5702; 1922 dev_ok = B_TRUE; 1923 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1924 cidp->pci_type = BGE_PCI; 1925 break; 1926 1927 case DEVICE_ID_5703C: 1928 case DEVICE_ID_5703S: 1929 case DEVICE_ID_5703: 1930 /* 1931 * Revision A0 of the 5703/5793 had various errata 1932 * that we can't or don't work around, so it's not 1933 * supported, but all later versions are 1934 */ 1935 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 1936 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 1937 dev_ok = B_TRUE; 1938 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1939 break; 1940 1941 case DEVICE_ID_5704C: 1942 case DEVICE_ID_5704S: 1943 case DEVICE_ID_5704: 1944 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 1945 cidp->mbuf_base = bge_mbuf_pool_base_5704; 1946 cidp->mbuf_length = bge_mbuf_pool_len_5704; 1947 dev_ok = B_TRUE; 1948 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1949 break; 1950 1951 case DEVICE_ID_5705C: 1952 case DEVICE_ID_5705M: 1953 case DEVICE_ID_5705MA3: 1954 case DEVICE_ID_5705F: 1955 case DEVICE_ID_5705_2: 1956 case DEVICE_ID_5754: 1957 if (cidp->device == DEVICE_ID_5754) { 1958 cidp->chip_label = 5754; 1959 cidp->pci_type = BGE_PCI_E; 1960 } else { 1961 cidp->chip_label = 5705; 1962 cidp->pci_type = BGE_PCI; 1963 } 1964 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 1965 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 1966 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 1967 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1968 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1969 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1970 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1971 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 1972 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1973 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1974 cidp->statistic_type = BGE_STAT_REG; 1975 dev_ok = B_TRUE; 1976 break; 1977 1978 case DEVICE_ID_5753: 1979 cidp->chip_label = 5753; 1980 cidp->pci_type = BGE_PCI_E; 1981 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 1982 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 1983 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 1984 cidp->mbuf_base = bge_mbuf_pool_base_5705; 1985 cidp->mbuf_length = bge_mbuf_pool_len_5705; 1986 cidp->recv_slots = BGE_RECV_SLOTS_5705; 1987 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1988 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 1989 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 1990 cidp->flags |= CHIP_FLAG_NO_JUMBO; 1991 cidp->statistic_type = BGE_STAT_REG; 1992 dev_ok = B_TRUE; 1993 break; 1994 1995 case DEVICE_ID_5755: 1996 case DEVICE_ID_5755M: 1997 cidp->chip_label = 5755; 1998 cidp->pci_type = BGE_PCI_E; 1999 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2000 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2001 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2002 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2003 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2004 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2005 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2006 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2007 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2008 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2009 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2010 cidp->statistic_type = BGE_STAT_REG; 2011 dev_ok = B_TRUE; 2012 break; 2013 2014 case DEVICE_ID_5787: 2015 case DEVICE_ID_5787M: 2016 cidp->chip_label = 5787; 2017 cidp->pci_type = BGE_PCI_E; 2018 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2019 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2020 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2021 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2022 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2023 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2024 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2025 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2026 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2027 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2028 cidp->statistic_type = BGE_STAT_REG; 2029 dev_ok = B_TRUE; 2030 break; 2031 2032 case DEVICE_ID_5706: 2033 cidp->chip_label = 5706; 2034 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2035 break; 2036 2037 case DEVICE_ID_5782: 2038 /* 2039 * Apart from the label, we treat this as a 5705(?) 2040 */ 2041 cidp->chip_label = 5782; 2042 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2043 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2044 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2045 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2046 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2047 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2048 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2049 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2050 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2051 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2052 cidp->statistic_type = BGE_STAT_REG; 2053 dev_ok = B_TRUE; 2054 break; 2055 2056 case DEVICE_ID_5788: 2057 /* 2058 * Apart from the label, we treat this as a 5705(?) 2059 */ 2060 cidp->chip_label = 5788; 2061 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2062 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2063 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2064 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2065 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2066 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2067 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2068 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2069 cidp->statistic_type = BGE_STAT_REG; 2070 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2071 dev_ok = B_TRUE; 2072 break; 2073 2074 case DEVICE_ID_5714C: 2075 if (cidp->revision >= REVISION_ID_5714_A2) 2076 cidp->msi_enabled = bge_enable_msi; 2077 /* FALLTHRU */ 2078 case DEVICE_ID_5714S: 2079 cidp->chip_label = 5714; 2080 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2081 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2082 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2083 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2084 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2085 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2086 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2087 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2088 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2089 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2090 cidp->pci_type = BGE_PCI_E; 2091 cidp->statistic_type = BGE_STAT_REG; 2092 dev_ok = B_TRUE; 2093 break; 2094 2095 case DEVICE_ID_5715C: 2096 case DEVICE_ID_5715S: 2097 cidp->chip_label = 5715; 2098 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2099 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2100 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2101 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2102 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2103 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2104 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2105 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2106 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2107 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2108 cidp->pci_type = BGE_PCI_E; 2109 cidp->statistic_type = BGE_STAT_REG; 2110 if (cidp->revision >= REVISION_ID_5715_A2) 2111 cidp->msi_enabled = bge_enable_msi; 2112 dev_ok = B_TRUE; 2113 break; 2114 2115 case DEVICE_ID_5721: 2116 cidp->chip_label = 5721; 2117 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2118 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2119 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2120 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2121 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2122 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2123 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2124 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2125 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2126 cidp->pci_type = BGE_PCI_E; 2127 cidp->statistic_type = BGE_STAT_REG; 2128 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2129 dev_ok = B_TRUE; 2130 break; 2131 2132 case DEVICE_ID_5722: 2133 cidp->chip_label = 5722; 2134 cidp->pci_type = BGE_PCI_E; 2135 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2136 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2137 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2138 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2139 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2140 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2141 cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 2142 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2143 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2144 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2145 cidp->statistic_type = BGE_STAT_REG; 2146 dev_ok = B_TRUE; 2147 break; 2148 2149 case DEVICE_ID_5751: 2150 case DEVICE_ID_5751M: 2151 cidp->chip_label = 5751; 2152 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2153 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2154 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2155 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2156 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2157 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2158 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2159 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2160 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2161 cidp->pci_type = BGE_PCI_E; 2162 cidp->statistic_type = BGE_STAT_REG; 2163 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2164 dev_ok = B_TRUE; 2165 break; 2166 2167 case DEVICE_ID_5752: 2168 case DEVICE_ID_5752M: 2169 cidp->chip_label = 5752; 2170 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2171 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2172 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2173 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2174 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2175 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2176 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2177 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2178 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2179 cidp->pci_type = BGE_PCI_E; 2180 cidp->statistic_type = BGE_STAT_REG; 2181 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2182 dev_ok = B_TRUE; 2183 break; 2184 2185 case DEVICE_ID_5789: 2186 cidp->chip_label = 5789; 2187 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2188 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2189 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2190 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2191 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2192 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2193 cidp->pci_type = BGE_PCI_E; 2194 cidp->statistic_type = BGE_STAT_REG; 2195 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2196 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2197 cidp->msi_enabled = B_TRUE; 2198 dev_ok = B_TRUE; 2199 break; 2200 2201 } 2202 2203 /* 2204 * Setup the default jumbo parameter. 2205 */ 2206 cidp->ethmax_size = ETHERMAX; 2207 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2208 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2209 2210 /* 2211 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2212 * setup below jumbo specific parameters. 2213 * 2214 * For BCM5714/5715, there is only one standard receive ring. So the 2215 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2216 * feature is enabled. 2217 */ 2218 if (bge_jumbo_enable && 2219 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2220 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2221 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2222 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2223 cidp->mbuf_lo_water_rdma = 2224 RDMA_MBUF_LOWAT_5714_JUMBO; 2225 cidp->mbuf_lo_water_rmac = 2226 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2227 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2228 cidp->jumbo_slots = 0; 2229 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2230 } else { 2231 cidp->mbuf_lo_water_rdma = 2232 RDMA_MBUF_LOWAT_JUMBO; 2233 cidp->mbuf_lo_water_rmac = 2234 MAC_RX_MBUF_LOWAT_JUMBO; 2235 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2236 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2237 } 2238 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2239 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2240 cidp->ethmax_size = cidp->default_mtu + 2241 sizeof (struct ether_header); 2242 } 2243 2244 /* 2245 * Identify the NV memory type: SEEPROM or Flash? 2246 */ 2247 cidp->nvtype = bge_nvmem_id(bgep); 2248 2249 /* 2250 * Now, we want to check whether this device is part of a 2251 * supported subsystem (e.g., on the motherboard of a Sun 2252 * branded platform). 2253 * 2254 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2255 */ 2256 if (cidp->subven == VENDOR_ID_SUN) 2257 sys_ok = B_TRUE; 2258 2259 /* 2260 * Rule 2: If it's on the list on known subsystems, then it's OK. 2261 * Note: 0x14e41647 should *not* appear in the list, but the code 2262 * doesn't enforce that. 2263 */ 2264 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2265 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2266 if (err == DDI_PROP_SUCCESS) { 2267 /* 2268 * Got the list; scan for a matching subsystem vendor/device 2269 */ 2270 subid = (cidp->subven << 16) | cidp->subdev; 2271 while (i--) 2272 if (ids[i] == subid) 2273 sys_ok = B_TRUE; 2274 ddi_prop_free(ids); 2275 } 2276 2277 /* 2278 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2279 * 2280 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2281 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2282 * we have to check specially for the exact device paths to the 2283 * motherboard devices on those platforms ;-( 2284 * 2285 * Note: we can't just use the "supported-subsystems" mechanism 2286 * above, because the entry would have to be 0x14e41647 -- which 2287 * would then accept *any* plugin card that *didn't* contain a 2288 * (valid) SEEPROM ;-( 2289 */ 2290 sysname = ddi_node_name(ddi_root_node()); 2291 devname = ddi_pathname(bgep->devinfo, buf); 2292 ASSERT(strlen(devname) > 0); 2293 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2294 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2295 sys_ok = B_TRUE; 2296 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2297 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2298 sys_ok = B_TRUE; 2299 2300 /* 2301 * Now check what we've discovered: is this truly a supported 2302 * chip on (the motherboard of) a supported platform? 2303 * 2304 * Possible problems here: 2305 * 1) it's a completely unheard-of chip (e.g. 5761) 2306 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2307 * 3) it's a chip we would support if it were on the motherboard 2308 * of a Sun platform, but this one isn't ;-( 2309 */ 2310 if (cidp->chip_label == 0) 2311 bge_problem(bgep, 2312 "Device 'pci%04x,%04x' not recognized (%d?)", 2313 cidp->vendor, cidp->device, cidp->device); 2314 else if (!dev_ok) 2315 bge_problem(bgep, 2316 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2317 cidp->vendor, cidp->device, cidp->chip_label, 2318 cidp->revision); 2319 #if BGE_DEBUGGING 2320 else if (!sys_ok) 2321 bge_problem(bgep, 2322 "%d-based subsystem 'pci%04x,%04x' not validated", 2323 cidp->chip_label, cidp->subven, cidp->subdev); 2324 #endif 2325 else 2326 cidp->flags |= CHIP_FLAG_SUPPORTED; 2327 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2328 return (EIO); 2329 return (0); 2330 } 2331 2332 void 2333 bge_chip_msi_trig(bge_t *bgep) 2334 { 2335 uint32_t regval; 2336 2337 regval = bgep->param_msi_cnt<<4; 2338 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2339 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2340 } 2341 2342 /* 2343 * Various registers that control the chip's internal engines (state 2344 * machines) have a <reset> and <enable> bits (fortunately, in the 2345 * same place in each such register :-). 2346 * 2347 * To reset the state machine, the <reset> bit must be written with 1; 2348 * it will then read back as 1 while the reset is in progress, but 2349 * self-clear to 0 when the reset completes. 2350 * 2351 * To enable a state machine, one must set the <enable> bit, which 2352 * will continue to read back as 0 until the state machine is running. 2353 * 2354 * To disable a state machine, the <enable> bit must be cleared, but 2355 * it will continue to read back as 1 until the state machine actually 2356 * stops. 2357 * 2358 * This routine implements polling for completion of a reset, enable 2359 * or disable operation, returning B_TRUE on success (bit reached the 2360 * required state) or B_FALSE on timeout (200*100us == 20ms). 2361 */ 2362 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2363 uint32_t mask, uint32_t val); 2364 #pragma no_inline(bge_chip_poll_engine) 2365 2366 static boolean_t 2367 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2368 uint32_t mask, uint32_t val) 2369 { 2370 uint32_t regval; 2371 uint32_t n; 2372 2373 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2374 (void *)bgep, regno, mask, val)); 2375 2376 for (n = 200; n; --n) { 2377 regval = bge_reg_get32(bgep, regno); 2378 if ((regval & mask) == val) 2379 return (B_TRUE); 2380 drv_usecwait(100); 2381 } 2382 2383 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2384 return (B_FALSE); 2385 } 2386 2387 /* 2388 * Various registers that control the chip's internal engines (state 2389 * machines) have a <reset> bit (fortunately, in the same place in 2390 * each such register :-). To reset the state machine, this bit must 2391 * be written with 1; it will then read back as 1 while the reset is 2392 * in progress, but self-clear to 0 when the reset completes. 2393 * 2394 * This code sets the bit, then polls for it to read back as zero. 2395 * The return value is B_TRUE on success (reset bit cleared itself), 2396 * or B_FALSE if the state machine didn't recover :( 2397 * 2398 * NOTE: the Core reset is similar to other resets, except that we 2399 * can't poll for completion, since the Core reset disables memory 2400 * access! So we just have to assume that it will all complete in 2401 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2402 */ 2403 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2404 #pragma no_inline(bge_chip_reset_engine) 2405 2406 static boolean_t 2407 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2408 { 2409 uint32_t regval; 2410 uint32_t val32; 2411 2412 regval = bge_reg_get32(bgep, regno); 2413 2414 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2415 (void *)bgep, regno)); 2416 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2417 regno, regval)); 2418 2419 regval |= STATE_MACHINE_RESET_BIT; 2420 2421 switch (regno) { 2422 case MISC_CONFIG_REG: 2423 /* 2424 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2425 * resetting PCIE block and bringing PCIE link down, bit 29 2426 * in the register needs to be set first, and then set it again 2427 * while the reset bit is written. 2428 * See:P500 of 57xx-PG102-RDS.pdf. 2429 */ 2430 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2431 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2432 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2433 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2434 if (bgep->chipid.pci_type == BGE_PCI_E) { 2435 if (bgep->chipid.asic_rev == 2436 MHCR_CHIP_REV_5751_A0 || 2437 bgep->chipid.asic_rev == 2438 MHCR_CHIP_REV_5721_A0 || 2439 bgep->chipid.asic_rev == 2440 MHCR_CHIP_REV_5755_A0) { 2441 val32 = bge_reg_get32(bgep, 2442 PHY_TEST_CTRL_REG); 2443 if (val32 == (PHY_PCIE_SCRAM_MODE | 2444 PHY_PCIE_LTASS_MODE)) 2445 bge_reg_put32(bgep, 2446 PHY_TEST_CTRL_REG, 2447 PHY_PCIE_SCRAM_MODE); 2448 val32 = pci_config_get32 2449 (bgep->cfg_handle, 2450 PCI_CONF_BGE_CLKCTL); 2451 val32 |= CLKCTL_PCIE_A0_FIX; 2452 pci_config_put32(bgep->cfg_handle, 2453 PCI_CONF_BGE_CLKCTL, val32); 2454 } 2455 bge_reg_set32(bgep, regno, 2456 MISC_CONFIG_GRC_RESET_DISABLE); 2457 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2458 } 2459 } 2460 2461 /* 2462 * Special case - causes Core reset 2463 * 2464 * On SPARC v9 we want to ensure that we don't start 2465 * timing until the I/O access has actually reached 2466 * the chip, otherwise we might make the next access 2467 * too early. And we can't just force the write out 2468 * by following it with a read (even to config space) 2469 * because that would cause the fault we're trying 2470 * to avoid. Hence the need for membar_sync() here. 2471 */ 2472 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2473 #ifdef __sparcv9 2474 membar_sync(); 2475 #endif /* __sparcv9 */ 2476 /* 2477 * On some platforms,system need about 300us for 2478 * link setup. 2479 */ 2480 drv_usecwait(300); 2481 2482 if (bgep->chipid.pci_type == BGE_PCI_E) { 2483 /* PCI-E device need more reset time */ 2484 drv_usecwait(120000); 2485 2486 /* Set PCIE max payload size and clear error status. */ 2487 if ((bgep->chipid.chip_label == 5721) || 2488 (bgep->chipid.chip_label == 5751) || 2489 (bgep->chipid.chip_label == 5752) || 2490 (bgep->chipid.chip_label == 5789)) { 2491 pci_config_put16(bgep->cfg_handle, 2492 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2493 pci_config_put16(bgep->cfg_handle, 2494 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2495 } 2496 } 2497 2498 BGE_PCICHK(bgep); 2499 return (B_TRUE); 2500 2501 default: 2502 bge_reg_put32(bgep, regno, regval); 2503 return (bge_chip_poll_engine(bgep, regno, 2504 STATE_MACHINE_RESET_BIT, 0)); 2505 } 2506 } 2507 2508 /* 2509 * Various registers that control the chip's internal engines (state 2510 * machines) have an <enable> bit (fortunately, in the same place in 2511 * each such register :-). To stop the state machine, this bit must 2512 * be written with 0, then polled to see when the state machine has 2513 * actually stopped. 2514 * 2515 * The return value is B_TRUE on success (enable bit cleared), or 2516 * B_FALSE if the state machine didn't stop :( 2517 */ 2518 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2519 uint32_t morebits); 2520 #pragma no_inline(bge_chip_disable_engine) 2521 2522 static boolean_t 2523 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2524 { 2525 uint32_t regval; 2526 2527 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2528 (void *)bgep, regno, morebits)); 2529 2530 switch (regno) { 2531 case FTQ_RESET_REG: 2532 /* 2533 * For Schumacher's bugfix CR6490108 2534 */ 2535 #ifdef BGE_IPMI_ASF 2536 #ifdef BGE_NETCONSOLE 2537 if (bgep->asf_enabled) 2538 return (B_TRUE); 2539 #endif 2540 #endif 2541 /* 2542 * Not quite like the others; it doesn't 2543 * have an <enable> bit, but instead we 2544 * have to set and then clear all the bits 2545 */ 2546 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2547 drv_usecwait(100); 2548 bge_reg_put32(bgep, regno, 0); 2549 return (B_TRUE); 2550 2551 default: 2552 regval = bge_reg_get32(bgep, regno); 2553 regval &= ~STATE_MACHINE_ENABLE_BIT; 2554 regval &= ~morebits; 2555 bge_reg_put32(bgep, regno, regval); 2556 return (bge_chip_poll_engine(bgep, regno, 2557 STATE_MACHINE_ENABLE_BIT, 0)); 2558 } 2559 } 2560 2561 /* 2562 * Various registers that control the chip's internal engines (state 2563 * machines) have an <enable> bit (fortunately, in the same place in 2564 * each such register :-). To start the state machine, this bit must 2565 * be written with 1, then polled to see when the state machine has 2566 * actually started. 2567 * 2568 * The return value is B_TRUE on success (enable bit set), or 2569 * B_FALSE if the state machine didn't start :( 2570 */ 2571 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2572 uint32_t morebits); 2573 #pragma no_inline(bge_chip_enable_engine) 2574 2575 static boolean_t 2576 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2577 { 2578 uint32_t regval; 2579 2580 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2581 (void *)bgep, regno, morebits)); 2582 2583 switch (regno) { 2584 case FTQ_RESET_REG: 2585 #ifdef BGE_IPMI_ASF 2586 #ifdef BGE_NETCONSOLE 2587 if (bgep->asf_enabled) 2588 return (B_TRUE); 2589 #endif 2590 #endif 2591 /* 2592 * Not quite like the others; it doesn't 2593 * have an <enable> bit, but instead we 2594 * have to set and then clear all the bits 2595 */ 2596 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2597 drv_usecwait(100); 2598 bge_reg_put32(bgep, regno, 0); 2599 return (B_TRUE); 2600 2601 default: 2602 regval = bge_reg_get32(bgep, regno); 2603 regval |= STATE_MACHINE_ENABLE_BIT; 2604 regval |= morebits; 2605 bge_reg_put32(bgep, regno, regval); 2606 return (bge_chip_poll_engine(bgep, regno, 2607 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2608 } 2609 } 2610 2611 /* 2612 * Reprogram the Ethernet, Transmit, and Receive MAC 2613 * modes to match the param_* variables 2614 */ 2615 void bge_sync_mac_modes(bge_t *bgep); 2616 #pragma no_inline(bge_sync_mac_modes) 2617 2618 void 2619 bge_sync_mac_modes(bge_t *bgep) 2620 { 2621 uint32_t macmode; 2622 uint32_t regval; 2623 2624 ASSERT(mutex_owned(bgep->genlock)); 2625 2626 /* 2627 * Reprogram the Ethernet MAC mode ... 2628 */ 2629 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2630 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2631 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2632 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2633 else 2634 macmode |= ETHERNET_MODE_LINK_POLARITY; 2635 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2636 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2637 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2638 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2639 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2640 macmode |= ETHERNET_MODE_PORTMODE_MII; 2641 else 2642 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2643 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2644 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2645 else 2646 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2647 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2648 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2649 else 2650 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2651 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2652 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2653 (void *)bgep, regval, macmode)); 2654 2655 /* 2656 * ... the Transmit MAC mode ... 2657 */ 2658 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2659 if (bgep->param_link_tx_pause) 2660 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2661 else 2662 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2663 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2664 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2665 (void *)bgep, regval, macmode)); 2666 2667 /* 2668 * ... and the Receive MAC mode 2669 */ 2670 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2671 if (bgep->param_link_rx_pause) 2672 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2673 else 2674 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2675 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2676 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2677 (void *)bgep, regval, macmode)); 2678 } 2679 2680 /* 2681 * bge_chip_sync() -- program the chip with the unicast MAC address, 2682 * the multicast hash table, the required level of promiscuity, and 2683 * the current loopback mode ... 2684 */ 2685 #ifdef BGE_IPMI_ASF 2686 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2687 #else 2688 int bge_chip_sync(bge_t *bgep); 2689 #endif 2690 #pragma no_inline(bge_chip_sync) 2691 2692 int 2693 #ifdef BGE_IPMI_ASF 2694 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2695 #else 2696 bge_chip_sync(bge_t *bgep) 2697 #endif 2698 { 2699 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2700 boolean_t promisc; 2701 uint64_t macaddr; 2702 uint32_t fill; 2703 int i, j; 2704 int retval = DDI_SUCCESS; 2705 2706 BGE_TRACE(("bge_chip_sync($%p)", 2707 (void *)bgep)); 2708 2709 ASSERT(mutex_owned(bgep->genlock)); 2710 2711 promisc = B_FALSE; 2712 fill = ~(uint32_t)0; 2713 2714 if (bgep->promisc) 2715 promisc = B_TRUE; 2716 else 2717 fill = (uint32_t)0; 2718 2719 /* 2720 * If the TX/RX MAC engines are already running, we should stop 2721 * them (and reset the RX engine) before changing the parameters. 2722 * If they're not running, this will have no effect ... 2723 * 2724 * NOTE: this is currently disabled by default because stopping 2725 * and restarting the Tx engine may cause an outgoing packet in 2726 * transit to be truncated. Also, stopping and restarting the 2727 * Rx engine seems to not work correctly on the 5705. Testing 2728 * has not (yet!) revealed any problems with NOT stopping and 2729 * restarting these engines (and Broadcom say their drivers don't 2730 * do this), but if it is found to cause problems, this variable 2731 * can be patched to re-enable the old behaviour ... 2732 */ 2733 if (bge_stop_start_on_sync) { 2734 #ifdef BGE_IPMI_ASF 2735 if (!bgep->asf_enabled) { 2736 if (!bge_chip_disable_engine(bgep, 2737 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2738 retval = DDI_FAILURE; 2739 } else { 2740 if (!bge_chip_disable_engine(bgep, 2741 RECEIVE_MAC_MODE_REG, 0)) 2742 retval = DDI_FAILURE; 2743 } 2744 #else 2745 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2746 RECEIVE_MODE_KEEP_VLAN_TAG)) 2747 retval = DDI_FAILURE; 2748 #endif 2749 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2750 retval = DDI_FAILURE; 2751 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2752 retval = DDI_FAILURE; 2753 } 2754 2755 /* 2756 * Reprogram the hashed multicast address table ... 2757 */ 2758 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2759 bge_reg_put32(bgep, MAC_HASH_REG(i), 0); 2760 2761 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2762 bge_reg_put32(bgep, MAC_HASH_REG(i), 2763 bgep->mcast_hash[i] | fill); 2764 2765 #ifdef BGE_IPMI_ASF 2766 if (!bgep->asf_enabled || !asf_keeplive) { 2767 #endif 2768 /* 2769 * Transform the MAC address(es) from host to chip format, then 2770 * reprogram the transmit random backoff seed and the unicast 2771 * MAC address(es) ... 2772 */ 2773 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2774 for (i = 0, fill = 0, macaddr = 0ull; 2775 i < ETHERADDRL; ++i) { 2776 macaddr <<= 8; 2777 macaddr |= bgep->curr_addr[j].addr[i]; 2778 fill += bgep->curr_addr[j].addr[i]; 2779 } 2780 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2781 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2782 } 2783 2784 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2785 (void *)bgep, macaddr)); 2786 #ifdef BGE_IPMI_ASF 2787 } 2788 #endif 2789 2790 /* 2791 * Set or clear the PROMISCUOUS mode bit 2792 */ 2793 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2794 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2795 2796 /* 2797 * Sync the rest of the MAC modes too ... 2798 */ 2799 bge_sync_mac_modes(bgep); 2800 2801 /* 2802 * Restart RX/TX MAC engines if required ... 2803 */ 2804 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2805 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2806 retval = DDI_FAILURE; 2807 #ifdef BGE_IPMI_ASF 2808 if (!bgep->asf_enabled) { 2809 if (!bge_chip_enable_engine(bgep, 2810 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2811 retval = DDI_FAILURE; 2812 } else { 2813 if (!bge_chip_enable_engine(bgep, 2814 RECEIVE_MAC_MODE_REG, 0)) 2815 retval = DDI_FAILURE; 2816 } 2817 #else 2818 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2819 RECEIVE_MODE_KEEP_VLAN_TAG)) 2820 retval = DDI_FAILURE; 2821 #endif 2822 } 2823 return (retval); 2824 } 2825 2826 /* 2827 * This array defines the sequence of state machine control registers 2828 * in which the <enable> bit must be cleared to bring the chip to a 2829 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2830 */ 2831 static bge_regno_t shutdown_engine_regs[] = { 2832 RECEIVE_MAC_MODE_REG, 2833 RCV_BD_INITIATOR_MODE_REG, 2834 RCV_LIST_PLACEMENT_MODE_REG, 2835 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2836 RCV_DATA_BD_INITIATOR_MODE_REG, 2837 RCV_DATA_COMPLETION_MODE_REG, 2838 RCV_BD_COMPLETION_MODE_REG, 2839 2840 SEND_BD_SELECTOR_MODE_REG, 2841 SEND_BD_INITIATOR_MODE_REG, 2842 SEND_DATA_INITIATOR_MODE_REG, 2843 READ_DMA_MODE_REG, 2844 SEND_DATA_COMPLETION_MODE_REG, 2845 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2846 SEND_BD_COMPLETION_MODE_REG, 2847 TRANSMIT_MAC_MODE_REG, 2848 2849 HOST_COALESCE_MODE_REG, 2850 WRITE_DMA_MODE_REG, 2851 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2852 FTQ_RESET_REG, /* special - see code */ 2853 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2854 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2855 BGE_REGNO_NONE /* terminator */ 2856 }; 2857 2858 /* 2859 * bge_chip_stop() -- stop all chip processing 2860 * 2861 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2862 * we've detected a problem internally; otherwise, this is a normal 2863 * (clean) stop (at user request i.e. the last STREAM has been closed). 2864 */ 2865 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2866 #pragma no_inline(bge_chip_stop) 2867 2868 void 2869 bge_chip_stop(bge_t *bgep, boolean_t fault) 2870 { 2871 bge_regno_t regno; 2872 bge_regno_t *rbp; 2873 boolean_t ok; 2874 2875 BGE_TRACE(("bge_chip_stop($%p)", 2876 (void *)bgep)); 2877 2878 ASSERT(mutex_owned(bgep->genlock)); 2879 2880 rbp = shutdown_engine_regs; 2881 /* 2882 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2883 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2884 * -ory arbiter should not be disabled. 2885 */ 2886 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2887 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2888 ok &= bge_chip_disable_engine(bgep, regno, 0); 2889 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2890 (regno != DMA_COMPLETION_MODE_REG) && 2891 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2892 (regno != BUFFER_MANAGER_MODE_REG) && 2893 (regno != MEMORY_ARBITER_MODE_REG)) 2894 ok &= bge_chip_disable_engine(bgep, 2895 regno, 0); 2896 } 2897 2898 if (!ok && !fault) 2899 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2900 2901 /* 2902 * Finally, disable (all) MAC events & clear the MAC status 2903 */ 2904 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2905 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2906 2907 /* 2908 * if we're stopping the chip because of a detected fault then do 2909 * appropriate actions 2910 */ 2911 if (fault) { 2912 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2913 bgep->bge_chip_state = BGE_CHIP_FAULT; 2914 if (!bgep->manual_reset) 2915 ddi_fm_service_impact(bgep->devinfo, 2916 DDI_SERVICE_LOST); 2917 if (bgep->bge_dma_error) { 2918 /* 2919 * need to free buffers in case the fault was 2920 * due to a memory error in a buffer - got to 2921 * do a fair bit of tidying first 2922 */ 2923 if (bgep->progress & PROGRESS_KSTATS) { 2924 bge_fini_kstats(bgep); 2925 bgep->progress &= ~PROGRESS_KSTATS; 2926 } 2927 if (bgep->progress & PROGRESS_INTR) { 2928 bge_intr_disable(bgep); 2929 rw_enter(bgep->errlock, RW_WRITER); 2930 bge_fini_rings(bgep); 2931 rw_exit(bgep->errlock); 2932 bgep->progress &= ~PROGRESS_INTR; 2933 } 2934 if (bgep->progress & PROGRESS_BUFS) { 2935 bge_free_bufs(bgep); 2936 bgep->progress &= ~PROGRESS_BUFS; 2937 } 2938 bgep->bge_dma_error = B_FALSE; 2939 } 2940 } 2941 } else 2942 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2943 } 2944 2945 /* 2946 * Poll for completion of chip's ROM firmware; also, at least on the 2947 * first time through, find and return the hardware MAC address, if any. 2948 */ 2949 static uint64_t bge_poll_firmware(bge_t *bgep); 2950 #pragma no_inline(bge_poll_firmware) 2951 2952 static uint64_t 2953 bge_poll_firmware(bge_t *bgep) 2954 { 2955 uint64_t magic; 2956 uint64_t mac; 2957 uint32_t gen; 2958 uint32_t i; 2959 2960 /* 2961 * Step 19: poll for firmware completion (GENCOMM port set 2962 * to the ones complement of T3_MAGIC_NUMBER). 2963 * 2964 * While we're at it, we also read the MAC address register; 2965 * at some stage the firmware will load this with the 2966 * factory-set value. 2967 * 2968 * When both the magic number and the MAC address are set, 2969 * we're done; but we impose a time limit of one second 2970 * (1000*1000us) in case the firmware fails in some fashion 2971 * or the SEEPROM that provides that MAC address isn't fitted. 2972 * 2973 * After the first time through (chip state != INITIAL), we 2974 * don't need the MAC address to be set (we've already got it 2975 * or not, from the first time), so we don't wait for it, but 2976 * we still have to wait for the T3_MAGIC_NUMBER. 2977 * 2978 * Note: the magic number is only a 32-bit quantity, but the NIC 2979 * memory is 64-bit (and big-endian) internally. Addressing the 2980 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2981 * it work correctly on both big- and little-endian hosts. 2982 */ 2983 for (i = 0; i < 1000; ++i) { 2984 drv_usecwait(1000); 2985 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2986 if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep)) 2987 drv_usecwait(100000); 2988 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2989 #ifdef BGE_IPMI_ASF 2990 if (!bgep->asf_enabled) { 2991 #endif 2992 if (gen != ~T3_MAGIC_NUMBER) 2993 continue; 2994 #ifdef BGE_IPMI_ASF 2995 } 2996 #endif 2997 if (mac != 0ULL) 2998 break; 2999 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 3000 break; 3001 } 3002 3003 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 3004 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 3005 (void *)bgep, gen, i)); 3006 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 3007 mac, magic)); 3008 3009 return (mac); 3010 } 3011 3012 /* 3013 * Maximum times of trying to get the NVRAM access lock 3014 * by calling bge_nvmem_acquire() 3015 */ 3016 #define MAX_TRY_NVMEM_ACQUIRE 10000 3017 3018 #ifdef BGE_IPMI_ASF 3019 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3020 #else 3021 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3022 #endif 3023 #pragma no_inline(bge_chip_reset) 3024 3025 int 3026 #ifdef BGE_IPMI_ASF 3027 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3028 #else 3029 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3030 #endif 3031 { 3032 chip_id_t chipid; 3033 uint64_t mac; 3034 uint64_t magic; 3035 uint32_t modeflags; 3036 uint32_t mhcr; 3037 uint32_t sx0; 3038 uint32_t i, tries; 3039 #ifdef BGE_IPMI_ASF 3040 uint32_t mailbox; 3041 #endif 3042 int retval = DDI_SUCCESS; 3043 3044 BGE_TRACE(("bge_chip_reset($%p, %d)", 3045 (void *)bgep, enable_dma)); 3046 3047 ASSERT(mutex_owned(bgep->genlock)); 3048 3049 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3050 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3051 3052 /* 3053 * Do we need to stop the chip cleanly before resetting? 3054 */ 3055 switch (bgep->bge_chip_state) { 3056 default: 3057 _NOTE(NOTREACHED) 3058 return (DDI_FAILURE); 3059 3060 case BGE_CHIP_INITIAL: 3061 case BGE_CHIP_STOPPED: 3062 case BGE_CHIP_RESET: 3063 break; 3064 3065 case BGE_CHIP_RUNNING: 3066 case BGE_CHIP_ERROR: 3067 case BGE_CHIP_FAULT: 3068 bge_chip_stop(bgep, B_FALSE); 3069 break; 3070 } 3071 3072 #ifdef BGE_IPMI_ASF 3073 if (bgep->asf_enabled) { 3074 #ifdef __sparc 3075 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3076 MHCR_ENABLE_TAGGED_STATUS_MODE | 3077 MHCR_MASK_INTERRUPT_MODE | 3078 MHCR_MASK_PCI_INT_OUTPUT | 3079 MHCR_CLEAR_INTERRUPT_INTA | 3080 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3081 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3082 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3083 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3084 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3085 MEMORY_ARBITER_ENABLE); 3086 #endif 3087 if (asf_mode == ASF_MODE_INIT) { 3088 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3089 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3090 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3091 } 3092 } 3093 #endif 3094 /* 3095 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3096 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3097 * 3098 * Before reset Core clock,it is 3099 * also required to initialize the Memory Arbiter as specified in step9 3100 * and Misc Host Control Register as specified in step-13 3101 * Step 4-5: reset Core clock & wait for completion 3102 * Steps 6-8: are done by bge_chip_cfg_init() 3103 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3104 */ 3105 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3106 retval = DDI_FAILURE; 3107 3108 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3109 MHCR_ENABLE_TAGGED_STATUS_MODE | 3110 MHCR_MASK_INTERRUPT_MODE | 3111 MHCR_MASK_PCI_INT_OUTPUT | 3112 MHCR_CLEAR_INTERRUPT_INTA; 3113 #ifdef _BIG_ENDIAN 3114 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3115 #endif /* _BIG_ENDIAN */ 3116 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3117 #ifdef BGE_IPMI_ASF 3118 if (bgep->asf_enabled) 3119 bgep->asf_wordswapped = B_FALSE; 3120 #endif 3121 /* 3122 * NVRAM Corruption Workaround 3123 */ 3124 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3125 if (bge_nvmem_acquire(bgep) != EAGAIN) 3126 break; 3127 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3128 BGE_DEBUG(("%s: fail to acquire nvram lock", 3129 bgep->ifname)); 3130 3131 #ifdef BGE_IPMI_ASF 3132 if (!bgep->asf_enabled) { 3133 #endif 3134 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3135 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3136 #ifdef BGE_IPMI_ASF 3137 } 3138 #endif 3139 3140 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3141 retval = DDI_FAILURE; 3142 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3143 3144 /* 3145 * Step 8a: This may belong elsewhere, but BCM5721 needs 3146 * a bit set to avoid a fifo overflow/underflow bug. 3147 */ 3148 if ((bgep->chipid.chip_label == 5721) || 3149 (bgep->chipid.chip_label == 5751) || 3150 (bgep->chipid.chip_label == 5752) || 3151 (bgep->chipid.chip_label == 5755) || 3152 (bgep->chipid.chip_label == 5789)) 3153 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3154 3155 3156 /* 3157 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3158 * not be changed. 3159 */ 3160 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3161 retval = DDI_FAILURE; 3162 3163 /* 3164 * Steps 10-11: configure PIO endianness options and 3165 * enable indirect register access -- already done 3166 * Steps 12-13: enable writing to the PCI state & clock 3167 * control registers -- not required; we aren't going to 3168 * use those features. 3169 * Steps 14-15: Configure DMA endianness options. See 3170 * the comments on the setting of the MHCR above. 3171 */ 3172 #ifdef _BIG_ENDIAN 3173 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3174 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3175 #else 3176 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3177 #endif /* _BIG_ENDIAN */ 3178 #ifdef BGE_IPMI_ASF 3179 if (bgep->asf_enabled) 3180 modeflags |= MODE_HOST_STACK_UP; 3181 #endif 3182 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3183 3184 #ifdef BGE_IPMI_ASF 3185 if (bgep->asf_enabled) { 3186 #ifdef __sparc 3187 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3188 MEMORY_ARBITER_ENABLE | 3189 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3190 #endif 3191 3192 #ifdef BGE_NETCONSOLE 3193 if (!bgep->asf_newhandshake) { 3194 if ((asf_mode == ASF_MODE_INIT) || 3195 (asf_mode == ASF_MODE_POST_INIT)) { 3196 bge_asf_post_reset_old_mode(bgep, 3197 BGE_INIT_RESET); 3198 } else { 3199 bge_asf_post_reset_old_mode(bgep, 3200 BGE_SHUTDOWN_RESET); 3201 } 3202 } 3203 #endif 3204 3205 /* Wait for NVRAM init */ 3206 i = 0; 3207 drv_usecwait(5000); 3208 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3209 3210 while ((mailbox != (uint32_t) 3211 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3212 (i < 10000)) { 3213 drv_usecwait(100); 3214 mailbox = bge_nic_get32(bgep, 3215 BGE_FIRMWARE_MAILBOX); 3216 i++; 3217 } 3218 3219 #ifndef BGE_NETCONSOLE 3220 if (!bgep->asf_newhandshake) { 3221 if ((asf_mode == ASF_MODE_INIT) || 3222 (asf_mode == ASF_MODE_POST_INIT)) { 3223 3224 bge_asf_post_reset_old_mode(bgep, 3225 BGE_INIT_RESET); 3226 } else { 3227 bge_asf_post_reset_old_mode(bgep, 3228 BGE_SHUTDOWN_RESET); 3229 } 3230 } 3231 #endif 3232 } 3233 #endif 3234 /* 3235 * Steps 16-17: poll for firmware completion 3236 */ 3237 mac = bge_poll_firmware(bgep); 3238 3239 /* 3240 * Step 18: enable external memory -- doesn't apply. 3241 * 3242 * However we take the opportunity to set the MLCR anyway, as 3243 * this register also controls the SEEPROM auto-access method 3244 * which we may want to use later ... 3245 * 3246 * The proper value here depends on the way the chip is wired 3247 * into the circuit board, as this register *also* controls which 3248 * of the "Miscellaneous I/O" pins are driven as outputs and the 3249 * values driven onto those pins! 3250 * 3251 * See also step 74 in the PRM ... 3252 */ 3253 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3254 bgep->chipid.bge_mlcr_default); 3255 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3256 3257 /* 3258 * Step 20: clear the Ethernet MAC mode register 3259 */ 3260 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3261 3262 /* 3263 * Step 21: restore cache-line-size, latency timer, and 3264 * subsystem ID registers to their original values (not 3265 * those read into the local structure <chipid>, 'cos 3266 * that was after they were cleared by the RESET). 3267 * 3268 * Note: the Subsystem Vendor/Device ID registers are not 3269 * directly writable in config space, so we use the shadow 3270 * copy in "Page Zero" of register space to restore them 3271 * both in one go ... 3272 */ 3273 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3274 bgep->chipid.clsize); 3275 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3276 bgep->chipid.latency); 3277 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3278 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3279 3280 /* 3281 * The SEND INDEX registers should be reset to zero by the 3282 * global chip reset; if they're not, there'll be trouble 3283 * later on. 3284 */ 3285 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3286 if (sx0 != 0) { 3287 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3288 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3289 retval = DDI_FAILURE; 3290 } 3291 3292 /* Enable MSI code */ 3293 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3294 bge_reg_set32(bgep, MSI_MODE_REG, 3295 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3296 3297 /* 3298 * On the first time through, save the factory-set MAC address 3299 * (if any). If bge_poll_firmware() above didn't return one 3300 * (from a chip register) consider looking in the attached NV 3301 * memory device, if any. Once we have it, we save it in both 3302 * register-image (64-bit) and byte-array forms. All-zero and 3303 * all-one addresses are not valid, and we refuse to stash those. 3304 */ 3305 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3306 if (mac == 0ULL) 3307 mac = bge_get_nvmac(bgep); 3308 if (mac != 0ULL && mac != ~0ULL) { 3309 bgep->chipid.hw_mac_addr = mac; 3310 for (i = ETHERADDRL; i-- != 0; ) { 3311 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3312 mac >>= 8; 3313 } 3314 bgep->chipid.vendor_addr.set = B_TRUE; 3315 } 3316 } 3317 3318 #ifdef BGE_IPMI_ASF 3319 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3320 if (asf_mode != ASF_MODE_NONE) { 3321 if ((asf_mode == ASF_MODE_INIT) || 3322 (asf_mode == ASF_MODE_POST_INIT)) { 3323 3324 bge_asf_post_reset_new_mode(bgep, 3325 BGE_INIT_RESET); 3326 } else { 3327 bge_asf_post_reset_new_mode(bgep, 3328 BGE_SHUTDOWN_RESET); 3329 } 3330 } 3331 } 3332 #endif 3333 3334 /* 3335 * Record the new state 3336 */ 3337 bgep->chip_resets += 1; 3338 bgep->bge_chip_state = BGE_CHIP_RESET; 3339 return (retval); 3340 } 3341 3342 /* 3343 * bge_chip_start() -- start the chip transmitting and/or receiving, 3344 * including enabling interrupts 3345 */ 3346 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3347 #pragma no_inline(bge_chip_start) 3348 3349 int 3350 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3351 { 3352 uint32_t coalmode; 3353 uint32_t ledctl; 3354 uint32_t mtu; 3355 uint32_t maxring; 3356 uint32_t stats_mask; 3357 uint32_t dma_wrprio; 3358 uint64_t ring; 3359 int retval = DDI_SUCCESS; 3360 3361 BGE_TRACE(("bge_chip_start($%p)", 3362 (void *)bgep)); 3363 3364 ASSERT(mutex_owned(bgep->genlock)); 3365 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3366 3367 /* 3368 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3369 * The document specifies 95 separate steps to fully 3370 * initialise the chip!!!! 3371 * 3372 * The reset code above has already got us as far as step 3373 * 21, so we continue with ... 3374 * 3375 * Step 22: clear the MAC statistics block 3376 * (0x0300-0x0aff in NIC-local memory) 3377 */ 3378 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3379 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3380 NIC_MEM_STATISTICS_SIZE); 3381 3382 /* 3383 * Step 23: clear the status block (in host memory) 3384 */ 3385 DMA_ZERO(bgep->status_block); 3386 3387 /* 3388 * Step 24: set DMA read/write control register 3389 */ 3390 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3391 bgep->chipid.bge_dma_rwctrl); 3392 3393 /* 3394 * Step 25: Configure DMA endianness -- already done (16/17) 3395 * Step 26: Configure Host-Based Send Rings 3396 * Step 27: Indicate Host Stack Up 3397 */ 3398 bge_reg_set32(bgep, MODE_CONTROL_REG, 3399 MODE_HOST_SEND_BDS | 3400 MODE_HOST_STACK_UP); 3401 3402 /* 3403 * Step 28: Configure checksum options: 3404 * Solaris supports the hardware default checksum options. 3405 * 3406 * Workaround for Incorrect pseudo-header checksum calculation. 3407 */ 3408 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3409 bge_reg_set32(bgep, MODE_CONTROL_REG, 3410 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3411 3412 /* 3413 * Step 29: configure Timer Prescaler. The value is always the 3414 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3415 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3416 * for the whole chip! 3417 */ 3418 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3419 3420 /* 3421 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3422 * 3423 * If the mbuf_length is specified as 0, we just leave these at 3424 * their hardware defaults, rather than explicitly setting them. 3425 * As the Broadcom HRM,driver better not change the parameters 3426 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3427 */ 3428 if ((bgep->chipid.mbuf_length != 0) && 3429 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3430 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3431 bgep->chipid.mbuf_base); 3432 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3433 bgep->chipid.mbuf_length); 3434 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3435 DMAD_POOL_BASE_DEFAULT); 3436 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3437 DMAD_POOL_LENGTH_DEFAULT); 3438 } 3439 3440 /* 3441 * Step 32: configure MAC memory pool watermarks 3442 */ 3443 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3444 bgep->chipid.mbuf_lo_water_rdma); 3445 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3446 bgep->chipid.mbuf_lo_water_rmac); 3447 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3448 bgep->chipid.mbuf_hi_water); 3449 3450 /* 3451 * Step 33: configure DMA resource watermarks 3452 */ 3453 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3454 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3455 bge_dmad_lo_water); 3456 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3457 bge_dmad_hi_water); 3458 } 3459 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3460 3461 /* 3462 * Steps 34-36: enable buffer manager & internal h/w queues 3463 */ 3464 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3465 STATE_MACHINE_ATTN_ENABLE_BIT)) 3466 retval = DDI_FAILURE; 3467 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3468 retval = DDI_FAILURE; 3469 3470 /* 3471 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3472 */ 3473 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3474 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3475 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3476 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3477 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3478 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3479 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3480 } 3481 3482 /* 3483 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3484 */ 3485 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3486 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3487 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3488 bge_replenish_jumbo); 3489 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3490 bge_replenish_mini); 3491 } 3492 3493 /* 3494 * Steps 41-43: clear Send Ring Producer Indices and initialise 3495 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3496 */ 3497 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3498 maxring = BGE_SEND_RINGS_MAX; 3499 else 3500 maxring = BGE_SEND_RINGS_MAX_5705; 3501 for (ring = 0; ring < maxring; ++ring) { 3502 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3503 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3504 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3505 &bgep->send[ring].hw_rcb); 3506 } 3507 3508 /* 3509 * Steps 44-45: initialise Receive Return Rings 3510 * (0x0200-0x02ff in NIC-local memory) 3511 */ 3512 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3513 maxring = BGE_RECV_RINGS_MAX; 3514 else 3515 maxring = BGE_RECV_RINGS_MAX_5705; 3516 for (ring = 0; ring < maxring; ++ring) 3517 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3518 &bgep->recv[ring].hw_rcb); 3519 3520 /* 3521 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3522 */ 3523 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3524 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3525 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3526 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3527 } 3528 /* 3529 * Step 47: configure the MAC unicast address 3530 * Step 48: configure the random backoff seed 3531 * Step 96: set up multicast filters 3532 */ 3533 #ifdef BGE_IPMI_ASF 3534 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3535 #else 3536 if (bge_chip_sync(bgep) == DDI_FAILURE) 3537 #endif 3538 retval = DDI_FAILURE; 3539 3540 /* 3541 * Step 49: configure the MTU 3542 */ 3543 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3544 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3545 3546 /* 3547 * Step 50: configure the IPG et al 3548 */ 3549 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3550 3551 /* 3552 * Step 51: configure the default Rx Return Ring 3553 */ 3554 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3555 3556 /* 3557 * Steps 52-54: configure Receive List Placement, 3558 * and enable Receive List Placement Statistics 3559 */ 3560 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3561 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3562 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3563 case MHCR_CHIP_ASIC_REV_5700: 3564 case MHCR_CHIP_ASIC_REV_5701: 3565 case MHCR_CHIP_ASIC_REV_5703: 3566 case MHCR_CHIP_ASIC_REV_5704: 3567 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3568 break; 3569 case MHCR_CHIP_ASIC_REV_5705: 3570 break; 3571 default: 3572 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3573 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3574 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3575 break; 3576 } 3577 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3578 3579 if (bgep->chipid.rx_rings > 1) 3580 bge_init_recv_rule(bgep); 3581 3582 /* 3583 * Steps 55-56: enable Send Data Initiator Statistics 3584 */ 3585 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3586 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3587 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3588 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3589 } else { 3590 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3591 SEND_INIT_STATS_ENABLE); 3592 } 3593 /* 3594 * Steps 57-58: stop (?) the Host Coalescing Engine 3595 */ 3596 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3597 retval = DDI_FAILURE; 3598 3599 /* 3600 * Steps 59-62: initialise Host Coalescing parameters 3601 */ 3602 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3603 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3604 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3605 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3606 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3607 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3608 bge_tx_count_intr); 3609 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3610 bge_tx_ticks_intr); 3611 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3612 bge_rx_count_intr); 3613 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3614 bge_rx_ticks_intr); 3615 } 3616 3617 /* 3618 * Steps 63-64: initialise status block & statistics 3619 * host memory addresses 3620 * The statistic block does not exist in some chipsets 3621 * Step 65: initialise Statistics Coalescing Tick Counter 3622 */ 3623 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3624 bgep->status_block.cookie.dmac_laddress); 3625 3626 /* 3627 * Steps 66-67: initialise status block & statistics 3628 * NIC-local memory addresses 3629 */ 3630 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3631 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3632 bgep->statistics.cookie.dmac_laddress); 3633 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3634 STATISTICS_TICKS_DEFAULT); 3635 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3636 NIC_MEM_STATUS_BLOCK); 3637 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3638 NIC_MEM_STATISTICS); 3639 } 3640 3641 /* 3642 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3643 * Completion Engine, the Receive List Placement Engine, and the 3644 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3645 * and BCM5715. 3646 */ 3647 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3648 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3649 coalmode = COALESCE_64_BYTE_STATUS; 3650 else 3651 coalmode = 0; 3652 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3653 retval = DDI_FAILURE; 3654 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3655 STATE_MACHINE_ATTN_ENABLE_BIT)) 3656 retval = DDI_FAILURE; 3657 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3658 retval = DDI_FAILURE; 3659 3660 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3661 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3662 STATE_MACHINE_ATTN_ENABLE_BIT)) 3663 retval = DDI_FAILURE; 3664 3665 /* 3666 * Step 72: Enable MAC DMA engines 3667 * Step 73: Clear & enable MAC statistics 3668 */ 3669 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3670 ETHERNET_MODE_ENABLE_FHDE | 3671 ETHERNET_MODE_ENABLE_RDE | 3672 ETHERNET_MODE_ENABLE_TDE); 3673 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3674 ETHERNET_MODE_ENABLE_TX_STATS | 3675 ETHERNET_MODE_ENABLE_RX_STATS | 3676 ETHERNET_MODE_CLEAR_TX_STATS | 3677 ETHERNET_MODE_CLEAR_RX_STATS); 3678 3679 /* 3680 * Step 74: configure the MLCR (Miscellaneous Local Control 3681 * Register); not required, as we set up the MLCR in step 10 3682 * (part of the reset code) above. 3683 * 3684 * Step 75: clear Interrupt Mailbox 0 3685 */ 3686 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3687 3688 /* 3689 * Steps 76-87: Gentlemen, start your engines ... 3690 * 3691 * Enable the DMA Completion Engine, the Write DMA Engine, 3692 * the Read DMA Engine, Receive Data Completion Engine, 3693 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3694 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3695 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3696 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3697 * 3698 * Beware exhaust fumes? 3699 */ 3700 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3701 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3702 retval = DDI_FAILURE; 3703 dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | 3704 ALL_DMA_ATTN_BITS; 3705 if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) == 3706 MHCR_CHIP_ASIC_REV_5755) { 3707 dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384; 3708 } 3709 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3710 dma_wrprio)) 3711 retval = DDI_FAILURE; 3712 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3713 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3714 retval = DDI_FAILURE; 3715 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3716 STATE_MACHINE_ATTN_ENABLE_BIT)) 3717 retval = DDI_FAILURE; 3718 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3719 if (!bge_chip_enable_engine(bgep, 3720 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3721 retval = DDI_FAILURE; 3722 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3723 retval = DDI_FAILURE; 3724 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3725 STATE_MACHINE_ATTN_ENABLE_BIT)) 3726 retval = DDI_FAILURE; 3727 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3728 RCV_BD_DISABLED_RING_ATTN)) 3729 retval = DDI_FAILURE; 3730 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3731 RCV_DATA_BD_ILL_RING_ATTN)) 3732 retval = DDI_FAILURE; 3733 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3734 retval = DDI_FAILURE; 3735 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3736 STATE_MACHINE_ATTN_ENABLE_BIT)) 3737 retval = DDI_FAILURE; 3738 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3739 STATE_MACHINE_ATTN_ENABLE_BIT)) 3740 retval = DDI_FAILURE; 3741 3742 /* 3743 * Step 88: download firmware -- doesn't apply 3744 * Steps 89-90: enable Transmit & Receive MAC Engines 3745 */ 3746 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3747 retval = DDI_FAILURE; 3748 #ifdef BGE_IPMI_ASF 3749 if (!bgep->asf_enabled) { 3750 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3751 RECEIVE_MODE_KEEP_VLAN_TAG)) 3752 retval = DDI_FAILURE; 3753 } else { 3754 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3755 retval = DDI_FAILURE; 3756 } 3757 #else 3758 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3759 RECEIVE_MODE_KEEP_VLAN_TAG)) 3760 retval = DDI_FAILURE; 3761 #endif 3762 3763 /* 3764 * Step 91: disable auto-polling of PHY status 3765 */ 3766 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3767 3768 /* 3769 * Step 92: configure D0 power state (not required) 3770 * Step 93: initialise LED control register () 3771 */ 3772 ledctl = LED_CONTROL_DEFAULT; 3773 switch (bgep->chipid.device) { 3774 case DEVICE_ID_5700: 3775 case DEVICE_ID_5700x: 3776 case DEVICE_ID_5701: 3777 /* 3778 * Switch to 5700 (MAC) mode on these older chips 3779 */ 3780 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3781 ledctl |= LED_CONTROL_LED_MODE_5700; 3782 break; 3783 3784 default: 3785 break; 3786 } 3787 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3788 3789 /* 3790 * Step 94: activate link 3791 */ 3792 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3793 3794 /* 3795 * Step 95: set up physical layer (PHY/SerDes) 3796 * restart autoneg (if required) 3797 */ 3798 if (reset_phys) 3799 if (bge_phys_update(bgep) == DDI_FAILURE) 3800 retval = DDI_FAILURE; 3801 3802 /* 3803 * Extra step (DSG): hand over all the Receive Buffers to the chip 3804 */ 3805 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3806 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3807 bgep->buff[ring].rf_next); 3808 3809 /* 3810 * MSI bits:The least significant MSI 16-bit word. 3811 * ISR will be triggered different. 3812 */ 3813 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3814 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3815 3816 /* 3817 * Extra step (DSG): select which interrupts are enabled 3818 * 3819 * Program the Ethernet MAC engine to signal attention on 3820 * Link Change events, then enable interrupts on MAC, DMA, 3821 * and FLOW attention signals. 3822 */ 3823 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3824 ETHERNET_EVENT_LINK_INT | 3825 ETHERNET_STATUS_PCS_ERROR_INT); 3826 #ifdef BGE_IPMI_ASF 3827 if (bgep->asf_enabled) { 3828 bge_reg_set32(bgep, MODE_CONTROL_REG, 3829 MODE_INT_ON_FLOW_ATTN | 3830 MODE_INT_ON_DMA_ATTN | 3831 MODE_HOST_STACK_UP| 3832 MODE_INT_ON_MAC_ATTN); 3833 } else { 3834 #endif 3835 bge_reg_set32(bgep, MODE_CONTROL_REG, 3836 MODE_INT_ON_FLOW_ATTN | 3837 MODE_INT_ON_DMA_ATTN | 3838 MODE_INT_ON_MAC_ATTN); 3839 #ifdef BGE_IPMI_ASF 3840 } 3841 #endif 3842 3843 /* 3844 * Step 97: enable PCI interrupts!!! 3845 */ 3846 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3847 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3848 MHCR_MASK_PCI_INT_OUTPUT); 3849 3850 /* 3851 * All done! 3852 */ 3853 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3854 return (retval); 3855 } 3856 3857 3858 /* 3859 * ========== Hardware interrupt handler ========== 3860 */ 3861 3862 #undef BGE_DBG 3863 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3864 3865 /* 3866 * Sync the status block, then atomically clear the specified bits in 3867 * the <flags-and-tag> field of the status block. 3868 * the <flags> word of the status block, returning the value of the 3869 * <tag> and the <flags> before the bits were cleared. 3870 */ 3871 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3872 #pragma inline(bge_status_sync) 3873 3874 static int 3875 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3876 { 3877 bge_status_t *bsp; 3878 int retval; 3879 3880 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3881 (void *)bgep, bits)); 3882 3883 ASSERT(bgep->bge_guard == BGE_GUARD); 3884 3885 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3886 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3887 if (retval != DDI_FM_OK) 3888 return (retval); 3889 3890 bsp = DMA_VPTR(bgep->status_block); 3891 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3892 3893 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3894 (void *)bgep, bits, *flags)); 3895 3896 return (retval); 3897 } 3898 3899 void bge_wake_factotum(bge_t *bgep); 3900 #pragma inline(bge_wake_factotum) 3901 3902 void 3903 bge_wake_factotum(bge_t *bgep) 3904 { 3905 mutex_enter(bgep->softintrlock); 3906 if (bgep->factotum_flag == 0) { 3907 bgep->factotum_flag = 1; 3908 ddi_trigger_softintr(bgep->factotum_id); 3909 } 3910 mutex_exit(bgep->softintrlock); 3911 } 3912 3913 /* 3914 * bge_intr() -- handle chip interrupts 3915 */ 3916 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3917 #pragma no_inline(bge_intr) 3918 3919 uint_t 3920 bge_intr(caddr_t arg1, caddr_t arg2) 3921 { 3922 bge_t *bgep = (void *)arg1; /* private device info */ 3923 bge_status_t *bsp; 3924 uint64_t flags; 3925 uint32_t regval; 3926 uint_t result; 3927 int retval, loop_cnt = 0; 3928 3929 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3930 3931 /* 3932 * GLD v2 checks that s/w setup is complete before passing 3933 * interrupts to this routine, thus eliminating the old 3934 * (and well-known) race condition around ddi_add_intr() 3935 */ 3936 ASSERT(bgep->progress & PROGRESS_HWINT); 3937 3938 result = DDI_INTR_UNCLAIMED; 3939 mutex_enter(bgep->genlock); 3940 3941 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3942 /* 3943 * Check whether chip's says it's asserting #INTA; 3944 * if not, don't process or claim the interrupt. 3945 * 3946 * Note that the PCI signal is active low, so the 3947 * bit is *zero* when the interrupt is asserted. 3948 */ 3949 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3950 if (regval & MLCR_INTA_STATE) { 3951 if (bge_check_acc_handle(bgep, bgep->io_handle) 3952 != DDI_FM_OK) 3953 goto chip_stop; 3954 mutex_exit(bgep->genlock); 3955 return (result); 3956 } 3957 3958 /* 3959 * Block further PCI interrupts ... 3960 */ 3961 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3962 MHCR_MASK_PCI_INT_OUTPUT); 3963 3964 } else { 3965 /* 3966 * Check MSI status 3967 */ 3968 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 3969 if (regval & MSI_ERROR_ATTENTION) { 3970 BGE_REPORT((bgep, "msi error attention," 3971 " status=0x%x", regval)); 3972 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 3973 } 3974 } 3975 3976 result = DDI_INTR_CLAIMED; 3977 3978 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 3979 3980 /* 3981 * Sync the status block and grab the flags-n-tag from it. 3982 * We count the number of interrupts where there doesn't 3983 * seem to have been a DMA update of the status block; if 3984 * it *has* been updated, the counter will be cleared in 3985 * the while() loop below ... 3986 */ 3987 bgep->missed_dmas += 1; 3988 bsp = DMA_VPTR(bgep->status_block); 3989 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 3990 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 3991 /* 3992 * bge_chip_stop() may have freed dma area etc 3993 * while we were in this interrupt handler - 3994 * better not call bge_status_sync() 3995 */ 3996 (void) bge_check_acc_handle(bgep, 3997 bgep->io_handle); 3998 mutex_exit(bgep->genlock); 3999 return (DDI_INTR_CLAIMED); 4000 } 4001 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 4002 &flags); 4003 if (retval != DDI_FM_OK) { 4004 bgep->bge_dma_error = B_TRUE; 4005 goto chip_stop; 4006 } 4007 4008 if (!(flags & STATUS_FLAG_UPDATED)) 4009 break; 4010 4011 /* 4012 * Tell the chip that we're processing the interrupt 4013 */ 4014 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4015 INTERRUPT_MBOX_DISABLE(flags)); 4016 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4017 DDI_FM_OK) 4018 goto chip_stop; 4019 4020 /* 4021 * Drop the mutex while we: 4022 * Receive any newly-arrived packets 4023 * Recycle any newly-finished send buffers 4024 */ 4025 bgep->bge_intr_running = B_TRUE; 4026 mutex_exit(bgep->genlock); 4027 bge_receive(bgep, bsp); 4028 bge_recycle(bgep, bsp); 4029 mutex_enter(bgep->genlock); 4030 bgep->bge_intr_running = B_FALSE; 4031 4032 /* 4033 * Tell the chip we've finished processing, and 4034 * give it the tag that we got from the status 4035 * block earlier, so that it knows just how far 4036 * we've gone. If it's got more for us to do, 4037 * it will now update the status block and try 4038 * to assert an interrupt (but we've got the 4039 * #INTA blocked at present). If we see the 4040 * update, we'll loop around to do some more. 4041 * Eventually we'll get out of here ... 4042 */ 4043 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4044 INTERRUPT_MBOX_ENABLE(flags)); 4045 if (bgep->chipid.pci_type == BGE_PCI_E) 4046 (void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG); 4047 bgep->missed_dmas = 0; 4048 } 4049 4050 /* 4051 * Check for exceptional conditions that we need to handle 4052 * 4053 * Link status changed 4054 * Status block not updated 4055 */ 4056 if (flags & STATUS_FLAG_LINK_CHANGED) 4057 bge_wake_factotum(bgep); 4058 4059 if (bgep->missed_dmas) { 4060 /* 4061 * Probably due to the internal status tag not 4062 * being reset. Force a status block update now; 4063 * this should ensure that we get an update and 4064 * a new interrupt. After that, we should be in 4065 * sync again ... 4066 */ 4067 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4068 "not updated?", flags)); 4069 bgep->missed_updates++; 4070 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4071 COALESCE_NOW); 4072 4073 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4074 /* 4075 * If this happens multiple times in a row, 4076 * it means DMA is just not working. Maybe 4077 * the chip's failed, or maybe there's a 4078 * problem on the PCI bus or in the host-PCI 4079 * bridge (Tomatillo). 4080 * 4081 * At all events, we want to stop further 4082 * interrupts and let the recovery code take 4083 * over to see whether anything can be done 4084 * about it ... 4085 */ 4086 bge_fm_ereport(bgep, 4087 DDI_FM_DEVICE_BADINT_LIMIT); 4088 goto chip_stop; 4089 } 4090 } 4091 4092 /* 4093 * Reenable assertion of #INTA, unless there's a DMA fault 4094 */ 4095 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4096 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4097 MHCR_MASK_PCI_INT_OUTPUT); 4098 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4099 DDI_FM_OK) 4100 goto chip_stop; 4101 } 4102 4103 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4104 goto chip_stop; 4105 4106 mutex_exit(bgep->genlock); 4107 return (result); 4108 4109 chip_stop: 4110 #ifdef BGE_IPMI_ASF 4111 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4112 /* 4113 * We must stop ASF heart beat before 4114 * bge_chip_stop(), otherwise some 4115 * computers (ex. IBM HS20 blade 4116 * server) may crash. 4117 */ 4118 bge_asf_update_status(bgep); 4119 bge_asf_stop_timer(bgep); 4120 bgep->asf_status = ASF_STAT_STOP; 4121 4122 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4123 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4124 } 4125 #endif 4126 bge_chip_stop(bgep, B_TRUE); 4127 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4128 mutex_exit(bgep->genlock); 4129 return (result); 4130 } 4131 4132 /* 4133 * ========== Factotum, implemented as a softint handler ========== 4134 */ 4135 4136 #undef BGE_DBG 4137 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4138 4139 static void bge_factotum_error_handler(bge_t *bgep); 4140 #pragma no_inline(bge_factotum_error_handler) 4141 4142 static void 4143 bge_factotum_error_handler(bge_t *bgep) 4144 { 4145 uint32_t flow; 4146 uint32_t rdma; 4147 uint32_t wdma; 4148 uint32_t tmac; 4149 uint32_t rmac; 4150 uint32_t rxrs; 4151 uint32_t txrs = 0; 4152 4153 ASSERT(mutex_owned(bgep->genlock)); 4154 4155 /* 4156 * Read all the registers that show the possible 4157 * reasons for the ERROR bit to be asserted 4158 */ 4159 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4160 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4161 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4162 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4163 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4164 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4165 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4166 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4167 4168 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4169 (void *)bgep, flow, rdma, wdma)); 4170 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4171 (void *)bgep, tmac, rmac, rxrs, txrs)); 4172 4173 /* 4174 * For now, just clear all the errors ... 4175 */ 4176 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4177 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4178 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4179 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4180 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4181 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4182 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4183 } 4184 4185 /* 4186 * Handler for hardware link state change. 4187 * 4188 * When this routine is called, the hardware link state has changed 4189 * and the new state is reflected in the param_* variables. Here 4190 * we must update the softstate and reprogram the MAC to match. 4191 */ 4192 static void bge_factotum_link_handler(bge_t *bgep); 4193 #pragma no_inline(bge_factotum_link_handler) 4194 4195 static void 4196 bge_factotum_link_handler(bge_t *bgep) 4197 { 4198 ASSERT(mutex_owned(bgep->genlock)); 4199 4200 /* 4201 * Update the s/w link_state 4202 */ 4203 if (bgep->param_link_up) 4204 bgep->link_state = LINK_STATE_UP; 4205 else 4206 bgep->link_state = LINK_STATE_DOWN; 4207 4208 /* 4209 * Reprogram the MAC modes to match 4210 */ 4211 bge_sync_mac_modes(bgep); 4212 } 4213 4214 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4215 #pragma no_inline(bge_factotum_link_check) 4216 4217 static boolean_t 4218 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4219 { 4220 boolean_t check; 4221 uint64_t flags; 4222 uint32_t tmac_status; 4223 4224 ASSERT(mutex_owned(bgep->genlock)); 4225 4226 /* 4227 * Get & clear the writable status bits in the Tx status register 4228 * (some bits are write-1-to-clear, others are just readonly). 4229 */ 4230 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4231 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4232 4233 /* 4234 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4235 */ 4236 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4237 STATUS_FLAG_LINK_CHANGED, &flags); 4238 if (*dma_state != DDI_FM_OK) 4239 return (B_FALSE); 4240 4241 /* 4242 * Clear any errors flagged in the status block ... 4243 */ 4244 if (flags & STATUS_FLAG_ERROR) 4245 bge_factotum_error_handler(bgep); 4246 4247 /* 4248 * We need to check the link status if: 4249 * the status block says there's been a link change 4250 * or there's any discrepancy between the various 4251 * flags indicating the link state (link_state, 4252 * param_link_up, and the LINK STATE bit in the 4253 * Transmit MAC status register). 4254 */ 4255 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4256 switch (bgep->link_state) { 4257 case LINK_STATE_UP: 4258 check |= (bgep->param_link_up == B_FALSE); 4259 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4260 break; 4261 4262 case LINK_STATE_DOWN: 4263 check |= (bgep->param_link_up != B_FALSE); 4264 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4265 break; 4266 4267 default: 4268 check = B_TRUE; 4269 break; 4270 } 4271 4272 /* 4273 * If <check> is false, we're sure the link hasn't changed. 4274 * If true, however, it's not yet definitive; we have to call 4275 * bge_phys_check() to determine whether the link has settled 4276 * into a new state yet ... and if it has, then call the link 4277 * state change handler.But when the chip is 5700 in Dell 6650 4278 * ,even if check is false, the link may have changed.So we 4279 * have to call bge_phys_check() to determine the link state. 4280 */ 4281 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4282 check = bge_phys_check(bgep); 4283 if (check) 4284 bge_factotum_link_handler(bgep); 4285 } 4286 4287 return (check); 4288 } 4289 4290 /* 4291 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4292 */ 4293 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4294 #pragma no_inline(bge_factotum_stall_check) 4295 4296 static boolean_t 4297 bge_factotum_stall_check(bge_t *bgep) 4298 { 4299 uint32_t dogval; 4300 4301 ASSERT(mutex_owned(bgep->genlock)); 4302 4303 /* 4304 * Specific check for Tx stall ... 4305 * 4306 * The 'watchdog' counter is incremented whenever a packet 4307 * is queued, reset to 1 when some (but not all) buffers 4308 * are reclaimed, reset to 0 (disabled) when all buffers 4309 * are reclaimed, and shifted left here. If it exceeds the 4310 * threshold value, the chip is assumed to have stalled and 4311 * is put into the ERROR state. The factotum will then reset 4312 * it on the next pass. 4313 * 4314 * All of which should ensure that we don't get into a state 4315 * where packets are left pending indefinitely! 4316 */ 4317 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4318 if (dogval < bge_watchdog_count) 4319 return (B_FALSE); 4320 4321 #if !defined(BGE_NETCONSOLE) 4322 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4323 #endif 4324 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4325 return (B_TRUE); 4326 } 4327 4328 /* 4329 * The factotum is woken up when there's something to do that we'd rather 4330 * not do from inside a hardware interrupt handler or high-level cyclic. 4331 * Its two main tasks are: 4332 * reset & restart the chip after an error 4333 * check the link status whenever necessary 4334 */ 4335 uint_t bge_chip_factotum(caddr_t arg); 4336 #pragma no_inline(bge_chip_factotum) 4337 4338 uint_t 4339 bge_chip_factotum(caddr_t arg) 4340 { 4341 bge_t *bgep; 4342 uint_t result; 4343 boolean_t error; 4344 boolean_t linkchg; 4345 int dma_state; 4346 4347 bgep = (void *)arg; 4348 4349 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4350 4351 mutex_enter(bgep->softintrlock); 4352 if (bgep->factotum_flag == 0) { 4353 mutex_exit(bgep->softintrlock); 4354 return (DDI_INTR_UNCLAIMED); 4355 } 4356 bgep->factotum_flag = 0; 4357 mutex_exit(bgep->softintrlock); 4358 4359 result = DDI_INTR_CLAIMED; 4360 error = B_FALSE; 4361 linkchg = B_FALSE; 4362 4363 mutex_enter(bgep->genlock); 4364 switch (bgep->bge_chip_state) { 4365 default: 4366 break; 4367 4368 case BGE_CHIP_RUNNING: 4369 linkchg = bge_factotum_link_check(bgep, &dma_state); 4370 error = bge_factotum_stall_check(bgep); 4371 if (dma_state != DDI_FM_OK) { 4372 bgep->bge_dma_error = B_TRUE; 4373 error = B_TRUE; 4374 } 4375 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4376 error = B_TRUE; 4377 if (error) 4378 bgep->bge_chip_state = BGE_CHIP_ERROR; 4379 break; 4380 4381 case BGE_CHIP_ERROR: 4382 error = B_TRUE; 4383 break; 4384 4385 case BGE_CHIP_FAULT: 4386 /* 4387 * Fault detected, time to reset ... 4388 */ 4389 if (bge_autorecover) { 4390 if (!(bgep->progress & PROGRESS_BUFS)) { 4391 /* 4392 * if we can't allocate the ring buffers, 4393 * try later 4394 */ 4395 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4396 mutex_exit(bgep->genlock); 4397 return (result); 4398 } 4399 bgep->progress |= PROGRESS_BUFS; 4400 } 4401 if (!(bgep->progress & PROGRESS_INTR)) { 4402 bge_init_rings(bgep); 4403 bge_intr_enable(bgep); 4404 bgep->progress |= PROGRESS_INTR; 4405 } 4406 if (!(bgep->progress & PROGRESS_KSTATS)) { 4407 bge_init_kstats(bgep, 4408 ddi_get_instance(bgep->devinfo)); 4409 bgep->progress |= PROGRESS_KSTATS; 4410 } 4411 4412 BGE_REPORT((bgep, "automatic recovery activated")); 4413 4414 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4415 bgep->bge_chip_state = BGE_CHIP_ERROR; 4416 error = B_TRUE; 4417 } 4418 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4419 DDI_FM_OK) { 4420 bgep->bge_chip_state = BGE_CHIP_ERROR; 4421 error = B_TRUE; 4422 } 4423 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4424 DDI_FM_OK) { 4425 bgep->bge_chip_state = BGE_CHIP_ERROR; 4426 error = B_TRUE; 4427 } 4428 if (error == B_FALSE) { 4429 #ifdef BGE_IPMI_ASF 4430 if (bgep->asf_enabled && 4431 bgep->asf_status != ASF_STAT_RUN) { 4432 bgep->asf_timeout_id = timeout( 4433 bge_asf_heartbeat, (void *)bgep, 4434 drv_usectohz( 4435 BGE_ASF_HEARTBEAT_INTERVAL)); 4436 bgep->asf_status = ASF_STAT_RUN; 4437 } 4438 #endif 4439 if (!bgep->manual_reset) { 4440 ddi_fm_service_impact(bgep->devinfo, 4441 DDI_SERVICE_RESTORED); 4442 } 4443 } 4444 } 4445 break; 4446 } 4447 4448 4449 /* 4450 * If an error is detected, stop the chip now, marking it as 4451 * faulty, so that it will be reset next time through ... 4452 * 4453 * Note that if intr_running is set, then bge_intr() has dropped 4454 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4455 * this point so have to wait until the next time the factotum runs. 4456 */ 4457 if (error && !bgep->bge_intr_running) { 4458 #ifdef BGE_IPMI_ASF 4459 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4460 /* 4461 * We must stop ASF heart beat before bge_chip_stop(), 4462 * otherwise some computers (ex. IBM HS20 blade server) 4463 * may crash. 4464 */ 4465 bge_asf_update_status(bgep); 4466 bge_asf_stop_timer(bgep); 4467 bgep->asf_status = ASF_STAT_STOP; 4468 4469 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4470 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4471 } 4472 #endif 4473 bge_chip_stop(bgep, B_TRUE); 4474 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4475 } 4476 mutex_exit(bgep->genlock); 4477 4478 /* 4479 * If the link state changed, tell the world about it. 4480 * Note: can't do this while still holding the mutex. 4481 */ 4482 if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT && 4483 bgep->link_state != LINK_STATE_UNKNOWN) 4484 linkchg = B_TRUE; 4485 else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT && 4486 bgep->link_state == LINK_STATE_DOWN) 4487 linkchg = B_FALSE; 4488 4489 if (linkchg) { 4490 mac_link_update(bgep->mh, bgep->link_state); 4491 bgep->link_update_timer = BGE_LINK_UPDATE_DONE; 4492 } 4493 if (bgep->manual_reset) { 4494 bgep->manual_reset = B_FALSE; 4495 } 4496 4497 return (result); 4498 } 4499 4500 /* 4501 * High-level cyclic handler 4502 * 4503 * This routine schedules a (low-level) softint callback to the 4504 * factotum, and prods the chip to update the status block (which 4505 * will cause a hardware interrupt when complete). 4506 */ 4507 void bge_chip_cyclic(void *arg); 4508 #pragma no_inline(bge_chip_cyclic) 4509 4510 void 4511 bge_chip_cyclic(void *arg) 4512 { 4513 bge_t *bgep; 4514 4515 bgep = arg; 4516 4517 switch (bgep->bge_chip_state) { 4518 default: 4519 return; 4520 4521 case BGE_CHIP_RUNNING: 4522 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4523 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4524 ddi_fm_service_impact(bgep->devinfo, 4525 DDI_SERVICE_UNAFFECTED); 4526 4527 if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT) 4528 bgep->link_update_timer++; 4529 4530 break; 4531 4532 case BGE_CHIP_FAULT: 4533 case BGE_CHIP_ERROR: 4534 break; 4535 } 4536 4537 bge_wake_factotum(bgep); 4538 } 4539 4540 4541 /* 4542 * ========== Ioctl subfunctions ========== 4543 */ 4544 4545 #undef BGE_DBG 4546 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4547 4548 #if BGE_DEBUGGING || BGE_DO_PPIO 4549 4550 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4551 #pragma no_inline(bge_chip_peek_cfg) 4552 4553 static void 4554 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4555 { 4556 uint64_t regval; 4557 uint64_t regno; 4558 4559 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4560 (void *)bgep, (void *)ppd)); 4561 4562 regno = ppd->pp_acc_offset; 4563 4564 switch (ppd->pp_acc_size) { 4565 case 1: 4566 regval = pci_config_get8(bgep->cfg_handle, regno); 4567 break; 4568 4569 case 2: 4570 regval = pci_config_get16(bgep->cfg_handle, regno); 4571 break; 4572 4573 case 4: 4574 regval = pci_config_get32(bgep->cfg_handle, regno); 4575 break; 4576 4577 case 8: 4578 regval = pci_config_get64(bgep->cfg_handle, regno); 4579 break; 4580 } 4581 4582 ppd->pp_acc_data = regval; 4583 } 4584 4585 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4586 #pragma no_inline(bge_chip_poke_cfg) 4587 4588 static void 4589 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4590 { 4591 uint64_t regval; 4592 uint64_t regno; 4593 4594 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4595 (void *)bgep, (void *)ppd)); 4596 4597 regno = ppd->pp_acc_offset; 4598 regval = ppd->pp_acc_data; 4599 4600 switch (ppd->pp_acc_size) { 4601 case 1: 4602 pci_config_put8(bgep->cfg_handle, regno, regval); 4603 break; 4604 4605 case 2: 4606 pci_config_put16(bgep->cfg_handle, regno, regval); 4607 break; 4608 4609 case 4: 4610 pci_config_put32(bgep->cfg_handle, regno, regval); 4611 break; 4612 4613 case 8: 4614 pci_config_put64(bgep->cfg_handle, regno, regval); 4615 break; 4616 } 4617 } 4618 4619 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4620 #pragma no_inline(bge_chip_peek_reg) 4621 4622 static void 4623 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4624 { 4625 uint64_t regval; 4626 void *regaddr; 4627 4628 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4629 (void *)bgep, (void *)ppd)); 4630 4631 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4632 4633 switch (ppd->pp_acc_size) { 4634 case 1: 4635 regval = ddi_get8(bgep->io_handle, regaddr); 4636 break; 4637 4638 case 2: 4639 regval = ddi_get16(bgep->io_handle, regaddr); 4640 break; 4641 4642 case 4: 4643 regval = ddi_get32(bgep->io_handle, regaddr); 4644 break; 4645 4646 case 8: 4647 regval = ddi_get64(bgep->io_handle, regaddr); 4648 break; 4649 } 4650 4651 ppd->pp_acc_data = regval; 4652 } 4653 4654 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4655 #pragma no_inline(bge_chip_peek_reg) 4656 4657 static void 4658 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4659 { 4660 uint64_t regval; 4661 void *regaddr; 4662 4663 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4664 (void *)bgep, (void *)ppd)); 4665 4666 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4667 regval = ppd->pp_acc_data; 4668 4669 switch (ppd->pp_acc_size) { 4670 case 1: 4671 ddi_put8(bgep->io_handle, regaddr, regval); 4672 break; 4673 4674 case 2: 4675 ddi_put16(bgep->io_handle, regaddr, regval); 4676 break; 4677 4678 case 4: 4679 ddi_put32(bgep->io_handle, regaddr, regval); 4680 break; 4681 4682 case 8: 4683 ddi_put64(bgep->io_handle, regaddr, regval); 4684 break; 4685 } 4686 BGE_PCICHK(bgep); 4687 } 4688 4689 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4690 #pragma no_inline(bge_chip_peek_nic) 4691 4692 static void 4693 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4694 { 4695 uint64_t regoff; 4696 uint64_t regval; 4697 void *regaddr; 4698 4699 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4700 (void *)bgep, (void *)ppd)); 4701 4702 regoff = ppd->pp_acc_offset; 4703 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4704 regoff &= MWBAR_GRANULE_MASK; 4705 regoff += NIC_MEM_WINDOW_OFFSET; 4706 regaddr = PIO_ADDR(bgep, regoff); 4707 4708 switch (ppd->pp_acc_size) { 4709 case 1: 4710 regval = ddi_get8(bgep->io_handle, regaddr); 4711 break; 4712 4713 case 2: 4714 regval = ddi_get16(bgep->io_handle, regaddr); 4715 break; 4716 4717 case 4: 4718 regval = ddi_get32(bgep->io_handle, regaddr); 4719 break; 4720 4721 case 8: 4722 regval = ddi_get64(bgep->io_handle, regaddr); 4723 break; 4724 } 4725 4726 ppd->pp_acc_data = regval; 4727 } 4728 4729 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4730 #pragma no_inline(bge_chip_poke_nic) 4731 4732 static void 4733 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4734 { 4735 uint64_t regoff; 4736 uint64_t regval; 4737 void *regaddr; 4738 4739 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4740 (void *)bgep, (void *)ppd)); 4741 4742 regoff = ppd->pp_acc_offset; 4743 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4744 regoff &= MWBAR_GRANULE_MASK; 4745 regoff += NIC_MEM_WINDOW_OFFSET; 4746 regaddr = PIO_ADDR(bgep, regoff); 4747 regval = ppd->pp_acc_data; 4748 4749 switch (ppd->pp_acc_size) { 4750 case 1: 4751 ddi_put8(bgep->io_handle, regaddr, regval); 4752 break; 4753 4754 case 2: 4755 ddi_put16(bgep->io_handle, regaddr, regval); 4756 break; 4757 4758 case 4: 4759 ddi_put32(bgep->io_handle, regaddr, regval); 4760 break; 4761 4762 case 8: 4763 ddi_put64(bgep->io_handle, regaddr, regval); 4764 break; 4765 } 4766 BGE_PCICHK(bgep); 4767 } 4768 4769 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4770 #pragma no_inline(bge_chip_peek_mii) 4771 4772 static void 4773 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4774 { 4775 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4776 (void *)bgep, (void *)ppd)); 4777 4778 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4779 } 4780 4781 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4782 #pragma no_inline(bge_chip_poke_mii) 4783 4784 static void 4785 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4786 { 4787 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4788 (void *)bgep, (void *)ppd)); 4789 4790 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4791 } 4792 4793 #if BGE_SEE_IO32 4794 4795 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4796 #pragma no_inline(bge_chip_peek_seeprom) 4797 4798 static void 4799 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4800 { 4801 uint32_t data; 4802 int err; 4803 4804 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4805 (void *)bgep, (void *)ppd)); 4806 4807 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4808 ppd->pp_acc_data = err ? ~0ull : data; 4809 } 4810 4811 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4812 #pragma no_inline(bge_chip_poke_seeprom) 4813 4814 static void 4815 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4816 { 4817 uint32_t data; 4818 4819 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4820 (void *)bgep, (void *)ppd)); 4821 4822 data = ppd->pp_acc_data; 4823 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4824 } 4825 #endif /* BGE_SEE_IO32 */ 4826 4827 #if BGE_FLASH_IO32 4828 4829 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4830 #pragma no_inline(bge_chip_peek_flash) 4831 4832 static void 4833 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4834 { 4835 uint32_t data; 4836 int err; 4837 4838 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4839 (void *)bgep, (void *)ppd)); 4840 4841 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4842 ppd->pp_acc_data = err ? ~0ull : data; 4843 } 4844 4845 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4846 #pragma no_inline(bge_chip_poke_flash) 4847 4848 static void 4849 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4850 { 4851 uint32_t data; 4852 4853 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4854 (void *)bgep, (void *)ppd)); 4855 4856 data = ppd->pp_acc_data; 4857 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4858 ppd->pp_acc_offset, &data); 4859 } 4860 #endif /* BGE_FLASH_IO32 */ 4861 4862 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4863 #pragma no_inline(bge_chip_peek_mem) 4864 4865 static void 4866 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4867 { 4868 uint64_t regval; 4869 void *vaddr; 4870 4871 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4872 (void *)bgep, (void *)ppd)); 4873 4874 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4875 4876 switch (ppd->pp_acc_size) { 4877 case 1: 4878 regval = *(uint8_t *)vaddr; 4879 break; 4880 4881 case 2: 4882 regval = *(uint16_t *)vaddr; 4883 break; 4884 4885 case 4: 4886 regval = *(uint32_t *)vaddr; 4887 break; 4888 4889 case 8: 4890 regval = *(uint64_t *)vaddr; 4891 break; 4892 } 4893 4894 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4895 (void *)bgep, (void *)ppd, regval, vaddr)); 4896 4897 ppd->pp_acc_data = regval; 4898 } 4899 4900 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4901 #pragma no_inline(bge_chip_poke_mem) 4902 4903 static void 4904 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4905 { 4906 uint64_t regval; 4907 void *vaddr; 4908 4909 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4910 (void *)bgep, (void *)ppd)); 4911 4912 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4913 regval = ppd->pp_acc_data; 4914 4915 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4916 (void *)bgep, (void *)ppd, regval, vaddr)); 4917 4918 switch (ppd->pp_acc_size) { 4919 case 1: 4920 *(uint8_t *)vaddr = (uint8_t)regval; 4921 break; 4922 4923 case 2: 4924 *(uint16_t *)vaddr = (uint16_t)regval; 4925 break; 4926 4927 case 4: 4928 *(uint32_t *)vaddr = (uint32_t)regval; 4929 break; 4930 4931 case 8: 4932 *(uint64_t *)vaddr = (uint64_t)regval; 4933 break; 4934 } 4935 } 4936 4937 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4938 struct iocblk *iocp); 4939 #pragma no_inline(bge_pp_ioctl) 4940 4941 static enum ioc_reply 4942 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4943 { 4944 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4945 bge_peekpoke_t *ppd; 4946 dma_area_t *areap; 4947 uint64_t sizemask; 4948 uint64_t mem_va; 4949 uint64_t maxoff; 4950 boolean_t peek; 4951 4952 switch (cmd) { 4953 default: 4954 /* NOTREACHED */ 4955 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4956 return (IOC_INVAL); 4957 4958 case BGE_PEEK: 4959 peek = B_TRUE; 4960 break; 4961 4962 case BGE_POKE: 4963 peek = B_FALSE; 4964 break; 4965 } 4966 4967 /* 4968 * Validate format of ioctl 4969 */ 4970 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4971 return (IOC_INVAL); 4972 if (mp->b_cont == NULL) 4973 return (IOC_INVAL); 4974 ppd = (void *)mp->b_cont->b_rptr; 4975 4976 /* 4977 * Validate request parameters 4978 */ 4979 switch (ppd->pp_acc_space) { 4980 default: 4981 return (IOC_INVAL); 4982 4983 case BGE_PP_SPACE_CFG: 4984 /* 4985 * Config space 4986 */ 4987 sizemask = 8|4|2|1; 4988 mem_va = 0; 4989 maxoff = PCI_CONF_HDR_SIZE; 4990 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4991 break; 4992 4993 case BGE_PP_SPACE_REG: 4994 /* 4995 * Memory-mapped I/O space 4996 */ 4997 sizemask = 8|4|2|1; 4998 mem_va = 0; 4999 maxoff = RIAAR_REGISTER_MAX; 5000 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 5001 break; 5002 5003 case BGE_PP_SPACE_NIC: 5004 /* 5005 * NIC on-chip memory 5006 */ 5007 sizemask = 8|4|2|1; 5008 mem_va = 0; 5009 maxoff = MWBAR_ONCHIP_MAX; 5010 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 5011 break; 5012 5013 case BGE_PP_SPACE_MII: 5014 /* 5015 * PHY's MII registers 5016 * NB: all PHY registers are two bytes, but the 5017 * addresses increment in ones (word addressing). 5018 * So we scale the address here, then undo the 5019 * transformation inside the peek/poke functions. 5020 */ 5021 ppd->pp_acc_offset *= 2; 5022 sizemask = 2; 5023 mem_va = 0; 5024 maxoff = (MII_MAXREG+1)*2; 5025 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5026 break; 5027 5028 #if BGE_SEE_IO32 5029 case BGE_PP_SPACE_SEEPROM: 5030 /* 5031 * Attached SEEPROM(s), if any. 5032 * NB: we use the high-order bits of the 'address' as 5033 * a device select to accommodate multiple SEEPROMS, 5034 * If each one is the maximum size (64kbytes), this 5035 * makes them appear contiguous. Otherwise, there may 5036 * be holes in the mapping. ENxS doesn't have any 5037 * SEEPROMs anyway ... 5038 */ 5039 sizemask = 4; 5040 mem_va = 0; 5041 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5042 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5043 break; 5044 #endif /* BGE_SEE_IO32 */ 5045 5046 #if BGE_FLASH_IO32 5047 case BGE_PP_SPACE_FLASH: 5048 /* 5049 * Attached Flash device (if any); a maximum of one device 5050 * is currently supported. But it can be up to 1MB (unlike 5051 * the 64k limit on SEEPROMs) so why would you need more ;-) 5052 */ 5053 sizemask = 4; 5054 mem_va = 0; 5055 maxoff = NVM_FLASH_ADDR_MASK; 5056 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5057 break; 5058 #endif /* BGE_FLASH_IO32 */ 5059 5060 case BGE_PP_SPACE_BGE: 5061 /* 5062 * BGE data structure! 5063 */ 5064 sizemask = 8|4|2|1; 5065 mem_va = (uintptr_t)bgep; 5066 maxoff = sizeof (*bgep); 5067 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5068 break; 5069 5070 case BGE_PP_SPACE_STATUS: 5071 case BGE_PP_SPACE_STATISTICS: 5072 case BGE_PP_SPACE_TXDESC: 5073 case BGE_PP_SPACE_TXBUFF: 5074 case BGE_PP_SPACE_RXDESC: 5075 case BGE_PP_SPACE_RXBUFF: 5076 /* 5077 * Various DMA_AREAs 5078 */ 5079 switch (ppd->pp_acc_space) { 5080 case BGE_PP_SPACE_TXDESC: 5081 areap = &bgep->tx_desc; 5082 break; 5083 case BGE_PP_SPACE_TXBUFF: 5084 areap = &bgep->tx_buff[0]; 5085 break; 5086 case BGE_PP_SPACE_RXDESC: 5087 areap = &bgep->rx_desc[0]; 5088 break; 5089 case BGE_PP_SPACE_RXBUFF: 5090 areap = &bgep->rx_buff[0]; 5091 break; 5092 case BGE_PP_SPACE_STATUS: 5093 areap = &bgep->status_block; 5094 break; 5095 case BGE_PP_SPACE_STATISTICS: 5096 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5097 areap = &bgep->statistics; 5098 break; 5099 } 5100 5101 sizemask = 8|4|2|1; 5102 mem_va = (uintptr_t)areap->mem_va; 5103 maxoff = areap->alength; 5104 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5105 break; 5106 } 5107 5108 switch (ppd->pp_acc_size) { 5109 default: 5110 return (IOC_INVAL); 5111 5112 case 8: 5113 case 4: 5114 case 2: 5115 case 1: 5116 if ((ppd->pp_acc_size & sizemask) == 0) 5117 return (IOC_INVAL); 5118 break; 5119 } 5120 5121 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5122 return (IOC_INVAL); 5123 5124 if (ppd->pp_acc_offset >= maxoff) 5125 return (IOC_INVAL); 5126 5127 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5128 return (IOC_INVAL); 5129 5130 /* 5131 * All OK - go do it! 5132 */ 5133 ppd->pp_acc_offset += mem_va; 5134 (*ppfn)(bgep, ppd); 5135 return (peek ? IOC_REPLY : IOC_ACK); 5136 } 5137 5138 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5139 struct iocblk *iocp); 5140 #pragma no_inline(bge_diag_ioctl) 5141 5142 static enum ioc_reply 5143 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5144 { 5145 ASSERT(mutex_owned(bgep->genlock)); 5146 5147 switch (cmd) { 5148 default: 5149 /* NOTREACHED */ 5150 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5151 return (IOC_INVAL); 5152 5153 case BGE_DIAG: 5154 /* 5155 * Currently a no-op 5156 */ 5157 return (IOC_ACK); 5158 5159 case BGE_PEEK: 5160 case BGE_POKE: 5161 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5162 5163 case BGE_PHY_RESET: 5164 return (IOC_RESTART_ACK); 5165 5166 case BGE_SOFT_RESET: 5167 case BGE_HARD_RESET: 5168 /* 5169 * Reset and reinitialise the 570x hardware 5170 */ 5171 bgep->bge_chip_state = BGE_CHIP_FAULT; 5172 ddi_trigger_softintr(bgep->factotum_id); 5173 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5174 return (IOC_ACK); 5175 } 5176 5177 /* NOTREACHED */ 5178 } 5179 5180 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5181 5182 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5183 struct iocblk *iocp); 5184 #pragma no_inline(bge_mii_ioctl) 5185 5186 static enum ioc_reply 5187 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5188 { 5189 struct bge_mii_rw *miirwp; 5190 5191 /* 5192 * Validate format of ioctl 5193 */ 5194 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5195 return (IOC_INVAL); 5196 if (mp->b_cont == NULL) 5197 return (IOC_INVAL); 5198 miirwp = (void *)mp->b_cont->b_rptr; 5199 5200 /* 5201 * Validate request parameters ... 5202 */ 5203 if (miirwp->mii_reg > MII_MAXREG) 5204 return (IOC_INVAL); 5205 5206 switch (cmd) { 5207 default: 5208 /* NOTREACHED */ 5209 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5210 return (IOC_INVAL); 5211 5212 case BGE_MII_READ: 5213 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5214 return (IOC_REPLY); 5215 5216 case BGE_MII_WRITE: 5217 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5218 return (IOC_ACK); 5219 } 5220 5221 /* NOTREACHED */ 5222 } 5223 5224 #if BGE_SEE_IO32 5225 5226 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5227 struct iocblk *iocp); 5228 #pragma no_inline(bge_see_ioctl) 5229 5230 static enum ioc_reply 5231 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5232 { 5233 struct bge_see_rw *seerwp; 5234 5235 /* 5236 * Validate format of ioctl 5237 */ 5238 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5239 return (IOC_INVAL); 5240 if (mp->b_cont == NULL) 5241 return (IOC_INVAL); 5242 seerwp = (void *)mp->b_cont->b_rptr; 5243 5244 /* 5245 * Validate request parameters ... 5246 */ 5247 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5248 return (IOC_INVAL); 5249 5250 switch (cmd) { 5251 default: 5252 /* NOTREACHED */ 5253 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5254 return (IOC_INVAL); 5255 5256 case BGE_SEE_READ: 5257 case BGE_SEE_WRITE: 5258 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5259 seerwp->see_addr, &seerwp->see_data); 5260 return (IOC_REPLY); 5261 } 5262 5263 /* NOTREACHED */ 5264 } 5265 5266 #endif /* BGE_SEE_IO32 */ 5267 5268 #if BGE_FLASH_IO32 5269 5270 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5271 struct iocblk *iocp); 5272 #pragma no_inline(bge_flash_ioctl) 5273 5274 static enum ioc_reply 5275 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5276 { 5277 struct bge_flash_rw *flashrwp; 5278 5279 /* 5280 * Validate format of ioctl 5281 */ 5282 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5283 return (IOC_INVAL); 5284 if (mp->b_cont == NULL) 5285 return (IOC_INVAL); 5286 flashrwp = (void *)mp->b_cont->b_rptr; 5287 5288 /* 5289 * Validate request parameters ... 5290 */ 5291 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5292 return (IOC_INVAL); 5293 5294 switch (cmd) { 5295 default: 5296 /* NOTREACHED */ 5297 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5298 return (IOC_INVAL); 5299 5300 case BGE_FLASH_READ: 5301 case BGE_FLASH_WRITE: 5302 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5303 flashrwp->flash_addr, &flashrwp->flash_data); 5304 return (IOC_REPLY); 5305 } 5306 5307 /* NOTREACHED */ 5308 } 5309 5310 #endif /* BGE_FLASH_IO32 */ 5311 5312 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5313 struct iocblk *iocp); 5314 #pragma no_inline(bge_chip_ioctl) 5315 5316 enum ioc_reply 5317 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5318 { 5319 int cmd; 5320 5321 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5322 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5323 5324 ASSERT(mutex_owned(bgep->genlock)); 5325 5326 cmd = iocp->ioc_cmd; 5327 switch (cmd) { 5328 default: 5329 /* NOTREACHED */ 5330 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5331 return (IOC_INVAL); 5332 5333 case BGE_DIAG: 5334 case BGE_PEEK: 5335 case BGE_POKE: 5336 case BGE_PHY_RESET: 5337 case BGE_SOFT_RESET: 5338 case BGE_HARD_RESET: 5339 #if BGE_DEBUGGING || BGE_DO_PPIO 5340 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5341 #else 5342 return (IOC_INVAL); 5343 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5344 5345 case BGE_MII_READ: 5346 case BGE_MII_WRITE: 5347 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5348 5349 #if BGE_SEE_IO32 5350 case BGE_SEE_READ: 5351 case BGE_SEE_WRITE: 5352 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5353 #endif /* BGE_SEE_IO32 */ 5354 5355 #if BGE_FLASH_IO32 5356 case BGE_FLASH_READ: 5357 case BGE_FLASH_WRITE: 5358 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5359 #endif /* BGE_FLASH_IO32 */ 5360 } 5361 5362 /* NOTREACHED */ 5363 } 5364 5365 void 5366 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5367 { 5368 bge_t *bgep = arg; 5369 5370 mutex_enter(bgep->genlock); 5371 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5372 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5373 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5374 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5375 mutex_exit(bgep->genlock); 5376 } 5377 5378 #ifdef BGE_IPMI_ASF 5379 5380 uint32_t 5381 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5382 { 5383 uint32_t data; 5384 5385 #ifndef __sparc 5386 if (!bgep->asf_wordswapped) { 5387 /* a workaround word swap error */ 5388 if (addr & 4) 5389 addr = addr - 4; 5390 else 5391 addr = addr + 4; 5392 } 5393 #endif 5394 5395 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5396 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5397 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5398 5399 data = LE_32(data); 5400 return (data); 5401 } 5402 5403 void 5404 bge_asf_update_status(bge_t *bgep) 5405 { 5406 uint32_t event; 5407 5408 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5409 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5410 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5411 5412 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5413 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5414 } 5415 5416 5417 /* 5418 * The driver is supposed to notify ASF that the OS is still running 5419 * every three seconds, otherwise the management server may attempt 5420 * to reboot the machine. If it hasn't actually failed, this is 5421 * not a desirable result. However, this isn't running as a real-time 5422 * thread, and even if it were, it might not be able to generate the 5423 * heartbeat in a timely manner due to system load. As it isn't a 5424 * significant strain on the machine, we will set the interval to half 5425 * of the required value. 5426 */ 5427 void 5428 bge_asf_heartbeat(void *arg) 5429 { 5430 bge_t *bgep = (bge_t *)arg; 5431 5432 mutex_enter(bgep->genlock); 5433 bge_asf_update_status((bge_t *)bgep); 5434 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5435 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5436 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5437 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5438 mutex_exit(bgep->genlock); 5439 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5440 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5441 } 5442 5443 5444 void 5445 bge_asf_stop_timer(bge_t *bgep) 5446 { 5447 timeout_id_t tmp_id = 0; 5448 5449 while ((bgep->asf_timeout_id != 0) && 5450 (tmp_id != bgep->asf_timeout_id)) { 5451 tmp_id = bgep->asf_timeout_id; 5452 (void) untimeout(tmp_id); 5453 } 5454 bgep->asf_timeout_id = 0; 5455 } 5456 5457 5458 5459 /* 5460 * This function should be placed at the earliest position of bge_attach(). 5461 */ 5462 void 5463 bge_asf_get_config(bge_t *bgep) 5464 { 5465 uint32_t nicsig; 5466 uint32_t niccfg; 5467 5468 bgep->asf_enabled = B_FALSE; 5469 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5470 if (nicsig == BGE_NIC_DATA_SIG) { 5471 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5472 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5473 /* 5474 * Here, we don't consider BAXTER, because BGE haven't 5475 * supported BAXTER (that is 5752). Also, as I know, 5476 * BAXTER doesn't support ASF feature. 5477 */ 5478 bgep->asf_enabled = B_TRUE; 5479 else 5480 bgep->asf_enabled = B_FALSE; 5481 } else 5482 bgep->asf_enabled = B_FALSE; 5483 } 5484 5485 5486 void 5487 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5488 { 5489 uint32_t tries; 5490 uint32_t event; 5491 5492 ASSERT(bgep->asf_enabled); 5493 5494 /* Issues "pause firmware" command and wait for ACK */ 5495 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5496 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5497 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5498 5499 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5500 tries = 0; 5501 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5502 drv_usecwait(1); 5503 tries ++; 5504 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5505 } 5506 5507 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5508 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5509 5510 if (bgep->asf_newhandshake) { 5511 switch (mode) { 5512 case BGE_INIT_RESET: 5513 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5514 BGE_DRV_STATE_START); 5515 break; 5516 case BGE_SHUTDOWN_RESET: 5517 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5518 BGE_DRV_STATE_UNLOAD); 5519 break; 5520 case BGE_SUSPEND_RESET: 5521 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5522 BGE_DRV_STATE_SUSPEND); 5523 break; 5524 default: 5525 break; 5526 } 5527 } 5528 } 5529 5530 5531 void 5532 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5533 { 5534 switch (mode) { 5535 case BGE_INIT_RESET: 5536 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5537 BGE_DRV_STATE_START); 5538 break; 5539 case BGE_SHUTDOWN_RESET: 5540 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5541 BGE_DRV_STATE_UNLOAD); 5542 break; 5543 case BGE_SUSPEND_RESET: 5544 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5545 BGE_DRV_STATE_SUSPEND); 5546 break; 5547 default: 5548 break; 5549 } 5550 } 5551 5552 5553 void 5554 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5555 { 5556 switch (mode) { 5557 case BGE_INIT_RESET: 5558 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5559 BGE_DRV_STATE_START_DONE); 5560 break; 5561 case BGE_SHUTDOWN_RESET: 5562 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5563 BGE_DRV_STATE_UNLOAD_DONE); 5564 break; 5565 default: 5566 break; 5567 } 5568 } 5569 5570 #endif /* BGE_IPMI_ASF */ 5571