1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include "bge_impl.h" 30 31 #define PIO_ADDR(bgep, offset) ((void *)((caddr_t)(bgep)->io_regs+(offset))) 32 33 /* 34 * Future features ... ? 35 */ 36 #define BGE_CFG_IO8 1 /* 8/16-bit cfg space BIS/BIC */ 37 #define BGE_IND_IO32 1 /* indirect access code */ 38 #define BGE_SEE_IO32 1 /* SEEPROM access code */ 39 #define BGE_FLASH_IO32 1 /* FLASH access code */ 40 41 /* 42 * BGE MSI tunable: 43 * 44 * By default MSI is enabled on all supported platforms but it is disabled 45 * for some Broadcom chips due to known MSI hardware issues. Currently MSI 46 * is enabled only for 5714C A2 and 5715C A2 broadcom chips. 47 */ 48 #if defined(__sparc) 49 boolean_t bge_enable_msi = B_TRUE; 50 #else 51 boolean_t bge_enable_msi = B_FALSE; 52 #endif 53 54 /* 55 * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver 56 */ 57 boolean_t bge_relaxed_ordering = B_TRUE; 58 59 /* 60 * Property names 61 */ 62 static char knownids_propname[] = "bge-known-subsystems"; 63 64 /* 65 * Patchable globals: 66 * 67 * bge_autorecover 68 * Enables/disables automatic recovery after fault detection 69 * 70 * bge_mlcr_default 71 * Value to program into the MLCR; controls the chip's GPIO pins 72 * 73 * bge_dma_{rd,wr}prio 74 * Relative priorities of DMA reads & DMA writes respectively. 75 * These may each be patched to any value 0-3. Equal values 76 * will give "fair" (round-robin) arbitration for PCI access. 77 * Unequal values will give one or the other function priority. 78 * 79 * bge_dma_rwctrl 80 * Value to put in the Read/Write DMA control register. See 81 * the Broadcom PRM for things you can fiddle with in this 82 * register ... 83 * 84 * bge_{tx,rx}_{count,ticks}_{norm,intr} 85 * Send/receive interrupt coalescing parameters. Counts are 86 * #s of descriptors, ticks are in microseconds. *norm* values 87 * apply between status updates/interrupts; the *intr* values 88 * refer to the 'during-interrupt' versions - see the PRM. 89 * 90 * NOTE: these values have been determined by measurement. They 91 * differ significantly from the values recommended in the PRM. 92 */ 93 static uint32_t bge_autorecover = 1; 94 static uint32_t bge_mlcr_default = MLCR_DEFAULT; 95 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714; 96 97 static uint32_t bge_dma_rdprio = 1; 98 static uint32_t bge_dma_wrprio = 0; 99 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT; 100 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721; 101 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714; 102 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715; 103 104 uint32_t bge_rx_ticks_norm = 128; 105 uint32_t bge_tx_ticks_norm = 2048; /* 8 for FJ2+ !?!? */ 106 uint32_t bge_rx_count_norm = 8; 107 uint32_t bge_tx_count_norm = 128; 108 109 static uint32_t bge_rx_ticks_intr = 128; 110 static uint32_t bge_tx_ticks_intr = 0; /* 8 for FJ2+ !?!? */ 111 static uint32_t bge_rx_count_intr = 2; 112 static uint32_t bge_tx_count_intr = 0; 113 114 /* 115 * Memory pool configuration parameters. 116 * 117 * These are generally specific to each member of the chip family, since 118 * each one may have a different memory size/configuration. 119 * 120 * Setting the mbuf pool length for a specific type of chip to 0 inhibits 121 * the driver from programming the various registers; instead they are left 122 * at their hardware defaults. This is the preferred option for later chips 123 * (5705+), whereas the older chips *required* these registers to be set, 124 * since the h/w default was 0 ;-( 125 */ 126 static uint32_t bge_mbuf_pool_base = MBUF_POOL_BASE_DEFAULT; 127 static uint32_t bge_mbuf_pool_base_5704 = MBUF_POOL_BASE_5704; 128 static uint32_t bge_mbuf_pool_base_5705 = MBUF_POOL_BASE_5705; 129 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721; 130 static uint32_t bge_mbuf_pool_len = MBUF_POOL_LENGTH_DEFAULT; 131 static uint32_t bge_mbuf_pool_len_5704 = MBUF_POOL_LENGTH_5704; 132 static uint32_t bge_mbuf_pool_len_5705 = 0; /* use h/w default */ 133 static uint32_t bge_mbuf_pool_len_5721 = 0; 134 135 /* 136 * Various high and low water marks, thresholds, etc ... 137 * 138 * Note: these are taken from revision 7 of the PRM, and some are different 139 * from both the values in earlier PRMs *and* those determined experimentally 140 * and used in earlier versions of this driver ... 141 */ 142 static uint32_t bge_mbuf_hi_water = MBUF_HIWAT_DEFAULT; 143 static uint32_t bge_mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_DEFAULT; 144 static uint32_t bge_mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_DEFAULT; 145 146 static uint32_t bge_dmad_lo_water = DMAD_POOL_LOWAT_DEFAULT; 147 static uint32_t bge_dmad_hi_water = DMAD_POOL_HIWAT_DEFAULT; 148 static uint32_t bge_lowat_recv_frames = LOWAT_MAX_RECV_FRAMES_DEFAULT; 149 150 static uint32_t bge_replenish_std = STD_RCV_BD_REPLENISH_DEFAULT; 151 static uint32_t bge_replenish_mini = MINI_RCV_BD_REPLENISH_DEFAULT; 152 static uint32_t bge_replenish_jumbo = JUMBO_RCV_BD_REPLENISH_DEFAULT; 153 154 static uint32_t bge_watchdog_count = 1 << 16; 155 static uint16_t bge_dma_miss_limit = 20; 156 157 static uint32_t bge_stop_start_on_sync = 0; 158 159 boolean_t bge_jumbo_enable = B_TRUE; 160 static uint32_t bge_default_jumbo_size = BGE_JUMBO_BUFF_SIZE; 161 162 /* 163 * bge_intr_max_loop controls the maximum loop number within bge_intr. 164 * When loading NIC with heavy network traffic, it is useful. 165 * Increasing this value could have positive effect to throughput, 166 * but it might also increase ticks of a bge ISR stick on CPU, which might 167 * lead to bad UI interactive experience. So tune this with caution. 168 */ 169 static int bge_intr_max_loop = 1; 170 171 /* 172 * ========== Low-level chip & ring buffer manipulation ========== 173 */ 174 175 #define BGE_DBG BGE_DBG_REGS /* debug flag for this code */ 176 177 178 /* 179 * Config space read-modify-write routines 180 */ 181 182 #if BGE_CFG_IO8 183 184 /* 185 * 8- and 16-bit set/clr operations are not used; all the config registers 186 * that we need to do bit-twiddling on are 32 bits wide. I'll leave the 187 * code here, though, in case we ever find that we do want it after all ... 188 */ 189 190 static void bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 191 #pragma inline(bge_cfg_set8) 192 193 static void 194 bge_cfg_set8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 195 { 196 uint8_t regval; 197 198 BGE_TRACE(("bge_cfg_set8($%p, 0x%lx, 0x%x)", 199 (void *)bgep, regno, bits)); 200 201 regval = pci_config_get8(bgep->cfg_handle, regno); 202 203 BGE_DEBUG(("bge_cfg_set8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 204 (void *)bgep, regno, bits, regval, regval | bits)); 205 206 regval |= bits; 207 pci_config_put8(bgep->cfg_handle, regno, regval); 208 } 209 210 static void bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits); 211 #pragma inline(bge_cfg_clr8) 212 213 static void 214 bge_cfg_clr8(bge_t *bgep, bge_regno_t regno, uint8_t bits) 215 { 216 uint8_t regval; 217 218 BGE_TRACE(("bge_cfg_clr8($%p, 0x%lx, 0x%x)", 219 (void *)bgep, regno, bits)); 220 221 regval = pci_config_get8(bgep->cfg_handle, regno); 222 223 BGE_DEBUG(("bge_cfg_clr8($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 224 (void *)bgep, regno, bits, regval, regval & ~bits)); 225 226 regval &= ~bits; 227 pci_config_put8(bgep->cfg_handle, regno, regval); 228 } 229 230 static void bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 231 #pragma inline(bge_cfg_set16) 232 233 static void 234 bge_cfg_set16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 235 { 236 uint16_t regval; 237 238 BGE_TRACE(("bge_cfg_set16($%p, 0x%lx, 0x%x)", 239 (void *)bgep, regno, bits)); 240 241 regval = pci_config_get16(bgep->cfg_handle, regno); 242 243 BGE_DEBUG(("bge_cfg_set16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 244 (void *)bgep, regno, bits, regval, regval | bits)); 245 246 regval |= bits; 247 pci_config_put16(bgep->cfg_handle, regno, regval); 248 } 249 250 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits); 251 #pragma inline(bge_cfg_clr16) 252 253 static void 254 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits) 255 { 256 uint16_t regval; 257 258 BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)", 259 (void *)bgep, regno, bits)); 260 261 regval = pci_config_get16(bgep->cfg_handle, regno); 262 263 BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 264 (void *)bgep, regno, bits, regval, regval & ~bits)); 265 266 regval &= ~bits; 267 pci_config_put16(bgep->cfg_handle, regno, regval); 268 } 269 270 #endif /* BGE_CFG_IO8 */ 271 272 static void bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 273 #pragma inline(bge_cfg_set32) 274 275 static void 276 bge_cfg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 277 { 278 uint32_t regval; 279 280 BGE_TRACE(("bge_cfg_set32($%p, 0x%lx, 0x%x)", 281 (void *)bgep, regno, bits)); 282 283 regval = pci_config_get32(bgep->cfg_handle, regno); 284 285 BGE_DEBUG(("bge_cfg_set32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 286 (void *)bgep, regno, bits, regval, regval | bits)); 287 288 regval |= bits; 289 pci_config_put32(bgep->cfg_handle, regno, regval); 290 } 291 292 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 293 #pragma inline(bge_cfg_clr32) 294 295 static void 296 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 297 { 298 uint32_t regval; 299 300 BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)", 301 (void *)bgep, regno, bits)); 302 303 regval = pci_config_get32(bgep->cfg_handle, regno); 304 305 BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x", 306 (void *)bgep, regno, bits, regval, regval & ~bits)); 307 308 regval &= ~bits; 309 pci_config_put32(bgep->cfg_handle, regno, regval); 310 } 311 312 #if BGE_IND_IO32 313 314 /* 315 * Indirect access to registers & RISC scratchpads, using config space 316 * accesses only. 317 * 318 * This isn't currently used, but someday we might want to use it for 319 * restoring the Subsystem Device/Vendor registers (which aren't directly 320 * writable in Config Space), or for downloading firmware into the RISCs 321 * 322 * In any case there are endian issues to be resolved before this code is 323 * enabled; the bizarre way that bytes get twisted by this chip AND by 324 * the PCI bridge in SPARC systems mean that we shouldn't enable it until 325 * it's been thoroughly tested for all access sizes on all supported 326 * architectures (SPARC *and* x86!). 327 */ 328 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno); 329 #pragma inline(bge_ind_get32) 330 331 uint32_t 332 bge_ind_get32(bge_t *bgep, bge_regno_t regno) 333 { 334 uint32_t val; 335 336 BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno)); 337 338 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 339 val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR); 340 341 BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x", 342 (void *)bgep, regno, val)); 343 344 val = LE_32(val); 345 346 return (val); 347 } 348 349 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val); 350 #pragma inline(bge_ind_put32) 351 352 void 353 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val) 354 { 355 BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)", 356 (void *)bgep, regno, val)); 357 358 val = LE_32(val); 359 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno); 360 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val); 361 } 362 363 #endif /* BGE_IND_IO32 */ 364 365 #if BGE_DEBUGGING 366 367 static void bge_pci_check(bge_t *bgep); 368 #pragma no_inline(bge_pci_check) 369 370 static void 371 bge_pci_check(bge_t *bgep) 372 { 373 uint16_t pcistatus; 374 375 pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT); 376 if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0) 377 BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x", 378 (void *)bgep, pcistatus)); 379 } 380 381 #endif /* BGE_DEBUGGING */ 382 383 /* 384 * Perform first-stage chip (re-)initialisation, using only config-space 385 * accesses: 386 * 387 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 388 * returning the data in the structure pointed to by <idp>. 389 * + Configure the target-mode endianness (swap) options. 390 * + Disable interrupts and enable Memory Space accesses. 391 * + Enable or disable Bus Mastering according to the <enable_dma> flag. 392 * 393 * This sequence is adapted from Broadcom document 570X-PG102-R, 394 * page 102, steps 1-3, 6-8 and 11-13. The omitted parts of the sequence 395 * are 4 and 5 (Reset Core and wait) which are handled elsewhere. 396 * 397 * This function MUST be called before any non-config-space accesses 398 * are made; on this first call <enable_dma> is B_FALSE, and it 399 * effectively performs steps 3-1(!) of the initialisation sequence 400 * (the rest are not required but should be harmless). 401 * 402 * It MUST also be called after a chip reset, as this disables 403 * Memory Space cycles! In this case, <enable_dma> is B_TRUE, and 404 * it is effectively performing steps 6-8. 405 */ 406 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma); 407 #pragma no_inline(bge_chip_cfg_init) 408 409 void 410 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma) 411 { 412 ddi_acc_handle_t handle; 413 uint16_t command; 414 uint32_t mhcr; 415 uint16_t value16; 416 int i; 417 418 BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)", 419 (void *)bgep, (void *)cidp, enable_dma)); 420 421 /* 422 * Step 3: save PCI cache line size and subsystem vendor ID 423 * 424 * Read all the config-space registers that characterise the 425 * chip, specifically vendor/device/revision/subsystem vendor 426 * and subsystem device id. We expect (but don't check) that 427 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704) 428 * 429 * Also save all bus-transaction related registers (cache-line 430 * size, bus-grant/latency parameters, etc). Some of these are 431 * cleared by reset, so we'll have to restore them later. This 432 * comes from the Broadcom document 570X-PG102-R ... 433 * 434 * Note: Broadcom document 570X-PG102-R seems to be in error 435 * here w.r.t. the offsets of the Subsystem Vendor ID and 436 * Subsystem (Device) ID registers, which are the opposite way 437 * round according to the PCI standard. For good measure, we 438 * save/restore both anyway. 439 */ 440 handle = bgep->cfg_handle; 441 442 mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR); 443 cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK; 444 cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE); 445 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 446 447 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 448 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 449 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 450 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 451 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 452 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 453 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 454 455 BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s", 456 cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X", 457 cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow", 458 cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide", 459 cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low")); 460 BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 461 cidp->vendor, cidp->device, cidp->revision)); 462 BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x", 463 cidp->subven, cidp->subdev, cidp->asic_rev)); 464 BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x", 465 cidp->clsize, cidp->latency, cidp->command)); 466 467 /* 468 * Step 2 (also step 6): disable and clear interrupts. 469 * Steps 11-13: configure PIO endianness options, and enable 470 * indirect register access. We'll also select any other 471 * options controlled by the MHCR (e.g. tagged status, mask 472 * interrupt mode) at this stage ... 473 * 474 * Note: internally, the chip is 64-bit and BIG-endian, but 475 * since it talks to the host over a (LITTLE-endian) PCI bus, 476 * it normally swaps bytes around at the PCI interface. 477 * However, the PCI host bridge on SPARC systems normally 478 * swaps the byte lanes around too, since SPARCs are also 479 * BIG-endian. So it turns out that on SPARC, the right 480 * option is to tell the chip to swap (and the host bridge 481 * will swap back again), whereas on x86 we ask the chip 482 * NOT to swap, so the natural little-endianness of the 483 * PCI bus is assumed. Then the only thing that doesn't 484 * automatically work right is access to an 8-byte register 485 * by a little-endian host; but we don't want to set the 486 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte 487 * accesses don't go where expected ;-( So we live with 488 * that, and perform word-swaps in software in the few cases 489 * where a chip register is defined as an 8-byte value -- 490 * see the code below for details ... 491 * 492 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't 493 * very clear in the register description in the PRM, but 494 * Broadcom document 570X-PG104-R page 248 explains a little 495 * more (under "Broadcom Mask Mode"). The bit changes the way 496 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE 497 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same 498 * way as the 5700 did, which isn't very convenient. Setting 499 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT 500 * bit do just what its name says -- MASK the PCI #INTA output 501 * (i.e. deassert the signal at the pin) leaving all internal 502 * state unchanged. This is much more convenient for our 503 * interrupt handler, so we set MASK_INTERRUPT_MODE here. 504 * 505 * Note: the inconvenient semantics of the interrupt mailbox 506 * (nonzero disables and acknowledges/clears the interrupt, 507 * zero enables AND CLEARS it) would make race conditions 508 * likely in the interrupt handler: 509 * 510 * (1) acknowledge & disable interrupts 511 * (2) while (more to do) 512 * process packets 513 * (3) enable interrupts -- also clears pending 514 * 515 * If the chip received more packets and internally generated 516 * an interrupt between the check at (2) and the mbox write 517 * at (3), this interrupt would be lost :-( 518 * 519 * The best way to avoid this is to use TAGGED STATUS mode, 520 * where the chip includes a unique tag in each status block 521 * update, and the host, when re-enabling interrupts, passes 522 * the last tag it saw back to the chip; then the chip can 523 * see whether the host is truly up to date, and regenerate 524 * its interrupt if not. 525 */ 526 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 527 MHCR_ENABLE_TAGGED_STATUS_MODE | 528 MHCR_MASK_INTERRUPT_MODE | 529 MHCR_CLEAR_INTERRUPT_INTA; 530 531 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 532 mhcr |= MHCR_MASK_PCI_INT_OUTPUT; 533 534 #ifdef _BIG_ENDIAN 535 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 536 #endif /* _BIG_ENDIAN */ 537 538 pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr); 539 540 #ifdef BGE_IPMI_ASF 541 bgep->asf_wordswapped = B_FALSE; 542 #endif 543 /* 544 * Step 1 (also step 7): Enable PCI Memory Space accesses 545 * Disable Memory Write/Invalidate 546 * Enable or disable Bus Mastering 547 * 548 * Note that all other bits are taken from the original value saved 549 * the first time through here, rather than from the current register 550 * value, 'cos that will have been cleared by a soft RESET since. 551 * In this way we preserve the OBP/nexus-parent's preferred settings 552 * of the parity-error and system-error enable bits across multiple 553 * chip RESETs. 554 */ 555 command = bgep->chipid.command | PCI_COMM_MAE; 556 command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL); 557 if (enable_dma) 558 command |= PCI_COMM_ME; 559 /* 560 * on BCM5714 revision A0, false parity error gets generated 561 * due to a logic bug. Provide a workaround by disabling parity 562 * error. 563 */ 564 if (((cidp->device == DEVICE_ID_5714C) || 565 (cidp->device == DEVICE_ID_5714S)) && 566 (cidp->revision == REVISION_ID_5714_A0)) { 567 command &= ~PCI_COMM_PARITY_DETECT; 568 } 569 pci_config_put16(handle, PCI_CONF_COMM, command); 570 571 /* 572 * On some PCI-E device, there were instances when 573 * the device was still link training. 574 */ 575 if (bgep->chipid.pci_type == BGE_PCI_E) { 576 i = 0; 577 value16 = pci_config_get16(handle, PCI_CONF_COMM); 578 while ((value16 != command) && (i < 100)) { 579 drv_usecwait(200); 580 value16 = pci_config_get16(handle, PCI_CONF_COMM); 581 ++i; 582 } 583 } 584 585 /* 586 * Clear any remaining error status bits 587 */ 588 pci_config_put16(handle, PCI_CONF_STAT, ~0); 589 590 /* 591 * Do following if and only if the device is NOT BCM5714C OR 592 * BCM5715C 593 */ 594 if (!((cidp->device == DEVICE_ID_5714C) || 595 (cidp->device == DEVICE_ID_5715C))) { 596 /* 597 * Make sure these indirect-access registers are sane 598 * rather than random after power-up or reset 599 */ 600 pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0); 601 pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0); 602 } 603 /* 604 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering 605 */ 606 bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED); 607 608 if (cidp->pci_type == BGE_PCI_E) 609 bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL, 610 DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED); 611 } 612 613 #ifdef __amd64 614 /* 615 * Distinguish CPU types 616 * 617 * These use to distinguish AMD64 or Intel EM64T of CPU running mode. 618 * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine 619 * for PCI-Express based network interface card. This is the work-around 620 * for those nics. 621 */ 622 static boolean_t bge_get_em64t_type(void); 623 #pragma inline(bge_get_em64t_type) 624 625 static boolean_t 626 bge_get_em64t_type(void) 627 { 628 629 return (x86_vendor == X86_VENDOR_Intel); 630 } 631 #endif 632 633 /* 634 * Operating register get/set access routines 635 */ 636 637 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno); 638 #pragma inline(bge_reg_get32) 639 640 uint32_t 641 bge_reg_get32(bge_t *bgep, bge_regno_t regno) 642 { 643 BGE_TRACE(("bge_reg_get32($%p, 0x%lx)", 644 (void *)bgep, regno)); 645 646 return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno))); 647 } 648 649 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data); 650 #pragma inline(bge_reg_put32) 651 652 void 653 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data) 654 { 655 BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)", 656 (void *)bgep, regno, data)); 657 658 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data); 659 BGE_PCICHK(bgep); 660 } 661 662 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 663 #pragma inline(bge_reg_set32) 664 665 void 666 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 667 { 668 uint32_t regval; 669 670 BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)", 671 (void *)bgep, regno, bits)); 672 673 regval = bge_reg_get32(bgep, regno); 674 regval |= bits; 675 bge_reg_put32(bgep, regno, regval); 676 } 677 678 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits); 679 #pragma inline(bge_reg_clr32) 680 681 void 682 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits) 683 { 684 uint32_t regval; 685 686 BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)", 687 (void *)bgep, regno, bits)); 688 689 regval = bge_reg_get32(bgep, regno); 690 regval &= ~bits; 691 bge_reg_put32(bgep, regno, regval); 692 } 693 694 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno); 695 #pragma inline(bge_reg_get64) 696 697 static uint64_t 698 bge_reg_get64(bge_t *bgep, bge_regno_t regno) 699 { 700 uint64_t regval; 701 702 #ifdef __amd64 703 if (bge_get_em64t_type()) { 704 regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4)); 705 regval <<= 32; 706 regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)); 707 } else { 708 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 709 } 710 #else 711 regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno)); 712 #endif 713 714 #ifdef _LITTLE_ENDIAN 715 regval = (regval >> 32) | (regval << 32); 716 #endif /* _LITTLE_ENDIAN */ 717 718 BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx", 719 (void *)bgep, regno, regval)); 720 721 return (regval); 722 } 723 724 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data); 725 #pragma inline(bge_reg_put64) 726 727 static void 728 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data) 729 { 730 BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)", 731 (void *)bgep, regno, data)); 732 733 #ifdef _LITTLE_ENDIAN 734 data = ((data >> 32) | (data << 32)); 735 #endif /* _LITTLE_ENDIAN */ 736 737 #ifdef __amd64 738 if (bge_get_em64t_type()) { 739 ddi_put32(bgep->io_handle, 740 PIO_ADDR(bgep, regno), (uint32_t)data); 741 BGE_PCICHK(bgep); 742 ddi_put32(bgep->io_handle, 743 PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32)); 744 745 } else { 746 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 747 } 748 #else 749 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data); 750 #endif 751 752 BGE_PCICHK(bgep); 753 } 754 755 /* 756 * The DDI doesn't provide get/put functions for 128 bit data 757 * so we put RCBs out as two 64-bit chunks instead. 758 */ 759 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 760 #pragma inline(bge_reg_putrcb) 761 762 static void 763 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 764 { 765 uint64_t *p; 766 767 BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 768 (void *)bgep, addr, rcbp->host_ring_addr, 769 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 770 771 ASSERT((addr % sizeof (*rcbp)) == 0); 772 773 p = (void *)rcbp; 774 bge_reg_put64(bgep, addr, *p++); 775 bge_reg_put64(bgep, addr+8, *p); 776 } 777 778 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data); 779 #pragma inline(bge_mbx_put) 780 781 void 782 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data) 783 { 784 BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)", 785 (void *)bgep, regno, data)); 786 787 /* 788 * Mailbox registers are nominally 64 bits on the 5701, but 789 * the MSW isn't used. On the 5703, they're only 32 bits 790 * anyway. So here we just write the lower(!) 32 bits - 791 * remembering that the chip is big-endian, even though the 792 * PCI bus is little-endian ... 793 */ 794 #ifdef _BIG_ENDIAN 795 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data); 796 #else 797 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data); 798 #endif /* _BIG_ENDIAN */ 799 BGE_PCICHK(bgep); 800 } 801 802 #if BGE_DEBUGGING 803 804 void bge_led_mark(bge_t *bgep); 805 #pragma no_inline(bge_led_mark) 806 807 void 808 bge_led_mark(bge_t *bgep) 809 { 810 uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK | 811 LED_CONTROL_1000MBPS_LED | 812 LED_CONTROL_100MBPS_LED | 813 LED_CONTROL_10MBPS_LED; 814 815 /* 816 * Blink all three LINK LEDs on simultaneously, then all off, 817 * then restore to automatic hardware control. This is used 818 * in laboratory testing to trigger a logic analyser or scope. 819 */ 820 bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 821 led_ctrl ^= LED_CONTROL_OVERRIDE_LINK; 822 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 823 led_ctrl = LED_CONTROL_OVERRIDE_LINK; 824 bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl); 825 } 826 827 #endif /* BGE_DEBUGGING */ 828 829 /* 830 * NIC on-chip memory access routines 831 * 832 * Only 32K of NIC memory is visible at a time, controlled by the 833 * Memory Window Base Address Register (in PCI config space). Once 834 * this is set, the 32K region of NIC-local memory that it refers 835 * to can be directly addressed in the upper 32K of the 64K of PCI 836 * memory space used for the device. 837 */ 838 839 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base); 840 #pragma inline(bge_nic_setwin) 841 842 static void 843 bge_nic_setwin(bge_t *bgep, bge_regno_t base) 844 { 845 chip_id_t *cidp; 846 847 BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)", 848 (void *)bgep, base)); 849 850 ASSERT((base & MWBAR_GRANULE_MASK) == 0); 851 852 /* 853 * Don't do repeated zero data writes, 854 * if the device is BCM5714C/15C. 855 */ 856 cidp = &bgep->chipid; 857 if ((cidp->device == DEVICE_ID_5714C) || 858 (cidp->device == DEVICE_ID_5715C)) { 859 if (bgep->lastWriteZeroData && (base == (bge_regno_t)0)) 860 return; 861 /* Adjust lastWriteZeroData */ 862 bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ? 863 B_TRUE : B_FALSE); 864 } 865 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base); 866 } 867 868 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr); 869 #pragma inline(bge_nic_get32) 870 871 static uint32_t 872 bge_nic_get32(bge_t *bgep, bge_regno_t addr) 873 { 874 uint32_t data; 875 876 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 877 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 878 /* workaround for word swap error */ 879 if (addr & 4) 880 addr = addr - 4; 881 else 882 addr = addr + 4; 883 } 884 #endif 885 886 #ifdef __sparc 887 data = bge_nic_read32(bgep, addr); 888 #else 889 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 890 addr &= MWBAR_GRANULE_MASK; 891 addr += NIC_MEM_WINDOW_OFFSET; 892 893 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 894 #endif 895 896 BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x", 897 (void *)bgep, addr, data)); 898 899 return (data); 900 } 901 902 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data); 903 #pragma inline(bge_nic_put32) 904 905 void 906 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data) 907 { 908 BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)", 909 (void *)bgep, addr, data)); 910 911 #if defined(BGE_IPMI_ASF) && !defined(__sparc) 912 if (bgep->asf_enabled && !bgep->asf_wordswapped) { 913 /* workaround for word swap error */ 914 if (addr & 4) 915 addr = addr - 4; 916 else 917 addr = addr + 4; 918 } 919 #endif 920 921 #ifdef __sparc 922 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 923 data = LE_32(data); 924 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data); 925 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 926 #else 927 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 928 addr &= MWBAR_GRANULE_MASK; 929 addr += NIC_MEM_WINDOW_OFFSET; 930 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data); 931 BGE_PCICHK(bgep); 932 #endif 933 } 934 935 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr); 936 #pragma inline(bge_nic_get64) 937 938 static uint64_t 939 bge_nic_get64(bge_t *bgep, bge_regno_t addr) 940 { 941 uint64_t data; 942 943 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 944 addr &= MWBAR_GRANULE_MASK; 945 addr += NIC_MEM_WINDOW_OFFSET; 946 947 #ifdef __amd64 948 if (bge_get_em64t_type()) { 949 data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr)); 950 data <<= 32; 951 data |= ddi_get32(bgep->io_handle, 952 PIO_ADDR(bgep, addr + 4)); 953 } else { 954 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 955 } 956 #else 957 data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr)); 958 #endif 959 960 BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx", 961 (void *)bgep, addr, data)); 962 963 return (data); 964 } 965 966 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data); 967 #pragma inline(bge_nic_put64) 968 969 static void 970 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data) 971 { 972 BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)", 973 (void *)bgep, addr, data)); 974 975 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 976 addr &= MWBAR_GRANULE_MASK; 977 addr += NIC_MEM_WINDOW_OFFSET; 978 979 #ifdef __amd64 980 if (bge_get_em64t_type()) { 981 ddi_put32(bgep->io_handle, 982 PIO_ADDR(bgep, addr), (uint32_t)data); 983 BGE_PCICHK(bgep); 984 ddi_put32(bgep->io_handle, 985 PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32)); 986 } else { 987 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 988 } 989 #else 990 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data); 991 #endif 992 993 BGE_PCICHK(bgep); 994 } 995 996 /* 997 * The DDI doesn't provide get/put functions for 128 bit data 998 * so we put RCBs out as two 64-bit chunks instead. 999 */ 1000 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp); 1001 #pragma inline(bge_nic_putrcb) 1002 1003 static void 1004 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp) 1005 { 1006 uint64_t *p; 1007 1008 BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)", 1009 (void *)bgep, addr, rcbp->host_ring_addr, 1010 rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr)); 1011 1012 ASSERT((addr % sizeof (*rcbp)) == 0); 1013 1014 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1015 addr &= MWBAR_GRANULE_MASK; 1016 addr += NIC_MEM_WINDOW_OFFSET; 1017 1018 p = (void *)rcbp; 1019 #ifdef __amd64 1020 if (bge_get_em64t_type()) { 1021 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), 1022 (uint32_t)(*p)); 1023 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4), 1024 (uint32_t)(*p >> 32)); 1025 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8), 1026 (uint32_t)(*(p + 1))); 1027 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12), 1028 (uint32_t)(*p >> 32)); 1029 1030 } else { 1031 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1032 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p); 1033 } 1034 #else 1035 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++); 1036 ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p); 1037 #endif 1038 1039 BGE_PCICHK(bgep); 1040 } 1041 1042 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes); 1043 #pragma inline(bge_nic_zero) 1044 1045 static void 1046 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes) 1047 { 1048 BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)", 1049 (void *)bgep, addr, nbytes)); 1050 1051 ASSERT((addr & ~MWBAR_GRANULE_MASK) == 1052 ((addr+nbytes) & ~MWBAR_GRANULE_MASK)); 1053 1054 bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK); 1055 addr &= MWBAR_GRANULE_MASK; 1056 addr += NIC_MEM_WINDOW_OFFSET; 1057 1058 (void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr), 1059 nbytes, 1, DDI_DATA_SZ08_ACC); 1060 BGE_PCICHK(bgep); 1061 } 1062 1063 /* 1064 * MII (PHY) register get/set access routines 1065 * 1066 * These use the chip's MII auto-access method, controlled by the 1067 * MII Communication register at 0x044c, so the CPU doesn't have 1068 * to fiddle with the individual bits. 1069 */ 1070 1071 #undef BGE_DBG 1072 #define BGE_DBG BGE_DBG_MII /* debug flag for this code */ 1073 1074 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno, 1075 uint16_t data, uint32_t cmd); 1076 #pragma no_inline(bge_mii_access) 1077 1078 static uint16_t 1079 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd) 1080 { 1081 uint32_t timeout; 1082 uint32_t regval1; 1083 uint32_t regval2; 1084 1085 BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)", 1086 (void *)bgep, regno, data, cmd)); 1087 1088 ASSERT(mutex_owned(bgep->genlock)); 1089 1090 /* 1091 * Assemble the command ... 1092 */ 1093 cmd |= data << MI_COMMS_DATA_SHIFT; 1094 cmd |= regno << MI_COMMS_REGISTER_SHIFT; 1095 cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT; 1096 cmd |= MI_COMMS_START; 1097 1098 /* 1099 * Wait for any command already in progress ... 1100 * 1101 * Note: this *shouldn't* ever find that there is a command 1102 * in progress, because we already hold the <genlock> mutex. 1103 * Nonetheless, we have sometimes seen the MI_COMMS_START 1104 * bit set here -- it seems that the chip can initiate MII 1105 * accesses internally, even with polling OFF. 1106 */ 1107 regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1108 for (timeout = 100; ; ) { 1109 if ((regval2 & MI_COMMS_START) == 0) { 1110 bge_reg_put32(bgep, MI_COMMS_REG, cmd); 1111 break; 1112 } 1113 if (--timeout == 0) 1114 break; 1115 drv_usecwait(10); 1116 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1117 } 1118 1119 if (timeout == 0) 1120 return ((uint16_t)~0u); 1121 1122 if (timeout != 100) 1123 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1124 "MI_COMMS_START set for %d us; 0x%x->0x%x", 1125 cmd, 10*(100-timeout), regval1, regval2)); 1126 1127 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1128 for (timeout = 1000; ; ) { 1129 if ((regval1 & MI_COMMS_START) == 0) 1130 break; 1131 if (--timeout == 0) 1132 break; 1133 drv_usecwait(10); 1134 regval1 = bge_reg_get32(bgep, MI_COMMS_REG); 1135 } 1136 1137 /* 1138 * Drop out early if the READ FAILED bit is set -- this chip 1139 * could be a 5703/4S, with a SerDes instead of a PHY! 1140 */ 1141 if (regval2 & MI_COMMS_READ_FAILED) 1142 return ((uint16_t)~0u); 1143 1144 if (timeout == 0) 1145 return ((uint16_t)~0u); 1146 1147 /* 1148 * The PRM says to wait 5us after seeing the START bit clear 1149 * and then re-read the register to get the final value of the 1150 * data field, in order to avoid a race condition where the 1151 * START bit is clear but the data field isn't yet valid. 1152 * 1153 * Note: we don't actually seem to be encounter this race; 1154 * except when the START bit is seen set again (see below), 1155 * the data field doesn't change during this 5us interval. 1156 */ 1157 drv_usecwait(5); 1158 regval2 = bge_reg_get32(bgep, MI_COMMS_REG); 1159 1160 /* 1161 * Unfortunately, when following the PRMs instructions above, 1162 * we have occasionally seen the START bit set again(!) in the 1163 * value read after the 5us delay. This seems to be due to the 1164 * chip autonomously starting another MII access internally. 1165 * In such cases, the command/data/etc fields relate to the 1166 * internal command, rather than the one that we thought had 1167 * just finished. So in this case, we fall back to returning 1168 * the data from the original read that showed START clear. 1169 */ 1170 if (regval2 & MI_COMMS_START) { 1171 BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- " 1172 "MI_COMMS_START set after transaction; 0x%x->0x%x", 1173 cmd, regval1, regval2)); 1174 regval2 = regval1; 1175 } 1176 1177 if (regval2 & MI_COMMS_START) 1178 return ((uint16_t)~0u); 1179 1180 if (regval2 & MI_COMMS_READ_FAILED) 1181 return ((uint16_t)~0u); 1182 1183 return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT); 1184 } 1185 1186 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno); 1187 #pragma no_inline(bge_mii_get16) 1188 1189 uint16_t 1190 bge_mii_get16(bge_t *bgep, bge_regno_t regno) 1191 { 1192 BGE_TRACE(("bge_mii_get16($%p, 0x%lx)", 1193 (void *)bgep, regno)); 1194 1195 ASSERT(mutex_owned(bgep->genlock)); 1196 1197 return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ)); 1198 } 1199 1200 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data); 1201 #pragma no_inline(bge_mii_put16) 1202 1203 void 1204 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data) 1205 { 1206 BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)", 1207 (void *)bgep, regno, data)); 1208 1209 ASSERT(mutex_owned(bgep->genlock)); 1210 1211 (void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE); 1212 } 1213 1214 #undef BGE_DBG 1215 #define BGE_DBG BGE_DBG_SEEPROM /* debug flag for this code */ 1216 1217 #if BGE_SEE_IO32 || BGE_FLASH_IO32 1218 1219 /* 1220 * Basic SEEPROM get/set access routine 1221 * 1222 * This uses the chip's SEEPROM auto-access method, controlled by the 1223 * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU 1224 * doesn't have to fiddle with the individual bits. 1225 * 1226 * The caller should hold <genlock> and *also* have already acquired 1227 * the right to access the SEEPROM, via bge_nvmem_acquire() above. 1228 * 1229 * Return value: 1230 * 0 on success, 1231 * ENODATA on access timeout (maybe retryable: device may just be busy) 1232 * EPROTO on other h/w or s/w errors. 1233 * 1234 * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output 1235 * from a (successful) SEEPROM_ACCESS_READ. 1236 */ 1237 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1238 uint32_t *dp); 1239 #pragma no_inline(bge_seeprom_access) 1240 1241 static int 1242 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1243 { 1244 uint32_t tries; 1245 uint32_t regval; 1246 1247 ASSERT(mutex_owned(bgep->genlock)); 1248 1249 /* 1250 * On the newer chips that support both SEEPROM & Flash, we need 1251 * to specifically enable SEEPROM access (Flash is the default). 1252 * On older chips, we don't; SEEPROM is the only NVtype supported, 1253 * and the NVM control registers don't exist ... 1254 */ 1255 switch (bgep->chipid.nvtype) { 1256 case BGE_NVTYPE_NONE: 1257 case BGE_NVTYPE_UNKNOWN: 1258 _NOTE(NOTREACHED) 1259 case BGE_NVTYPE_SEEPROM: 1260 break; 1261 1262 case BGE_NVTYPE_LEGACY_SEEPROM: 1263 case BGE_NVTYPE_UNBUFFERED_FLASH: 1264 case BGE_NVTYPE_BUFFERED_FLASH: 1265 default: 1266 bge_reg_set32(bgep, NVM_CONFIG1_REG, 1267 NVM_CFG1_LEGACY_SEEPROM_MODE); 1268 break; 1269 } 1270 1271 /* 1272 * Check there's no command in progress. 1273 * 1274 * Note: this *shouldn't* ever find that there is a command 1275 * in progress, because we already hold the <genlock> mutex. 1276 * Also, to ensure we don't have a conflict with the chip's 1277 * internal firmware or a process accessing the same (shared) 1278 * SEEPROM through the other port of a 5704, we've already 1279 * been through the "software arbitration" protocol. 1280 * So this is just a final consistency check: we shouldn't 1281 * see EITHER the START bit (command started but not complete) 1282 * OR the COMPLETE bit (command completed but not cleared). 1283 */ 1284 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1285 if (regval & SEEPROM_ACCESS_START) 1286 return (EPROTO); 1287 if (regval & SEEPROM_ACCESS_COMPLETE) 1288 return (EPROTO); 1289 1290 /* 1291 * Assemble the command ... 1292 */ 1293 cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK; 1294 addr >>= SEEPROM_ACCESS_ADDRESS_SIZE; 1295 addr <<= SEEPROM_ACCESS_DEVID_SHIFT; 1296 cmd |= addr & SEEPROM_ACCESS_DEVID_MASK; 1297 cmd |= SEEPROM_ACCESS_START; 1298 cmd |= SEEPROM_ACCESS_COMPLETE; 1299 cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK; 1300 1301 bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp); 1302 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd); 1303 1304 /* 1305 * By observation, a successful access takes ~20us on a 5703/4, 1306 * but apparently much longer (up to 1000us) on the obsolescent 1307 * BCM5700/BCM5701. We want to be sure we don't get any false 1308 * timeouts here; but OTOH, we don't want a bogus access to lock 1309 * out interrupts for longer than necessary. So we'll allow up 1310 * to 1000us ... 1311 */ 1312 for (tries = 0; tries < 1000; ++tries) { 1313 regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG); 1314 if (regval & SEEPROM_ACCESS_COMPLETE) 1315 break; 1316 drv_usecwait(1); 1317 } 1318 1319 if (regval & SEEPROM_ACCESS_COMPLETE) { 1320 /* 1321 * All OK; read the SEEPROM data register, then write back 1322 * the value read from the address register in order to 1323 * clear the <complete> bit and leave the SEEPROM access 1324 * state machine idle, ready for the next access ... 1325 */ 1326 BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries)); 1327 *dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG); 1328 bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval); 1329 return (0); 1330 } 1331 1332 /* 1333 * Hmm ... what happened here? 1334 * 1335 * Most likely, the user addressed a non-existent SEEPROM. Or 1336 * maybe the SEEPROM was busy internally (e.g. processing a write) 1337 * and didn't respond to being addressed. Either way, it's left 1338 * the SEEPROM access state machine wedged. So we'll reset it 1339 * before we leave, so it's ready for next time ... 1340 */ 1341 BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries)); 1342 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 1343 return (ENODATA); 1344 } 1345 1346 /* 1347 * Basic Flash get/set access routine 1348 * 1349 * These use the chip's Flash auto-access method, controlled by the 1350 * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to 1351 * fiddle with the individual bits. 1352 * 1353 * The caller should hold <genlock> and *also* have already acquired 1354 * the right to access the Flash, via bge_nvmem_acquire() above. 1355 * 1356 * Return value: 1357 * 0 on success, 1358 * ENODATA on access timeout (maybe retryable: device may just be busy) 1359 * ENODEV if the NVmem device is missing or otherwise unusable 1360 * 1361 * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output 1362 * from a (successful) NVM_FLASH_CMD_RD. 1363 */ 1364 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, 1365 uint32_t *dp); 1366 #pragma no_inline(bge_flash_access) 1367 1368 static int 1369 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1370 { 1371 uint32_t tries; 1372 uint32_t regval; 1373 1374 ASSERT(mutex_owned(bgep->genlock)); 1375 1376 /* 1377 * On the newer chips that support both SEEPROM & Flash, we need 1378 * to specifically disable SEEPROM access while accessing Flash. 1379 * The older chips don't support Flash, and the NVM registers don't 1380 * exist, so we shouldn't be here at all! 1381 */ 1382 switch (bgep->chipid.nvtype) { 1383 case BGE_NVTYPE_NONE: 1384 case BGE_NVTYPE_UNKNOWN: 1385 _NOTE(NOTREACHED) 1386 case BGE_NVTYPE_SEEPROM: 1387 return (ENODEV); 1388 1389 case BGE_NVTYPE_LEGACY_SEEPROM: 1390 case BGE_NVTYPE_UNBUFFERED_FLASH: 1391 case BGE_NVTYPE_BUFFERED_FLASH: 1392 default: 1393 bge_reg_clr32(bgep, NVM_CONFIG1_REG, 1394 NVM_CFG1_LEGACY_SEEPROM_MODE); 1395 break; 1396 } 1397 1398 /* 1399 * Assemble the command ... 1400 */ 1401 addr &= NVM_FLASH_ADDR_MASK; 1402 cmd |= NVM_FLASH_CMD_DOIT; 1403 cmd |= NVM_FLASH_CMD_FIRST; 1404 cmd |= NVM_FLASH_CMD_LAST; 1405 cmd |= NVM_FLASH_CMD_DONE; 1406 1407 bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp); 1408 bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr); 1409 bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd); 1410 1411 /* 1412 * Allow up to 1000ms ... 1413 */ 1414 for (tries = 0; tries < 1000; ++tries) { 1415 regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG); 1416 if (regval & NVM_FLASH_CMD_DONE) 1417 break; 1418 drv_usecwait(1); 1419 } 1420 1421 if (regval & NVM_FLASH_CMD_DONE) { 1422 /* 1423 * All OK; read the data from the Flash read register 1424 */ 1425 BGE_DEBUG(("bge_flash_access: complete after %d us", tries)); 1426 *dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG); 1427 return (0); 1428 } 1429 1430 /* 1431 * Hmm ... what happened here? 1432 * 1433 * Most likely, the user addressed a non-existent Flash. Or 1434 * maybe the Flash was busy internally (e.g. processing a write) 1435 * and didn't respond to being addressed. Either way, there's 1436 * nothing we can here ... 1437 */ 1438 BGE_DEBUG(("bge_flash_access: timed out after %d us", tries)); 1439 return (ENODATA); 1440 } 1441 1442 /* 1443 * The next two functions regulate access to the NVram (if fitted). 1444 * 1445 * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash 1446 * (SPI) interface, but they can be accessed through either port. These 1447 * are managed by different instance of this driver and have no software 1448 * state in common. 1449 * 1450 * In addition (and even on a single core chip) the chip's internal 1451 * firmware can access the SEEPROM/Flash, most notably after a RESET 1452 * when it may download code to run internally. 1453 * 1454 * So we need to arbitrate between these various software agents. For 1455 * this purpose, the chip provides the Software Arbitration Register, 1456 * which implements hardware(!) arbitration. 1457 * 1458 * This functionality didn't exist on older (5700/5701) chips, so there's 1459 * nothing we can do by way of arbitration on those; also, if there's no 1460 * SEEPROM/Flash fitted (or we couldn't determine what type), there's also 1461 * nothing to do. 1462 * 1463 * The internal firmware appears to use Request 0, which is the highest 1464 * priority. So we'd like to use Request 2, leaving one higher and one 1465 * lower for any future developments ... but apparently this doesn't 1466 * always work. So for now, the code uses Request 1 ;-( 1467 */ 1468 1469 #define NVM_READ_REQ NVM_READ_REQ1 1470 #define NVM_RESET_REQ NVM_RESET_REQ1 1471 #define NVM_SET_REQ NVM_SET_REQ1 1472 1473 static void bge_nvmem_relinquish(bge_t *bgep); 1474 #pragma no_inline(bge_nvmem_relinquish) 1475 1476 static void 1477 bge_nvmem_relinquish(bge_t *bgep) 1478 { 1479 ASSERT(mutex_owned(bgep->genlock)); 1480 1481 switch (bgep->chipid.nvtype) { 1482 case BGE_NVTYPE_NONE: 1483 case BGE_NVTYPE_UNKNOWN: 1484 _NOTE(NOTREACHED) 1485 return; 1486 1487 case BGE_NVTYPE_SEEPROM: 1488 /* 1489 * No arbitration performed, no release needed 1490 */ 1491 return; 1492 1493 case BGE_NVTYPE_LEGACY_SEEPROM: 1494 case BGE_NVTYPE_UNBUFFERED_FLASH: 1495 case BGE_NVTYPE_BUFFERED_FLASH: 1496 default: 1497 break; 1498 } 1499 1500 /* 1501 * Our own request should be present (whether or not granted) ... 1502 */ 1503 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1504 1505 /* 1506 * ... this will make it go away. 1507 */ 1508 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ); 1509 (void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1510 } 1511 1512 /* 1513 * Arbitrate for access to the NVmem, if necessary 1514 * 1515 * Return value: 1516 * 0 on success 1517 * EAGAIN if the device is in use (retryable) 1518 * ENODEV if the NVmem device is missing or otherwise unusable 1519 */ 1520 static int bge_nvmem_acquire(bge_t *bgep); 1521 #pragma no_inline(bge_nvmem_acquire) 1522 1523 static int 1524 bge_nvmem_acquire(bge_t *bgep) 1525 { 1526 uint32_t regval; 1527 uint32_t tries; 1528 1529 ASSERT(mutex_owned(bgep->genlock)); 1530 1531 switch (bgep->chipid.nvtype) { 1532 case BGE_NVTYPE_NONE: 1533 case BGE_NVTYPE_UNKNOWN: 1534 /* 1535 * Access denied: no (recognisable) device fitted 1536 */ 1537 return (ENODEV); 1538 1539 case BGE_NVTYPE_SEEPROM: 1540 /* 1541 * Access granted: no arbitration needed (or possible) 1542 */ 1543 return (0); 1544 1545 case BGE_NVTYPE_LEGACY_SEEPROM: 1546 case BGE_NVTYPE_UNBUFFERED_FLASH: 1547 case BGE_NVTYPE_BUFFERED_FLASH: 1548 default: 1549 /* 1550 * Access conditional: conduct arbitration protocol 1551 */ 1552 break; 1553 } 1554 1555 /* 1556 * We're holding the per-port mutex <genlock>, so no-one other 1557 * thread can be attempting to access the NVmem through *this* 1558 * port. But it could be in use by the *other* port (of a 5704), 1559 * or by the chip's internal firmware, so we have to go through 1560 * the full (hardware) arbitration protocol ... 1561 * 1562 * Note that *because* we're holding <genlock>, the interrupt handler 1563 * won't be able to progress. So we're only willing to spin for a 1564 * fairly short time. Specifically: 1565 * 1566 * We *must* wait long enough for the hardware to resolve all 1567 * requests and determine the winner. Fortunately, this is 1568 * "almost instantaneous", even as observed by GHz CPUs. 1569 * 1570 * A successful access by another Solaris thread (via either 1571 * port) typically takes ~20us. So waiting a bit longer than 1572 * that will give a good chance of success, if the other user 1573 * *is* another thread on the other port. 1574 * 1575 * However, the internal firmware can hold on to the NVmem 1576 * for *much* longer: at least 10 milliseconds just after a 1577 * RESET, and maybe even longer if the NVmem actually contains 1578 * code to download and run on the internal CPUs. 1579 * 1580 * So, we'll allow 50us; if that's not enough then it's up to the 1581 * caller to retry later (hence the choice of return code EAGAIN). 1582 */ 1583 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1584 bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ); 1585 1586 for (tries = 0; tries < 50; ++tries) { 1587 regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG); 1588 if (regval & NVM_WON_REQ1) 1589 break; 1590 drv_usecwait(1); 1591 } 1592 1593 if (regval & NVM_WON_REQ1) { 1594 BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries)); 1595 return (0); 1596 } 1597 1598 /* 1599 * Somebody else must be accessing the NVmem, so abandon our 1600 * attempt take control of it. The caller can try again later ... 1601 */ 1602 BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries)); 1603 bge_nvmem_relinquish(bgep); 1604 return (EAGAIN); 1605 } 1606 1607 /* 1608 * This code assumes that the GPIO1 bit has been wired up to the NVmem 1609 * write protect line in such a way that the NVmem is protected when 1610 * GPIO1 is an input, or is an output but driven high. Thus, to make the 1611 * NVmem writable we have to change GPIO1 to an output AND drive it low. 1612 * 1613 * Note: there's only one set of GPIO pins on a 5704, even though they 1614 * can be accessed through either port. So the chip has to resolve what 1615 * happens if the two ports program a single pin differently ... the rule 1616 * it uses is that if the ports disagree about the *direction* of a pin, 1617 * "output" wins over "input", but if they disagree about its *value* as 1618 * an output, then the pin is TRISTATED instead! In such a case, no-one 1619 * wins, and the external signal does whatever the external circuitry 1620 * defines as the default -- which we've assumed is the PROTECTED state. 1621 * So, we always change GPIO1 back to being an *input* whenever we're not 1622 * specifically using it to unprotect the NVmem. This allows either port 1623 * to update the NVmem, although obviously only one at a time! 1624 * 1625 * The caller should hold <genlock> and *also* have already acquired the 1626 * right to access the NVmem, via bge_nvmem_acquire() above. 1627 */ 1628 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect); 1629 #pragma inline(bge_nvmem_protect) 1630 1631 static void 1632 bge_nvmem_protect(bge_t *bgep, boolean_t protect) 1633 { 1634 uint32_t regval; 1635 1636 ASSERT(mutex_owned(bgep->genlock)); 1637 1638 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 1639 if (protect) { 1640 regval |= MLCR_MISC_PINS_OUTPUT_1; 1641 regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1642 } else { 1643 regval &= ~MLCR_MISC_PINS_OUTPUT_1; 1644 regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1; 1645 } 1646 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval); 1647 } 1648 1649 /* 1650 * Now put it all together ... 1651 * 1652 * Try to acquire control of the NVmem; if successful, then: 1653 * unprotect it (if we want to write to it) 1654 * perform the requested access 1655 * reprotect it (after a write) 1656 * relinquish control 1657 * 1658 * Return value: 1659 * 0 on success, 1660 * EAGAIN if the device is in use (retryable) 1661 * ENODATA on access timeout (maybe retryable: device may just be busy) 1662 * ENODEV if the NVmem device is missing or otherwise unusable 1663 * EPROTO on other h/w or s/w errors. 1664 */ 1665 static int 1666 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp) 1667 { 1668 int err; 1669 1670 if ((err = bge_nvmem_acquire(bgep)) == 0) { 1671 switch (cmd) { 1672 case BGE_SEE_READ: 1673 err = bge_seeprom_access(bgep, 1674 SEEPROM_ACCESS_READ, addr, dp); 1675 break; 1676 1677 case BGE_SEE_WRITE: 1678 bge_nvmem_protect(bgep, B_FALSE); 1679 err = bge_seeprom_access(bgep, 1680 SEEPROM_ACCESS_WRITE, addr, dp); 1681 bge_nvmem_protect(bgep, B_TRUE); 1682 break; 1683 1684 case BGE_FLASH_READ: 1685 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1686 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1687 bge_reg_set32(bgep, NVM_ACCESS_REG, 1688 NVM_ACCESS_ENABLE); 1689 } 1690 err = bge_flash_access(bgep, 1691 NVM_FLASH_CMD_RD, addr, dp); 1692 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1693 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1694 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1695 NVM_ACCESS_ENABLE); 1696 } 1697 break; 1698 1699 case BGE_FLASH_WRITE: 1700 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1701 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1702 bge_reg_set32(bgep, NVM_ACCESS_REG, 1703 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1704 } 1705 bge_nvmem_protect(bgep, B_FALSE); 1706 err = bge_flash_access(bgep, 1707 NVM_FLASH_CMD_WR, addr, dp); 1708 bge_nvmem_protect(bgep, B_TRUE); 1709 if (DEVICE_5721_SERIES_CHIPSETS(bgep) || 1710 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 1711 bge_reg_clr32(bgep, NVM_ACCESS_REG, 1712 NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE); 1713 } 1714 1715 break; 1716 1717 default: 1718 _NOTE(NOTREACHED) 1719 break; 1720 } 1721 bge_nvmem_relinquish(bgep); 1722 } 1723 1724 BGE_DEBUG(("bge_nvmem_rw32: err %d", err)); 1725 return (err); 1726 } 1727 1728 /* 1729 * Attempt to get a MAC address from the SEEPROM or Flash, if any 1730 */ 1731 static uint64_t bge_get_nvmac(bge_t *bgep); 1732 #pragma no_inline(bge_get_nvmac) 1733 1734 static uint64_t 1735 bge_get_nvmac(bge_t *bgep) 1736 { 1737 uint32_t mac_high; 1738 uint32_t mac_low; 1739 uint32_t addr; 1740 uint32_t cmd; 1741 uint64_t mac; 1742 1743 BGE_TRACE(("bge_get_nvmac($%p)", 1744 (void *)bgep)); 1745 1746 switch (bgep->chipid.nvtype) { 1747 case BGE_NVTYPE_NONE: 1748 case BGE_NVTYPE_UNKNOWN: 1749 default: 1750 return (0ULL); 1751 1752 case BGE_NVTYPE_SEEPROM: 1753 case BGE_NVTYPE_LEGACY_SEEPROM: 1754 cmd = BGE_SEE_READ; 1755 break; 1756 1757 case BGE_NVTYPE_UNBUFFERED_FLASH: 1758 case BGE_NVTYPE_BUFFERED_FLASH: 1759 cmd = BGE_FLASH_READ; 1760 break; 1761 } 1762 1763 addr = NVMEM_DATA_MAC_ADDRESS; 1764 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high)) 1765 return (0ULL); 1766 addr += 4; 1767 if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low)) 1768 return (0ULL); 1769 1770 /* 1771 * The Broadcom chip is natively BIG-endian, so that's how the 1772 * MAC address is represented in NVmem. We may need to swap it 1773 * around on a little-endian host ... 1774 */ 1775 #ifdef _BIG_ENDIAN 1776 mac = mac_high; 1777 mac = mac << 32; 1778 mac |= mac_low; 1779 #else 1780 mac = BGE_BSWAP_32(mac_high); 1781 mac = mac << 32; 1782 mac |= BGE_BSWAP_32(mac_low); 1783 #endif /* _BIG_ENDIAN */ 1784 1785 return (mac); 1786 } 1787 1788 #else /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1789 1790 /* 1791 * Dummy version for when we're not supporting NVmem access 1792 */ 1793 static uint64_t bge_get_nvmac(bge_t *bgep); 1794 #pragma inline(bge_get_nvmac) 1795 1796 static uint64_t 1797 bge_get_nvmac(bge_t *bgep) 1798 { 1799 _NOTE(ARGUNUSED(bgep)) 1800 return (0ULL); 1801 } 1802 1803 #endif /* BGE_SEE_IO32 || BGE_FLASH_IO32 */ 1804 1805 /* 1806 * Determine the type of NVmem that is (or may be) attached to this chip, 1807 */ 1808 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep); 1809 #pragma no_inline(bge_nvmem_id) 1810 1811 static enum bge_nvmem_type 1812 bge_nvmem_id(bge_t *bgep) 1813 { 1814 enum bge_nvmem_type nvtype; 1815 uint32_t config1; 1816 1817 BGE_TRACE(("bge_nvmem_id($%p)", 1818 (void *)bgep)); 1819 1820 switch (bgep->chipid.device) { 1821 default: 1822 /* 1823 * We shouldn't get here; it means we don't recognise 1824 * the chip, which means we don't know how to determine 1825 * what sort of NVmem (if any) it has. So we'll say 1826 * NONE, to disable the NVmem access code ... 1827 */ 1828 nvtype = BGE_NVTYPE_NONE; 1829 break; 1830 1831 case DEVICE_ID_5700: 1832 case DEVICE_ID_5700x: 1833 case DEVICE_ID_5701: 1834 /* 1835 * These devices support *only* SEEPROMs 1836 */ 1837 nvtype = BGE_NVTYPE_SEEPROM; 1838 break; 1839 1840 case DEVICE_ID_5702: 1841 case DEVICE_ID_5702fe: 1842 case DEVICE_ID_5703C: 1843 case DEVICE_ID_5703S: 1844 case DEVICE_ID_5704C: 1845 case DEVICE_ID_5704S: 1846 case DEVICE_ID_5704: 1847 case DEVICE_ID_5705M: 1848 case DEVICE_ID_5705C: 1849 case DEVICE_ID_5705_2: 1850 case DEVICE_ID_5706: 1851 case DEVICE_ID_5782: 1852 case DEVICE_ID_5788: 1853 case DEVICE_ID_5789: 1854 case DEVICE_ID_5751: 1855 case DEVICE_ID_5751M: 1856 case DEVICE_ID_5752: 1857 case DEVICE_ID_5752M: 1858 case DEVICE_ID_5754: 1859 case DEVICE_ID_5721: 1860 case DEVICE_ID_5714C: 1861 case DEVICE_ID_5714S: 1862 case DEVICE_ID_5715C: 1863 case DEVICE_ID_5715S: 1864 config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG); 1865 if (config1 & NVM_CFG1_FLASH_MODE) 1866 if (config1 & NVM_CFG1_BUFFERED_MODE) 1867 nvtype = BGE_NVTYPE_BUFFERED_FLASH; 1868 else 1869 nvtype = BGE_NVTYPE_UNBUFFERED_FLASH; 1870 else 1871 nvtype = BGE_NVTYPE_LEGACY_SEEPROM; 1872 break; 1873 } 1874 1875 return (nvtype); 1876 } 1877 1878 #undef BGE_DBG 1879 #define BGE_DBG BGE_DBG_CHIP /* debug flag for this code */ 1880 1881 static void 1882 bge_init_recv_rule(bge_t *bgep) 1883 { 1884 bge_recv_rule_t *rulep; 1885 uint32_t i; 1886 1887 /* 1888 * receive rule: direct all TCP traffic to ring RULE_MATCH_TO_RING 1889 * 1. to direct UDP traffic, set: 1890 * rulep->control = RULE_PROTO_CONTROL; 1891 * rulep->mask_value = RULE_UDP_MASK_VALUE; 1892 * 2. to direct ICMP traffic, set: 1893 * rulep->control = RULE_PROTO_CONTROL; 1894 * rulep->mask_value = RULE_ICMP_MASK_VALUE; 1895 * 3. to direct traffic by source ip, set: 1896 * rulep->control = RULE_SIP_CONTROL; 1897 * rulep->mask_value = RULE_SIP_MASK_VALUE; 1898 */ 1899 rulep = bgep->recv_rules; 1900 rulep->control = RULE_PROTO_CONTROL; 1901 rulep->mask_value = RULE_TCP_MASK_VALUE; 1902 1903 /* 1904 * set receive rule registers 1905 */ 1906 rulep = bgep->recv_rules; 1907 for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) { 1908 bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value); 1909 bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control); 1910 } 1911 } 1912 1913 /* 1914 * Using the values captured by bge_chip_cfg_init(), and additional probes 1915 * as required, characterise the chip fully: determine the label by which 1916 * to refer to this chip, the correct settings for various registers, and 1917 * of course whether the device and/or subsystem are supported! 1918 */ 1919 int bge_chip_id_init(bge_t *bgep); 1920 #pragma no_inline(bge_chip_id_init) 1921 1922 int 1923 bge_chip_id_init(bge_t *bgep) 1924 { 1925 char buf[MAXPATHLEN]; /* any risk of stack overflow? */ 1926 boolean_t sys_ok; 1927 boolean_t dev_ok; 1928 chip_id_t *cidp; 1929 uint32_t subid; 1930 char *devname; 1931 char *sysname; 1932 int *ids; 1933 int err; 1934 uint_t i; 1935 1936 ASSERT(bgep->bge_chip_state == BGE_CHIP_INITIAL); 1937 1938 sys_ok = dev_ok = B_FALSE; 1939 cidp = &bgep->chipid; 1940 1941 /* 1942 * Check the PCI device ID to determine the generic chip type and 1943 * select parameters that depend on this. 1944 * 1945 * Note: because the SPARC platforms in general don't fit the 1946 * SEEPROM 'behind' the chip, the PCI revision ID register reads 1947 * as zero - which is why we use <asic_rev> rather than <revision> 1948 * below ... 1949 * 1950 * Note: in general we can't distinguish between the Copper/SerDes 1951 * versions by ID alone, as some Copper devices (e.g. some but not 1952 * all 5703Cs) have the same ID as the SerDes equivalents. So we 1953 * treat them the same here, and the MII code works out the media 1954 * type later on ... 1955 */ 1956 cidp->mbuf_base = bge_mbuf_pool_base; 1957 cidp->mbuf_length = bge_mbuf_pool_len; 1958 cidp->recv_slots = BGE_RECV_SLOTS_USED; 1959 cidp->bge_dma_rwctrl = bge_dma_rwctrl; 1960 cidp->pci_type = BGE_PCI_X; 1961 cidp->statistic_type = BGE_STAT_BLK; 1962 cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma; 1963 cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac; 1964 cidp->mbuf_hi_water = bge_mbuf_hi_water; 1965 1966 if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX) 1967 cidp->rx_rings = BGE_RECV_RINGS_DEFAULT; 1968 if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX) 1969 cidp->tx_rings = BGE_SEND_RINGS_DEFAULT; 1970 1971 cidp->msi_enabled = B_FALSE; 1972 1973 switch (cidp->device) { 1974 case DEVICE_ID_5700: 1975 case DEVICE_ID_5700x: 1976 cidp->chip_label = 5700; 1977 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1978 break; 1979 1980 case DEVICE_ID_5701: 1981 cidp->chip_label = 5701; 1982 dev_ok = B_TRUE; 1983 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1984 break; 1985 1986 case DEVICE_ID_5702: 1987 case DEVICE_ID_5702fe: 1988 cidp->chip_label = 5702; 1989 dev_ok = B_TRUE; 1990 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 1991 cidp->pci_type = BGE_PCI; 1992 break; 1993 1994 case DEVICE_ID_5703C: 1995 case DEVICE_ID_5703S: 1996 case DEVICE_ID_5703: 1997 /* 1998 * Revision A0 of the 5703/5793 had various errata 1999 * that we can't or don't work around, so it's not 2000 * supported, but all later versions are 2001 */ 2002 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703; 2003 if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0) 2004 dev_ok = B_TRUE; 2005 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2006 break; 2007 2008 case DEVICE_ID_5704C: 2009 case DEVICE_ID_5704S: 2010 case DEVICE_ID_5704: 2011 /* 2012 * Revision A0 of the 5704/5794 had various errata 2013 * but we have workarounds, so it *is* supported. 2014 */ 2015 cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704; 2016 cidp->mbuf_base = bge_mbuf_pool_base_5704; 2017 cidp->mbuf_length = bge_mbuf_pool_len_5704; 2018 dev_ok = B_TRUE; 2019 if (cidp->asic_rev < MHCR_CHIP_REV_5704_B0) 2020 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2021 break; 2022 2023 case DEVICE_ID_5705C: 2024 case DEVICE_ID_5705M: 2025 case DEVICE_ID_5705MA3: 2026 case DEVICE_ID_5705F: 2027 case DEVICE_ID_5705_2: 2028 case DEVICE_ID_5754: 2029 if (cidp->device == DEVICE_ID_5754) { 2030 cidp->chip_label = 5754; 2031 cidp->pci_type = BGE_PCI_E; 2032 } else { 2033 cidp->chip_label = 5705; 2034 cidp->pci_type = BGE_PCI; 2035 } 2036 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2037 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2038 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2039 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2040 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2041 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2042 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2043 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2044 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2045 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2046 cidp->statistic_type = BGE_STAT_REG; 2047 dev_ok = B_TRUE; 2048 break; 2049 2050 case DEVICE_ID_5706: 2051 cidp->chip_label = 5706; 2052 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2053 break; 2054 2055 case DEVICE_ID_5782: 2056 /* 2057 * Apart from the label, we treat this as a 5705(?) 2058 */ 2059 cidp->chip_label = 5782; 2060 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2061 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2062 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2063 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2064 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2065 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2066 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2067 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2068 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2069 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2070 cidp->statistic_type = BGE_STAT_REG; 2071 dev_ok = B_TRUE; 2072 break; 2073 2074 case DEVICE_ID_5788: 2075 /* 2076 * Apart from the label, we treat this as a 5705(?) 2077 */ 2078 cidp->chip_label = 5788; 2079 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2080 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2081 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2082 cidp->mbuf_base = bge_mbuf_pool_base_5705; 2083 cidp->mbuf_length = bge_mbuf_pool_len_5705; 2084 cidp->recv_slots = BGE_RECV_SLOTS_5705; 2085 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2086 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2087 cidp->statistic_type = BGE_STAT_REG; 2088 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2089 dev_ok = B_TRUE; 2090 break; 2091 2092 case DEVICE_ID_5714C: 2093 if (cidp->revision >= REVISION_ID_5714_A2) 2094 cidp->msi_enabled = bge_enable_msi; 2095 /* FALLTHRU */ 2096 case DEVICE_ID_5714S: 2097 cidp->chip_label = 5714; 2098 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2099 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2100 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2101 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2102 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2103 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2104 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714; 2105 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2106 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2107 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2108 cidp->pci_type = BGE_PCI_E; 2109 cidp->statistic_type = BGE_STAT_REG; 2110 dev_ok = B_TRUE; 2111 break; 2112 2113 case DEVICE_ID_5715C: 2114 case DEVICE_ID_5715S: 2115 cidp->chip_label = 5715; 2116 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2117 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2118 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2119 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2120 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2121 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2122 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715; 2123 cidp->bge_mlcr_default = bge_mlcr_default_5714; 2124 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2125 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2126 cidp->pci_type = BGE_PCI_E; 2127 cidp->statistic_type = BGE_STAT_REG; 2128 if (cidp->revision >= REVISION_ID_5715_A2) 2129 cidp->msi_enabled = bge_enable_msi; 2130 dev_ok = B_TRUE; 2131 break; 2132 2133 case DEVICE_ID_5721: 2134 cidp->chip_label = 5721; 2135 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2136 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2137 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2138 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2139 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2140 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2141 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2142 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2143 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2144 cidp->pci_type = BGE_PCI_E; 2145 cidp->statistic_type = BGE_STAT_REG; 2146 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2147 dev_ok = B_TRUE; 2148 break; 2149 2150 case DEVICE_ID_5751: 2151 case DEVICE_ID_5751M: 2152 cidp->chip_label = 5751; 2153 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2154 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2155 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2156 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2157 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2158 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2159 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2160 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2161 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2162 cidp->pci_type = BGE_PCI_E; 2163 cidp->statistic_type = BGE_STAT_REG; 2164 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2165 dev_ok = B_TRUE; 2166 break; 2167 2168 case DEVICE_ID_5752: 2169 case DEVICE_ID_5752M: 2170 cidp->chip_label = 5752; 2171 cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705; 2172 cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705; 2173 cidp->mbuf_hi_water = MBUF_HIWAT_5705; 2174 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2175 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2176 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2177 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2178 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2179 cidp->tx_rings = BGE_SEND_RINGS_MAX_5705; 2180 cidp->pci_type = BGE_PCI_E; 2181 cidp->statistic_type = BGE_STAT_REG; 2182 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2183 dev_ok = B_TRUE; 2184 break; 2185 2186 case DEVICE_ID_5789: 2187 cidp->chip_label = 5789; 2188 cidp->mbuf_base = bge_mbuf_pool_base_5721; 2189 cidp->mbuf_length = bge_mbuf_pool_len_5721; 2190 cidp->recv_slots = BGE_RECV_SLOTS_5721; 2191 cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721; 2192 cidp->rx_rings = BGE_RECV_RINGS_MAX_5705; 2193 cidp->tx_rings = BGE_RECV_RINGS_MAX_5705; 2194 cidp->pci_type = BGE_PCI_E; 2195 cidp->statistic_type = BGE_STAT_REG; 2196 cidp->flags |= CHIP_FLAG_PARTIAL_CSUM; 2197 cidp->flags |= CHIP_FLAG_NO_JUMBO; 2198 cidp->msi_enabled = B_TRUE; 2199 dev_ok = B_TRUE; 2200 break; 2201 2202 } 2203 2204 /* 2205 * Setup the default jumbo parameter. 2206 */ 2207 cidp->ethmax_size = ETHERMAX; 2208 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT; 2209 cidp->std_buf_size = BGE_STD_BUFF_SIZE; 2210 2211 /* 2212 * If jumbo is enabled and this kind of chipset supports jumbo feature, 2213 * setup below jumbo specific parameters. 2214 * 2215 * For BCM5714/5715, there is only one standard receive ring. So the 2216 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo 2217 * feature is enabled. 2218 */ 2219 if (bge_jumbo_enable && 2220 !(cidp->flags & CHIP_FLAG_NO_JUMBO) && 2221 (cidp->default_mtu > BGE_DEFAULT_MTU) && 2222 (cidp->default_mtu <= BGE_MAXIMUM_MTU)) { 2223 if (DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2224 cidp->mbuf_lo_water_rdma = 2225 RDMA_MBUF_LOWAT_5714_JUMBO; 2226 cidp->mbuf_lo_water_rmac = 2227 MAC_RX_MBUF_LOWAT_5714_JUMBO; 2228 cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO; 2229 cidp->jumbo_slots = 0; 2230 cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE; 2231 } else { 2232 cidp->mbuf_lo_water_rdma = 2233 RDMA_MBUF_LOWAT_JUMBO; 2234 cidp->mbuf_lo_water_rmac = 2235 MAC_RX_MBUF_LOWAT_JUMBO; 2236 cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO; 2237 cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED; 2238 } 2239 cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE; 2240 cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO; 2241 cidp->ethmax_size = cidp->default_mtu + 2242 sizeof (struct ether_header); 2243 } 2244 2245 /* 2246 * Identify the NV memory type: SEEPROM or Flash? 2247 */ 2248 cidp->nvtype = bge_nvmem_id(bgep); 2249 2250 /* 2251 * Now, we want to check whether this device is part of a 2252 * supported subsystem (e.g., on the motherboard of a Sun 2253 * branded platform). 2254 * 2255 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-) 2256 */ 2257 if (cidp->subven == VENDOR_ID_SUN) 2258 sys_ok = B_TRUE; 2259 2260 /* 2261 * Rule 2: If it's on the list on known subsystems, then it's OK. 2262 * Note: 0x14e41647 should *not* appear in the list, but the code 2263 * doesn't enforce that. 2264 */ 2265 err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo, 2266 DDI_PROP_DONTPASS, knownids_propname, &ids, &i); 2267 if (err == DDI_PROP_SUCCESS) { 2268 /* 2269 * Got the list; scan for a matching subsystem vendor/device 2270 */ 2271 subid = (cidp->subven << 16) | cidp->subdev; 2272 while (i--) 2273 if (ids[i] == subid) 2274 sys_ok = B_TRUE; 2275 ddi_prop_free(ids); 2276 } 2277 2278 /* 2279 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK 2280 * 2281 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram 2282 * the Subsystem Vendor ID, so it defaults to Broadcom. Therefore, 2283 * we have to check specially for the exact device paths to the 2284 * motherboard devices on those platforms ;-( 2285 * 2286 * Note: we can't just use the "supported-subsystems" mechanism 2287 * above, because the entry would have to be 0x14e41647 -- which 2288 * would then accept *any* plugin card that *didn't* contain a 2289 * (valid) SEEPROM ;-( 2290 */ 2291 sysname = ddi_node_name(ddi_root_node()); 2292 devname = ddi_pathname(bgep->devinfo, buf); 2293 ASSERT(strlen(devname) > 0); 2294 if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0) /* Taco */ 2295 if (strcmp(devname, "/pci@1f,700000/network@2") == 0) 2296 sys_ok = B_TRUE; 2297 if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0) /* ENWS */ 2298 if (strcmp(devname, "/pci@1c,600000/network@3") == 0) 2299 sys_ok = B_TRUE; 2300 2301 /* 2302 * Now check what we've discovered: is this truly a supported 2303 * chip on (the motherboard of) a supported platform? 2304 * 2305 * Possible problems here: 2306 * 1) it's a completely unheard-of chip (e.g. 5761) 2307 * 2) it's a recognised but unsupported chip (e.g. 5701, 5703C-A0) 2308 * 3) it's a chip we would support if it were on the motherboard 2309 * of a Sun platform, but this one isn't ;-( 2310 */ 2311 if (cidp->chip_label == 0) 2312 bge_problem(bgep, 2313 "Device 'pci%04x,%04x' not recognized (%d?)", 2314 cidp->vendor, cidp->device, cidp->device); 2315 else if (!dev_ok) 2316 bge_problem(bgep, 2317 "Device 'pci%04x,%04x' (%d) revision %d not supported", 2318 cidp->vendor, cidp->device, cidp->chip_label, 2319 cidp->revision); 2320 #if BGE_DEBUGGING 2321 else if (!sys_ok) 2322 bge_problem(bgep, 2323 "%d-based subsystem 'pci%04x,%04x' not validated", 2324 cidp->chip_label, cidp->subven, cidp->subdev); 2325 #endif 2326 else 2327 cidp->flags |= CHIP_FLAG_SUPPORTED; 2328 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 2329 return (EIO); 2330 return (0); 2331 } 2332 2333 void 2334 bge_chip_msi_trig(bge_t *bgep) 2335 { 2336 uint32_t regval; 2337 2338 regval = bgep->param_msi_cnt<<4; 2339 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval); 2340 BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval)); 2341 } 2342 2343 /* 2344 * Various registers that control the chip's internal engines (state 2345 * machines) have a <reset> and <enable> bits (fortunately, in the 2346 * same place in each such register :-). 2347 * 2348 * To reset the state machine, the <reset> bit must be written with 1; 2349 * it will then read back as 1 while the reset is in progress, but 2350 * self-clear to 0 when the reset completes. 2351 * 2352 * To enable a state machine, one must set the <enable> bit, which 2353 * will continue to read back as 0 until the state machine is running. 2354 * 2355 * To disable a state machine, the <enable> bit must be cleared, but 2356 * it will continue to read back as 1 until the state machine actually 2357 * stops. 2358 * 2359 * This routine implements polling for completion of a reset, enable 2360 * or disable operation, returning B_TRUE on success (bit reached the 2361 * required state) or B_FALSE on timeout (200*100us == 20ms). 2362 */ 2363 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2364 uint32_t mask, uint32_t val); 2365 #pragma no_inline(bge_chip_poll_engine) 2366 2367 static boolean_t 2368 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno, 2369 uint32_t mask, uint32_t val) 2370 { 2371 uint32_t regval; 2372 uint32_t n; 2373 2374 BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)", 2375 (void *)bgep, regno, mask, val)); 2376 2377 for (n = 200; n; --n) { 2378 regval = bge_reg_get32(bgep, regno); 2379 if ((regval & mask) == val) 2380 return (B_TRUE); 2381 drv_usecwait(100); 2382 } 2383 2384 bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE); 2385 return (B_FALSE); 2386 } 2387 2388 /* 2389 * Various registers that control the chip's internal engines (state 2390 * machines) have a <reset> bit (fortunately, in the same place in 2391 * each such register :-). To reset the state machine, this bit must 2392 * be written with 1; it will then read back as 1 while the reset is 2393 * in progress, but self-clear to 0 when the reset completes. 2394 * 2395 * This code sets the bit, then polls for it to read back as zero. 2396 * The return value is B_TRUE on success (reset bit cleared itself), 2397 * or B_FALSE if the state machine didn't recover :( 2398 * 2399 * NOTE: the Core reset is similar to other resets, except that we 2400 * can't poll for completion, since the Core reset disables memory 2401 * access! So we just have to assume that it will all complete in 2402 * 100us. See Broadcom document 570X-PG102-R, p102, steps 4-5. 2403 */ 2404 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno); 2405 #pragma no_inline(bge_chip_reset_engine) 2406 2407 static boolean_t 2408 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno) 2409 { 2410 uint32_t regval; 2411 uint32_t val32; 2412 2413 regval = bge_reg_get32(bgep, regno); 2414 2415 BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)", 2416 (void *)bgep, regno)); 2417 BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x", 2418 regno, regval)); 2419 2420 regval |= STATE_MACHINE_RESET_BIT; 2421 2422 switch (regno) { 2423 case MISC_CONFIG_REG: 2424 /* 2425 * BCM5714/5721/5751 pcie chip special case. In order to avoid 2426 * resetting PCIE block and bringing PCIE link down, bit 29 2427 * in the register needs to be set first, and then set it again 2428 * while the reset bit is written. 2429 * See:P500 of 57xx-PG102-RDS.pdf. 2430 */ 2431 if (DEVICE_5705_SERIES_CHIPSETS(bgep)|| 2432 DEVICE_5721_SERIES_CHIPSETS(bgep)|| 2433 DEVICE_5714_SERIES_CHIPSETS(bgep)) { 2434 regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE; 2435 if (bgep->chipid.pci_type == BGE_PCI_E) { 2436 if (bgep->chipid.asic_rev == 2437 MHCR_CHIP_REV_5751_A0 || 2438 bgep->chipid.asic_rev == 2439 MHCR_CHIP_REV_5721_A0) { 2440 val32 = bge_reg_get32(bgep, 2441 PHY_TEST_CTRL_REG); 2442 if (val32 == (PHY_PCIE_SCRAM_MODE | 2443 PHY_PCIE_LTASS_MODE)) 2444 bge_reg_put32(bgep, 2445 PHY_TEST_CTRL_REG, 2446 PHY_PCIE_SCRAM_MODE); 2447 val32 = pci_config_get32 2448 (bgep->cfg_handle, 2449 PCI_CONF_BGE_CLKCTL); 2450 val32 |= CLKCTL_PCIE_A0_FIX; 2451 pci_config_put32(bgep->cfg_handle, 2452 PCI_CONF_BGE_CLKCTL, val32); 2453 } 2454 bge_reg_set32(bgep, regno, 2455 MISC_CONFIG_GRC_RESET_DISABLE); 2456 regval |= MISC_CONFIG_GRC_RESET_DISABLE; 2457 } 2458 } 2459 2460 /* 2461 * Special case - causes Core reset 2462 * 2463 * On SPARC v9 we want to ensure that we don't start 2464 * timing until the I/O access has actually reached 2465 * the chip, otherwise we might make the next access 2466 * too early. And we can't just force the write out 2467 * by following it with a read (even to config space) 2468 * because that would cause the fault we're trying 2469 * to avoid. Hence the need for membar_sync() here. 2470 */ 2471 ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval); 2472 #ifdef __sparcv9 2473 membar_sync(); 2474 #endif /* __sparcv9 */ 2475 /* 2476 * On some platforms,system need about 300us for 2477 * link setup. 2478 */ 2479 drv_usecwait(300); 2480 2481 if (bgep->chipid.pci_type == BGE_PCI_E) { 2482 /* PCI-E device need more reset time */ 2483 drv_usecwait(120000); 2484 2485 /* Set PCIE max payload size and clear error status. */ 2486 if ((bgep->chipid.chip_label == 5721) || 2487 (bgep->chipid.chip_label == 5751) || 2488 (bgep->chipid.chip_label == 5752) || 2489 (bgep->chipid.chip_label == 5789)) { 2490 pci_config_put16(bgep->cfg_handle, 2491 PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX); 2492 pci_config_put16(bgep->cfg_handle, 2493 PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS); 2494 } 2495 } 2496 2497 BGE_PCICHK(bgep); 2498 return (B_TRUE); 2499 2500 default: 2501 bge_reg_put32(bgep, regno, regval); 2502 return (bge_chip_poll_engine(bgep, regno, 2503 STATE_MACHINE_RESET_BIT, 0)); 2504 } 2505 } 2506 2507 /* 2508 * Various registers that control the chip's internal engines (state 2509 * machines) have an <enable> bit (fortunately, in the same place in 2510 * each such register :-). To stop the state machine, this bit must 2511 * be written with 0, then polled to see when the state machine has 2512 * actually stopped. 2513 * 2514 * The return value is B_TRUE on success (enable bit cleared), or 2515 * B_FALSE if the state machine didn't stop :( 2516 */ 2517 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, 2518 uint32_t morebits); 2519 #pragma no_inline(bge_chip_disable_engine) 2520 2521 static boolean_t 2522 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2523 { 2524 uint32_t regval; 2525 2526 BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)", 2527 (void *)bgep, regno, morebits)); 2528 2529 switch (regno) { 2530 case FTQ_RESET_REG: 2531 /* 2532 * For Schumacher's bugfix CR6490108 2533 */ 2534 #ifdef BGE_IPMI_ASF 2535 #ifdef BGE_NETCONSOLE 2536 if (bgep->asf_enabled) 2537 return (B_TRUE); 2538 #endif 2539 #endif 2540 /* 2541 * Not quite like the others; it doesn't 2542 * have an <enable> bit, but instead we 2543 * have to set and then clear all the bits 2544 */ 2545 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2546 drv_usecwait(100); 2547 bge_reg_put32(bgep, regno, 0); 2548 return (B_TRUE); 2549 2550 default: 2551 regval = bge_reg_get32(bgep, regno); 2552 regval &= ~STATE_MACHINE_ENABLE_BIT; 2553 regval &= ~morebits; 2554 bge_reg_put32(bgep, regno, regval); 2555 return (bge_chip_poll_engine(bgep, regno, 2556 STATE_MACHINE_ENABLE_BIT, 0)); 2557 } 2558 } 2559 2560 /* 2561 * Various registers that control the chip's internal engines (state 2562 * machines) have an <enable> bit (fortunately, in the same place in 2563 * each such register :-). To start the state machine, this bit must 2564 * be written with 1, then polled to see when the state machine has 2565 * actually started. 2566 * 2567 * The return value is B_TRUE on success (enable bit set), or 2568 * B_FALSE if the state machine didn't start :( 2569 */ 2570 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, 2571 uint32_t morebits); 2572 #pragma no_inline(bge_chip_enable_engine) 2573 2574 static boolean_t 2575 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits) 2576 { 2577 uint32_t regval; 2578 2579 BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)", 2580 (void *)bgep, regno, morebits)); 2581 2582 switch (regno) { 2583 case FTQ_RESET_REG: 2584 #ifdef BGE_IPMI_ASF 2585 #ifdef BGE_NETCONSOLE 2586 if (bgep->asf_enabled) 2587 return (B_TRUE); 2588 #endif 2589 #endif 2590 /* 2591 * Not quite like the others; it doesn't 2592 * have an <enable> bit, but instead we 2593 * have to set and then clear all the bits 2594 */ 2595 bge_reg_put32(bgep, regno, ~(uint32_t)0); 2596 drv_usecwait(100); 2597 bge_reg_put32(bgep, regno, 0); 2598 return (B_TRUE); 2599 2600 default: 2601 regval = bge_reg_get32(bgep, regno); 2602 regval |= STATE_MACHINE_ENABLE_BIT; 2603 regval |= morebits; 2604 bge_reg_put32(bgep, regno, regval); 2605 return (bge_chip_poll_engine(bgep, regno, 2606 STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT)); 2607 } 2608 } 2609 2610 /* 2611 * Reprogram the Ethernet, Transmit, and Receive MAC 2612 * modes to match the param_* variables 2613 */ 2614 static void bge_sync_mac_modes(bge_t *bgep); 2615 #pragma no_inline(bge_sync_mac_modes) 2616 2617 static void 2618 bge_sync_mac_modes(bge_t *bgep) 2619 { 2620 uint32_t macmode; 2621 uint32_t regval; 2622 2623 ASSERT(mutex_owned(bgep->genlock)); 2624 2625 /* 2626 * Reprogram the Ethernet MAC mode ... 2627 */ 2628 macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG); 2629 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2630 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2631 macmode &= ~ETHERNET_MODE_LINK_POLARITY; 2632 else 2633 macmode |= ETHERNET_MODE_LINK_POLARITY; 2634 macmode &= ~ETHERNET_MODE_PORTMODE_MASK; 2635 if ((bgep->chipid.flags & CHIP_FLAG_SERDES) && 2636 (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) 2637 macmode |= ETHERNET_MODE_PORTMODE_TBI; 2638 else if (bgep->param_link_speed == 10 || bgep->param_link_speed == 100) 2639 macmode |= ETHERNET_MODE_PORTMODE_MII; 2640 else 2641 macmode |= ETHERNET_MODE_PORTMODE_GMII; 2642 if (bgep->param_link_duplex == LINK_DUPLEX_HALF) 2643 macmode |= ETHERNET_MODE_HALF_DUPLEX; 2644 else 2645 macmode &= ~ETHERNET_MODE_HALF_DUPLEX; 2646 if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC) 2647 macmode |= ETHERNET_MODE_MAC_LOOPBACK; 2648 else 2649 macmode &= ~ETHERNET_MODE_MAC_LOOPBACK; 2650 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode); 2651 BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x", 2652 (void *)bgep, regval, macmode)); 2653 2654 /* 2655 * ... the Transmit MAC mode ... 2656 */ 2657 macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG); 2658 if (bgep->param_link_tx_pause) 2659 macmode |= TRANSMIT_MODE_FLOW_CONTROL; 2660 else 2661 macmode &= ~TRANSMIT_MODE_FLOW_CONTROL; 2662 bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode); 2663 BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x", 2664 (void *)bgep, regval, macmode)); 2665 2666 /* 2667 * ... and the Receive MAC mode 2668 */ 2669 macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG); 2670 if (bgep->param_link_rx_pause) 2671 macmode |= RECEIVE_MODE_FLOW_CONTROL; 2672 else 2673 macmode &= ~RECEIVE_MODE_FLOW_CONTROL; 2674 bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode); 2675 BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x", 2676 (void *)bgep, regval, macmode)); 2677 } 2678 2679 /* 2680 * bge_chip_sync() -- program the chip with the unicast MAC address, 2681 * the multicast hash table, the required level of promiscuity, and 2682 * the current loopback mode ... 2683 */ 2684 #ifdef BGE_IPMI_ASF 2685 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive); 2686 #else 2687 int bge_chip_sync(bge_t *bgep); 2688 #endif 2689 #pragma no_inline(bge_chip_sync) 2690 2691 int 2692 #ifdef BGE_IPMI_ASF 2693 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive) 2694 #else 2695 bge_chip_sync(bge_t *bgep) 2696 #endif 2697 { 2698 void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits); 2699 boolean_t promisc; 2700 uint64_t macaddr; 2701 uint32_t fill; 2702 int i, j; 2703 int retval = DDI_SUCCESS; 2704 2705 BGE_TRACE(("bge_chip_sync($%p)", 2706 (void *)bgep)); 2707 2708 ASSERT(mutex_owned(bgep->genlock)); 2709 2710 promisc = B_FALSE; 2711 fill = ~(uint32_t)0; 2712 2713 if (bgep->promisc) 2714 promisc = B_TRUE; 2715 else 2716 fill = (uint32_t)0; 2717 2718 /* 2719 * If the TX/RX MAC engines are already running, we should stop 2720 * them (and reset the RX engine) before changing the parameters. 2721 * If they're not running, this will have no effect ... 2722 * 2723 * NOTE: this is currently disabled by default because stopping 2724 * and restarting the Tx engine may cause an outgoing packet in 2725 * transit to be truncated. Also, stopping and restarting the 2726 * Rx engine seems to not work correctly on the 5705. Testing 2727 * has not (yet!) revealed any problems with NOT stopping and 2728 * restarting these engines (and Broadcom say their drivers don't 2729 * do this), but if it is found to cause problems, this variable 2730 * can be patched to re-enable the old behaviour ... 2731 */ 2732 if (bge_stop_start_on_sync) { 2733 #ifdef BGE_IPMI_ASF 2734 if (!bgep->asf_enabled) { 2735 if (!bge_chip_disable_engine(bgep, 2736 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2737 retval = DDI_FAILURE; 2738 } else { 2739 if (!bge_chip_disable_engine(bgep, 2740 RECEIVE_MAC_MODE_REG, 0)) 2741 retval = DDI_FAILURE; 2742 } 2743 #else 2744 if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG, 2745 RECEIVE_MODE_KEEP_VLAN_TAG)) 2746 retval = DDI_FAILURE; 2747 #endif 2748 if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2749 retval = DDI_FAILURE; 2750 if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG)) 2751 retval = DDI_FAILURE; 2752 } 2753 2754 /* 2755 * Reprogram the hashed multicast address table ... 2756 */ 2757 for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i) 2758 bge_reg_put32(bgep, MAC_HASH_REG(i), 2759 bgep->mcast_hash[i] | fill); 2760 2761 #ifdef BGE_IPMI_ASF 2762 if (!bgep->asf_enabled || !asf_keeplive) { 2763 #endif 2764 /* 2765 * Transform the MAC address(es) from host to chip format, then 2766 * reprogram the transmit random backoff seed and the unicast 2767 * MAC address(es) ... 2768 */ 2769 for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) { 2770 for (i = 0, fill = 0, macaddr = 0ull; 2771 i < ETHERADDRL; ++i) { 2772 macaddr <<= 8; 2773 macaddr |= bgep->curr_addr[j].addr[i]; 2774 fill += bgep->curr_addr[j].addr[i]; 2775 } 2776 bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill); 2777 bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr); 2778 } 2779 2780 BGE_DEBUG(("bge_chip_sync($%p) setting MAC address %012llx", 2781 (void *)bgep, macaddr)); 2782 #ifdef BGE_IPMI_ASF 2783 } 2784 #endif 2785 2786 /* 2787 * Set or clear the PROMISCUOUS mode bit 2788 */ 2789 opfn = promisc ? bge_reg_set32 : bge_reg_clr32; 2790 (*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS); 2791 2792 /* 2793 * Sync the rest of the MAC modes too ... 2794 */ 2795 bge_sync_mac_modes(bgep); 2796 2797 /* 2798 * Restart RX/TX MAC engines if required ... 2799 */ 2800 if (bgep->bge_chip_state == BGE_CHIP_RUNNING) { 2801 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 2802 retval = DDI_FAILURE; 2803 #ifdef BGE_IPMI_ASF 2804 if (!bgep->asf_enabled) { 2805 if (!bge_chip_enable_engine(bgep, 2806 RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG)) 2807 retval = DDI_FAILURE; 2808 } else { 2809 if (!bge_chip_enable_engine(bgep, 2810 RECEIVE_MAC_MODE_REG, 0)) 2811 retval = DDI_FAILURE; 2812 } 2813 #else 2814 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 2815 RECEIVE_MODE_KEEP_VLAN_TAG)) 2816 retval = DDI_FAILURE; 2817 #endif 2818 } 2819 return (retval); 2820 } 2821 2822 /* 2823 * This array defines the sequence of state machine control registers 2824 * in which the <enable> bit must be cleared to bring the chip to a 2825 * clean stop. Taken from Broadcom document 570X-PG102-R, p116. 2826 */ 2827 static bge_regno_t shutdown_engine_regs[] = { 2828 RECEIVE_MAC_MODE_REG, 2829 RCV_BD_INITIATOR_MODE_REG, 2830 RCV_LIST_PLACEMENT_MODE_REG, 2831 RCV_LIST_SELECTOR_MODE_REG, /* BCM5704 series only */ 2832 RCV_DATA_BD_INITIATOR_MODE_REG, 2833 RCV_DATA_COMPLETION_MODE_REG, 2834 RCV_BD_COMPLETION_MODE_REG, 2835 2836 SEND_BD_SELECTOR_MODE_REG, 2837 SEND_BD_INITIATOR_MODE_REG, 2838 SEND_DATA_INITIATOR_MODE_REG, 2839 READ_DMA_MODE_REG, 2840 SEND_DATA_COMPLETION_MODE_REG, 2841 DMA_COMPLETION_MODE_REG, /* BCM5704 series only */ 2842 SEND_BD_COMPLETION_MODE_REG, 2843 TRANSMIT_MAC_MODE_REG, 2844 2845 HOST_COALESCE_MODE_REG, 2846 WRITE_DMA_MODE_REG, 2847 MBUF_CLUSTER_FREE_MODE_REG, /* BCM5704 series only */ 2848 FTQ_RESET_REG, /* special - see code */ 2849 BUFFER_MANAGER_MODE_REG, /* BCM5704 series only */ 2850 MEMORY_ARBITER_MODE_REG, /* BCM5704 series only */ 2851 BGE_REGNO_NONE /* terminator */ 2852 }; 2853 2854 /* 2855 * bge_chip_stop() -- stop all chip processing 2856 * 2857 * If the <fault> parameter is B_TRUE, we're stopping the chip because 2858 * we've detected a problem internally; otherwise, this is a normal 2859 * (clean) stop (at user request i.e. the last STREAM has been closed). 2860 */ 2861 void bge_chip_stop(bge_t *bgep, boolean_t fault); 2862 #pragma no_inline(bge_chip_stop) 2863 2864 void 2865 bge_chip_stop(bge_t *bgep, boolean_t fault) 2866 { 2867 bge_regno_t regno; 2868 bge_regno_t *rbp; 2869 boolean_t ok; 2870 2871 BGE_TRACE(("bge_chip_stop($%p)", 2872 (void *)bgep)); 2873 2874 ASSERT(mutex_owned(bgep->genlock)); 2875 2876 rbp = shutdown_engine_regs; 2877 /* 2878 * When driver try to shutdown the BCM5705/5788/5721/5751/ 2879 * 5752/5714 and 5715 chipsets,the buffer manager and the mem 2880 * -ory arbiter should not be disabled. 2881 */ 2882 for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) { 2883 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 2884 ok &= bge_chip_disable_engine(bgep, regno, 0); 2885 else if ((regno != RCV_LIST_SELECTOR_MODE_REG) && 2886 (regno != DMA_COMPLETION_MODE_REG) && 2887 (regno != MBUF_CLUSTER_FREE_MODE_REG)&& 2888 (regno != BUFFER_MANAGER_MODE_REG) && 2889 (regno != MEMORY_ARBITER_MODE_REG)) 2890 ok &= bge_chip_disable_engine(bgep, 2891 regno, 0); 2892 } 2893 2894 if (!ok && !fault) 2895 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 2896 2897 /* 2898 * Finally, disable (all) MAC events & clear the MAC status 2899 */ 2900 bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0); 2901 bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0); 2902 2903 /* 2904 * if we're stopping the chip because of a detected fault then do 2905 * appropriate actions 2906 */ 2907 if (fault) { 2908 if (bgep->bge_chip_state != BGE_CHIP_FAULT) { 2909 bgep->bge_chip_state = BGE_CHIP_FAULT; 2910 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_LOST); 2911 if (bgep->bge_dma_error) { 2912 /* 2913 * need to free buffers in case the fault was 2914 * due to a memory error in a buffer - got to 2915 * do a fair bit of tidying first 2916 */ 2917 if (bgep->progress & PROGRESS_KSTATS) { 2918 bge_fini_kstats(bgep); 2919 bgep->progress &= ~PROGRESS_KSTATS; 2920 } 2921 if (bgep->progress & PROGRESS_INTR) { 2922 bge_intr_disable(bgep); 2923 rw_enter(bgep->errlock, RW_WRITER); 2924 bge_fini_rings(bgep); 2925 rw_exit(bgep->errlock); 2926 bgep->progress &= ~PROGRESS_INTR; 2927 } 2928 if (bgep->progress & PROGRESS_BUFS) { 2929 bge_free_bufs(bgep); 2930 bgep->progress &= ~PROGRESS_BUFS; 2931 } 2932 bgep->bge_dma_error = B_FALSE; 2933 } 2934 } 2935 } else 2936 bgep->bge_chip_state = BGE_CHIP_STOPPED; 2937 } 2938 2939 /* 2940 * Poll for completion of chip's ROM firmware; also, at least on the 2941 * first time through, find and return the hardware MAC address, if any. 2942 */ 2943 static uint64_t bge_poll_firmware(bge_t *bgep); 2944 #pragma no_inline(bge_poll_firmware) 2945 2946 static uint64_t 2947 bge_poll_firmware(bge_t *bgep) 2948 { 2949 uint64_t magic; 2950 uint64_t mac; 2951 uint32_t gen; 2952 uint32_t i; 2953 2954 /* 2955 * Step 19: poll for firmware completion (GENCOMM port set 2956 * to the ones complement of T3_MAGIC_NUMBER). 2957 * 2958 * While we're at it, we also read the MAC address register; 2959 * at some stage the firmware will load this with the 2960 * factory-set value. 2961 * 2962 * When both the magic number and the MAC address are set, 2963 * we're done; but we impose a time limit of one second 2964 * (1000*1000us) in case the firmware fails in some fashion 2965 * or the SEEPROM that provides that MAC address isn't fitted. 2966 * 2967 * After the first time through (chip state != INITIAL), we 2968 * don't need the MAC address to be set (we've already got it 2969 * or not, from the first time), so we don't wait for it, but 2970 * we still have to wait for the T3_MAGIC_NUMBER. 2971 * 2972 * Note: the magic number is only a 32-bit quantity, but the NIC 2973 * memory is 64-bit (and big-endian) internally. Addressing the 2974 * GENCOMM word as "the upper half of a 64-bit quantity" makes 2975 * it work correctly on both big- and little-endian hosts. 2976 */ 2977 for (i = 0; i < 1000; ++i) { 2978 drv_usecwait(1000); 2979 gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32; 2980 mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0)); 2981 #ifdef BGE_IPMI_ASF 2982 if (!bgep->asf_enabled) { 2983 #endif 2984 if (gen != ~T3_MAGIC_NUMBER) 2985 continue; 2986 #ifdef BGE_IPMI_ASF 2987 } 2988 #endif 2989 if (mac != 0ULL) 2990 break; 2991 if (bgep->bge_chip_state != BGE_CHIP_INITIAL) 2992 break; 2993 } 2994 2995 magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM); 2996 BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops", 2997 (void *)bgep, gen, i)); 2998 BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx", 2999 mac, magic)); 3000 3001 return (mac); 3002 } 3003 3004 /* 3005 * Maximum times of trying to get the NVRAM access lock 3006 * by calling bge_nvmem_acquire() 3007 */ 3008 #define MAX_TRY_NVMEM_ACQUIRE 10000 3009 3010 #ifdef BGE_IPMI_ASF 3011 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode); 3012 #else 3013 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma); 3014 #endif 3015 #pragma no_inline(bge_chip_reset) 3016 3017 int 3018 #ifdef BGE_IPMI_ASF 3019 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode) 3020 #else 3021 bge_chip_reset(bge_t *bgep, boolean_t enable_dma) 3022 #endif 3023 { 3024 chip_id_t chipid; 3025 uint64_t mac; 3026 uint64_t magic; 3027 uint32_t modeflags; 3028 uint32_t mhcr; 3029 uint32_t sx0; 3030 uint32_t i, tries; 3031 #ifdef BGE_IPMI_ASF 3032 uint32_t mailbox; 3033 #endif 3034 int retval = DDI_SUCCESS; 3035 3036 BGE_TRACE(("bge_chip_reset($%p, %d)", 3037 (void *)bgep, enable_dma)); 3038 3039 ASSERT(mutex_owned(bgep->genlock)); 3040 3041 BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d", 3042 (void *)bgep, enable_dma, bgep->bge_chip_state)); 3043 3044 /* 3045 * Do we need to stop the chip cleanly before resetting? 3046 */ 3047 switch (bgep->bge_chip_state) { 3048 default: 3049 _NOTE(NOTREACHED) 3050 return (DDI_FAILURE); 3051 3052 case BGE_CHIP_INITIAL: 3053 case BGE_CHIP_STOPPED: 3054 case BGE_CHIP_RESET: 3055 break; 3056 3057 case BGE_CHIP_RUNNING: 3058 case BGE_CHIP_ERROR: 3059 case BGE_CHIP_FAULT: 3060 bge_chip_stop(bgep, B_FALSE); 3061 break; 3062 } 3063 3064 #ifdef BGE_IPMI_ASF 3065 if (bgep->asf_enabled) { 3066 #ifdef __sparc 3067 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3068 MHCR_ENABLE_TAGGED_STATUS_MODE | 3069 MHCR_MASK_INTERRUPT_MODE | 3070 MHCR_MASK_PCI_INT_OUTPUT | 3071 MHCR_CLEAR_INTERRUPT_INTA | 3072 MHCR_ENABLE_ENDIAN_WORD_SWAP | 3073 MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3074 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3075 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3076 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) | 3077 MEMORY_ARBITER_ENABLE); 3078 #endif 3079 if (asf_mode == ASF_MODE_INIT) { 3080 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 3081 } else if (asf_mode == ASF_MODE_SHUTDOWN) { 3082 bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET); 3083 } 3084 } 3085 #endif 3086 /* 3087 * Adapted from Broadcom document 570X-PG102-R, pp 102-116. 3088 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159. 3089 * 3090 * Before reset Core clock,it is 3091 * also required to initialize the Memory Arbiter as specified in step9 3092 * and Misc Host Control Register as specified in step-13 3093 * Step 4-5: reset Core clock & wait for completion 3094 * Steps 6-8: are done by bge_chip_cfg_init() 3095 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset 3096 */ 3097 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3098 retval = DDI_FAILURE; 3099 3100 mhcr = MHCR_ENABLE_INDIRECT_ACCESS | 3101 MHCR_ENABLE_TAGGED_STATUS_MODE | 3102 MHCR_MASK_INTERRUPT_MODE | 3103 MHCR_MASK_PCI_INT_OUTPUT | 3104 MHCR_CLEAR_INTERRUPT_INTA; 3105 #ifdef _BIG_ENDIAN 3106 mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP; 3107 #endif /* _BIG_ENDIAN */ 3108 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr); 3109 #ifdef BGE_IPMI_ASF 3110 if (bgep->asf_enabled) 3111 bgep->asf_wordswapped = B_FALSE; 3112 #endif 3113 /* 3114 * NVRAM Corruption Workaround 3115 */ 3116 for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++) 3117 if (bge_nvmem_acquire(bgep) != EAGAIN) 3118 break; 3119 if (tries >= MAX_TRY_NVMEM_ACQUIRE) 3120 BGE_DEBUG(("%s: fail to acquire nvram lock", 3121 bgep->ifname)); 3122 3123 #ifdef BGE_IPMI_ASF 3124 if (!bgep->asf_enabled) { 3125 #endif 3126 magic = (uint64_t)T3_MAGIC_NUMBER << 32; 3127 bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic); 3128 #ifdef BGE_IPMI_ASF 3129 } 3130 #endif 3131 3132 if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG)) 3133 retval = DDI_FAILURE; 3134 bge_chip_cfg_init(bgep, &chipid, enable_dma); 3135 3136 /* 3137 * Step 8a: This may belong elsewhere, but BCM5721 needs 3138 * a bit set to avoid a fifo overflow/underflow bug. 3139 */ 3140 if ((bgep->chipid.chip_label == 5721) || 3141 (bgep->chipid.chip_label == 5751) || 3142 (bgep->chipid.chip_label == 5752) || 3143 (bgep->chipid.chip_label == 5789)) 3144 bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT); 3145 3146 3147 /* 3148 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should 3149 * not be changed. 3150 */ 3151 if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0)) 3152 retval = DDI_FAILURE; 3153 3154 /* 3155 * Steps 10-11: configure PIO endianness options and 3156 * enable indirect register access -- already done 3157 * Steps 12-13: enable writing to the PCI state & clock 3158 * control registers -- not required; we aren't going to 3159 * use those features. 3160 * Steps 14-15: Configure DMA endianness options. See 3161 * the comments on the setting of the MHCR above. 3162 */ 3163 #ifdef _BIG_ENDIAN 3164 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME | 3165 MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME; 3166 #else 3167 modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME; 3168 #endif /* _BIG_ENDIAN */ 3169 #ifdef BGE_IPMI_ASF 3170 if (bgep->asf_enabled) 3171 modeflags |= MODE_HOST_STACK_UP; 3172 #endif 3173 bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags); 3174 3175 #ifdef BGE_IPMI_ASF 3176 if (bgep->asf_enabled) { 3177 #ifdef __sparc 3178 bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG, 3179 MEMORY_ARBITER_ENABLE | 3180 bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG)); 3181 #endif 3182 3183 #ifdef BGE_NETCONSOLE 3184 if (!bgep->asf_newhandshake) { 3185 if ((asf_mode == ASF_MODE_INIT) || 3186 (asf_mode == ASF_MODE_POST_INIT)) { 3187 bge_asf_post_reset_old_mode(bgep, 3188 BGE_INIT_RESET); 3189 } else { 3190 bge_asf_post_reset_old_mode(bgep, 3191 BGE_SHUTDOWN_RESET); 3192 } 3193 } 3194 #endif 3195 3196 /* Wait for NVRAM init */ 3197 i = 0; 3198 drv_usecwait(5000); 3199 mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX); 3200 3201 while ((mailbox != (uint32_t) 3202 ~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) && 3203 (i < 10000)) { 3204 drv_usecwait(100); 3205 mailbox = bge_nic_get32(bgep, 3206 BGE_FIRMWARE_MAILBOX); 3207 i++; 3208 } 3209 3210 #ifndef BGE_NETCONSOLE 3211 if (!bgep->asf_newhandshake) { 3212 if ((asf_mode == ASF_MODE_INIT) || 3213 (asf_mode == ASF_MODE_POST_INIT)) { 3214 3215 bge_asf_post_reset_old_mode(bgep, 3216 BGE_INIT_RESET); 3217 } else { 3218 bge_asf_post_reset_old_mode(bgep, 3219 BGE_SHUTDOWN_RESET); 3220 } 3221 } 3222 #endif 3223 } 3224 #endif 3225 /* 3226 * Steps 16-17: poll for firmware completion 3227 */ 3228 mac = bge_poll_firmware(bgep); 3229 3230 /* 3231 * Step 18: enable external memory -- doesn't apply. 3232 * 3233 * However we take the opportunity to set the MLCR anyway, as 3234 * this register also controls the SEEPROM auto-access method 3235 * which we may want to use later ... 3236 * 3237 * The proper value here depends on the way the chip is wired 3238 * into the circuit board, as this register *also* controls which 3239 * of the "Miscellaneous I/O" pins are driven as outputs and the 3240 * values driven onto those pins! 3241 * 3242 * See also step 74 in the PRM ... 3243 */ 3244 bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, 3245 bgep->chipid.bge_mlcr_default); 3246 bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT); 3247 3248 /* 3249 * Step 20: clear the Ethernet MAC mode register 3250 */ 3251 bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0); 3252 3253 /* 3254 * Step 21: restore cache-line-size, latency timer, and 3255 * subsystem ID registers to their original values (not 3256 * those read into the local structure <chipid>, 'cos 3257 * that was after they were cleared by the RESET). 3258 * 3259 * Note: the Subsystem Vendor/Device ID registers are not 3260 * directly writable in config space, so we use the shadow 3261 * copy in "Page Zero" of register space to restore them 3262 * both in one go ... 3263 */ 3264 pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ, 3265 bgep->chipid.clsize); 3266 pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 3267 bgep->chipid.latency); 3268 bge_reg_put32(bgep, PCI_CONF_SUBVENID, 3269 (bgep->chipid.subdev << 16) | bgep->chipid.subven); 3270 3271 /* 3272 * The SEND INDEX registers should be reset to zero by the 3273 * global chip reset; if they're not, there'll be trouble 3274 * later on. 3275 */ 3276 sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0)); 3277 if (sx0 != 0) { 3278 BGE_REPORT((bgep, "SEND INDEX - device didn't RESET")); 3279 bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE); 3280 retval = DDI_FAILURE; 3281 } 3282 3283 /* Enable MSI code */ 3284 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3285 bge_reg_set32(bgep, MSI_MODE_REG, 3286 MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION); 3287 3288 /* 3289 * On the first time through, save the factory-set MAC address 3290 * (if any). If bge_poll_firmware() above didn't return one 3291 * (from a chip register) consider looking in the attached NV 3292 * memory device, if any. Once we have it, we save it in both 3293 * register-image (64-bit) and byte-array forms. All-zero and 3294 * all-one addresses are not valid, and we refuse to stash those. 3295 */ 3296 if (bgep->bge_chip_state == BGE_CHIP_INITIAL) { 3297 if (mac == 0ULL) 3298 mac = bge_get_nvmac(bgep); 3299 if (mac != 0ULL && mac != ~0ULL) { 3300 bgep->chipid.hw_mac_addr = mac; 3301 for (i = ETHERADDRL; i-- != 0; ) { 3302 bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac; 3303 mac >>= 8; 3304 } 3305 bgep->chipid.vendor_addr.set = B_TRUE; 3306 } 3307 } 3308 3309 #ifdef BGE_IPMI_ASF 3310 if (bgep->asf_enabled && bgep->asf_newhandshake) { 3311 if (asf_mode != ASF_MODE_NONE) { 3312 if ((asf_mode == ASF_MODE_INIT) || 3313 (asf_mode == ASF_MODE_POST_INIT)) { 3314 3315 bge_asf_post_reset_new_mode(bgep, 3316 BGE_INIT_RESET); 3317 } else { 3318 bge_asf_post_reset_new_mode(bgep, 3319 BGE_SHUTDOWN_RESET); 3320 } 3321 } 3322 } 3323 #endif 3324 3325 /* 3326 * Record the new state 3327 */ 3328 bgep->chip_resets += 1; 3329 bgep->bge_chip_state = BGE_CHIP_RESET; 3330 return (retval); 3331 } 3332 3333 /* 3334 * bge_chip_start() -- start the chip transmitting and/or receiving, 3335 * including enabling interrupts 3336 */ 3337 int bge_chip_start(bge_t *bgep, boolean_t reset_phys); 3338 #pragma no_inline(bge_chip_start) 3339 3340 int 3341 bge_chip_start(bge_t *bgep, boolean_t reset_phys) 3342 { 3343 uint32_t coalmode; 3344 uint32_t ledctl; 3345 uint32_t mtu; 3346 uint32_t maxring; 3347 uint32_t stats_mask; 3348 uint64_t ring; 3349 int retval = DDI_SUCCESS; 3350 3351 BGE_TRACE(("bge_chip_start($%p)", 3352 (void *)bgep)); 3353 3354 ASSERT(mutex_owned(bgep->genlock)); 3355 ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET); 3356 3357 /* 3358 * Taken from Broadcom document 570X-PG102-R, pp 102-116. 3359 * The document specifies 95 separate steps to fully 3360 * initialise the chip!!!! 3361 * 3362 * The reset code above has already got us as far as step 3363 * 21, so we continue with ... 3364 * 3365 * Step 22: clear the MAC statistics block 3366 * (0x0300-0x0aff in NIC-local memory) 3367 */ 3368 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 3369 bge_nic_zero(bgep, NIC_MEM_STATISTICS, 3370 NIC_MEM_STATISTICS_SIZE); 3371 3372 /* 3373 * Step 23: clear the status block (in host memory) 3374 */ 3375 DMA_ZERO(bgep->status_block); 3376 3377 /* 3378 * Step 24: set DMA read/write control register 3379 */ 3380 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR, 3381 bgep->chipid.bge_dma_rwctrl); 3382 3383 /* 3384 * Step 25: Configure DMA endianness -- already done (16/17) 3385 * Step 26: Configure Host-Based Send Rings 3386 * Step 27: Indicate Host Stack Up 3387 */ 3388 bge_reg_set32(bgep, MODE_CONTROL_REG, 3389 MODE_HOST_SEND_BDS | 3390 MODE_HOST_STACK_UP); 3391 3392 /* 3393 * Step 28: Configure checksum options: 3394 * Solaris supports the hardware default checksum options. 3395 * 3396 * Workaround for Incorrect pseudo-header checksum calculation. 3397 */ 3398 if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM) 3399 bge_reg_set32(bgep, MODE_CONTROL_REG, 3400 MODE_SEND_NO_PSEUDO_HDR_CSUM); 3401 3402 /* 3403 * Step 29: configure Timer Prescaler. The value is always the 3404 * same: the Core Clock frequency in MHz (66), minus 1, shifted 3405 * into bits 7-1. Don't set bit 0, 'cos that's the RESET bit 3406 * for the whole chip! 3407 */ 3408 bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT); 3409 3410 /* 3411 * Steps 30-31: Configure MAC local memory pool & DMA pool registers 3412 * 3413 * If the mbuf_length is specified as 0, we just leave these at 3414 * their hardware defaults, rather than explicitly setting them. 3415 * As the Broadcom HRM,driver better not change the parameters 3416 * when the chipsets is 5705/5788/5721/5751/5714 and 5715. 3417 */ 3418 if ((bgep->chipid.mbuf_length != 0) && 3419 (DEVICE_5704_SERIES_CHIPSETS(bgep))) { 3420 bge_reg_put32(bgep, MBUF_POOL_BASE_REG, 3421 bgep->chipid.mbuf_base); 3422 bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG, 3423 bgep->chipid.mbuf_length); 3424 bge_reg_put32(bgep, DMAD_POOL_BASE_REG, 3425 DMAD_POOL_BASE_DEFAULT); 3426 bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG, 3427 DMAD_POOL_LENGTH_DEFAULT); 3428 } 3429 3430 /* 3431 * Step 32: configure MAC memory pool watermarks 3432 */ 3433 bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG, 3434 bgep->chipid.mbuf_lo_water_rdma); 3435 bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG, 3436 bgep->chipid.mbuf_lo_water_rmac); 3437 bge_reg_put32(bgep, MBUF_HIWAT_REG, 3438 bgep->chipid.mbuf_hi_water); 3439 3440 /* 3441 * Step 33: configure DMA resource watermarks 3442 */ 3443 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3444 bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG, 3445 bge_dmad_lo_water); 3446 bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG, 3447 bge_dmad_hi_water); 3448 } 3449 bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames); 3450 3451 /* 3452 * Steps 34-36: enable buffer manager & internal h/w queues 3453 */ 3454 if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG, 3455 STATE_MACHINE_ATTN_ENABLE_BIT)) 3456 retval = DDI_FAILURE; 3457 if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0)) 3458 retval = DDI_FAILURE; 3459 3460 /* 3461 * Steps 37-39: initialise Receive Buffer (Producer) RCBs 3462 */ 3463 bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG, 3464 &bgep->buff[BGE_STD_BUFF_RING].hw_rcb); 3465 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3466 bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG, 3467 &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb); 3468 bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG, 3469 &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb); 3470 } 3471 3472 /* 3473 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds 3474 */ 3475 bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std); 3476 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3477 bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG, 3478 bge_replenish_jumbo); 3479 bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG, 3480 bge_replenish_mini); 3481 } 3482 3483 /* 3484 * Steps 41-43: clear Send Ring Producer Indices and initialise 3485 * Send Producer Rings (0x0100-0x01ff in NIC-local memory) 3486 */ 3487 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3488 maxring = BGE_SEND_RINGS_MAX; 3489 else 3490 maxring = BGE_SEND_RINGS_MAX_5705; 3491 for (ring = 0; ring < maxring; ++ring) { 3492 bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0); 3493 bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0); 3494 bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring), 3495 &bgep->send[ring].hw_rcb); 3496 } 3497 3498 /* 3499 * Steps 44-45: initialise Receive Return Rings 3500 * (0x0200-0x02ff in NIC-local memory) 3501 */ 3502 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3503 maxring = BGE_RECV_RINGS_MAX; 3504 else 3505 maxring = BGE_RECV_RINGS_MAX_5705; 3506 for (ring = 0; ring < maxring; ++ring) 3507 bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring), 3508 &bgep->recv[ring].hw_rcb); 3509 3510 /* 3511 * Step 46: initialise Receive Buffer (Producer) Ring indexes 3512 */ 3513 bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0); 3514 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3515 bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0); 3516 bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0); 3517 } 3518 /* 3519 * Step 47: configure the MAC unicast address 3520 * Step 48: configure the random backoff seed 3521 * Step 96: set up multicast filters 3522 */ 3523 #ifdef BGE_IPMI_ASF 3524 if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE) 3525 #else 3526 if (bge_chip_sync(bgep) == DDI_FAILURE) 3527 #endif 3528 retval = DDI_FAILURE; 3529 3530 /* 3531 * Step 49: configure the MTU 3532 */ 3533 mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ; 3534 bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu); 3535 3536 /* 3537 * Step 50: configure the IPG et al 3538 */ 3539 bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT); 3540 3541 /* 3542 * Step 51: configure the default Rx Return Ring 3543 */ 3544 bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT); 3545 3546 /* 3547 * Steps 52-54: configure Receive List Placement, 3548 * and enable Receive List Placement Statistics 3549 */ 3550 bge_reg_put32(bgep, RCV_LP_CONFIG_REG, 3551 RCV_LP_CONFIG(bgep->chipid.rx_rings)); 3552 switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) { 3553 case MHCR_CHIP_ASIC_REV_5700: 3554 case MHCR_CHIP_ASIC_REV_5701: 3555 case MHCR_CHIP_ASIC_REV_5703: 3556 case MHCR_CHIP_ASIC_REV_5704: 3557 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0); 3558 break; 3559 case MHCR_CHIP_ASIC_REV_5705: 3560 break; 3561 default: 3562 stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG); 3563 stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ; 3564 bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask); 3565 break; 3566 } 3567 bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE); 3568 3569 if (bgep->chipid.rx_rings > 1) 3570 bge_init_recv_rule(bgep); 3571 3572 /* 3573 * Steps 55-56: enable Send Data Initiator Statistics 3574 */ 3575 bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0); 3576 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3577 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3578 SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER); 3579 } else { 3580 bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG, 3581 SEND_INIT_STATS_ENABLE); 3582 } 3583 /* 3584 * Steps 57-58: stop (?) the Host Coalescing Engine 3585 */ 3586 if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0)) 3587 retval = DDI_FAILURE; 3588 3589 /* 3590 * Steps 59-62: initialise Host Coalescing parameters 3591 */ 3592 bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG, bge_tx_count_norm); 3593 bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG, bge_tx_ticks_norm); 3594 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, bge_rx_count_norm); 3595 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, bge_rx_ticks_norm); 3596 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3597 bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG, 3598 bge_tx_count_intr); 3599 bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG, 3600 bge_tx_ticks_intr); 3601 bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG, 3602 bge_rx_count_intr); 3603 bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG, 3604 bge_rx_ticks_intr); 3605 } 3606 3607 /* 3608 * Steps 63-64: initialise status block & statistics 3609 * host memory addresses 3610 * The statistic block does not exist in some chipsets 3611 * Step 65: initialise Statistics Coalescing Tick Counter 3612 */ 3613 bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG, 3614 bgep->status_block.cookie.dmac_laddress); 3615 3616 /* 3617 * Steps 66-67: initialise status block & statistics 3618 * NIC-local memory addresses 3619 */ 3620 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) { 3621 bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG, 3622 bgep->statistics.cookie.dmac_laddress); 3623 bge_reg_put32(bgep, STATISTICS_TICKS_REG, 3624 STATISTICS_TICKS_DEFAULT); 3625 bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG, 3626 NIC_MEM_STATUS_BLOCK); 3627 bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG, 3628 NIC_MEM_STATISTICS); 3629 } 3630 3631 /* 3632 * Steps 68-71: start the Host Coalescing Engine, the Receive BD 3633 * Completion Engine, the Receive List Placement Engine, and the 3634 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714 3635 * and BCM5715. 3636 */ 3637 if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS && 3638 bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS) 3639 coalmode = COALESCE_64_BYTE_STATUS; 3640 else 3641 coalmode = 0; 3642 if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode)) 3643 retval = DDI_FAILURE; 3644 if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG, 3645 STATE_MACHINE_ATTN_ENABLE_BIT)) 3646 retval = DDI_FAILURE; 3647 if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0)) 3648 retval = DDI_FAILURE; 3649 3650 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3651 if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG, 3652 STATE_MACHINE_ATTN_ENABLE_BIT)) 3653 retval = DDI_FAILURE; 3654 3655 /* 3656 * Step 72: Enable MAC DMA engines 3657 * Step 73: Clear & enable MAC statistics 3658 */ 3659 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3660 ETHERNET_MODE_ENABLE_FHDE | 3661 ETHERNET_MODE_ENABLE_RDE | 3662 ETHERNET_MODE_ENABLE_TDE); 3663 bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG, 3664 ETHERNET_MODE_ENABLE_TX_STATS | 3665 ETHERNET_MODE_ENABLE_RX_STATS | 3666 ETHERNET_MODE_CLEAR_TX_STATS | 3667 ETHERNET_MODE_CLEAR_RX_STATS); 3668 3669 /* 3670 * Step 74: configure the MLCR (Miscellaneous Local Control 3671 * Register); not required, as we set up the MLCR in step 10 3672 * (part of the reset code) above. 3673 * 3674 * Step 75: clear Interrupt Mailbox 0 3675 */ 3676 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0); 3677 3678 /* 3679 * Steps 76-87: Gentlemen, start your engines ... 3680 * 3681 * Enable the DMA Completion Engine, the Write DMA Engine, 3682 * the Read DMA Engine, Receive Data Completion Engine, 3683 * the MBuf Cluster Free Engine, the Send Data Completion Engine, 3684 * the Send BD Completion Engine, the Receive BD Initiator Engine, 3685 * the Receive Data Initiator Engine, the Send Data Initiator Engine, 3686 * the Send BD Initiator Engine, and the Send BD Selector Engine. 3687 * 3688 * Beware exhaust fumes? 3689 */ 3690 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3691 if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0)) 3692 retval = DDI_FAILURE; 3693 if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG, 3694 (bge_dma_wrprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3695 retval = DDI_FAILURE; 3696 if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG, 3697 (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS)) 3698 retval = DDI_FAILURE; 3699 if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG, 3700 STATE_MACHINE_ATTN_ENABLE_BIT)) 3701 retval = DDI_FAILURE; 3702 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 3703 if (!bge_chip_enable_engine(bgep, 3704 MBUF_CLUSTER_FREE_MODE_REG, 0)) 3705 retval = DDI_FAILURE; 3706 if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0)) 3707 retval = DDI_FAILURE; 3708 if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG, 3709 STATE_MACHINE_ATTN_ENABLE_BIT)) 3710 retval = DDI_FAILURE; 3711 if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG, 3712 RCV_BD_DISABLED_RING_ATTN)) 3713 retval = DDI_FAILURE; 3714 if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG, 3715 RCV_DATA_BD_ILL_RING_ATTN)) 3716 retval = DDI_FAILURE; 3717 if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0)) 3718 retval = DDI_FAILURE; 3719 if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG, 3720 STATE_MACHINE_ATTN_ENABLE_BIT)) 3721 retval = DDI_FAILURE; 3722 if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG, 3723 STATE_MACHINE_ATTN_ENABLE_BIT)) 3724 retval = DDI_FAILURE; 3725 3726 /* 3727 * Step 88: download firmware -- doesn't apply 3728 * Steps 89-90: enable Transmit & Receive MAC Engines 3729 */ 3730 if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0)) 3731 retval = DDI_FAILURE; 3732 #ifdef BGE_IPMI_ASF 3733 if (!bgep->asf_enabled) { 3734 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3735 RECEIVE_MODE_KEEP_VLAN_TAG)) 3736 retval = DDI_FAILURE; 3737 } else { 3738 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0)) 3739 retval = DDI_FAILURE; 3740 } 3741 #else 3742 if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 3743 RECEIVE_MODE_KEEP_VLAN_TAG)) 3744 retval = DDI_FAILURE; 3745 #endif 3746 3747 /* 3748 * Step 91: disable auto-polling of PHY status 3749 */ 3750 bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT); 3751 3752 /* 3753 * Step 92: configure D0 power state (not required) 3754 * Step 93: initialise LED control register () 3755 */ 3756 ledctl = LED_CONTROL_DEFAULT; 3757 switch (bgep->chipid.device) { 3758 case DEVICE_ID_5700: 3759 case DEVICE_ID_5700x: 3760 case DEVICE_ID_5701: 3761 /* 3762 * Switch to 5700 (MAC) mode on these older chips 3763 */ 3764 ledctl &= ~LED_CONTROL_LED_MODE_MASK; 3765 ledctl |= LED_CONTROL_LED_MODE_5700; 3766 break; 3767 3768 default: 3769 break; 3770 } 3771 bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl); 3772 3773 /* 3774 * Step 94: activate link 3775 */ 3776 bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK); 3777 3778 /* 3779 * Step 95: set up physical layer (PHY/SerDes) 3780 * restart autoneg (if required) 3781 */ 3782 if (reset_phys) 3783 if (bge_phys_update(bgep) == DDI_FAILURE) 3784 retval = DDI_FAILURE; 3785 3786 /* 3787 * Extra step (DSG): hand over all the Receive Buffers to the chip 3788 */ 3789 for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring) 3790 bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg, 3791 bgep->buff[ring].rf_next); 3792 3793 /* 3794 * MSI bits:The least significant MSI 16-bit word. 3795 * ISR will be triggered different. 3796 */ 3797 if (bgep->intr_type == DDI_INTR_TYPE_MSI) 3798 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70); 3799 3800 /* 3801 * Extra step (DSG): select which interrupts are enabled 3802 * 3803 * Program the Ethernet MAC engine to signal attention on 3804 * Link Change events, then enable interrupts on MAC, DMA, 3805 * and FLOW attention signals. 3806 */ 3807 bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 3808 ETHERNET_EVENT_LINK_INT | 3809 ETHERNET_STATUS_PCS_ERROR_INT); 3810 #ifdef BGE_IPMI_ASF 3811 if (bgep->asf_enabled) { 3812 bge_reg_set32(bgep, MODE_CONTROL_REG, 3813 MODE_INT_ON_FLOW_ATTN | 3814 MODE_INT_ON_DMA_ATTN | 3815 MODE_HOST_STACK_UP| 3816 MODE_INT_ON_MAC_ATTN); 3817 } else { 3818 #endif 3819 bge_reg_set32(bgep, MODE_CONTROL_REG, 3820 MODE_INT_ON_FLOW_ATTN | 3821 MODE_INT_ON_DMA_ATTN | 3822 MODE_INT_ON_MAC_ATTN); 3823 #ifdef BGE_IPMI_ASF 3824 } 3825 #endif 3826 3827 /* 3828 * Step 97: enable PCI interrupts!!! 3829 */ 3830 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) 3831 bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR, 3832 MHCR_MASK_PCI_INT_OUTPUT); 3833 3834 /* 3835 * All done! 3836 */ 3837 bgep->bge_chip_state = BGE_CHIP_RUNNING; 3838 return (retval); 3839 } 3840 3841 3842 /* 3843 * ========== Hardware interrupt handler ========== 3844 */ 3845 3846 #undef BGE_DBG 3847 #define BGE_DBG BGE_DBG_INT /* debug flag for this code */ 3848 3849 /* 3850 * Sync the status block, then atomically clear the specified bits in 3851 * the <flags-and-tag> field of the status block. 3852 * the <flags> word of the status block, returning the value of the 3853 * <tag> and the <flags> before the bits were cleared. 3854 */ 3855 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags); 3856 #pragma inline(bge_status_sync) 3857 3858 static int 3859 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags) 3860 { 3861 bge_status_t *bsp; 3862 int retval; 3863 3864 BGE_TRACE(("bge_status_sync($%p, 0x%llx)", 3865 (void *)bgep, bits)); 3866 3867 ASSERT(bgep->bge_guard == BGE_GUARD); 3868 3869 DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL); 3870 retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl); 3871 if (retval != DDI_FM_OK) 3872 return (retval); 3873 3874 bsp = DMA_VPTR(bgep->status_block); 3875 *flags = bge_atomic_clr64(&bsp->flags_n_tag, bits); 3876 3877 BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx", 3878 (void *)bgep, bits, *flags)); 3879 3880 return (retval); 3881 } 3882 3883 static void bge_wake_factotum(bge_t *bgep); 3884 #pragma inline(bge_wake_factotum) 3885 3886 static void 3887 bge_wake_factotum(bge_t *bgep) 3888 { 3889 mutex_enter(bgep->softintrlock); 3890 if (bgep->factotum_flag == 0) { 3891 bgep->factotum_flag = 1; 3892 ddi_trigger_softintr(bgep->factotum_id); 3893 } 3894 mutex_exit(bgep->softintrlock); 3895 } 3896 3897 /* 3898 * bge_intr() -- handle chip interrupts 3899 */ 3900 uint_t bge_intr(caddr_t arg1, caddr_t arg2); 3901 #pragma no_inline(bge_intr) 3902 3903 uint_t 3904 bge_intr(caddr_t arg1, caddr_t arg2) 3905 { 3906 bge_t *bgep = (bge_t *)arg1; /* private device info */ 3907 bge_status_t *bsp; 3908 uint64_t flags; 3909 uint32_t regval; 3910 uint_t result; 3911 int retval, loop_cnt = 0; 3912 3913 BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2)); 3914 3915 /* 3916 * GLD v2 checks that s/w setup is complete before passing 3917 * interrupts to this routine, thus eliminating the old 3918 * (and well-known) race condition around ddi_add_intr() 3919 */ 3920 ASSERT(bgep->progress & PROGRESS_HWINT); 3921 3922 result = DDI_INTR_UNCLAIMED; 3923 mutex_enter(bgep->genlock); 3924 3925 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 3926 /* 3927 * Check whether chip's says it's asserting #INTA; 3928 * if not, don't process or claim the interrupt. 3929 * 3930 * Note that the PCI signal is active low, so the 3931 * bit is *zero* when the interrupt is asserted. 3932 */ 3933 regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG); 3934 if (regval & MLCR_INTA_STATE) { 3935 if (bge_check_acc_handle(bgep, bgep->io_handle) 3936 != DDI_FM_OK) 3937 goto chip_stop; 3938 mutex_exit(bgep->genlock); 3939 return (result); 3940 } 3941 3942 /* 3943 * Block further PCI interrupts ... 3944 */ 3945 bge_reg_set32(bgep, PCI_CONF_BGE_MHCR, 3946 MHCR_MASK_PCI_INT_OUTPUT); 3947 3948 } else { 3949 /* 3950 * Check MSI status 3951 */ 3952 regval = bge_reg_get32(bgep, MSI_STATUS_REG); 3953 if (regval & MSI_ERROR_ATTENTION) { 3954 BGE_REPORT((bgep, "msi error attention," 3955 " status=0x%x", regval)); 3956 bge_reg_put32(bgep, MSI_STATUS_REG, regval); 3957 } 3958 } 3959 3960 result = DDI_INTR_CLAIMED; 3961 3962 BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval)); 3963 3964 /* 3965 * Sync the status block and grab the flags-n-tag from it. 3966 * We count the number of interrupts where there doesn't 3967 * seem to have been a DMA update of the status block; if 3968 * it *has* been updated, the counter will be cleared in 3969 * the while() loop below ... 3970 */ 3971 bgep->missed_dmas += 1; 3972 bsp = DMA_VPTR(bgep->status_block); 3973 for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) { 3974 if (bgep->bge_chip_state != BGE_CHIP_RUNNING) { 3975 /* 3976 * bge_chip_stop() may have freed dma area etc 3977 * while we were in this interrupt handler - 3978 * better not call bge_status_sync() 3979 */ 3980 (void) bge_check_acc_handle(bgep, 3981 bgep->io_handle); 3982 mutex_exit(bgep->genlock); 3983 return (DDI_INTR_CLAIMED); 3984 } 3985 retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED, 3986 &flags); 3987 if (retval != DDI_FM_OK) { 3988 bgep->bge_dma_error = B_TRUE; 3989 goto chip_stop; 3990 } 3991 3992 if (!(flags & STATUS_FLAG_UPDATED)) 3993 break; 3994 3995 /* 3996 * Tell the chip that we're processing the interrupt 3997 */ 3998 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 3999 INTERRUPT_MBOX_DISABLE(flags)); 4000 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4001 DDI_FM_OK) 4002 goto chip_stop; 4003 4004 /* 4005 * Drop the mutex while we: 4006 * Receive any newly-arrived packets 4007 * Recycle any newly-finished send buffers 4008 */ 4009 bgep->bge_intr_running = B_TRUE; 4010 mutex_exit(bgep->genlock); 4011 bge_receive(bgep, bsp); 4012 bge_recycle(bgep, bsp); 4013 mutex_enter(bgep->genlock); 4014 bgep->bge_intr_running = B_FALSE; 4015 4016 /* 4017 * Tell the chip we've finished processing, and 4018 * give it the tag that we got from the status 4019 * block earlier, so that it knows just how far 4020 * we've gone. If it's got more for us to do, 4021 * it will now update the status block and try 4022 * to assert an interrupt (but we've got the 4023 * #INTA blocked at present). If we see the 4024 * update, we'll loop around to do some more. 4025 * Eventually we'll get out of here ... 4026 */ 4027 bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 4028 INTERRUPT_MBOX_ENABLE(flags)); 4029 bgep->missed_dmas = 0; 4030 } 4031 4032 /* 4033 * Check for exceptional conditions that we need to handle 4034 * 4035 * Link status changed 4036 * Status block not updated 4037 */ 4038 if (flags & STATUS_FLAG_LINK_CHANGED) 4039 bge_wake_factotum(bgep); 4040 4041 if (bgep->missed_dmas) { 4042 /* 4043 * Probably due to the internal status tag not 4044 * being reset. Force a status block update now; 4045 * this should ensure that we get an update and 4046 * a new interrupt. After that, we should be in 4047 * sync again ... 4048 */ 4049 BGE_REPORT((bgep, "interrupt: flags 0x%llx - " 4050 "not updated?", flags)); 4051 bgep->missed_updates++; 4052 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 4053 COALESCE_NOW); 4054 4055 if (bgep->missed_dmas >= bge_dma_miss_limit) { 4056 /* 4057 * If this happens multiple times in a row, 4058 * it means DMA is just not working. Maybe 4059 * the chip's failed, or maybe there's a 4060 * problem on the PCI bus or in the host-PCI 4061 * bridge (Tomatillo). 4062 * 4063 * At all events, we want to stop further 4064 * interrupts and let the recovery code take 4065 * over to see whether anything can be done 4066 * about it ... 4067 */ 4068 bge_fm_ereport(bgep, 4069 DDI_FM_DEVICE_BADINT_LIMIT); 4070 goto chip_stop; 4071 } 4072 } 4073 4074 /* 4075 * Reenable assertion of #INTA, unless there's a DMA fault 4076 */ 4077 if (bgep->intr_type == DDI_INTR_TYPE_FIXED) { 4078 bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR, 4079 MHCR_MASK_PCI_INT_OUTPUT); 4080 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4081 DDI_FM_OK) 4082 goto chip_stop; 4083 } 4084 4085 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4086 goto chip_stop; 4087 4088 mutex_exit(bgep->genlock); 4089 return (result); 4090 4091 chip_stop: 4092 #ifdef BGE_IPMI_ASF 4093 if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) { 4094 /* 4095 * We must stop ASF heart beat before 4096 * bge_chip_stop(), otherwise some 4097 * computers (ex. IBM HS20 blade 4098 * server) may crash. 4099 */ 4100 bge_asf_update_status(bgep); 4101 bge_asf_stop_timer(bgep); 4102 bgep->asf_status = ASF_STAT_STOP; 4103 4104 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4105 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4106 } 4107 #endif 4108 bge_chip_stop(bgep, B_TRUE); 4109 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4110 mutex_exit(bgep->genlock); 4111 return (result); 4112 } 4113 4114 /* 4115 * ========== Factotum, implemented as a softint handler ========== 4116 */ 4117 4118 #undef BGE_DBG 4119 #define BGE_DBG BGE_DBG_FACT /* debug flag for this code */ 4120 4121 static void bge_factotum_error_handler(bge_t *bgep); 4122 #pragma no_inline(bge_factotum_error_handler) 4123 4124 static void 4125 bge_factotum_error_handler(bge_t *bgep) 4126 { 4127 uint32_t flow; 4128 uint32_t rdma; 4129 uint32_t wdma; 4130 uint32_t tmac; 4131 uint32_t rmac; 4132 uint32_t rxrs; 4133 uint32_t txrs = 0; 4134 4135 ASSERT(mutex_owned(bgep->genlock)); 4136 4137 /* 4138 * Read all the registers that show the possible 4139 * reasons for the ERROR bit to be asserted 4140 */ 4141 flow = bge_reg_get32(bgep, FLOW_ATTN_REG); 4142 rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG); 4143 wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG); 4144 tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4145 rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG); 4146 rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG); 4147 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4148 txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG); 4149 4150 BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x", 4151 (void *)bgep, flow, rdma, wdma)); 4152 BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x", 4153 (void *)bgep, tmac, rmac, rxrs, txrs)); 4154 4155 /* 4156 * For now, just clear all the errors ... 4157 */ 4158 if (DEVICE_5704_SERIES_CHIPSETS(bgep)) 4159 bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0); 4160 bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0); 4161 bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0); 4162 bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0); 4163 bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0); 4164 bge_reg_put32(bgep, FLOW_ATTN_REG, ~0); 4165 } 4166 4167 /* 4168 * Handler for hardware link state change. 4169 * 4170 * When this routine is called, the hardware link state has changed 4171 * and the new state is reflected in the param_* variables. Here 4172 * we must update the softstate, reprogram the MAC to match, and 4173 * record the change in the log and/or on the console. 4174 */ 4175 static void bge_factotum_link_handler(bge_t *bgep); 4176 #pragma no_inline(bge_factotum_link_handler) 4177 4178 static void 4179 bge_factotum_link_handler(bge_t *bgep) 4180 { 4181 void (*logfn)(bge_t *bgep, const char *fmt, ...); 4182 const char *msg; 4183 hrtime_t deltat; 4184 4185 ASSERT(mutex_owned(bgep->genlock)); 4186 4187 /* 4188 * Update the s/w link_state 4189 */ 4190 if (bgep->param_link_up) 4191 bgep->link_state = LINK_STATE_UP; 4192 else 4193 bgep->link_state = LINK_STATE_DOWN; 4194 4195 /* 4196 * Reprogram the MAC modes to match 4197 */ 4198 bge_sync_mac_modes(bgep); 4199 4200 /* 4201 * Finally, we have to decide whether to write a message 4202 * on the console or only in the log. If the PHY has 4203 * been reprogrammed (at user request) "recently", then 4204 * the message only goes in the log. Otherwise it's an 4205 * "unexpected" event, and it goes on the console as well. 4206 */ 4207 deltat = bgep->phys_event_time - bgep->phys_write_time; 4208 if (deltat > BGE_LINK_SETTLE_TIME) 4209 msg = ""; 4210 else if (bgep->param_link_up) 4211 msg = bgep->link_up_msg; 4212 else 4213 msg = bgep->link_down_msg; 4214 4215 logfn = (msg == NULL || *msg == '\0') ? bge_notice : bge_log; 4216 (*logfn)(bgep, "link %s%s", bgep->link_mode_msg, msg); 4217 } 4218 4219 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state); 4220 #pragma no_inline(bge_factotum_link_check) 4221 4222 static boolean_t 4223 bge_factotum_link_check(bge_t *bgep, int *dma_state) 4224 { 4225 boolean_t check; 4226 uint64_t flags; 4227 uint32_t tmac_status; 4228 4229 ASSERT(mutex_owned(bgep->genlock)); 4230 4231 /* 4232 * Get & clear the writable status bits in the Tx status register 4233 * (some bits are write-1-to-clear, others are just readonly). 4234 */ 4235 tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG); 4236 bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status); 4237 4238 /* 4239 * Get & clear the ERROR and LINK_CHANGED bits from the status block 4240 */ 4241 *dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR | 4242 STATUS_FLAG_LINK_CHANGED, &flags); 4243 if (*dma_state != DDI_FM_OK) 4244 return (B_FALSE); 4245 4246 /* 4247 * Clear any errors flagged in the status block ... 4248 */ 4249 if (flags & STATUS_FLAG_ERROR) 4250 bge_factotum_error_handler(bgep); 4251 4252 /* 4253 * We need to check the link status if: 4254 * the status block says there's been a link change 4255 * or there's any discrepancy between the various 4256 * flags indicating the link state (link_state, 4257 * param_link_up, and the LINK STATE bit in the 4258 * Transmit MAC status register). 4259 */ 4260 check = (flags & STATUS_FLAG_LINK_CHANGED) != 0; 4261 switch (bgep->link_state) { 4262 case LINK_STATE_UP: 4263 check |= (bgep->param_link_up == B_FALSE); 4264 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0); 4265 break; 4266 4267 case LINK_STATE_DOWN: 4268 check |= (bgep->param_link_up != B_FALSE); 4269 check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0); 4270 break; 4271 4272 default: 4273 check = B_TRUE; 4274 break; 4275 } 4276 4277 /* 4278 * If <check> is false, we're sure the link hasn't changed. 4279 * If true, however, it's not yet definitive; we have to call 4280 * bge_phys_check() to determine whether the link has settled 4281 * into a new state yet ... and if it has, then call the link 4282 * state change handler.But when the chip is 5700 in Dell 6650 4283 * ,even if check is false, the link may have changed.So we 4284 * have to call bge_phys_check() to determine the link state. 4285 */ 4286 if (check || bgep->chipid.device == DEVICE_ID_5700) { 4287 check = bge_phys_check(bgep); 4288 if (check) 4289 bge_factotum_link_handler(bgep); 4290 } 4291 4292 return (check); 4293 } 4294 4295 /* 4296 * Factotum routine to check for Tx stall, using the 'watchdog' counter 4297 */ 4298 static boolean_t bge_factotum_stall_check(bge_t *bgep); 4299 #pragma no_inline(bge_factotum_stall_check) 4300 4301 static boolean_t 4302 bge_factotum_stall_check(bge_t *bgep) 4303 { 4304 uint32_t dogval; 4305 4306 ASSERT(mutex_owned(bgep->genlock)); 4307 4308 /* 4309 * Specific check for Tx stall ... 4310 * 4311 * The 'watchdog' counter is incremented whenever a packet 4312 * is queued, reset to 1 when some (but not all) buffers 4313 * are reclaimed, reset to 0 (disabled) when all buffers 4314 * are reclaimed, and shifted left here. If it exceeds the 4315 * threshold value, the chip is assumed to have stalled and 4316 * is put into the ERROR state. The factotum will then reset 4317 * it on the next pass. 4318 * 4319 * All of which should ensure that we don't get into a state 4320 * where packets are left pending indefinitely! 4321 */ 4322 dogval = bge_atomic_shl32(&bgep->watchdog, 1); 4323 if (dogval < bge_watchdog_count) 4324 return (B_FALSE); 4325 4326 #if !defined(BGE_NETCONSOLE) 4327 BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval)); 4328 #endif 4329 bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL); 4330 return (B_TRUE); 4331 } 4332 4333 /* 4334 * The factotum is woken up when there's something to do that we'd rather 4335 * not do from inside a hardware interrupt handler or high-level cyclic. 4336 * Its two main tasks are: 4337 * reset & restart the chip after an error 4338 * check the link status whenever necessary 4339 */ 4340 uint_t bge_chip_factotum(caddr_t arg); 4341 #pragma no_inline(bge_chip_factotum) 4342 4343 uint_t 4344 bge_chip_factotum(caddr_t arg) 4345 { 4346 bge_t *bgep; 4347 uint_t result; 4348 boolean_t error; 4349 boolean_t linkchg; 4350 int dma_state; 4351 4352 bgep = (bge_t *)arg; 4353 4354 BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep)); 4355 4356 mutex_enter(bgep->softintrlock); 4357 if (bgep->factotum_flag == 0) { 4358 mutex_exit(bgep->softintrlock); 4359 return (DDI_INTR_UNCLAIMED); 4360 } 4361 bgep->factotum_flag = 0; 4362 mutex_exit(bgep->softintrlock); 4363 4364 result = DDI_INTR_CLAIMED; 4365 error = B_FALSE; 4366 linkchg = B_FALSE; 4367 4368 mutex_enter(bgep->genlock); 4369 switch (bgep->bge_chip_state) { 4370 default: 4371 break; 4372 4373 case BGE_CHIP_RUNNING: 4374 linkchg = bge_factotum_link_check(bgep, &dma_state); 4375 error = bge_factotum_stall_check(bgep); 4376 if (dma_state != DDI_FM_OK) { 4377 bgep->bge_dma_error = B_TRUE; 4378 error = B_TRUE; 4379 } 4380 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4381 error = B_TRUE; 4382 if (error) 4383 bgep->bge_chip_state = BGE_CHIP_ERROR; 4384 break; 4385 4386 case BGE_CHIP_ERROR: 4387 error = B_TRUE; 4388 break; 4389 4390 case BGE_CHIP_FAULT: 4391 /* 4392 * Fault detected, time to reset ... 4393 */ 4394 if (bge_autorecover) { 4395 if (!(bgep->progress & PROGRESS_BUFS)) { 4396 /* 4397 * if we can't allocate the ring buffers, 4398 * try later 4399 */ 4400 if (bge_alloc_bufs(bgep) != DDI_SUCCESS) { 4401 mutex_exit(bgep->genlock); 4402 return (result); 4403 } 4404 bgep->progress |= PROGRESS_BUFS; 4405 } 4406 if (!(bgep->progress & PROGRESS_INTR)) { 4407 bge_init_rings(bgep); 4408 bge_intr_enable(bgep); 4409 bgep->progress |= PROGRESS_INTR; 4410 } 4411 if (!(bgep->progress & PROGRESS_KSTATS)) { 4412 bge_init_kstats(bgep, 4413 ddi_get_instance(bgep->devinfo)); 4414 bgep->progress |= PROGRESS_KSTATS; 4415 } 4416 4417 BGE_REPORT((bgep, "automatic recovery activated")); 4418 4419 if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) { 4420 bgep->bge_chip_state = BGE_CHIP_ERROR; 4421 error = B_TRUE; 4422 } 4423 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != 4424 DDI_FM_OK) { 4425 bgep->bge_chip_state = BGE_CHIP_ERROR; 4426 error = B_TRUE; 4427 } 4428 if (bge_check_acc_handle(bgep, bgep->io_handle) != 4429 DDI_FM_OK) { 4430 bgep->bge_chip_state = BGE_CHIP_ERROR; 4431 error = B_TRUE; 4432 } 4433 if (error == B_FALSE) { 4434 #ifdef BGE_IPMI_ASF 4435 if (bgep->asf_enabled && 4436 bgep->asf_status != ASF_STAT_RUN) { 4437 bgep->asf_timeout_id = timeout( 4438 bge_asf_heartbeat, (void *)bgep, 4439 drv_usectohz( 4440 BGE_ASF_HEARTBEAT_INTERVAL)); 4441 bgep->asf_status = ASF_STAT_RUN; 4442 } 4443 #endif 4444 ddi_fm_service_impact(bgep->devinfo, 4445 DDI_SERVICE_RESTORED); 4446 } 4447 } 4448 break; 4449 } 4450 4451 4452 /* 4453 * If an error is detected, stop the chip now, marking it as 4454 * faulty, so that it will be reset next time through ... 4455 * 4456 * Note that if intr_running is set, then bge_intr() has dropped 4457 * genlock to call bge_receive/bge_recycle. Can't stop the chip at 4458 * this point so have to wait until the next time the factotum runs. 4459 */ 4460 if (error && !bgep->bge_intr_running) { 4461 #ifdef BGE_IPMI_ASF 4462 if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) { 4463 /* 4464 * We must stop ASF heart beat before bge_chip_stop(), 4465 * otherwise some computers (ex. IBM HS20 blade server) 4466 * may crash. 4467 */ 4468 bge_asf_update_status(bgep); 4469 bge_asf_stop_timer(bgep); 4470 bgep->asf_status = ASF_STAT_STOP; 4471 4472 bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET); 4473 (void) bge_check_acc_handle(bgep, bgep->cfg_handle); 4474 } 4475 #endif 4476 bge_chip_stop(bgep, B_TRUE); 4477 (void) bge_check_acc_handle(bgep, bgep->io_handle); 4478 } 4479 mutex_exit(bgep->genlock); 4480 4481 /* 4482 * If the link state changed, tell the world about it. 4483 * Note: can't do this while still holding the mutex. 4484 */ 4485 if (linkchg) 4486 mac_link_update(bgep->mh, bgep->link_state); 4487 4488 return (result); 4489 } 4490 4491 /* 4492 * High-level cyclic handler 4493 * 4494 * This routine schedules a (low-level) softint callback to the 4495 * factotum, and prods the chip to update the status block (which 4496 * will cause a hardware interrupt when complete). 4497 */ 4498 void bge_chip_cyclic(void *arg); 4499 #pragma no_inline(bge_chip_cyclic) 4500 4501 void 4502 bge_chip_cyclic(void *arg) 4503 { 4504 bge_t *bgep; 4505 4506 bgep = arg; 4507 4508 switch (bgep->bge_chip_state) { 4509 default: 4510 return; 4511 4512 case BGE_CHIP_RUNNING: 4513 bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW); 4514 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 4515 ddi_fm_service_impact(bgep->devinfo, 4516 DDI_SERVICE_UNAFFECTED); 4517 break; 4518 4519 case BGE_CHIP_FAULT: 4520 case BGE_CHIP_ERROR: 4521 break; 4522 } 4523 4524 bge_wake_factotum(bgep); 4525 } 4526 4527 4528 /* 4529 * ========== Ioctl subfunctions ========== 4530 */ 4531 4532 #undef BGE_DBG 4533 #define BGE_DBG BGE_DBG_PPIO /* debug flag for this code */ 4534 4535 #if BGE_DEBUGGING || BGE_DO_PPIO 4536 4537 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4538 #pragma no_inline(bge_chip_peek_cfg) 4539 4540 static void 4541 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4542 { 4543 uint64_t regval; 4544 uint64_t regno; 4545 4546 BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)", 4547 (void *)bgep, (void *)ppd)); 4548 4549 regno = ppd->pp_acc_offset; 4550 4551 switch (ppd->pp_acc_size) { 4552 case 1: 4553 regval = pci_config_get8(bgep->cfg_handle, regno); 4554 break; 4555 4556 case 2: 4557 regval = pci_config_get16(bgep->cfg_handle, regno); 4558 break; 4559 4560 case 4: 4561 regval = pci_config_get32(bgep->cfg_handle, regno); 4562 break; 4563 4564 case 8: 4565 regval = pci_config_get64(bgep->cfg_handle, regno); 4566 break; 4567 } 4568 4569 ppd->pp_acc_data = regval; 4570 } 4571 4572 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd); 4573 #pragma no_inline(bge_chip_poke_cfg) 4574 4575 static void 4576 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd) 4577 { 4578 uint64_t regval; 4579 uint64_t regno; 4580 4581 BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)", 4582 (void *)bgep, (void *)ppd)); 4583 4584 regno = ppd->pp_acc_offset; 4585 regval = ppd->pp_acc_data; 4586 4587 switch (ppd->pp_acc_size) { 4588 case 1: 4589 pci_config_put8(bgep->cfg_handle, regno, regval); 4590 break; 4591 4592 case 2: 4593 pci_config_put16(bgep->cfg_handle, regno, regval); 4594 break; 4595 4596 case 4: 4597 pci_config_put32(bgep->cfg_handle, regno, regval); 4598 break; 4599 4600 case 8: 4601 pci_config_put64(bgep->cfg_handle, regno, regval); 4602 break; 4603 } 4604 } 4605 4606 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4607 #pragma no_inline(bge_chip_peek_reg) 4608 4609 static void 4610 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4611 { 4612 uint64_t regval; 4613 void *regaddr; 4614 4615 BGE_TRACE(("bge_chip_peek_reg($%p, $%p)", 4616 (void *)bgep, (void *)ppd)); 4617 4618 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4619 4620 switch (ppd->pp_acc_size) { 4621 case 1: 4622 regval = ddi_get8(bgep->io_handle, regaddr); 4623 break; 4624 4625 case 2: 4626 regval = ddi_get16(bgep->io_handle, regaddr); 4627 break; 4628 4629 case 4: 4630 regval = ddi_get32(bgep->io_handle, regaddr); 4631 break; 4632 4633 case 8: 4634 regval = ddi_get64(bgep->io_handle, regaddr); 4635 break; 4636 } 4637 4638 ppd->pp_acc_data = regval; 4639 } 4640 4641 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd); 4642 #pragma no_inline(bge_chip_peek_reg) 4643 4644 static void 4645 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd) 4646 { 4647 uint64_t regval; 4648 void *regaddr; 4649 4650 BGE_TRACE(("bge_chip_poke_reg($%p, $%p)", 4651 (void *)bgep, (void *)ppd)); 4652 4653 regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset); 4654 regval = ppd->pp_acc_data; 4655 4656 switch (ppd->pp_acc_size) { 4657 case 1: 4658 ddi_put8(bgep->io_handle, regaddr, regval); 4659 break; 4660 4661 case 2: 4662 ddi_put16(bgep->io_handle, regaddr, regval); 4663 break; 4664 4665 case 4: 4666 ddi_put32(bgep->io_handle, regaddr, regval); 4667 break; 4668 4669 case 8: 4670 ddi_put64(bgep->io_handle, regaddr, regval); 4671 break; 4672 } 4673 BGE_PCICHK(bgep); 4674 } 4675 4676 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4677 #pragma no_inline(bge_chip_peek_nic) 4678 4679 static void 4680 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4681 { 4682 uint64_t regoff; 4683 uint64_t regval; 4684 void *regaddr; 4685 4686 BGE_TRACE(("bge_chip_peek_nic($%p, $%p)", 4687 (void *)bgep, (void *)ppd)); 4688 4689 regoff = ppd->pp_acc_offset; 4690 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4691 regoff &= MWBAR_GRANULE_MASK; 4692 regoff += NIC_MEM_WINDOW_OFFSET; 4693 regaddr = PIO_ADDR(bgep, regoff); 4694 4695 switch (ppd->pp_acc_size) { 4696 case 1: 4697 regval = ddi_get8(bgep->io_handle, regaddr); 4698 break; 4699 4700 case 2: 4701 regval = ddi_get16(bgep->io_handle, regaddr); 4702 break; 4703 4704 case 4: 4705 regval = ddi_get32(bgep->io_handle, regaddr); 4706 break; 4707 4708 case 8: 4709 regval = ddi_get64(bgep->io_handle, regaddr); 4710 break; 4711 } 4712 4713 ppd->pp_acc_data = regval; 4714 } 4715 4716 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd); 4717 #pragma no_inline(bge_chip_poke_nic) 4718 4719 static void 4720 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd) 4721 { 4722 uint64_t regoff; 4723 uint64_t regval; 4724 void *regaddr; 4725 4726 BGE_TRACE(("bge_chip_poke_nic($%p, $%p)", 4727 (void *)bgep, (void *)ppd)); 4728 4729 regoff = ppd->pp_acc_offset; 4730 bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK); 4731 regoff &= MWBAR_GRANULE_MASK; 4732 regoff += NIC_MEM_WINDOW_OFFSET; 4733 regaddr = PIO_ADDR(bgep, regoff); 4734 regval = ppd->pp_acc_data; 4735 4736 switch (ppd->pp_acc_size) { 4737 case 1: 4738 ddi_put8(bgep->io_handle, regaddr, regval); 4739 break; 4740 4741 case 2: 4742 ddi_put16(bgep->io_handle, regaddr, regval); 4743 break; 4744 4745 case 4: 4746 ddi_put32(bgep->io_handle, regaddr, regval); 4747 break; 4748 4749 case 8: 4750 ddi_put64(bgep->io_handle, regaddr, regval); 4751 break; 4752 } 4753 BGE_PCICHK(bgep); 4754 } 4755 4756 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4757 #pragma no_inline(bge_chip_peek_mii) 4758 4759 static void 4760 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4761 { 4762 BGE_TRACE(("bge_chip_peek_mii($%p, $%p)", 4763 (void *)bgep, (void *)ppd)); 4764 4765 ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2); 4766 } 4767 4768 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd); 4769 #pragma no_inline(bge_chip_poke_mii) 4770 4771 static void 4772 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd) 4773 { 4774 BGE_TRACE(("bge_chip_poke_mii($%p, $%p)", 4775 (void *)bgep, (void *)ppd)); 4776 4777 bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 4778 } 4779 4780 #if BGE_SEE_IO32 4781 4782 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4783 #pragma no_inline(bge_chip_peek_seeprom) 4784 4785 static void 4786 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4787 { 4788 uint32_t data; 4789 int err; 4790 4791 BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)", 4792 (void *)bgep, (void *)ppd)); 4793 4794 err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data); 4795 ppd->pp_acc_data = err ? ~0ull : data; 4796 } 4797 4798 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd); 4799 #pragma no_inline(bge_chip_poke_seeprom) 4800 4801 static void 4802 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd) 4803 { 4804 uint32_t data; 4805 4806 BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)", 4807 (void *)bgep, (void *)ppd)); 4808 4809 data = ppd->pp_acc_data; 4810 (void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data); 4811 } 4812 #endif /* BGE_SEE_IO32 */ 4813 4814 #if BGE_FLASH_IO32 4815 4816 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4817 #pragma no_inline(bge_chip_peek_flash) 4818 4819 static void 4820 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4821 { 4822 uint32_t data; 4823 int err; 4824 4825 BGE_TRACE(("bge_chip_peek_flash($%p, $%p)", 4826 (void *)bgep, (void *)ppd)); 4827 4828 err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data); 4829 ppd->pp_acc_data = err ? ~0ull : data; 4830 } 4831 4832 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd); 4833 #pragma no_inline(bge_chip_poke_flash) 4834 4835 static void 4836 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd) 4837 { 4838 uint32_t data; 4839 4840 BGE_TRACE(("bge_chip_poke_flash($%p, $%p)", 4841 (void *)bgep, (void *)ppd)); 4842 4843 data = ppd->pp_acc_data; 4844 (void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE, 4845 ppd->pp_acc_offset, &data); 4846 } 4847 #endif /* BGE_FLASH_IO32 */ 4848 4849 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4850 #pragma no_inline(bge_chip_peek_mem) 4851 4852 static void 4853 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4854 { 4855 uint64_t regval; 4856 void *vaddr; 4857 4858 BGE_TRACE(("bge_chip_peek_bge($%p, $%p)", 4859 (void *)bgep, (void *)ppd)); 4860 4861 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4862 4863 switch (ppd->pp_acc_size) { 4864 case 1: 4865 regval = *(uint8_t *)vaddr; 4866 break; 4867 4868 case 2: 4869 regval = *(uint16_t *)vaddr; 4870 break; 4871 4872 case 4: 4873 regval = *(uint32_t *)vaddr; 4874 break; 4875 4876 case 8: 4877 regval = *(uint64_t *)vaddr; 4878 break; 4879 } 4880 4881 BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 4882 (void *)bgep, (void *)ppd, regval, vaddr)); 4883 4884 ppd->pp_acc_data = regval; 4885 } 4886 4887 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd); 4888 #pragma no_inline(bge_chip_poke_mem) 4889 4890 static void 4891 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd) 4892 { 4893 uint64_t regval; 4894 void *vaddr; 4895 4896 BGE_TRACE(("bge_chip_poke_mem($%p, $%p)", 4897 (void *)bgep, (void *)ppd)); 4898 4899 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4900 regval = ppd->pp_acc_data; 4901 4902 BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 4903 (void *)bgep, (void *)ppd, regval, vaddr)); 4904 4905 switch (ppd->pp_acc_size) { 4906 case 1: 4907 *(uint8_t *)vaddr = (uint8_t)regval; 4908 break; 4909 4910 case 2: 4911 *(uint16_t *)vaddr = (uint16_t)regval; 4912 break; 4913 4914 case 4: 4915 *(uint32_t *)vaddr = (uint32_t)regval; 4916 break; 4917 4918 case 8: 4919 *(uint64_t *)vaddr = (uint64_t)regval; 4920 break; 4921 } 4922 } 4923 4924 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 4925 struct iocblk *iocp); 4926 #pragma no_inline(bge_pp_ioctl) 4927 4928 static enum ioc_reply 4929 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 4930 { 4931 void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd); 4932 bge_peekpoke_t *ppd; 4933 dma_area_t *areap; 4934 uint64_t sizemask; 4935 uint64_t mem_va; 4936 uint64_t maxoff; 4937 boolean_t peek; 4938 4939 switch (cmd) { 4940 default: 4941 /* NOTREACHED */ 4942 bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd); 4943 return (IOC_INVAL); 4944 4945 case BGE_PEEK: 4946 peek = B_TRUE; 4947 break; 4948 4949 case BGE_POKE: 4950 peek = B_FALSE; 4951 break; 4952 } 4953 4954 /* 4955 * Validate format of ioctl 4956 */ 4957 if (iocp->ioc_count != sizeof (bge_peekpoke_t)) 4958 return (IOC_INVAL); 4959 if (mp->b_cont == NULL) 4960 return (IOC_INVAL); 4961 ppd = (bge_peekpoke_t *)mp->b_cont->b_rptr; 4962 4963 /* 4964 * Validate request parameters 4965 */ 4966 switch (ppd->pp_acc_space) { 4967 default: 4968 return (IOC_INVAL); 4969 4970 case BGE_PP_SPACE_CFG: 4971 /* 4972 * Config space 4973 */ 4974 sizemask = 8|4|2|1; 4975 mem_va = 0; 4976 maxoff = PCI_CONF_HDR_SIZE; 4977 ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg; 4978 break; 4979 4980 case BGE_PP_SPACE_REG: 4981 /* 4982 * Memory-mapped I/O space 4983 */ 4984 sizemask = 8|4|2|1; 4985 mem_va = 0; 4986 maxoff = RIAAR_REGISTER_MAX; 4987 ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg; 4988 break; 4989 4990 case BGE_PP_SPACE_NIC: 4991 /* 4992 * NIC on-chip memory 4993 */ 4994 sizemask = 8|4|2|1; 4995 mem_va = 0; 4996 maxoff = MWBAR_ONCHIP_MAX; 4997 ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic; 4998 break; 4999 5000 case BGE_PP_SPACE_MII: 5001 /* 5002 * PHY's MII registers 5003 * NB: all PHY registers are two bytes, but the 5004 * addresses increment in ones (word addressing). 5005 * So we scale the address here, then undo the 5006 * transformation inside the peek/poke functions. 5007 */ 5008 ppd->pp_acc_offset *= 2; 5009 sizemask = 2; 5010 mem_va = 0; 5011 maxoff = (MII_MAXREG+1)*2; 5012 ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii; 5013 break; 5014 5015 #if BGE_SEE_IO32 5016 case BGE_PP_SPACE_SEEPROM: 5017 /* 5018 * Attached SEEPROM(s), if any. 5019 * NB: we use the high-order bits of the 'address' as 5020 * a device select to accommodate multiple SEEPROMS, 5021 * If each one is the maximum size (64kbytes), this 5022 * makes them appear contiguous. Otherwise, there may 5023 * be holes in the mapping. ENxS doesn't have any 5024 * SEEPROMs anyway ... 5025 */ 5026 sizemask = 4; 5027 mem_va = 0; 5028 maxoff = SEEPROM_DEV_AND_ADDR_MASK; 5029 ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom; 5030 break; 5031 #endif /* BGE_SEE_IO32 */ 5032 5033 #if BGE_FLASH_IO32 5034 case BGE_PP_SPACE_FLASH: 5035 /* 5036 * Attached Flash device (if any); a maximum of one device 5037 * is currently supported. But it can be up to 1MB (unlike 5038 * the 64k limit on SEEPROMs) so why would you need more ;-) 5039 */ 5040 sizemask = 4; 5041 mem_va = 0; 5042 maxoff = NVM_FLASH_ADDR_MASK; 5043 ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash; 5044 break; 5045 #endif /* BGE_FLASH_IO32 */ 5046 5047 case BGE_PP_SPACE_BGE: 5048 /* 5049 * BGE data structure! 5050 */ 5051 sizemask = 8|4|2|1; 5052 mem_va = (uintptr_t)bgep; 5053 maxoff = sizeof (*bgep); 5054 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5055 break; 5056 5057 case BGE_PP_SPACE_STATUS: 5058 case BGE_PP_SPACE_STATISTICS: 5059 case BGE_PP_SPACE_TXDESC: 5060 case BGE_PP_SPACE_TXBUFF: 5061 case BGE_PP_SPACE_RXDESC: 5062 case BGE_PP_SPACE_RXBUFF: 5063 /* 5064 * Various DMA_AREAs 5065 */ 5066 switch (ppd->pp_acc_space) { 5067 case BGE_PP_SPACE_TXDESC: 5068 areap = &bgep->tx_desc; 5069 break; 5070 case BGE_PP_SPACE_TXBUFF: 5071 areap = &bgep->tx_buff[0]; 5072 break; 5073 case BGE_PP_SPACE_RXDESC: 5074 areap = &bgep->rx_desc[0]; 5075 break; 5076 case BGE_PP_SPACE_RXBUFF: 5077 areap = &bgep->rx_buff[0]; 5078 break; 5079 case BGE_PP_SPACE_STATUS: 5080 areap = &bgep->status_block; 5081 break; 5082 case BGE_PP_SPACE_STATISTICS: 5083 if (bgep->chipid.statistic_type == BGE_STAT_BLK) 5084 areap = &bgep->statistics; 5085 break; 5086 } 5087 5088 sizemask = 8|4|2|1; 5089 mem_va = (uintptr_t)areap->mem_va; 5090 maxoff = areap->alength; 5091 ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem; 5092 break; 5093 } 5094 5095 switch (ppd->pp_acc_size) { 5096 default: 5097 return (IOC_INVAL); 5098 5099 case 8: 5100 case 4: 5101 case 2: 5102 case 1: 5103 if ((ppd->pp_acc_size & sizemask) == 0) 5104 return (IOC_INVAL); 5105 break; 5106 } 5107 5108 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 5109 return (IOC_INVAL); 5110 5111 if (ppd->pp_acc_offset >= maxoff) 5112 return (IOC_INVAL); 5113 5114 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 5115 return (IOC_INVAL); 5116 5117 /* 5118 * All OK - go do it! 5119 */ 5120 ppd->pp_acc_offset += mem_va; 5121 (*ppfn)(bgep, ppd); 5122 return (peek ? IOC_REPLY : IOC_ACK); 5123 } 5124 5125 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5126 struct iocblk *iocp); 5127 #pragma no_inline(bge_diag_ioctl) 5128 5129 static enum ioc_reply 5130 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5131 { 5132 ASSERT(mutex_owned(bgep->genlock)); 5133 5134 switch (cmd) { 5135 default: 5136 /* NOTREACHED */ 5137 bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd); 5138 return (IOC_INVAL); 5139 5140 case BGE_DIAG: 5141 /* 5142 * Currently a no-op 5143 */ 5144 return (IOC_ACK); 5145 5146 case BGE_PEEK: 5147 case BGE_POKE: 5148 return (bge_pp_ioctl(bgep, cmd, mp, iocp)); 5149 5150 case BGE_PHY_RESET: 5151 return (IOC_RESTART_ACK); 5152 5153 case BGE_SOFT_RESET: 5154 case BGE_HARD_RESET: 5155 /* 5156 * Reset and reinitialise the 570x hardware 5157 */ 5158 bgep->bge_chip_state = BGE_CHIP_FAULT; 5159 ddi_trigger_softintr(bgep->factotum_id); 5160 (void) bge_restart(bgep, cmd == BGE_HARD_RESET); 5161 return (IOC_ACK); 5162 } 5163 5164 /* NOTREACHED */ 5165 } 5166 5167 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5168 5169 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5170 struct iocblk *iocp); 5171 #pragma no_inline(bge_mii_ioctl) 5172 5173 static enum ioc_reply 5174 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5175 { 5176 struct bge_mii_rw *miirwp; 5177 5178 /* 5179 * Validate format of ioctl 5180 */ 5181 if (iocp->ioc_count != sizeof (struct bge_mii_rw)) 5182 return (IOC_INVAL); 5183 if (mp->b_cont == NULL) 5184 return (IOC_INVAL); 5185 miirwp = (struct bge_mii_rw *)mp->b_cont->b_rptr; 5186 5187 /* 5188 * Validate request parameters ... 5189 */ 5190 if (miirwp->mii_reg > MII_MAXREG) 5191 return (IOC_INVAL); 5192 5193 switch (cmd) { 5194 default: 5195 /* NOTREACHED */ 5196 bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd); 5197 return (IOC_INVAL); 5198 5199 case BGE_MII_READ: 5200 miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg); 5201 return (IOC_REPLY); 5202 5203 case BGE_MII_WRITE: 5204 bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data); 5205 return (IOC_ACK); 5206 } 5207 5208 /* NOTREACHED */ 5209 } 5210 5211 #if BGE_SEE_IO32 5212 5213 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5214 struct iocblk *iocp); 5215 #pragma no_inline(bge_see_ioctl) 5216 5217 static enum ioc_reply 5218 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5219 { 5220 struct bge_see_rw *seerwp; 5221 5222 /* 5223 * Validate format of ioctl 5224 */ 5225 if (iocp->ioc_count != sizeof (struct bge_see_rw)) 5226 return (IOC_INVAL); 5227 if (mp->b_cont == NULL) 5228 return (IOC_INVAL); 5229 seerwp = (struct bge_see_rw *)mp->b_cont->b_rptr; 5230 5231 /* 5232 * Validate request parameters ... 5233 */ 5234 if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK) 5235 return (IOC_INVAL); 5236 5237 switch (cmd) { 5238 default: 5239 /* NOTREACHED */ 5240 bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd); 5241 return (IOC_INVAL); 5242 5243 case BGE_SEE_READ: 5244 case BGE_SEE_WRITE: 5245 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5246 seerwp->see_addr, &seerwp->see_data); 5247 return (IOC_REPLY); 5248 } 5249 5250 /* NOTREACHED */ 5251 } 5252 5253 #endif /* BGE_SEE_IO32 */ 5254 5255 #if BGE_FLASH_IO32 5256 5257 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, 5258 struct iocblk *iocp); 5259 #pragma no_inline(bge_flash_ioctl) 5260 5261 static enum ioc_reply 5262 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp) 5263 { 5264 struct bge_flash_rw *flashrwp; 5265 5266 /* 5267 * Validate format of ioctl 5268 */ 5269 if (iocp->ioc_count != sizeof (struct bge_flash_rw)) 5270 return (IOC_INVAL); 5271 if (mp->b_cont == NULL) 5272 return (IOC_INVAL); 5273 flashrwp = (struct bge_flash_rw *)mp->b_cont->b_rptr; 5274 5275 /* 5276 * Validate request parameters ... 5277 */ 5278 if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK) 5279 return (IOC_INVAL); 5280 5281 switch (cmd) { 5282 default: 5283 /* NOTREACHED */ 5284 bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd); 5285 return (IOC_INVAL); 5286 5287 case BGE_FLASH_READ: 5288 case BGE_FLASH_WRITE: 5289 iocp->ioc_error = bge_nvmem_rw32(bgep, cmd, 5290 flashrwp->flash_addr, &flashrwp->flash_data); 5291 return (IOC_REPLY); 5292 } 5293 5294 /* NOTREACHED */ 5295 } 5296 5297 #endif /* BGE_FLASH_IO32 */ 5298 5299 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, 5300 struct iocblk *iocp); 5301 #pragma no_inline(bge_chip_ioctl) 5302 5303 enum ioc_reply 5304 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 5305 { 5306 int cmd; 5307 5308 BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)", 5309 (void *)bgep, (void *)wq, (void *)mp, (void *)iocp)); 5310 5311 ASSERT(mutex_owned(bgep->genlock)); 5312 5313 cmd = iocp->ioc_cmd; 5314 switch (cmd) { 5315 default: 5316 /* NOTREACHED */ 5317 bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd); 5318 return (IOC_INVAL); 5319 5320 case BGE_DIAG: 5321 case BGE_PEEK: 5322 case BGE_POKE: 5323 case BGE_PHY_RESET: 5324 case BGE_SOFT_RESET: 5325 case BGE_HARD_RESET: 5326 #if BGE_DEBUGGING || BGE_DO_PPIO 5327 return (bge_diag_ioctl(bgep, cmd, mp, iocp)); 5328 #else 5329 return (IOC_INVAL); 5330 #endif /* BGE_DEBUGGING || BGE_DO_PPIO */ 5331 5332 case BGE_MII_READ: 5333 case BGE_MII_WRITE: 5334 return (bge_mii_ioctl(bgep, cmd, mp, iocp)); 5335 5336 #if BGE_SEE_IO32 5337 case BGE_SEE_READ: 5338 case BGE_SEE_WRITE: 5339 return (bge_see_ioctl(bgep, cmd, mp, iocp)); 5340 #endif /* BGE_SEE_IO32 */ 5341 5342 #if BGE_FLASH_IO32 5343 case BGE_FLASH_READ: 5344 case BGE_FLASH_WRITE: 5345 return (bge_flash_ioctl(bgep, cmd, mp, iocp)); 5346 #endif /* BGE_FLASH_IO32 */ 5347 } 5348 5349 /* NOTREACHED */ 5350 } 5351 5352 void 5353 bge_chip_blank(void *arg, time_t ticks, uint_t count) 5354 { 5355 bge_t *bgep = arg; 5356 5357 mutex_enter(bgep->genlock); 5358 bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks); 5359 bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count); 5360 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5361 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED); 5362 mutex_exit(bgep->genlock); 5363 } 5364 5365 #ifdef BGE_IPMI_ASF 5366 5367 uint32_t 5368 bge_nic_read32(bge_t *bgep, bge_regno_t addr) 5369 { 5370 uint32_t data; 5371 5372 #ifndef __sparc 5373 if (!bgep->asf_wordswapped) { 5374 /* a workaround word swap error */ 5375 if (addr & 4) 5376 addr = addr - 4; 5377 else 5378 addr = addr + 4; 5379 } 5380 #endif 5381 5382 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr); 5383 data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR); 5384 pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0); 5385 5386 data = LE_32(data); 5387 return (data); 5388 } 5389 5390 void 5391 bge_asf_update_status(bge_t *bgep) 5392 { 5393 uint32_t event; 5394 5395 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE); 5396 bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4); 5397 bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX, 3); 5398 5399 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5400 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5401 } 5402 5403 5404 /* 5405 * The driver is supposed to notify ASF that the OS is still running 5406 * every three seconds, otherwise the management server may attempt 5407 * to reboot the machine. If it hasn't actually failed, this is 5408 * not a desirable result. However, this isn't running as a real-time 5409 * thread, and even if it were, it might not be able to generate the 5410 * heartbeat in a timely manner due to system load. As it isn't a 5411 * significant strain on the machine, we will set the interval to half 5412 * of the required value. 5413 */ 5414 void 5415 bge_asf_heartbeat(void *arg) 5416 { 5417 bge_t *bgep = (bge_t *)arg; 5418 5419 mutex_enter(bgep->genlock); 5420 bge_asf_update_status((bge_t *)bgep); 5421 if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK) 5422 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5423 if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK) 5424 ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED); 5425 mutex_exit(bgep->genlock); 5426 ((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep, 5427 drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL)); 5428 } 5429 5430 5431 void 5432 bge_asf_stop_timer(bge_t *bgep) 5433 { 5434 timeout_id_t tmp_id = 0; 5435 5436 while ((bgep->asf_timeout_id != 0) && 5437 (tmp_id != bgep->asf_timeout_id)) { 5438 tmp_id = bgep->asf_timeout_id; 5439 (void) untimeout(tmp_id); 5440 } 5441 bgep->asf_timeout_id = 0; 5442 } 5443 5444 5445 5446 /* 5447 * This function should be placed at the earliest position of bge_attach(). 5448 */ 5449 void 5450 bge_asf_get_config(bge_t *bgep) 5451 { 5452 uint32_t nicsig; 5453 uint32_t niccfg; 5454 5455 bgep->asf_enabled = B_FALSE; 5456 nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR); 5457 if (nicsig == BGE_NIC_DATA_SIG) { 5458 niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR); 5459 if (niccfg & BGE_NIC_CFG_ENABLE_ASF) 5460 /* 5461 * Here, we don't consider BAXTER, because BGE haven't 5462 * supported BAXTER (that is 5752). Also, as I know, 5463 * BAXTER doesn't support ASF feature. 5464 */ 5465 bgep->asf_enabled = B_TRUE; 5466 else 5467 bgep->asf_enabled = B_FALSE; 5468 } else 5469 bgep->asf_enabled = B_FALSE; 5470 } 5471 5472 5473 void 5474 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode) 5475 { 5476 uint32_t tries; 5477 uint32_t event; 5478 5479 ASSERT(bgep->asf_enabled); 5480 5481 /* Issues "pause firmware" command and wait for ACK */ 5482 bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW); 5483 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5484 bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT); 5485 5486 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5487 tries = 0; 5488 while ((event & RRER_ASF_EVENT) && (tries < 100)) { 5489 drv_usecwait(1); 5490 tries ++; 5491 event = bge_reg_get32(bgep, RX_RISC_EVENT_REG); 5492 } 5493 5494 bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX, 5495 BGE_MAGIC_NUM_FIRMWARE_INIT_DONE); 5496 5497 if (bgep->asf_newhandshake) { 5498 switch (mode) { 5499 case BGE_INIT_RESET: 5500 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5501 BGE_DRV_STATE_START); 5502 break; 5503 case BGE_SHUTDOWN_RESET: 5504 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5505 BGE_DRV_STATE_UNLOAD); 5506 break; 5507 case BGE_SUSPEND_RESET: 5508 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5509 BGE_DRV_STATE_SUSPEND); 5510 break; 5511 default: 5512 break; 5513 } 5514 } 5515 } 5516 5517 5518 void 5519 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode) 5520 { 5521 switch (mode) { 5522 case BGE_INIT_RESET: 5523 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5524 BGE_DRV_STATE_START); 5525 break; 5526 case BGE_SHUTDOWN_RESET: 5527 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5528 BGE_DRV_STATE_UNLOAD); 5529 break; 5530 case BGE_SUSPEND_RESET: 5531 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5532 BGE_DRV_STATE_SUSPEND); 5533 break; 5534 default: 5535 break; 5536 } 5537 } 5538 5539 5540 void 5541 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode) 5542 { 5543 switch (mode) { 5544 case BGE_INIT_RESET: 5545 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5546 BGE_DRV_STATE_START_DONE); 5547 break; 5548 case BGE_SHUTDOWN_RESET: 5549 bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX, 5550 BGE_DRV_STATE_UNLOAD_DONE); 5551 break; 5552 default: 5553 break; 5554 } 5555 } 5556 5557 #endif /* BGE_IPMI_ASF */ 5558