xref: /titanic_44/usr/src/uts/common/io/bge/bge_chip2.c (revision 0dc2366f7b9f9f36e10909b1e95edbf2a261c2ac)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #include "bge_impl.h"
28 
29 #define	PIO_ADDR(bgep, offset)	((void *)((caddr_t)(bgep)->io_regs+(offset)))
30 
31 /*
32  * Future features ... ?
33  */
34 #define	BGE_CFG_IO8	1	/* 8/16-bit cfg space BIS/BIC	*/
35 #define	BGE_IND_IO32	1	/* indirect access code		*/
36 #define	BGE_SEE_IO32	1	/* SEEPROM access code		*/
37 #define	BGE_FLASH_IO32	1	/* FLASH access code		*/
38 
39 /*
40  * BGE MSI tunable:
41  *
42  * By default MSI is enabled on all supported platforms but it is disabled
43  * for some Broadcom chips due to known MSI hardware issues. Currently MSI
44  * is enabled only for 5714C A2 and 5715C A2 broadcom chips.
45  */
46 boolean_t bge_enable_msi = B_TRUE;
47 
48 /*
49  * PCI-X/PCI-E relaxed ordering tunable for OS/Nexus driver
50  */
51 boolean_t bge_relaxed_ordering = B_TRUE;
52 
53 /*
54  * Property names
55  */
56 static char knownids_propname[] = "bge-known-subsystems";
57 
58 /*
59  * Patchable globals:
60  *
61  *	bge_autorecover
62  *		Enables/disables automatic recovery after fault detection
63  *
64  *	bge_mlcr_default
65  *		Value to program into the MLCR; controls the chip's GPIO pins
66  *
67  *	bge_dma_{rd,wr}prio
68  *		Relative priorities of DMA reads & DMA writes respectively.
69  *		These may each be patched to any value 0-3.  Equal values
70  *		will give "fair" (round-robin) arbitration for PCI access.
71  *		Unequal values will give one or the other function priority.
72  *
73  *	bge_dma_rwctrl
74  *		Value to put in the Read/Write DMA control register.  See
75  *	        the Broadcom PRM for things you can fiddle with in this
76  *		register ...
77  *
78  *	bge_{tx,rx}_{count,ticks}_{norm,intr}
79  *		Send/receive interrupt coalescing parameters.  Counts are
80  *		#s of descriptors, ticks are in microseconds.  *norm* values
81  *		apply between status updates/interrupts; the *intr* values
82  *		refer to the 'during-interrupt' versions - see the PRM.
83  *
84  *		NOTE: these values have been determined by measurement. They
85  *		differ significantly from the values recommended in the PRM.
86  */
87 static uint32_t bge_autorecover = 1;
88 static uint32_t bge_mlcr_default_5714 = MLCR_DEFAULT_5714;
89 
90 static uint32_t bge_dma_rdprio = 1;
91 static uint32_t bge_dma_wrprio = 0;
92 static uint32_t bge_dma_rwctrl = PDRWCR_VAR_DEFAULT;
93 static uint32_t bge_dma_rwctrl_5721 = PDRWCR_VAR_5721;
94 static uint32_t bge_dma_rwctrl_5714 = PDRWCR_VAR_5714;
95 static uint32_t bge_dma_rwctrl_5715 = PDRWCR_VAR_5715;
96 
97 uint32_t bge_rx_ticks_norm = 128;
98 uint32_t bge_tx_ticks_norm = 2048;		/* 8 for FJ2+ !?!?	*/
99 uint32_t bge_rx_count_norm = 8;
100 uint32_t bge_tx_count_norm = 128;
101 
102 static uint32_t bge_rx_ticks_intr = 128;
103 static uint32_t bge_tx_ticks_intr = 0;		/* 8 for FJ2+ !?!?	*/
104 static uint32_t bge_rx_count_intr = 2;
105 static uint32_t bge_tx_count_intr = 0;
106 
107 /*
108  * Memory pool configuration parameters.
109  *
110  * These are generally specific to each member of the chip family, since
111  * each one may have a different memory size/configuration.
112  *
113  * Setting the mbuf pool length for a specific type of chip to 0 inhibits
114  * the driver from programming the various registers; instead they are left
115  * at their hardware defaults.  This is the preferred option for later chips
116  * (5705+), whereas the older chips *required* these registers to be set,
117  * since the h/w default was 0 ;-(
118  */
119 static uint32_t bge_mbuf_pool_base	= MBUF_POOL_BASE_DEFAULT;
120 static uint32_t bge_mbuf_pool_base_5704	= MBUF_POOL_BASE_5704;
121 static uint32_t bge_mbuf_pool_base_5705	= MBUF_POOL_BASE_5705;
122 static uint32_t bge_mbuf_pool_base_5721 = MBUF_POOL_BASE_5721;
123 static uint32_t bge_mbuf_pool_len	= MBUF_POOL_LENGTH_DEFAULT;
124 static uint32_t bge_mbuf_pool_len_5704	= MBUF_POOL_LENGTH_5704;
125 static uint32_t bge_mbuf_pool_len_5705	= 0;	/* use h/w default	*/
126 static uint32_t bge_mbuf_pool_len_5721	= 0;
127 
128 /*
129  * Various high and low water marks, thresholds, etc ...
130  *
131  * Note: these are taken from revision 7 of the PRM, and some are different
132  * from both the values in earlier PRMs *and* those determined experimentally
133  * and used in earlier versions of this driver ...
134  */
135 static uint32_t bge_mbuf_hi_water	= MBUF_HIWAT_DEFAULT;
136 static uint32_t bge_mbuf_lo_water_rmac	= MAC_RX_MBUF_LOWAT_DEFAULT;
137 static uint32_t bge_mbuf_lo_water_rdma	= RDMA_MBUF_LOWAT_DEFAULT;
138 
139 static uint32_t bge_dmad_lo_water	= DMAD_POOL_LOWAT_DEFAULT;
140 static uint32_t bge_dmad_hi_water	= DMAD_POOL_HIWAT_DEFAULT;
141 static uint32_t bge_lowat_recv_frames	= LOWAT_MAX_RECV_FRAMES_DEFAULT;
142 
143 static uint32_t bge_replenish_std	= STD_RCV_BD_REPLENISH_DEFAULT;
144 static uint32_t bge_replenish_mini	= MINI_RCV_BD_REPLENISH_DEFAULT;
145 static uint32_t bge_replenish_jumbo	= JUMBO_RCV_BD_REPLENISH_DEFAULT;
146 
147 static uint32_t	bge_watchdog_count	= 1 << 16;
148 static uint16_t bge_dma_miss_limit	= 20;
149 
150 static uint32_t bge_stop_start_on_sync	= 0;
151 
152 /*
153  * bge_intr_max_loop controls the maximum loop number within bge_intr.
154  * When loading NIC with heavy network traffic, it is useful.
155  * Increasing this value could have positive effect to throughput,
156  * but it might also increase ticks of a bge ISR stick on CPU, which might
157  * lead to bad UI interactive experience. So tune this with caution.
158  */
159 static int bge_intr_max_loop = 1;
160 
161 /*
162  * ========== Low-level chip & ring buffer manipulation ==========
163  */
164 
165 #define	BGE_DBG		BGE_DBG_REGS	/* debug flag for this code	*/
166 
167 
168 /*
169  * Config space read-modify-write routines
170  */
171 
172 #if	BGE_CFG_IO8
173 
174 static void bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits);
175 #pragma	inline(bge_cfg_clr16)
176 
177 static void
178 bge_cfg_clr16(bge_t *bgep, bge_regno_t regno, uint16_t bits)
179 {
180 	uint16_t regval;
181 
182 	BGE_TRACE(("bge_cfg_clr16($%p, 0x%lx, 0x%x)",
183 	    (void *)bgep, regno, bits));
184 
185 	regval = pci_config_get16(bgep->cfg_handle, regno);
186 
187 	BGE_DEBUG(("bge_cfg_clr16($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
188 	    (void *)bgep, regno, bits, regval, regval & ~bits));
189 
190 	regval &= ~bits;
191 	pci_config_put16(bgep->cfg_handle, regno, regval);
192 }
193 
194 #endif	/* BGE_CFG_IO8 */
195 
196 static void bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
197 #pragma	inline(bge_cfg_clr32)
198 
199 static void
200 bge_cfg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
201 {
202 	uint32_t regval;
203 
204 	BGE_TRACE(("bge_cfg_clr32($%p, 0x%lx, 0x%x)",
205 	    (void *)bgep, regno, bits));
206 
207 	regval = pci_config_get32(bgep->cfg_handle, regno);
208 
209 	BGE_DEBUG(("bge_cfg_clr32($%p, 0x%lx, 0x%x): 0x%x => 0x%x",
210 	    (void *)bgep, regno, bits, regval, regval & ~bits));
211 
212 	regval &= ~bits;
213 	pci_config_put32(bgep->cfg_handle, regno, regval);
214 }
215 
216 #if	BGE_IND_IO32
217 
218 /*
219  * Indirect access to registers & RISC scratchpads, using config space
220  * accesses only.
221  *
222  * This isn't currently used, but someday we might want to use it for
223  * restoring the Subsystem Device/Vendor registers (which aren't directly
224  * writable in Config Space), or for downloading firmware into the RISCs
225  *
226  * In any case there are endian issues to be resolved before this code is
227  * enabled; the bizarre way that bytes get twisted by this chip AND by
228  * the PCI bridge in SPARC systems mean that we shouldn't enable it until
229  * it's been thoroughly tested for all access sizes on all supported
230  * architectures (SPARC *and* x86!).
231  */
232 uint32_t bge_ind_get32(bge_t *bgep, bge_regno_t regno);
233 #pragma	inline(bge_ind_get32)
234 
235 uint32_t
236 bge_ind_get32(bge_t *bgep, bge_regno_t regno)
237 {
238 	uint32_t val;
239 
240 	BGE_TRACE(("bge_ind_get32($%p, 0x%lx)", (void *)bgep, regno));
241 
242 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
243 	val = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_RIADR);
244 
245 	BGE_DEBUG(("bge_ind_get32($%p, 0x%lx) => 0x%x",
246 	    (void *)bgep, regno, val));
247 
248 	val = LE_32(val);
249 
250 	return (val);
251 }
252 
253 void bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val);
254 #pragma	inline(bge_ind_put32)
255 
256 void
257 bge_ind_put32(bge_t *bgep, bge_regno_t regno, uint32_t val)
258 {
259 	BGE_TRACE(("bge_ind_put32($%p, 0x%lx, 0x%x)",
260 	    (void *)bgep, regno, val));
261 
262 	val = LE_32(val);
263 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIAAR, regno);
264 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_RIADR, val);
265 }
266 
267 #endif	/* BGE_IND_IO32 */
268 
269 #if	BGE_DEBUGGING
270 
271 static void bge_pci_check(bge_t *bgep);
272 #pragma	no_inline(bge_pci_check)
273 
274 static void
275 bge_pci_check(bge_t *bgep)
276 {
277 	uint16_t pcistatus;
278 
279 	pcistatus = pci_config_get16(bgep->cfg_handle, PCI_CONF_STAT);
280 	if ((pcistatus & (PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB)) != 0)
281 		BGE_DEBUG(("bge_pci_check($%p): PCI status 0x%x",
282 		    (void *)bgep, pcistatus));
283 }
284 
285 #endif	/* BGE_DEBUGGING */
286 
287 /*
288  * Perform first-stage chip (re-)initialisation, using only config-space
289  * accesses:
290  *
291  * + Read the vendor/device/revision/subsystem/cache-line-size registers,
292  *   returning the data in the structure pointed to by <idp>.
293  * + Configure the target-mode endianness (swap) options.
294  * + Disable interrupts and enable Memory Space accesses.
295  * + Enable or disable Bus Mastering according to the <enable_dma> flag.
296  *
297  * This sequence is adapted from Broadcom document 570X-PG102-R,
298  * page 102, steps 1-3, 6-8 and 11-13.  The omitted parts of the sequence
299  * are 4 and 5 (Reset Core and wait) which are handled elsewhere.
300  *
301  * This function MUST be called before any non-config-space accesses
302  * are made; on this first call <enable_dma> is B_FALSE, and it
303  * effectively performs steps 3-1(!) of the initialisation sequence
304  * (the rest are not required but should be harmless).
305  *
306  * It MUST also be called after a chip reset, as this disables
307  * Memory Space cycles!  In this case, <enable_dma> is B_TRUE, and
308  * it is effectively performing steps 6-8.
309  */
310 void bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma);
311 #pragma	no_inline(bge_chip_cfg_init)
312 
313 void
314 bge_chip_cfg_init(bge_t *bgep, chip_id_t *cidp, boolean_t enable_dma)
315 {
316 	ddi_acc_handle_t handle;
317 	uint16_t command;
318 	uint32_t mhcr;
319 	uint16_t value16;
320 	int i;
321 
322 	BGE_TRACE(("bge_chip_cfg_init($%p, $%p, %d)",
323 	    (void *)bgep, (void *)cidp, enable_dma));
324 
325 	/*
326 	 * Step 3: save PCI cache line size and subsystem vendor ID
327 	 *
328 	 * Read all the config-space registers that characterise the
329 	 * chip, specifically vendor/device/revision/subsystem vendor
330 	 * and subsystem device id.  We expect (but don't check) that
331 	 * (vendor == VENDOR_ID_BROADCOM) && (device == DEVICE_ID_5704)
332 	 *
333 	 * Also save all bus-transaction related registers (cache-line
334 	 * size, bus-grant/latency parameters, etc).  Some of these are
335 	 * cleared by reset, so we'll have to restore them later.  This
336 	 * comes from the Broadcom document 570X-PG102-R ...
337 	 *
338 	 * Note: Broadcom document 570X-PG102-R seems to be in error
339 	 * here w.r.t. the offsets of the Subsystem Vendor ID and
340 	 * Subsystem (Device) ID registers, which are the opposite way
341 	 * round according to the PCI standard.  For good measure, we
342 	 * save/restore both anyway.
343 	 */
344 	handle = bgep->cfg_handle;
345 
346 	mhcr = pci_config_get32(handle, PCI_CONF_BGE_MHCR);
347 	cidp->asic_rev = mhcr & MHCR_CHIP_REV_MASK;
348 	cidp->businfo = pci_config_get32(handle, PCI_CONF_BGE_PCISTATE);
349 	cidp->command = pci_config_get16(handle, PCI_CONF_COMM);
350 
351 	cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID);
352 	cidp->device = pci_config_get16(handle, PCI_CONF_DEVID);
353 	cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID);
354 	cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID);
355 	cidp->revision = pci_config_get8(handle, PCI_CONF_REVID);
356 	cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ);
357 	cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER);
358 
359 	BGE_DEBUG(("bge_chip_cfg_init: %s bus is %s and %s; #INTA is %s",
360 	    cidp->businfo & PCISTATE_BUS_IS_PCI ? "PCI" : "PCI-X",
361 	    cidp->businfo & PCISTATE_BUS_IS_FAST ? "fast" : "slow",
362 	    cidp->businfo & PCISTATE_BUS_IS_32_BIT ? "narrow" : "wide",
363 	    cidp->businfo & PCISTATE_INTA_STATE ? "high" : "low"));
364 	BGE_DEBUG(("bge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x",
365 	    cidp->vendor, cidp->device, cidp->revision));
366 	BGE_DEBUG(("bge_chip_cfg_init: subven 0x%x subdev 0x%x asic_rev 0x%x",
367 	    cidp->subven, cidp->subdev, cidp->asic_rev));
368 	BGE_DEBUG(("bge_chip_cfg_init: clsize %d latency %d command 0x%x",
369 	    cidp->clsize, cidp->latency, cidp->command));
370 
371 	/*
372 	 * Step 2 (also step 6): disable and clear interrupts.
373 	 * Steps 11-13: configure PIO endianness options, and enable
374 	 * indirect register access.  We'll also select any other
375 	 * options controlled by the MHCR (e.g. tagged status, mask
376 	 * interrupt mode) at this stage ...
377 	 *
378 	 * Note: internally, the chip is 64-bit and BIG-endian, but
379 	 * since it talks to the host over a (LITTLE-endian) PCI bus,
380 	 * it normally swaps bytes around at the PCI interface.
381 	 * However, the PCI host bridge on SPARC systems normally
382 	 * swaps the byte lanes around too, since SPARCs are also
383 	 * BIG-endian.  So it turns out that on SPARC, the right
384 	 * option is to tell the chip to swap (and the host bridge
385 	 * will swap back again), whereas on x86 we ask the chip
386 	 * NOT to swap, so the natural little-endianness of the
387 	 * PCI bus is assumed.  Then the only thing that doesn't
388 	 * automatically work right is access to an 8-byte register
389 	 * by a little-endian host; but we don't want to set the
390 	 * MHCR_ENABLE_REGISTER_WORD_SWAP bit because then 4-byte
391 	 * accesses don't go where expected ;-(  So we live with
392 	 * that, and perform word-swaps in software in the few cases
393 	 * where a chip register is defined as an 8-byte value --
394 	 * see the code below for details ...
395 	 *
396 	 * Note: the meaning of the 'MASK_INTERRUPT_MODE' bit isn't
397 	 * very clear in the register description in the PRM, but
398 	 * Broadcom document 570X-PG104-R page 248 explains a little
399 	 * more (under "Broadcom Mask Mode").  The bit changes the way
400 	 * the MASK_PCI_INT_OUTPUT bit works: with MASK_INTERRUPT_MODE
401 	 * clear, the chip interprets MASK_PCI_INT_OUTPUT in the same
402 	 * way as the 5700 did, which isn't very convenient.  Setting
403 	 * the MASK_INTERRUPT_MODE bit makes the MASK_PCI_INT_OUTPUT
404 	 * bit do just what its name says -- MASK the PCI #INTA output
405 	 * (i.e. deassert the signal at the pin) leaving all internal
406 	 * state unchanged.  This is much more convenient for our
407 	 * interrupt handler, so we set MASK_INTERRUPT_MODE here.
408 	 *
409 	 * Note: the inconvenient semantics of the interrupt mailbox
410 	 * (nonzero disables and acknowledges/clears the interrupt,
411 	 * zero enables AND CLEARS it) would make race conditions
412 	 * likely in the interrupt handler:
413 	 *
414 	 * (1)	acknowledge & disable interrupts
415 	 * (2)	while (more to do)
416 	 * 		process packets
417 	 * (3)	enable interrupts -- also clears pending
418 	 *
419 	 * If the chip received more packets and internally generated
420 	 * an interrupt between the check at (2) and the mbox write
421 	 * at (3), this interrupt would be lost :-(
422 	 *
423 	 * The best way to avoid this is to use TAGGED STATUS mode,
424 	 * where the chip includes a unique tag in each status block
425 	 * update, and the host, when re-enabling interrupts, passes
426 	 * the last tag it saw back to the chip; then the chip can
427 	 * see whether the host is truly up to date, and regenerate
428 	 * its interrupt if not.
429 	 */
430 	mhcr =	MHCR_ENABLE_INDIRECT_ACCESS |
431 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
432 	    MHCR_MASK_INTERRUPT_MODE |
433 	    MHCR_CLEAR_INTERRUPT_INTA;
434 
435 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
436 		mhcr |= MHCR_MASK_PCI_INT_OUTPUT;
437 
438 #ifdef	_BIG_ENDIAN
439 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
440 #endif	/* _BIG_ENDIAN */
441 
442 	pci_config_put32(handle, PCI_CONF_BGE_MHCR, mhcr);
443 
444 #ifdef BGE_IPMI_ASF
445 	bgep->asf_wordswapped = B_FALSE;
446 #endif
447 	/*
448 	 * Step 1 (also step 7): Enable PCI Memory Space accesses
449 	 *			 Disable Memory Write/Invalidate
450 	 *			 Enable or disable Bus Mastering
451 	 *
452 	 * Note that all other bits are taken from the original value saved
453 	 * the first time through here, rather than from the current register
454 	 * value, 'cos that will have been cleared by a soft RESET since.
455 	 * In this way we preserve the OBP/nexus-parent's preferred settings
456 	 * of the parity-error and system-error enable bits across multiple
457 	 * chip RESETs.
458 	 */
459 	command = bgep->chipid.command | PCI_COMM_MAE;
460 	command &= ~(PCI_COMM_ME|PCI_COMM_MEMWR_INVAL);
461 	if (enable_dma)
462 		command |= PCI_COMM_ME;
463 	/*
464 	 * on BCM5714 revision A0, false parity error gets generated
465 	 * due to a logic bug. Provide a workaround by disabling parity
466 	 * error.
467 	 */
468 	if (((cidp->device == DEVICE_ID_5714C) ||
469 	    (cidp->device == DEVICE_ID_5714S)) &&
470 	    (cidp->revision == REVISION_ID_5714_A0)) {
471 		command &= ~PCI_COMM_PARITY_DETECT;
472 	}
473 	pci_config_put16(handle, PCI_CONF_COMM, command);
474 
475 	/*
476 	 * On some PCI-E device, there were instances when
477 	 * the device was still link training.
478 	 */
479 	if (bgep->chipid.pci_type == BGE_PCI_E) {
480 		i = 0;
481 		value16 = pci_config_get16(handle, PCI_CONF_COMM);
482 		while ((value16 != command) && (i < 100)) {
483 			drv_usecwait(200);
484 			value16 = pci_config_get16(handle, PCI_CONF_COMM);
485 			++i;
486 		}
487 	}
488 
489 	/*
490 	 * Clear any remaining error status bits
491 	 */
492 	pci_config_put16(handle, PCI_CONF_STAT, ~0);
493 
494 	/*
495 	 * Do following if and only if the device is NOT BCM5714C OR
496 	 * BCM5715C
497 	 */
498 	if (!((cidp->device == DEVICE_ID_5714C) ||
499 	    (cidp->device == DEVICE_ID_5715C))) {
500 		/*
501 		 * Make sure these indirect-access registers are sane
502 		 * rather than random after power-up or reset
503 		 */
504 		pci_config_put32(handle, PCI_CONF_BGE_RIAAR, 0);
505 		pci_config_put32(handle, PCI_CONF_BGE_MWBAR, 0);
506 	}
507 	/*
508 	 * Step 8: Disable PCI-X/PCI-E Relaxed Ordering
509 	 */
510 	bge_cfg_clr16(bgep, PCIX_CONF_COMM, PCIX_COMM_RELAXED);
511 
512 	if (cidp->pci_type == BGE_PCI_E) {
513 		if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
514 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL_5723,
515 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
516 		} else
517 			bge_cfg_clr16(bgep, PCI_CONF_DEV_CTRL,
518 			    DEV_CTRL_NO_SNOOP | DEV_CTRL_RELAXED);
519 	}
520 }
521 
522 #ifdef __amd64
523 /*
524  * Distinguish CPU types
525  *
526  * These use to  distinguish AMD64 or Intel EM64T of CPU running mode.
527  * If CPU runs on Intel EM64T mode,the 64bit operation cannot works fine
528  * for PCI-Express based network interface card. This is the work-around
529  * for those nics.
530  */
531 static boolean_t bge_get_em64t_type(void);
532 #pragma	inline(bge_get_em64t_type)
533 
534 static boolean_t
535 bge_get_em64t_type(void)
536 {
537 
538 	return (x86_vendor == X86_VENDOR_Intel);
539 }
540 #endif
541 
542 /*
543  * Operating register get/set access routines
544  */
545 
546 uint32_t bge_reg_get32(bge_t *bgep, bge_regno_t regno);
547 #pragma	inline(bge_reg_get32)
548 
549 uint32_t
550 bge_reg_get32(bge_t *bgep, bge_regno_t regno)
551 {
552 	BGE_TRACE(("bge_reg_get32($%p, 0x%lx)",
553 	    (void *)bgep, regno));
554 
555 	return (ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno)));
556 }
557 
558 void bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data);
559 #pragma	inline(bge_reg_put32)
560 
561 void
562 bge_reg_put32(bge_t *bgep, bge_regno_t regno, uint32_t data)
563 {
564 	BGE_TRACE(("bge_reg_put32($%p, 0x%lx, 0x%x)",
565 	    (void *)bgep, regno, data));
566 
567 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), data);
568 	BGE_PCICHK(bgep);
569 }
570 
571 void bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
572 #pragma	inline(bge_reg_set32)
573 
574 void
575 bge_reg_set32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
576 {
577 	uint32_t regval;
578 
579 	BGE_TRACE(("bge_reg_set32($%p, 0x%lx, 0x%x)",
580 	    (void *)bgep, regno, bits));
581 
582 	regval = bge_reg_get32(bgep, regno);
583 	regval |= bits;
584 	bge_reg_put32(bgep, regno, regval);
585 }
586 
587 void bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits);
588 #pragma	inline(bge_reg_clr32)
589 
590 void
591 bge_reg_clr32(bge_t *bgep, bge_regno_t regno, uint32_t bits)
592 {
593 	uint32_t regval;
594 
595 	BGE_TRACE(("bge_reg_clr32($%p, 0x%lx, 0x%x)",
596 	    (void *)bgep, regno, bits));
597 
598 	regval = bge_reg_get32(bgep, regno);
599 	regval &= ~bits;
600 	bge_reg_put32(bgep, regno, regval);
601 }
602 
603 static uint64_t bge_reg_get64(bge_t *bgep, bge_regno_t regno);
604 #pragma	inline(bge_reg_get64)
605 
606 static uint64_t
607 bge_reg_get64(bge_t *bgep, bge_regno_t regno)
608 {
609 	uint64_t regval;
610 
611 #ifdef	__amd64
612 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) {
613 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
614 		regval <<= 32;
615 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
616 	} else {
617 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
618 	}
619 #elif defined(__sparc)
620 	if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
621 		regval = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
622 		regval <<= 32;
623 		regval |= ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno + 4));
624 	} else {
625 		regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
626 	}
627 #else
628 	regval = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, regno));
629 #endif
630 
631 #ifdef	_LITTLE_ENDIAN
632 	regval = (regval >> 32) | (regval << 32);
633 #endif	/* _LITTLE_ENDIAN */
634 
635 	BGE_TRACE(("bge_reg_get64($%p, 0x%lx) = 0x%016llx",
636 	    (void *)bgep, regno, regval));
637 
638 	return (regval);
639 }
640 
641 static void bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data);
642 #pragma	inline(bge_reg_put64)
643 
644 static void
645 bge_reg_put64(bge_t *bgep, bge_regno_t regno, uint64_t data)
646 {
647 	BGE_TRACE(("bge_reg_put64($%p, 0x%lx, 0x%016llx)",
648 	    (void *)bgep, regno, data));
649 
650 #ifdef	_LITTLE_ENDIAN
651 	data = ((data >> 32) | (data << 32));
652 #endif	/* _LITTLE_ENDIAN */
653 
654 #ifdef	__amd64
655 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) {
656 		ddi_put32(bgep->io_handle,
657 		    PIO_ADDR(bgep, regno), (uint32_t)data);
658 		BGE_PCICHK(bgep);
659 		ddi_put32(bgep->io_handle,
660 		    PIO_ADDR(bgep, regno + 4), (uint32_t)(data >> 32));
661 
662 	} else {
663 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
664 	}
665 #elif defined(__sparc)
666 	if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
667 		ddi_put32(bgep->io_handle,
668 		    PIO_ADDR(bgep, regno + 4), (uint32_t)data);
669 		BGE_PCICHK(bgep);
670 		ddi_put32(bgep->io_handle,
671 		    PIO_ADDR(bgep, regno), (uint32_t)(data >> 32));
672 	} else {
673 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
674 	}
675 #else
676 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, regno), data);
677 #endif
678 
679 	BGE_PCICHK(bgep);
680 }
681 
682 /*
683  * The DDI doesn't provide get/put functions for 128 bit data
684  * so we put RCBs out as two 64-bit chunks instead.
685  */
686 static void bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
687 #pragma	inline(bge_reg_putrcb)
688 
689 static void
690 bge_reg_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
691 {
692 	uint64_t *p;
693 
694 	BGE_TRACE(("bge_reg_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
695 	    (void *)bgep, addr, rcbp->host_ring_addr,
696 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
697 
698 	ASSERT((addr % sizeof (*rcbp)) == 0);
699 
700 	p = (void *)rcbp;
701 	bge_reg_put64(bgep, addr, *p++);
702 	bge_reg_put64(bgep, addr+8, *p);
703 }
704 
705 void bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data);
706 #pragma	inline(bge_mbx_put)
707 
708 void
709 bge_mbx_put(bge_t *bgep, bge_regno_t regno, uint64_t data)
710 {
711 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
712 		regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
713 
714 	BGE_TRACE(("bge_mbx_put($%p, 0x%lx, 0x%016llx)",
715 	    (void *)bgep, regno, data));
716 
717 	/*
718 	 * Mailbox registers are nominally 64 bits on the 5701, but
719 	 * the MSW isn't used.  On the 5703, they're only 32 bits
720 	 * anyway.  So here we just write the lower(!) 32 bits -
721 	 * remembering that the chip is big-endian, even though the
722 	 * PCI bus is little-endian ...
723 	 */
724 #ifdef	_BIG_ENDIAN
725 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno+4), (uint32_t)data);
726 #else
727 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), (uint32_t)data);
728 #endif	/* _BIG_ENDIAN */
729 	BGE_PCICHK(bgep);
730 }
731 
732 uint32_t bge_mbx_get(bge_t *bgep, bge_regno_t regno);
733 #pragma inline(bge_mbx_get)
734 
735 uint32_t
736 bge_mbx_get(bge_t *bgep, bge_regno_t regno)
737 {
738 	uint32_t val32;
739 
740 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
741 		regno += INTERRUPT_LP_MBOX_0_REG - INTERRUPT_MBOX_0_REG + 4;
742 
743 	BGE_TRACE(("bge_mbx_get($%p, 0x%lx)",
744 	    (void *)bgep, regno));
745 
746 #ifdef	_BIG_ENDIAN
747 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno+4));
748 #else
749 	val32 = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, regno));
750 #endif	/* _BIG_ENDIAN */
751 	BGE_PCICHK(bgep);
752 
753 	return (val32);
754 }
755 
756 
757 #if	BGE_DEBUGGING
758 
759 void bge_led_mark(bge_t *bgep);
760 #pragma	no_inline(bge_led_mark)
761 
762 void
763 bge_led_mark(bge_t *bgep)
764 {
765 	uint32_t led_ctrl = LED_CONTROL_OVERRIDE_LINK |
766 	    LED_CONTROL_1000MBPS_LED |
767 	    LED_CONTROL_100MBPS_LED |
768 	    LED_CONTROL_10MBPS_LED;
769 
770 	/*
771 	 * Blink all three LINK LEDs on simultaneously, then all off,
772 	 * then restore to automatic hardware control.  This is used
773 	 * in laboratory testing to trigger a logic analyser or scope.
774 	 */
775 	bge_reg_set32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
776 	led_ctrl ^= LED_CONTROL_OVERRIDE_LINK;
777 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
778 	led_ctrl = LED_CONTROL_OVERRIDE_LINK;
779 	bge_reg_clr32(bgep, ETHERNET_MAC_LED_CONTROL_REG, led_ctrl);
780 }
781 
782 #endif	/* BGE_DEBUGGING */
783 
784 /*
785  * NIC on-chip memory access routines
786  *
787  * Only 32K of NIC memory is visible at a time, controlled by the
788  * Memory Window Base Address Register (in PCI config space).  Once
789  * this is set, the 32K region of NIC-local memory that it refers
790  * to can be directly addressed in the upper 32K of the 64K of PCI
791  * memory space used for the device.
792  */
793 
794 static void bge_nic_setwin(bge_t *bgep, bge_regno_t base);
795 #pragma	inline(bge_nic_setwin)
796 
797 static void
798 bge_nic_setwin(bge_t *bgep, bge_regno_t base)
799 {
800 	chip_id_t *cidp;
801 
802 	BGE_TRACE(("bge_nic_setwin($%p, 0x%lx)",
803 	    (void *)bgep, base));
804 
805 	ASSERT((base & MWBAR_GRANULE_MASK) == 0);
806 
807 	/*
808 	 * Don't do repeated zero data writes,
809 	 * if the device is BCM5714C/15C.
810 	 */
811 	cidp = &bgep->chipid;
812 	if ((cidp->device == DEVICE_ID_5714C) ||
813 	    (cidp->device == DEVICE_ID_5715C)) {
814 		if (bgep->lastWriteZeroData && (base == (bge_regno_t)0))
815 			return;
816 		/* Adjust lastWriteZeroData */
817 		bgep->lastWriteZeroData = ((base == (bge_regno_t)0) ?
818 		    B_TRUE : B_FALSE);
819 	}
820 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, base);
821 }
822 
823 static uint32_t bge_nic_get32(bge_t *bgep, bge_regno_t addr);
824 #pragma	inline(bge_nic_get32)
825 
826 static uint32_t
827 bge_nic_get32(bge_t *bgep, bge_regno_t addr)
828 {
829 	uint32_t data;
830 
831 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
832 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
833 		/* workaround for word swap error */
834 		if (addr & 4)
835 			addr = addr - 4;
836 		else
837 			addr = addr + 4;
838 	}
839 #endif
840 
841 #ifdef __sparc
842 	data = bge_nic_read32(bgep, addr);
843 #else
844 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
845 	addr &= MWBAR_GRANULE_MASK;
846 	addr += NIC_MEM_WINDOW_OFFSET;
847 
848 	data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
849 #endif
850 
851 	BGE_TRACE(("bge_nic_get32($%p, 0x%lx) = 0x%08x",
852 	    (void *)bgep, addr, data));
853 
854 	return (data);
855 }
856 
857 void bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data);
858 #pragma inline(bge_nic_put32)
859 
860 void
861 bge_nic_put32(bge_t *bgep, bge_regno_t addr, uint32_t data)
862 {
863 	BGE_TRACE(("bge_nic_put32($%p, 0x%lx, 0x%08x)",
864 	    (void *)bgep, addr, data));
865 
866 #if defined(BGE_IPMI_ASF) && !defined(__sparc)
867 	if (bgep->asf_enabled && !bgep->asf_wordswapped) {
868 		/* workaround for word swap error */
869 		if (addr & 4)
870 			addr = addr - 4;
871 		else
872 			addr = addr + 4;
873 	}
874 #endif
875 
876 #ifdef __sparc
877 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
878 	data = LE_32(data);
879 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR, data);
880 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
881 #else
882 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
883 	addr &= MWBAR_GRANULE_MASK;
884 	addr += NIC_MEM_WINDOW_OFFSET;
885 	ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr), data);
886 	BGE_PCICHK(bgep);
887 #endif
888 }
889 
890 static uint64_t bge_nic_get64(bge_t *bgep, bge_regno_t addr);
891 #pragma	inline(bge_nic_get64)
892 
893 static uint64_t
894 bge_nic_get64(bge_t *bgep, bge_regno_t addr)
895 {
896 	uint64_t data;
897 
898 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
899 	addr &= MWBAR_GRANULE_MASK;
900 	addr += NIC_MEM_WINDOW_OFFSET;
901 
902 #ifdef	__amd64
903 		if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) {
904 			data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
905 			data <<= 32;
906 			data |= ddi_get32(bgep->io_handle,
907 			    PIO_ADDR(bgep, addr + 4));
908 		} else {
909 			data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
910 		}
911 #elif defined(__sparc)
912 		if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
913 			data = ddi_get32(bgep->io_handle, PIO_ADDR(bgep, addr));
914 			data <<= 32;
915 			data |= ddi_get32(bgep->io_handle,
916 			    PIO_ADDR(bgep, addr + 4));
917 		} else {
918 			data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
919 		}
920 #else
921 		data = ddi_get64(bgep->io_handle, PIO_ADDR(bgep, addr));
922 #endif
923 
924 	BGE_TRACE(("bge_nic_get64($%p, 0x%lx) = 0x%016llx",
925 	    (void *)bgep, addr, data));
926 
927 	return (data);
928 }
929 
930 static void bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data);
931 #pragma	inline(bge_nic_put64)
932 
933 static void
934 bge_nic_put64(bge_t *bgep, bge_regno_t addr, uint64_t data)
935 {
936 	BGE_TRACE(("bge_nic_put64($%p, 0x%lx, 0x%016llx)",
937 	    (void *)bgep, addr, data));
938 
939 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
940 	addr &= MWBAR_GRANULE_MASK;
941 	addr += NIC_MEM_WINDOW_OFFSET;
942 
943 #ifdef	__amd64
944 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) {
945 		ddi_put32(bgep->io_handle,
946 		    PIO_ADDR(bgep, addr), (uint32_t)data);
947 		BGE_PCICHK(bgep);
948 		ddi_put32(bgep->io_handle,
949 		    PIO_ADDR(bgep, addr + 4), (uint32_t)(data >> 32));
950 	} else {
951 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
952 	}
953 #elif defined(__sparc)
954 	if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
955 		ddi_put32(bgep->io_handle,
956 		    PIO_ADDR(bgep, addr + 4), (uint32_t)data);
957 		BGE_PCICHK(bgep);
958 		ddi_put32(bgep->io_handle,
959 		    PIO_ADDR(bgep, addr), (uint32_t)(data >> 32));
960 	} else {
961 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
962 	}
963 #else
964 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), data);
965 #endif
966 
967 	BGE_PCICHK(bgep);
968 }
969 
970 /*
971  * The DDI doesn't provide get/put functions for 128 bit data
972  * so we put RCBs out as two 64-bit chunks instead.
973  */
974 static void bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp);
975 #pragma	inline(bge_nic_putrcb)
976 
977 static void
978 bge_nic_putrcb(bge_t *bgep, bge_regno_t addr, bge_rcb_t *rcbp)
979 {
980 	uint64_t *p;
981 
982 	BGE_TRACE(("bge_nic_putrcb($%p, 0x%lx, 0x%016llx:%04x:%04x:%08x)",
983 	    (void *)bgep, addr, rcbp->host_ring_addr,
984 	    rcbp->max_len, rcbp->flags, rcbp->nic_ring_addr));
985 
986 	ASSERT((addr % sizeof (*rcbp)) == 0);
987 
988 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
989 	addr &= MWBAR_GRANULE_MASK;
990 	addr += NIC_MEM_WINDOW_OFFSET;
991 
992 	p = (void *)rcbp;
993 #ifdef	__amd64
994 	if (DEVICE_5723_SERIES_CHIPSETS(bgep) || bge_get_em64t_type()) {
995 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
996 		    (uint32_t)(*p));
997 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
998 		    (uint32_t)(*p >> 32));
999 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1000 		    (uint32_t)(*(p + 1)));
1001 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1002 		    (uint32_t)(*p >> 32));
1003 
1004 	} else {
1005 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1006 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr+8), *p);
1007 	}
1008 #elif defined(__sparc)
1009 	if (DEVICE_5723_SERIES_CHIPSETS(bgep)) {
1010 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 4),
1011 		    (uint32_t)(*p));
1012 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr),
1013 		    (uint32_t)(*p >> 32));
1014 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 12),
1015 		    (uint32_t)(*(p + 1)));
1016 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, addr + 8),
1017 		    (uint32_t)(*p >> 32));
1018 	} else {
1019 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1020 		ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1021 	}
1022 #else
1023 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr), *p++);
1024 	ddi_put64(bgep->io_handle, PIO_ADDR(bgep, addr + 8), *p);
1025 #endif
1026 
1027 	BGE_PCICHK(bgep);
1028 }
1029 
1030 static void bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes);
1031 #pragma	inline(bge_nic_zero)
1032 
1033 static void
1034 bge_nic_zero(bge_t *bgep, bge_regno_t addr, uint32_t nbytes)
1035 {
1036 	BGE_TRACE(("bge_nic_zero($%p, 0x%lx, 0x%x)",
1037 	    (void *)bgep, addr, nbytes));
1038 
1039 	ASSERT((addr & ~MWBAR_GRANULE_MASK) ==
1040 	    ((addr+nbytes) & ~MWBAR_GRANULE_MASK));
1041 
1042 	bge_nic_setwin(bgep, addr & ~MWBAR_GRANULE_MASK);
1043 	addr &= MWBAR_GRANULE_MASK;
1044 	addr += NIC_MEM_WINDOW_OFFSET;
1045 
1046 	(void) ddi_device_zero(bgep->io_handle, PIO_ADDR(bgep, addr),
1047 	    nbytes, 1, DDI_DATA_SZ08_ACC);
1048 	BGE_PCICHK(bgep);
1049 }
1050 
1051 /*
1052  * MII (PHY) register get/set access routines
1053  *
1054  * These use the chip's MII auto-access method, controlled by the
1055  * MII Communication register at 0x044c, so the CPU doesn't have
1056  * to fiddle with the individual bits.
1057  */
1058 
1059 #undef	BGE_DBG
1060 #define	BGE_DBG		BGE_DBG_MII	/* debug flag for this code	*/
1061 
1062 static uint16_t bge_mii_access(bge_t *bgep, bge_regno_t regno,
1063 				uint16_t data, uint32_t cmd);
1064 #pragma	no_inline(bge_mii_access)
1065 
1066 static uint16_t
1067 bge_mii_access(bge_t *bgep, bge_regno_t regno, uint16_t data, uint32_t cmd)
1068 {
1069 	uint32_t timeout;
1070 	uint32_t regval1;
1071 	uint32_t regval2;
1072 
1073 	BGE_TRACE(("bge_mii_access($%p, 0x%lx, 0x%x, 0x%x)",
1074 	    (void *)bgep, regno, data, cmd));
1075 
1076 	ASSERT(mutex_owned(bgep->genlock));
1077 
1078 	/*
1079 	 * Assemble the command ...
1080 	 */
1081 	cmd |= data << MI_COMMS_DATA_SHIFT;
1082 	cmd |= regno << MI_COMMS_REGISTER_SHIFT;
1083 	cmd |= bgep->phy_mii_addr << MI_COMMS_ADDRESS_SHIFT;
1084 	cmd |= MI_COMMS_START;
1085 
1086 	/*
1087 	 * Wait for any command already in progress ...
1088 	 *
1089 	 * Note: this *shouldn't* ever find that there is a command
1090 	 * in progress, because we already hold the <genlock> mutex.
1091 	 * Nonetheless, we have sometimes seen the MI_COMMS_START
1092 	 * bit set here -- it seems that the chip can initiate MII
1093 	 * accesses internally, even with polling OFF.
1094 	 */
1095 	regval1 = regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1096 	for (timeout = 100; ; ) {
1097 		if ((regval2 & MI_COMMS_START) == 0) {
1098 			bge_reg_put32(bgep, MI_COMMS_REG, cmd);
1099 			break;
1100 		}
1101 		if (--timeout == 0)
1102 			break;
1103 		drv_usecwait(10);
1104 		regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1105 	}
1106 
1107 	if (timeout == 0)
1108 		return ((uint16_t)~0u);
1109 
1110 	if (timeout != 100)
1111 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1112 		    "MI_COMMS_START set for %d us; 0x%x->0x%x",
1113 		    cmd, 10*(100-timeout), regval1, regval2));
1114 
1115 	regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1116 	for (timeout = 1000; ; ) {
1117 		if ((regval1 & MI_COMMS_START) == 0)
1118 			break;
1119 		if (--timeout == 0)
1120 			break;
1121 		drv_usecwait(10);
1122 		regval1 = bge_reg_get32(bgep, MI_COMMS_REG);
1123 	}
1124 
1125 	/*
1126 	 * Drop out early if the READ FAILED bit is set -- this chip
1127 	 * could be a 5703/4S, with a SerDes instead of a PHY!
1128 	 */
1129 	if (regval2 & MI_COMMS_READ_FAILED)
1130 		return ((uint16_t)~0u);
1131 
1132 	if (timeout == 0)
1133 		return ((uint16_t)~0u);
1134 
1135 	/*
1136 	 * The PRM says to wait 5us after seeing the START bit clear
1137 	 * and then re-read the register to get the final value of the
1138 	 * data field, in order to avoid a race condition where the
1139 	 * START bit is clear but the data field isn't yet valid.
1140 	 *
1141 	 * Note: we don't actually seem to be encounter this race;
1142 	 * except when the START bit is seen set again (see below),
1143 	 * the data field doesn't change during this 5us interval.
1144 	 */
1145 	drv_usecwait(5);
1146 	regval2 = bge_reg_get32(bgep, MI_COMMS_REG);
1147 
1148 	/*
1149 	 * Unfortunately, when following the PRMs instructions above,
1150 	 * we have occasionally seen the START bit set again(!) in the
1151 	 * value read after the 5us delay. This seems to be due to the
1152 	 * chip autonomously starting another MII access internally.
1153 	 * In such cases, the command/data/etc fields relate to the
1154 	 * internal command, rather than the one that we thought had
1155 	 * just finished.  So in this case, we fall back to returning
1156 	 * the data from the original read that showed START clear.
1157 	 */
1158 	if (regval2 & MI_COMMS_START) {
1159 		BGE_REPORT((bgep, "bge_mii_access: cmd 0x%x -- "
1160 		    "MI_COMMS_START set after transaction; 0x%x->0x%x",
1161 		    cmd, regval1, regval2));
1162 		regval2 = regval1;
1163 	}
1164 
1165 	if (regval2 & MI_COMMS_START)
1166 		return ((uint16_t)~0u);
1167 
1168 	if (regval2 & MI_COMMS_READ_FAILED)
1169 		return ((uint16_t)~0u);
1170 
1171 	return ((regval2 & MI_COMMS_DATA_MASK) >> MI_COMMS_DATA_SHIFT);
1172 }
1173 
1174 uint16_t bge_mii_get16(bge_t *bgep, bge_regno_t regno);
1175 #pragma	no_inline(bge_mii_get16)
1176 
1177 uint16_t
1178 bge_mii_get16(bge_t *bgep, bge_regno_t regno)
1179 {
1180 	BGE_TRACE(("bge_mii_get16($%p, 0x%lx)",
1181 	    (void *)bgep, regno));
1182 
1183 	ASSERT(mutex_owned(bgep->genlock));
1184 
1185 	if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1186 	    (regno == MII_MSCONTROL)))
1187 		return (0);
1188 
1189 	return (bge_mii_access(bgep, regno, 0, MI_COMMS_COMMAND_READ));
1190 }
1191 
1192 void bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data);
1193 #pragma	no_inline(bge_mii_put16)
1194 
1195 void
1196 bge_mii_put16(bge_t *bgep, bge_regno_t regno, uint16_t data)
1197 {
1198 	BGE_TRACE(("bge_mii_put16($%p, 0x%lx, 0x%x)",
1199 	    (void *)bgep, regno, data));
1200 
1201 	ASSERT(mutex_owned(bgep->genlock));
1202 
1203 	if (DEVICE_5906_SERIES_CHIPSETS(bgep) && ((regno == MII_AUX_CONTROL) ||
1204 	    (regno == MII_MSCONTROL)))
1205 		return;
1206 
1207 	(void) bge_mii_access(bgep, regno, data, MI_COMMS_COMMAND_WRITE);
1208 }
1209 
1210 #undef	BGE_DBG
1211 #define	BGE_DBG		BGE_DBG_SEEPROM	/* debug flag for this code	*/
1212 
1213 #if	BGE_SEE_IO32 || BGE_FLASH_IO32
1214 
1215 /*
1216  * Basic SEEPROM get/set access routine
1217  *
1218  * This uses the chip's SEEPROM auto-access method, controlled by the
1219  * Serial EEPROM Address/Data Registers at 0x6838/683c, so the CPU
1220  * doesn't have to fiddle with the individual bits.
1221  *
1222  * The caller should hold <genlock> and *also* have already acquired
1223  * the right to access the SEEPROM, via bge_nvmem_acquire() above.
1224  *
1225  * Return value:
1226  *	0 on success,
1227  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1228  *	EPROTO on other h/w or s/w errors.
1229  *
1230  * <*dp> is an input to a SEEPROM_ACCESS_WRITE operation, or an output
1231  * from a (successful) SEEPROM_ACCESS_READ.
1232  */
1233 static int bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1234 				uint32_t *dp);
1235 #pragma	no_inline(bge_seeprom_access)
1236 
1237 static int
1238 bge_seeprom_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1239 {
1240 	uint32_t tries;
1241 	uint32_t regval;
1242 
1243 	ASSERT(mutex_owned(bgep->genlock));
1244 
1245 	/*
1246 	 * On the newer chips that support both SEEPROM & Flash, we need
1247 	 * to specifically enable SEEPROM access (Flash is the default).
1248 	 * On older chips, we don't; SEEPROM is the only NVtype supported,
1249 	 * and the NVM control registers don't exist ...
1250 	 */
1251 	switch (bgep->chipid.nvtype) {
1252 	case BGE_NVTYPE_NONE:
1253 	case BGE_NVTYPE_UNKNOWN:
1254 		_NOTE(NOTREACHED)
1255 	case BGE_NVTYPE_SEEPROM:
1256 		break;
1257 
1258 	case BGE_NVTYPE_LEGACY_SEEPROM:
1259 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1260 	case BGE_NVTYPE_BUFFERED_FLASH:
1261 	default:
1262 		bge_reg_set32(bgep, NVM_CONFIG1_REG,
1263 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1264 		break;
1265 	}
1266 
1267 	/*
1268 	 * Check there's no command in progress.
1269 	 *
1270 	 * Note: this *shouldn't* ever find that there is a command
1271 	 * in progress, because we already hold the <genlock> mutex.
1272 	 * Also, to ensure we don't have a conflict with the chip's
1273 	 * internal firmware or a process accessing the same (shared)
1274 	 * SEEPROM through the other port of a 5704, we've already
1275 	 * been through the "software arbitration" protocol.
1276 	 * So this is just a final consistency check: we shouldn't
1277 	 * see EITHER the START bit (command started but not complete)
1278 	 * OR the COMPLETE bit (command completed but not cleared).
1279 	 */
1280 	regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1281 	if (regval & SEEPROM_ACCESS_START)
1282 		return (EPROTO);
1283 	if (regval & SEEPROM_ACCESS_COMPLETE)
1284 		return (EPROTO);
1285 
1286 	/*
1287 	 * Assemble the command ...
1288 	 */
1289 	cmd |= addr & SEEPROM_ACCESS_ADDRESS_MASK;
1290 	addr >>= SEEPROM_ACCESS_ADDRESS_SIZE;
1291 	addr <<= SEEPROM_ACCESS_DEVID_SHIFT;
1292 	cmd |= addr & SEEPROM_ACCESS_DEVID_MASK;
1293 	cmd |= SEEPROM_ACCESS_START;
1294 	cmd |= SEEPROM_ACCESS_COMPLETE;
1295 	cmd |= regval & SEEPROM_ACCESS_HALFCLOCK_MASK;
1296 
1297 	bge_reg_put32(bgep, SERIAL_EEPROM_DATA_REG, *dp);
1298 	bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, cmd);
1299 
1300 	/*
1301 	 * By observation, a successful access takes ~20us on a 5703/4,
1302 	 * but apparently much longer (up to 1000us) on the obsolescent
1303 	 * BCM5700/BCM5701.  We want to be sure we don't get any false
1304 	 * timeouts here; but OTOH, we don't want a bogus access to lock
1305 	 * out interrupts for longer than necessary. So we'll allow up
1306 	 * to 1000us ...
1307 	 */
1308 	for (tries = 0; tries < 1000; ++tries) {
1309 		regval = bge_reg_get32(bgep, SERIAL_EEPROM_ADDRESS_REG);
1310 		if (regval & SEEPROM_ACCESS_COMPLETE)
1311 			break;
1312 		drv_usecwait(1);
1313 	}
1314 
1315 	if (regval & SEEPROM_ACCESS_COMPLETE) {
1316 		/*
1317 		 * All OK; read the SEEPROM data register, then write back
1318 		 * the value read from the address register in order to
1319 		 * clear the <complete> bit and leave the SEEPROM access
1320 		 * state machine idle, ready for the next access ...
1321 		 */
1322 		BGE_DEBUG(("bge_seeprom_access: complete after %d us", tries));
1323 		*dp = bge_reg_get32(bgep, SERIAL_EEPROM_DATA_REG);
1324 		bge_reg_put32(bgep, SERIAL_EEPROM_ADDRESS_REG, regval);
1325 		return (0);
1326 	}
1327 
1328 	/*
1329 	 * Hmm ... what happened here?
1330 	 *
1331 	 * Most likely, the user addressed a non-existent SEEPROM. Or
1332 	 * maybe the SEEPROM was busy internally (e.g. processing a write)
1333 	 * and didn't respond to being addressed. Either way, it's left
1334 	 * the SEEPROM access state machine wedged. So we'll reset it
1335 	 * before we leave, so it's ready for next time ...
1336 	 */
1337 	BGE_DEBUG(("bge_seeprom_access: timed out after %d us", tries));
1338 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
1339 	return (ENODATA);
1340 }
1341 
1342 /*
1343  * Basic Flash get/set access routine
1344  *
1345  * These use the chip's Flash auto-access method, controlled by the
1346  * Flash Access Registers at 0x7000-701c, so the CPU doesn't have to
1347  * fiddle with the individual bits.
1348  *
1349  * The caller should hold <genlock> and *also* have already acquired
1350  * the right to access the Flash, via bge_nvmem_acquire() above.
1351  *
1352  * Return value:
1353  *	0 on success,
1354  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1355  *	ENODEV if the NVmem device is missing or otherwise unusable
1356  *
1357  * <*dp> is an input to a NVM_FLASH_CMD_WR operation, or an output
1358  * from a (successful) NVM_FLASH_CMD_RD.
1359  */
1360 static int bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr,
1361 				uint32_t *dp);
1362 #pragma	no_inline(bge_flash_access)
1363 
1364 static int
1365 bge_flash_access(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1366 {
1367 	uint32_t tries;
1368 	uint32_t regval;
1369 
1370 	ASSERT(mutex_owned(bgep->genlock));
1371 
1372 	/*
1373 	 * On the newer chips that support both SEEPROM & Flash, we need
1374 	 * to specifically disable SEEPROM access while accessing Flash.
1375 	 * The older chips don't support Flash, and the NVM registers don't
1376 	 * exist, so we shouldn't be here at all!
1377 	 */
1378 	switch (bgep->chipid.nvtype) {
1379 	case BGE_NVTYPE_NONE:
1380 	case BGE_NVTYPE_UNKNOWN:
1381 		_NOTE(NOTREACHED)
1382 	case BGE_NVTYPE_SEEPROM:
1383 		return (ENODEV);
1384 
1385 	case BGE_NVTYPE_LEGACY_SEEPROM:
1386 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1387 	case BGE_NVTYPE_BUFFERED_FLASH:
1388 	default:
1389 		bge_reg_clr32(bgep, NVM_CONFIG1_REG,
1390 		    NVM_CFG1_LEGACY_SEEPROM_MODE);
1391 		break;
1392 	}
1393 
1394 	/*
1395 	 * Assemble the command ...
1396 	 */
1397 	addr &= NVM_FLASH_ADDR_MASK;
1398 	cmd |= NVM_FLASH_CMD_DOIT;
1399 	cmd |= NVM_FLASH_CMD_FIRST;
1400 	cmd |= NVM_FLASH_CMD_LAST;
1401 	cmd |= NVM_FLASH_CMD_DONE;
1402 
1403 	bge_reg_put32(bgep, NVM_FLASH_WRITE_REG, *dp);
1404 	bge_reg_put32(bgep, NVM_FLASH_ADDR_REG, addr);
1405 	bge_reg_put32(bgep, NVM_FLASH_CMD_REG, cmd);
1406 
1407 	/*
1408 	 * Allow up to 1000ms ...
1409 	 */
1410 	for (tries = 0; tries < 1000; ++tries) {
1411 		regval = bge_reg_get32(bgep, NVM_FLASH_CMD_REG);
1412 		if (regval & NVM_FLASH_CMD_DONE)
1413 			break;
1414 		drv_usecwait(1);
1415 	}
1416 
1417 	if (regval & NVM_FLASH_CMD_DONE) {
1418 		/*
1419 		 * All OK; read the data from the Flash read register
1420 		 */
1421 		BGE_DEBUG(("bge_flash_access: complete after %d us", tries));
1422 		*dp = bge_reg_get32(bgep, NVM_FLASH_READ_REG);
1423 		return (0);
1424 	}
1425 
1426 	/*
1427 	 * Hmm ... what happened here?
1428 	 *
1429 	 * Most likely, the user addressed a non-existent Flash. Or
1430 	 * maybe the Flash was busy internally (e.g. processing a write)
1431 	 * and didn't respond to being addressed. Either way, there's
1432 	 * nothing we can here ...
1433 	 */
1434 	BGE_DEBUG(("bge_flash_access: timed out after %d us", tries));
1435 	return (ENODATA);
1436 }
1437 
1438 /*
1439  * The next two functions regulate access to the NVram (if fitted).
1440  *
1441  * On a 5704 (dual core) chip, there's only one SEEPROM and one Flash
1442  * (SPI) interface, but they can be accessed through either port. These
1443  * are managed by different instance of this driver and have no software
1444  * state in common.
1445  *
1446  * In addition (and even on a single core chip) the chip's internal
1447  * firmware can access the SEEPROM/Flash, most notably after a RESET
1448  * when it may download code to run internally.
1449  *
1450  * So we need to arbitrate between these various software agents.  For
1451  * this purpose, the chip provides the Software Arbitration Register,
1452  * which implements hardware(!) arbitration.
1453  *
1454  * This functionality didn't exist on older (5700/5701) chips, so there's
1455  * nothing we can do by way of arbitration on those; also, if there's no
1456  * SEEPROM/Flash fitted (or we couldn't determine what type), there's also
1457  * nothing to do.
1458  *
1459  * The internal firmware appears to use Request 0, which is the highest
1460  * priority.  So we'd like to use Request 2, leaving one higher and one
1461  * lower for any future developments ... but apparently this doesn't
1462  * always work.  So for now, the code uses Request 1 ;-(
1463  */
1464 
1465 #define	NVM_READ_REQ	NVM_READ_REQ1
1466 #define	NVM_RESET_REQ	NVM_RESET_REQ1
1467 #define	NVM_SET_REQ	NVM_SET_REQ1
1468 
1469 static void bge_nvmem_relinquish(bge_t *bgep);
1470 #pragma	no_inline(bge_nvmem_relinquish)
1471 
1472 static void
1473 bge_nvmem_relinquish(bge_t *bgep)
1474 {
1475 	ASSERT(mutex_owned(bgep->genlock));
1476 
1477 	switch (bgep->chipid.nvtype) {
1478 	case BGE_NVTYPE_NONE:
1479 	case BGE_NVTYPE_UNKNOWN:
1480 		_NOTE(NOTREACHED)
1481 		return;
1482 
1483 	case BGE_NVTYPE_SEEPROM:
1484 		/*
1485 		 * No arbitration performed, no release needed
1486 		 */
1487 		return;
1488 
1489 	case BGE_NVTYPE_LEGACY_SEEPROM:
1490 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1491 	case BGE_NVTYPE_BUFFERED_FLASH:
1492 	default:
1493 		break;
1494 	}
1495 
1496 	/*
1497 	 * Our own request should be present (whether or not granted) ...
1498 	 */
1499 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1500 
1501 	/*
1502 	 * ... this will make it go away.
1503 	 */
1504 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_RESET_REQ);
1505 	(void) bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1506 }
1507 
1508 /*
1509  * Arbitrate for access to the NVmem, if necessary
1510  *
1511  * Return value:
1512  *	0 on success
1513  *	EAGAIN if the device is in use (retryable)
1514  *	ENODEV if the NVmem device is missing or otherwise unusable
1515  */
1516 static int bge_nvmem_acquire(bge_t *bgep);
1517 #pragma	no_inline(bge_nvmem_acquire)
1518 
1519 static int
1520 bge_nvmem_acquire(bge_t *bgep)
1521 {
1522 	uint32_t regval;
1523 	uint32_t tries;
1524 
1525 	ASSERT(mutex_owned(bgep->genlock));
1526 
1527 	switch (bgep->chipid.nvtype) {
1528 	case BGE_NVTYPE_NONE:
1529 	case BGE_NVTYPE_UNKNOWN:
1530 		/*
1531 		 * Access denied: no (recognisable) device fitted
1532 		 */
1533 		return (ENODEV);
1534 
1535 	case BGE_NVTYPE_SEEPROM:
1536 		/*
1537 		 * Access granted: no arbitration needed (or possible)
1538 		 */
1539 		return (0);
1540 
1541 	case BGE_NVTYPE_LEGACY_SEEPROM:
1542 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1543 	case BGE_NVTYPE_BUFFERED_FLASH:
1544 	default:
1545 		/*
1546 		 * Access conditional: conduct arbitration protocol
1547 		 */
1548 		break;
1549 	}
1550 
1551 	/*
1552 	 * We're holding the per-port mutex <genlock>, so no-one other
1553 	 * thread can be attempting to access the NVmem through *this*
1554 	 * port. But it could be in use by the *other* port (of a 5704),
1555 	 * or by the chip's internal firmware, so we have to go through
1556 	 * the full (hardware) arbitration protocol ...
1557 	 *
1558 	 * Note that *because* we're holding <genlock>, the interrupt handler
1559 	 * won't be able to progress.  So we're only willing to spin for a
1560 	 * fairly short time.  Specifically:
1561 	 *
1562 	 *	We *must* wait long enough for the hardware to resolve all
1563 	 *	requests and determine the winner.  Fortunately, this is
1564 	 *	"almost instantaneous", even as observed by GHz CPUs.
1565 	 *
1566 	 *	A successful access by another Solaris thread (via either
1567 	 *	port) typically takes ~20us.  So waiting a bit longer than
1568 	 *	that will give a good chance of success, if the other user
1569 	 *	*is* another thread on the other port.
1570 	 *
1571 	 *	However, the internal firmware can hold on to the NVmem
1572 	 *	for *much* longer: at least 10 milliseconds just after a
1573 	 *	RESET, and maybe even longer if the NVmem actually contains
1574 	 *	code to download and run on the internal CPUs.
1575 	 *
1576 	 * So, we'll allow 50us; if that's not enough then it's up to the
1577 	 * caller to retry later (hence the choice of return code EAGAIN).
1578 	 */
1579 	regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1580 	bge_reg_put32(bgep, NVM_SW_ARBITRATION_REG, NVM_SET_REQ);
1581 
1582 	for (tries = 0; tries < 50; ++tries) {
1583 		regval = bge_reg_get32(bgep, NVM_SW_ARBITRATION_REG);
1584 		if (regval & NVM_WON_REQ1)
1585 			break;
1586 		drv_usecwait(1);
1587 	}
1588 
1589 	if (regval & NVM_WON_REQ1) {
1590 		BGE_DEBUG(("bge_nvmem_acquire: won after %d us", tries));
1591 		return (0);
1592 	}
1593 
1594 	/*
1595 	 * Somebody else must be accessing the NVmem, so abandon our
1596 	 * attempt take control of it.  The caller can try again later ...
1597 	 */
1598 	BGE_DEBUG(("bge_nvmem_acquire: lost after %d us", tries));
1599 	bge_nvmem_relinquish(bgep);
1600 	return (EAGAIN);
1601 }
1602 
1603 /*
1604  * This code assumes that the GPIO1 bit has been wired up to the NVmem
1605  * write protect line in such a way that the NVmem is protected when
1606  * GPIO1 is an input, or is an output but driven high.  Thus, to make the
1607  * NVmem writable we have to change GPIO1 to an output AND drive it low.
1608  *
1609  * Note: there's only one set of GPIO pins on a 5704, even though they
1610  * can be accessed through either port.  So the chip has to resolve what
1611  * happens if the two ports program a single pin differently ... the rule
1612  * it uses is that if the ports disagree about the *direction* of a pin,
1613  * "output" wins over "input", but if they disagree about its *value* as
1614  * an output, then the pin is TRISTATED instead!  In such a case, no-one
1615  * wins, and the external signal does whatever the external circuitry
1616  * defines as the default -- which we've assumed is the PROTECTED state.
1617  * So, we always change GPIO1 back to being an *input* whenever we're not
1618  * specifically using it to unprotect the NVmem. This allows either port
1619  * to update the NVmem, although obviously only one at a time!
1620  *
1621  * The caller should hold <genlock> and *also* have already acquired the
1622  * right to access the NVmem, via bge_nvmem_acquire() above.
1623  */
1624 static void bge_nvmem_protect(bge_t *bgep, boolean_t protect);
1625 #pragma	inline(bge_nvmem_protect)
1626 
1627 static void
1628 bge_nvmem_protect(bge_t *bgep, boolean_t protect)
1629 {
1630 	uint32_t regval;
1631 
1632 	ASSERT(mutex_owned(bgep->genlock));
1633 
1634 	regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
1635 	if (protect) {
1636 		regval |= MLCR_MISC_PINS_OUTPUT_1;
1637 		regval &= ~MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1638 	} else {
1639 		regval &= ~MLCR_MISC_PINS_OUTPUT_1;
1640 		regval |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
1641 	}
1642 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG, regval);
1643 }
1644 
1645 /*
1646  * Now put it all together ...
1647  *
1648  * Try to acquire control of the NVmem; if successful, then:
1649  *	unprotect it (if we want to write to it)
1650  *	perform the requested access
1651  *	reprotect it (after a write)
1652  *	relinquish control
1653  *
1654  * Return value:
1655  *	0 on success,
1656  *	EAGAIN if the device is in use (retryable)
1657  *	ENODATA on access timeout (maybe retryable: device may just be busy)
1658  *	ENODEV if the NVmem device is missing or otherwise unusable
1659  *	EPROTO on other h/w or s/w errors.
1660  */
1661 static int
1662 bge_nvmem_rw32(bge_t *bgep, uint32_t cmd, bge_regno_t addr, uint32_t *dp)
1663 {
1664 	int err;
1665 
1666 	if ((err = bge_nvmem_acquire(bgep)) == 0) {
1667 		switch (cmd) {
1668 		case BGE_SEE_READ:
1669 			err = bge_seeprom_access(bgep,
1670 			    SEEPROM_ACCESS_READ, addr, dp);
1671 			break;
1672 
1673 		case BGE_SEE_WRITE:
1674 			bge_nvmem_protect(bgep, B_FALSE);
1675 			err = bge_seeprom_access(bgep,
1676 			    SEEPROM_ACCESS_WRITE, addr, dp);
1677 			bge_nvmem_protect(bgep, B_TRUE);
1678 			break;
1679 
1680 		case BGE_FLASH_READ:
1681 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1682 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1683 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1684 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1685 				    NVM_ACCESS_ENABLE);
1686 			}
1687 			err = bge_flash_access(bgep,
1688 			    NVM_FLASH_CMD_RD, addr, dp);
1689 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1690 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1691 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1692 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1693 				    NVM_ACCESS_ENABLE);
1694 			}
1695 			break;
1696 
1697 		case BGE_FLASH_WRITE:
1698 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1699 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1700 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1701 				bge_reg_set32(bgep, NVM_ACCESS_REG,
1702 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1703 			}
1704 			bge_nvmem_protect(bgep, B_FALSE);
1705 			err = bge_flash_access(bgep,
1706 			    NVM_FLASH_CMD_WR, addr, dp);
1707 			bge_nvmem_protect(bgep, B_TRUE);
1708 			if (DEVICE_5721_SERIES_CHIPSETS(bgep) ||
1709 			    DEVICE_5723_SERIES_CHIPSETS(bgep) ||
1710 			    DEVICE_5714_SERIES_CHIPSETS(bgep)) {
1711 				bge_reg_clr32(bgep, NVM_ACCESS_REG,
1712 				    NVM_WRITE_ENABLE|NVM_ACCESS_ENABLE);
1713 			}
1714 
1715 			break;
1716 
1717 		default:
1718 			_NOTE(NOTREACHED)
1719 			break;
1720 		}
1721 		bge_nvmem_relinquish(bgep);
1722 	}
1723 
1724 	BGE_DEBUG(("bge_nvmem_rw32: err %d", err));
1725 	return (err);
1726 }
1727 
1728 /*
1729  * Attempt to get a MAC address from the SEEPROM or Flash, if any
1730  */
1731 static uint64_t bge_get_nvmac(bge_t *bgep);
1732 #pragma no_inline(bge_get_nvmac)
1733 
1734 static uint64_t
1735 bge_get_nvmac(bge_t *bgep)
1736 {
1737 	uint32_t mac_high;
1738 	uint32_t mac_low;
1739 	uint32_t addr;
1740 	uint32_t cmd;
1741 	uint64_t mac;
1742 
1743 	BGE_TRACE(("bge_get_nvmac($%p)",
1744 	    (void *)bgep));
1745 
1746 	switch (bgep->chipid.nvtype) {
1747 	case BGE_NVTYPE_NONE:
1748 	case BGE_NVTYPE_UNKNOWN:
1749 	default:
1750 		return (0ULL);
1751 
1752 	case BGE_NVTYPE_SEEPROM:
1753 	case BGE_NVTYPE_LEGACY_SEEPROM:
1754 		cmd = BGE_SEE_READ;
1755 		break;
1756 
1757 	case BGE_NVTYPE_UNBUFFERED_FLASH:
1758 	case BGE_NVTYPE_BUFFERED_FLASH:
1759 		cmd = BGE_FLASH_READ;
1760 		break;
1761 	}
1762 
1763 	if (DEVICE_5906_SERIES_CHIPSETS(bgep))
1764 		addr = NVMEM_DATA_MAC_ADDRESS_5906;
1765 	else
1766 		addr = NVMEM_DATA_MAC_ADDRESS;
1767 
1768 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_high))
1769 		return (0ULL);
1770 	addr += 4;
1771 	if (bge_nvmem_rw32(bgep, cmd, addr, &mac_low))
1772 		return (0ULL);
1773 
1774 	/*
1775 	 * The Broadcom chip is natively BIG-endian, so that's how the
1776 	 * MAC address is represented in NVmem.  We may need to swap it
1777 	 * around on a little-endian host ...
1778 	 */
1779 #ifdef	_BIG_ENDIAN
1780 	mac = mac_high;
1781 	mac = mac << 32;
1782 	mac |= mac_low;
1783 #else
1784 	mac = BGE_BSWAP_32(mac_high);
1785 	mac = mac << 32;
1786 	mac |= BGE_BSWAP_32(mac_low);
1787 #endif	/* _BIG_ENDIAN */
1788 
1789 	return (mac);
1790 }
1791 
1792 #else	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1793 
1794 /*
1795  * Dummy version for when we're not supporting NVmem access
1796  */
1797 static uint64_t bge_get_nvmac(bge_t *bgep);
1798 #pragma inline(bge_get_nvmac)
1799 
1800 static uint64_t
1801 bge_get_nvmac(bge_t *bgep)
1802 {
1803 	_NOTE(ARGUNUSED(bgep))
1804 	return (0ULL);
1805 }
1806 
1807 #endif	/* BGE_SEE_IO32 || BGE_FLASH_IO32 */
1808 
1809 /*
1810  * Determine the type of NVmem that is (or may be) attached to this chip,
1811  */
1812 static enum bge_nvmem_type bge_nvmem_id(bge_t *bgep);
1813 #pragma no_inline(bge_nvmem_id)
1814 
1815 static enum bge_nvmem_type
1816 bge_nvmem_id(bge_t *bgep)
1817 {
1818 	enum bge_nvmem_type nvtype;
1819 	uint32_t config1;
1820 
1821 	BGE_TRACE(("bge_nvmem_id($%p)",
1822 	    (void *)bgep));
1823 
1824 	switch (bgep->chipid.device) {
1825 	default:
1826 		/*
1827 		 * We shouldn't get here; it means we don't recognise
1828 		 * the chip, which means we don't know how to determine
1829 		 * what sort of NVmem (if any) it has.  So we'll say
1830 		 * NONE, to disable the NVmem access code ...
1831 		 */
1832 		nvtype = BGE_NVTYPE_NONE;
1833 		break;
1834 
1835 	case DEVICE_ID_5700:
1836 	case DEVICE_ID_5700x:
1837 	case DEVICE_ID_5701:
1838 		/*
1839 		 * These devices support *only* SEEPROMs
1840 		 */
1841 		nvtype = BGE_NVTYPE_SEEPROM;
1842 		break;
1843 
1844 	case DEVICE_ID_5702:
1845 	case DEVICE_ID_5702fe:
1846 	case DEVICE_ID_5703C:
1847 	case DEVICE_ID_5703S:
1848 	case DEVICE_ID_5704C:
1849 	case DEVICE_ID_5704S:
1850 	case DEVICE_ID_5704:
1851 	case DEVICE_ID_5705M:
1852 	case DEVICE_ID_5705C:
1853 	case DEVICE_ID_5705_2:
1854 	case DEVICE_ID_5780:
1855 	case DEVICE_ID_5782:
1856 	case DEVICE_ID_5785:
1857 	case DEVICE_ID_5787:
1858 	case DEVICE_ID_5787M:
1859 	case DEVICE_ID_5788:
1860 	case DEVICE_ID_5789:
1861 	case DEVICE_ID_5751:
1862 	case DEVICE_ID_5751M:
1863 	case DEVICE_ID_5752:
1864 	case DEVICE_ID_5752M:
1865 	case DEVICE_ID_5754:
1866 	case DEVICE_ID_5755:
1867 	case DEVICE_ID_5755M:
1868 	case DEVICE_ID_5756M:
1869 	case DEVICE_ID_5721:
1870 	case DEVICE_ID_5722:
1871 	case DEVICE_ID_5723:
1872 	case DEVICE_ID_5761:
1873 	case DEVICE_ID_5761E:
1874 	case DEVICE_ID_5764:
1875 	case DEVICE_ID_5714C:
1876 	case DEVICE_ID_5714S:
1877 	case DEVICE_ID_5715C:
1878 	case DEVICE_ID_5715S:
1879 		config1 = bge_reg_get32(bgep, NVM_CONFIG1_REG);
1880 		if (config1 & NVM_CFG1_FLASH_MODE)
1881 			if (config1 & NVM_CFG1_BUFFERED_MODE)
1882 				nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1883 			else
1884 				nvtype = BGE_NVTYPE_UNBUFFERED_FLASH;
1885 		else
1886 			nvtype = BGE_NVTYPE_LEGACY_SEEPROM;
1887 		break;
1888 	case DEVICE_ID_5906:
1889 	case DEVICE_ID_5906M:
1890 		nvtype = BGE_NVTYPE_BUFFERED_FLASH;
1891 		break;
1892 	}
1893 
1894 	return (nvtype);
1895 }
1896 
1897 #undef	BGE_DBG
1898 #define	BGE_DBG		BGE_DBG_CHIP	/* debug flag for this code	*/
1899 
1900 static void
1901 bge_init_recv_rule(bge_t *bgep)
1902 {
1903 	bge_recv_rule_t *rulep = bgep->recv_rules;
1904 	uint32_t i;
1905 
1906 	/*
1907 	 * Initialize receive rule registers.
1908 	 * Note that rules may persist across each bge_m_start/stop() call.
1909 	 */
1910 	for (i = 0; i < RECV_RULES_NUM_MAX; i++, rulep++) {
1911 		bge_reg_put32(bgep, RECV_RULE_MASK_REG(i), rulep->mask_value);
1912 		bge_reg_put32(bgep, RECV_RULE_CONTROL_REG(i), rulep->control);
1913 	}
1914 }
1915 
1916 /*
1917  * Using the values captured by bge_chip_cfg_init(), and additional probes
1918  * as required, characterise the chip fully: determine the label by which
1919  * to refer to this chip, the correct settings for various registers, and
1920  * of course whether the device and/or subsystem are supported!
1921  */
1922 int bge_chip_id_init(bge_t *bgep);
1923 #pragma	no_inline(bge_chip_id_init)
1924 
1925 int
1926 bge_chip_id_init(bge_t *bgep)
1927 {
1928 	char buf[MAXPATHLEN];		/* any risk of stack overflow?	*/
1929 	boolean_t sys_ok;
1930 	boolean_t dev_ok;
1931 	chip_id_t *cidp;
1932 	uint32_t subid;
1933 	char *devname;
1934 	char *sysname;
1935 	int *ids;
1936 	int err;
1937 	uint_t i;
1938 
1939 	sys_ok = dev_ok = B_FALSE;
1940 	cidp = &bgep->chipid;
1941 
1942 	/*
1943 	 * Check the PCI device ID to determine the generic chip type and
1944 	 * select parameters that depend on this.
1945 	 *
1946 	 * Note: because the SPARC platforms in general don't fit the
1947 	 * SEEPROM 'behind' the chip, the PCI revision ID register reads
1948 	 * as zero - which is why we use <asic_rev> rather than <revision>
1949 	 * below ...
1950 	 *
1951 	 * Note: in general we can't distinguish between the Copper/SerDes
1952 	 * versions by ID alone, as some Copper devices (e.g. some but not
1953 	 * all 5703Cs) have the same ID as the SerDes equivalents.  So we
1954 	 * treat them the same here, and the MII code works out the media
1955 	 * type later on ...
1956 	 */
1957 	cidp->mbuf_base = bge_mbuf_pool_base;
1958 	cidp->mbuf_length = bge_mbuf_pool_len;
1959 	cidp->recv_slots = BGE_RECV_SLOTS_USED;
1960 	cidp->bge_dma_rwctrl = bge_dma_rwctrl;
1961 	cidp->pci_type = BGE_PCI_X;
1962 	cidp->statistic_type = BGE_STAT_BLK;
1963 	cidp->mbuf_lo_water_rdma = bge_mbuf_lo_water_rdma;
1964 	cidp->mbuf_lo_water_rmac = bge_mbuf_lo_water_rmac;
1965 	cidp->mbuf_hi_water = bge_mbuf_hi_water;
1966 	cidp->rx_ticks_norm = bge_rx_ticks_norm;
1967 	cidp->rx_count_norm = bge_rx_count_norm;
1968 	cidp->tx_ticks_norm = bge_tx_ticks_norm;
1969 	cidp->tx_count_norm = bge_tx_count_norm;
1970 
1971 	if (cidp->rx_rings == 0 || cidp->rx_rings > BGE_RECV_RINGS_MAX)
1972 		cidp->rx_rings = BGE_RECV_RINGS_DEFAULT;
1973 	if (cidp->tx_rings == 0 || cidp->tx_rings > BGE_SEND_RINGS_MAX)
1974 		cidp->tx_rings = BGE_SEND_RINGS_DEFAULT;
1975 
1976 	cidp->msi_enabled = B_FALSE;
1977 
1978 	switch (cidp->device) {
1979 	case DEVICE_ID_5700:
1980 	case DEVICE_ID_5700x:
1981 		cidp->chip_label = 5700;
1982 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1983 		break;
1984 
1985 	case DEVICE_ID_5701:
1986 		cidp->chip_label = 5701;
1987 		dev_ok = B_TRUE;
1988 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1989 		break;
1990 
1991 	case DEVICE_ID_5702:
1992 	case DEVICE_ID_5702fe:
1993 		cidp->chip_label = 5702;
1994 		dev_ok = B_TRUE;
1995 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
1996 		cidp->pci_type = BGE_PCI;
1997 		break;
1998 
1999 	case DEVICE_ID_5703C:
2000 	case DEVICE_ID_5703S:
2001 	case DEVICE_ID_5703:
2002 		/*
2003 		 * Revision A0 of the 5703/5793 had various errata
2004 		 * that we can't or don't work around, so it's not
2005 		 * supported, but all later versions are
2006 		 */
2007 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5793 : 5703;
2008 		if (bgep->chipid.asic_rev != MHCR_CHIP_REV_5703_A0)
2009 			dev_ok = B_TRUE;
2010 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2011 		break;
2012 
2013 	case DEVICE_ID_5704C:
2014 	case DEVICE_ID_5704S:
2015 	case DEVICE_ID_5704:
2016 		cidp->chip_label = cidp->subven == VENDOR_ID_SUN ? 5794 : 5704;
2017 		cidp->mbuf_base = bge_mbuf_pool_base_5704;
2018 		cidp->mbuf_length = bge_mbuf_pool_len_5704;
2019 		dev_ok = B_TRUE;
2020 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2021 		break;
2022 
2023 	case DEVICE_ID_5705C:
2024 	case DEVICE_ID_5705M:
2025 	case DEVICE_ID_5705MA3:
2026 	case DEVICE_ID_5705F:
2027 	case DEVICE_ID_5705_2:
2028 	case DEVICE_ID_5754:
2029 		if (cidp->device == DEVICE_ID_5754) {
2030 			cidp->chip_label = 5754;
2031 			cidp->pci_type = BGE_PCI_E;
2032 		} else {
2033 			cidp->chip_label = 5705;
2034 			cidp->pci_type = BGE_PCI;
2035 			cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2036 		}
2037 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2038 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2039 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2040 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2041 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2042 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2043 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2044 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2045 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2046 		cidp->statistic_type = BGE_STAT_REG;
2047 		dev_ok = B_TRUE;
2048 		break;
2049 
2050 	case DEVICE_ID_5906:
2051 	case DEVICE_ID_5906M:
2052 		cidp->chip_label = 5906;
2053 		cidp->pci_type = BGE_PCI_E;
2054 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5906;
2055 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5906;
2056 		cidp->mbuf_hi_water = MBUF_HIWAT_5906;
2057 		cidp->mbuf_base = bge_mbuf_pool_base;
2058 		cidp->mbuf_length = bge_mbuf_pool_len;
2059 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2060 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2061 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2062 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2063 		cidp->statistic_type = BGE_STAT_REG;
2064 		dev_ok = B_TRUE;
2065 		break;
2066 
2067 	case DEVICE_ID_5753:
2068 		cidp->chip_label = 5753;
2069 		cidp->pci_type = BGE_PCI_E;
2070 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2071 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2072 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2073 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2074 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2075 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2076 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2077 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2078 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2079 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2080 		cidp->statistic_type = BGE_STAT_REG;
2081 		dev_ok = B_TRUE;
2082 		break;
2083 
2084 	case DEVICE_ID_5755:
2085 	case DEVICE_ID_5755M:
2086 		cidp->chip_label = 5755;
2087 		cidp->pci_type = BGE_PCI_E;
2088 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2089 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2090 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2091 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2092 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2093 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2094 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2095 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2096 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2097 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2098 		if (cidp->device == DEVICE_ID_5755M)
2099 			cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2100 		cidp->statistic_type = BGE_STAT_REG;
2101 		dev_ok = B_TRUE;
2102 		break;
2103 
2104 	case DEVICE_ID_5756M:
2105 		/*
2106 		 * This is nearly identical to the 5755M.
2107 		 * (Actually reports the 5755 chip ID.)
2108 		 */
2109 		cidp->chip_label = 5756;
2110 		cidp->pci_type = BGE_PCI_E;
2111 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2112 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2113 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2114 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2115 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2116 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2117 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2118 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2119 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2120 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2121 		cidp->statistic_type = BGE_STAT_REG;
2122 		dev_ok = B_TRUE;
2123 		break;
2124 
2125 	case DEVICE_ID_5787:
2126 	case DEVICE_ID_5787M:
2127 		cidp->chip_label = 5787;
2128 		cidp->pci_type = BGE_PCI_E;
2129 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2130 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2131 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2132 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2133 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2134 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2135 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2136 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2137 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2138 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2139 		cidp->statistic_type = BGE_STAT_REG;
2140 		dev_ok = B_TRUE;
2141 		break;
2142 
2143 	case DEVICE_ID_5723:
2144 	case DEVICE_ID_5761:
2145 	case DEVICE_ID_5761E:
2146 		cidp->msi_enabled = bge_enable_msi;
2147 		/*
2148 		 * We don't use MSI for BCM5764 and BCM5785, as the
2149 		 * status block may fail to update when the network
2150 		 * traffic is heavy.
2151 		 */
2152 		/* FALLTHRU */
2153 	case DEVICE_ID_5785:
2154 	case DEVICE_ID_5764:
2155 		if (cidp->device == DEVICE_ID_5723)
2156 			cidp->chip_label = 5723;
2157 		else if (cidp->device == DEVICE_ID_5764)
2158 			cidp->chip_label = 5764;
2159 		else if (cidp->device == DEVICE_ID_5785)
2160 			cidp->chip_label = 5785;
2161 		else
2162 			cidp->chip_label = 5761;
2163 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2164 		cidp->pci_type = BGE_PCI_E;
2165 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2166 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2167 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2168 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2169 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2170 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2171 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2172 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2173 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2174 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2175 		cidp->statistic_type = BGE_STAT_REG;
2176 		dev_ok = B_TRUE;
2177 		break;
2178 
2179 	/* PCI-X device, identical to 5714 */
2180 	case DEVICE_ID_5780:
2181 		cidp->chip_label = 5780;
2182 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2183 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2184 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2185 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2186 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2187 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2188 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2189 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2190 		cidp->statistic_type = BGE_STAT_REG;
2191 		dev_ok = B_TRUE;
2192 		break;
2193 
2194 	case DEVICE_ID_5782:
2195 		/*
2196 		 * Apart from the label, we treat this as a 5705(?)
2197 		 */
2198 		cidp->chip_label = 5782;
2199 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2200 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2201 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2202 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2203 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2204 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2205 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2206 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2207 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2208 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2209 		cidp->statistic_type = BGE_STAT_REG;
2210 		dev_ok = B_TRUE;
2211 		break;
2212 
2213 	case DEVICE_ID_5788:
2214 		/*
2215 		 * Apart from the label, we treat this as a 5705(?)
2216 		 */
2217 		cidp->chip_label = 5788;
2218 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2219 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2220 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2221 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2222 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2223 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2224 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2225 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2226 		cidp->statistic_type = BGE_STAT_REG;
2227 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2228 		dev_ok = B_TRUE;
2229 		break;
2230 
2231 	case DEVICE_ID_5714C:
2232 		if (cidp->revision >= REVISION_ID_5714_A2)
2233 			cidp->msi_enabled = bge_enable_msi;
2234 		/* FALLTHRU */
2235 	case DEVICE_ID_5714S:
2236 		cidp->chip_label = 5714;
2237 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2238 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2239 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2240 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2241 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2242 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2243 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5714;
2244 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2245 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2246 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2247 		cidp->pci_type = BGE_PCI_E;
2248 		cidp->statistic_type = BGE_STAT_REG;
2249 		dev_ok = B_TRUE;
2250 		break;
2251 
2252 	case DEVICE_ID_5715C:
2253 	case DEVICE_ID_5715S:
2254 		cidp->chip_label = 5715;
2255 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2256 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2257 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2258 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2259 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2260 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2261 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5715;
2262 		cidp->bge_mlcr_default = bge_mlcr_default_5714;
2263 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2264 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2265 		cidp->pci_type = BGE_PCI_E;
2266 		cidp->statistic_type = BGE_STAT_REG;
2267 		if (cidp->revision >= REVISION_ID_5715_A2)
2268 			cidp->msi_enabled = bge_enable_msi;
2269 		dev_ok = B_TRUE;
2270 		break;
2271 
2272 	case DEVICE_ID_5721:
2273 		cidp->chip_label = 5721;
2274 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2275 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2276 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2277 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2278 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2279 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2280 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2281 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2282 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2283 		cidp->pci_type = BGE_PCI_E;
2284 		cidp->statistic_type = BGE_STAT_REG;
2285 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2286 		dev_ok = B_TRUE;
2287 		break;
2288 
2289 	case DEVICE_ID_5722:
2290 		cidp->chip_label = 5722;
2291 		cidp->pci_type = BGE_PCI_E;
2292 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2293 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2294 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2295 		cidp->mbuf_base = bge_mbuf_pool_base_5705;
2296 		cidp->mbuf_length = bge_mbuf_pool_len_5705;
2297 		cidp->recv_slots = BGE_RECV_SLOTS_5705;
2298 		cidp->bge_mlcr_default |= MLCR_MISC_PINS_OUTPUT_ENABLE_1;
2299 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2300 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2301 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2302 		cidp->statistic_type = BGE_STAT_REG;
2303 		dev_ok = B_TRUE;
2304 		break;
2305 
2306 	case DEVICE_ID_5751:
2307 	case DEVICE_ID_5751M:
2308 		cidp->chip_label = 5751;
2309 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2310 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2311 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2312 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2313 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2314 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2315 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2316 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2317 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2318 		cidp->pci_type = BGE_PCI_E;
2319 		cidp->statistic_type = BGE_STAT_REG;
2320 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2321 		dev_ok = B_TRUE;
2322 		break;
2323 
2324 	case DEVICE_ID_5752:
2325 	case DEVICE_ID_5752M:
2326 		cidp->chip_label = 5752;
2327 		cidp->mbuf_lo_water_rdma = RDMA_MBUF_LOWAT_5705;
2328 		cidp->mbuf_lo_water_rmac = MAC_RX_MBUF_LOWAT_5705;
2329 		cidp->mbuf_hi_water = MBUF_HIWAT_5705;
2330 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2331 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2332 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2333 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2334 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2335 		cidp->tx_rings = BGE_SEND_RINGS_MAX_5705;
2336 		cidp->pci_type = BGE_PCI_E;
2337 		cidp->statistic_type = BGE_STAT_REG;
2338 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2339 		dev_ok = B_TRUE;
2340 		break;
2341 
2342 	case DEVICE_ID_5789:
2343 		cidp->chip_label = 5789;
2344 		cidp->mbuf_base = bge_mbuf_pool_base_5721;
2345 		cidp->mbuf_length = bge_mbuf_pool_len_5721;
2346 		cidp->recv_slots = BGE_RECV_SLOTS_5721;
2347 		cidp->bge_dma_rwctrl = bge_dma_rwctrl_5721;
2348 		cidp->rx_rings = BGE_RECV_RINGS_MAX_5705;
2349 		cidp->tx_rings = BGE_RECV_RINGS_MAX_5705;
2350 		cidp->pci_type = BGE_PCI_E;
2351 		cidp->statistic_type = BGE_STAT_REG;
2352 		cidp->flags |= CHIP_FLAG_PARTIAL_CSUM;
2353 		cidp->flags |= CHIP_FLAG_NO_JUMBO;
2354 		cidp->msi_enabled = B_TRUE;
2355 		dev_ok = B_TRUE;
2356 		break;
2357 
2358 	}
2359 
2360 	/*
2361 	 * Setup the default jumbo parameter.
2362 	 */
2363 	cidp->ethmax_size = ETHERMAX;
2364 	cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_DEFAULT;
2365 	cidp->std_buf_size = BGE_STD_BUFF_SIZE;
2366 
2367 	/*
2368 	 * If jumbo is enabled and this kind of chipset supports jumbo feature,
2369 	 * setup below jumbo specific parameters.
2370 	 *
2371 	 * For BCM5714/5715, there is only one standard receive ring. So the
2372 	 * std buffer size should be set to BGE_JUMBO_BUFF_SIZE when jumbo
2373 	 * feature is enabled.
2374 	 */
2375 	if (!(cidp->flags & CHIP_FLAG_NO_JUMBO) &&
2376 	    (cidp->default_mtu > BGE_DEFAULT_MTU)) {
2377 		if (DEVICE_5714_SERIES_CHIPSETS(bgep)) {
2378 			cidp->mbuf_lo_water_rdma =
2379 			    RDMA_MBUF_LOWAT_5714_JUMBO;
2380 			cidp->mbuf_lo_water_rmac =
2381 			    MAC_RX_MBUF_LOWAT_5714_JUMBO;
2382 			cidp->mbuf_hi_water = MBUF_HIWAT_5714_JUMBO;
2383 			cidp->jumbo_slots = 0;
2384 			cidp->std_buf_size = BGE_JUMBO_BUFF_SIZE;
2385 		} else {
2386 			cidp->mbuf_lo_water_rdma =
2387 			    RDMA_MBUF_LOWAT_JUMBO;
2388 			cidp->mbuf_lo_water_rmac =
2389 			    MAC_RX_MBUF_LOWAT_JUMBO;
2390 			cidp->mbuf_hi_water = MBUF_HIWAT_JUMBO;
2391 			cidp->jumbo_slots = BGE_JUMBO_SLOTS_USED;
2392 		}
2393 		cidp->recv_jumbo_size = BGE_JUMBO_BUFF_SIZE;
2394 		cidp->snd_buff_size = BGE_SEND_BUFF_SIZE_JUMBO;
2395 		cidp->ethmax_size = cidp->default_mtu +
2396 		    sizeof (struct ether_header);
2397 	}
2398 
2399 	/*
2400 	 * Identify the NV memory type: SEEPROM or Flash?
2401 	 */
2402 	cidp->nvtype = bge_nvmem_id(bgep);
2403 
2404 	/*
2405 	 * Now, we want to check whether this device is part of a
2406 	 * supported subsystem (e.g., on the motherboard of a Sun
2407 	 * branded platform).
2408 	 *
2409 	 * Rule 1: If the Subsystem Vendor ID is "Sun", then it's OK ;-)
2410 	 */
2411 	if (cidp->subven == VENDOR_ID_SUN)
2412 		sys_ok = B_TRUE;
2413 
2414 	/*
2415 	 * Rule 2: If it's on the list on known subsystems, then it's OK.
2416 	 * Note: 0x14e41647 should *not* appear in the list, but the code
2417 	 * doesn't enforce that.
2418 	 */
2419 	err = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, bgep->devinfo,
2420 	    DDI_PROP_DONTPASS, knownids_propname, &ids, &i);
2421 	if (err == DDI_PROP_SUCCESS) {
2422 		/*
2423 		 * Got the list; scan for a matching subsystem vendor/device
2424 		 */
2425 		subid = (cidp->subven << 16) | cidp->subdev;
2426 		while (i--)
2427 			if (ids[i] == subid)
2428 				sys_ok = B_TRUE;
2429 		ddi_prop_free(ids);
2430 	}
2431 
2432 	/*
2433 	 * Rule 3: If it's a Taco/ENWS motherboard device, then it's OK
2434 	 *
2435 	 * Unfortunately, early SunBlade 1500s and 2500s didn't reprogram
2436 	 * the Subsystem Vendor ID, so it defaults to Broadcom.  Therefore,
2437 	 * we have to check specially for the exact device paths to the
2438 	 * motherboard devices on those platforms ;-(
2439 	 *
2440 	 * Note: we can't just use the "supported-subsystems" mechanism
2441 	 * above, because the entry would have to be 0x14e41647 -- which
2442 	 * would then accept *any* plugin card that *didn't* contain a
2443 	 * (valid) SEEPROM ;-(
2444 	 */
2445 	sysname = ddi_node_name(ddi_root_node());
2446 	devname = ddi_pathname(bgep->devinfo, buf);
2447 	ASSERT(strlen(devname) > 0);
2448 	if (strcmp(sysname, "SUNW,Sun-Blade-1500") == 0)	/* Taco */
2449 		if (strcmp(devname, "/pci@1f,700000/network@2") == 0)
2450 			sys_ok = B_TRUE;
2451 	if (strcmp(sysname, "SUNW,Sun-Blade-2500") == 0)	/* ENWS */
2452 		if (strcmp(devname, "/pci@1c,600000/network@3") == 0)
2453 			sys_ok = B_TRUE;
2454 
2455 	/*
2456 	 * Now check what we've discovered: is this truly a supported
2457 	 * chip on (the motherboard of) a supported platform?
2458 	 *
2459 	 * Possible problems here:
2460 	 * 1)	it's a completely unheard-of chip
2461 	 * 2)	it's a recognised but unsupported chip (e.g. 5701, 5703C-A0)
2462 	 * 3)	it's a chip we would support if it were on the motherboard
2463 	 *	of a Sun platform, but this one isn't ;-(
2464 	 */
2465 	if (cidp->chip_label == 0)
2466 		bge_problem(bgep,
2467 		    "Device 'pci%04x,%04x' not recognized (%d?)",
2468 		    cidp->vendor, cidp->device, cidp->device);
2469 	else if (!dev_ok)
2470 		bge_problem(bgep,
2471 		    "Device 'pci%04x,%04x' (%d) revision %d not supported",
2472 		    cidp->vendor, cidp->device, cidp->chip_label,
2473 		    cidp->revision);
2474 #if	BGE_DEBUGGING
2475 	else if (!sys_ok)
2476 		bge_problem(bgep,
2477 		    "%d-based subsystem 'pci%04x,%04x' not validated",
2478 		    cidp->chip_label, cidp->subven, cidp->subdev);
2479 #endif
2480 	else
2481 		cidp->flags |= CHIP_FLAG_SUPPORTED;
2482 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
2483 		return (EIO);
2484 	return (0);
2485 }
2486 
2487 void
2488 bge_chip_msi_trig(bge_t *bgep)
2489 {
2490 	uint32_t	regval;
2491 
2492 	regval = bgep->param_msi_cnt<<4;
2493 	bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, regval);
2494 	BGE_DEBUG(("bge_chip_msi_trig:data = %d", regval));
2495 }
2496 
2497 /*
2498  * Various registers that control the chip's internal engines (state
2499  * machines) have a <reset> and <enable> bits (fortunately, in the
2500  * same place in each such register :-).
2501  *
2502  * To reset the state machine, the <reset> bit must be written with 1;
2503  * it will then read back as 1 while the reset is in progress, but
2504  * self-clear to 0 when the reset completes.
2505  *
2506  * To enable a state machine, one must set the <enable> bit, which
2507  * will continue to read back as 0 until the state machine is running.
2508  *
2509  * To disable a state machine, the <enable> bit must be cleared, but
2510  * it will continue to read back as 1 until the state machine actually
2511  * stops.
2512  *
2513  * This routine implements polling for completion of a reset, enable
2514  * or disable operation, returning B_TRUE on success (bit reached the
2515  * required state) or B_FALSE on timeout (200*100us == 20ms).
2516  */
2517 static boolean_t bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2518 					uint32_t mask, uint32_t val);
2519 #pragma	no_inline(bge_chip_poll_engine)
2520 
2521 static boolean_t
2522 bge_chip_poll_engine(bge_t *bgep, bge_regno_t regno,
2523 	uint32_t mask, uint32_t val)
2524 {
2525 	uint32_t regval;
2526 	uint32_t n;
2527 
2528 	BGE_TRACE(("bge_chip_poll_engine($%p, 0x%lx, 0x%x, 0x%x)",
2529 	    (void *)bgep, regno, mask, val));
2530 
2531 	for (n = 200; n; --n) {
2532 		regval = bge_reg_get32(bgep, regno);
2533 		if ((regval & mask) == val)
2534 			return (B_TRUE);
2535 		drv_usecwait(100);
2536 	}
2537 
2538 	bge_fm_ereport(bgep, DDI_FM_DEVICE_NO_RESPONSE);
2539 	return (B_FALSE);
2540 }
2541 
2542 /*
2543  * Various registers that control the chip's internal engines (state
2544  * machines) have a <reset> bit (fortunately, in the same place in
2545  * each such register :-).  To reset the state machine, this bit must
2546  * be written with 1; it will then read back as 1 while the reset is
2547  * in progress, but self-clear to 0 when the reset completes.
2548  *
2549  * This code sets the bit, then polls for it to read back as zero.
2550  * The return value is B_TRUE on success (reset bit cleared itself),
2551  * or B_FALSE if the state machine didn't recover :(
2552  *
2553  * NOTE: the Core reset is similar to other resets, except that we
2554  * can't poll for completion, since the Core reset disables memory
2555  * access!  So we just have to assume that it will all complete in
2556  * 100us.  See Broadcom document 570X-PG102-R, p102, steps 4-5.
2557  */
2558 static boolean_t bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno);
2559 #pragma	no_inline(bge_chip_reset_engine)
2560 
2561 static boolean_t
2562 bge_chip_reset_engine(bge_t *bgep, bge_regno_t regno)
2563 {
2564 	uint32_t regval;
2565 	uint32_t val32;
2566 
2567 	regval = bge_reg_get32(bgep, regno);
2568 
2569 	BGE_TRACE(("bge_chip_reset_engine($%p, 0x%lx)",
2570 	    (void *)bgep, regno));
2571 	BGE_DEBUG(("bge_chip_reset_engine: 0x%lx before reset = 0x%08x",
2572 	    regno, regval));
2573 
2574 	regval |= STATE_MACHINE_RESET_BIT;
2575 
2576 	switch (regno) {
2577 	case MISC_CONFIG_REG:
2578 		/*
2579 		 * BCM5714/5721/5751 pcie chip special case. In order to avoid
2580 		 * resetting PCIE block and bringing PCIE link down, bit 29
2581 		 * in the register needs to be set first, and then set it again
2582 		 * while the reset bit is written.
2583 		 * See:P500 of 57xx-PG102-RDS.pdf.
2584 		 */
2585 		if (DEVICE_5705_SERIES_CHIPSETS(bgep)||
2586 		    DEVICE_5721_SERIES_CHIPSETS(bgep)||
2587 		    DEVICE_5723_SERIES_CHIPSETS(bgep)||
2588 		    DEVICE_5714_SERIES_CHIPSETS(bgep)||
2589 		    DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2590 			regval |= MISC_CONFIG_GPHY_POWERDOWN_OVERRIDE;
2591 			if (bgep->chipid.pci_type == BGE_PCI_E) {
2592 				if (bgep->chipid.asic_rev ==
2593 				    MHCR_CHIP_REV_5751_A0 ||
2594 				    bgep->chipid.asic_rev ==
2595 				    MHCR_CHIP_REV_5721_A0 ||
2596 				    bgep->chipid.asic_rev ==
2597 				    MHCR_CHIP_REV_5755_A0) {
2598 					val32 = bge_reg_get32(bgep,
2599 					    PHY_TEST_CTRL_REG);
2600 					if (val32 == (PHY_PCIE_SCRAM_MODE |
2601 					    PHY_PCIE_LTASS_MODE))
2602 						bge_reg_put32(bgep,
2603 						    PHY_TEST_CTRL_REG,
2604 						    PHY_PCIE_SCRAM_MODE);
2605 					val32 = pci_config_get32
2606 					    (bgep->cfg_handle,
2607 					    PCI_CONF_BGE_CLKCTL);
2608 					val32 |= CLKCTL_PCIE_A0_FIX;
2609 					pci_config_put32(bgep->cfg_handle,
2610 					    PCI_CONF_BGE_CLKCTL, val32);
2611 				}
2612 				bge_reg_set32(bgep, regno,
2613 				    MISC_CONFIG_GRC_RESET_DISABLE);
2614 				regval |= MISC_CONFIG_GRC_RESET_DISABLE;
2615 			}
2616 		}
2617 
2618 		/*
2619 		 * Special case - causes Core reset
2620 		 *
2621 		 * On SPARC v9 we want to ensure that we don't start
2622 		 * timing until the I/O access has actually reached
2623 		 * the chip, otherwise we might make the next access
2624 		 * too early.  And we can't just force the write out
2625 		 * by following it with a read (even to config space)
2626 		 * because that would cause the fault we're trying
2627 		 * to avoid.  Hence the need for membar_sync() here.
2628 		 */
2629 		ddi_put32(bgep->io_handle, PIO_ADDR(bgep, regno), regval);
2630 #ifdef	__sparcv9
2631 		membar_sync();
2632 #endif	/* __sparcv9 */
2633 		/*
2634 		 * On some platforms,system need about 300us for
2635 		 * link setup.
2636 		 */
2637 		drv_usecwait(300);
2638 		if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
2639 			bge_reg_set32(bgep, VCPU_STATUS_REG, VCPU_DRV_RESET);
2640 			bge_reg_clr32(
2641 			    bgep, VCPU_EXT_CTL, VCPU_EXT_CTL_HALF);
2642 		}
2643 
2644 		if (bgep->chipid.pci_type == BGE_PCI_E) {
2645 			/* PCI-E device need more reset time */
2646 			drv_usecwait(120000);
2647 
2648 			/* Set PCIE max payload size and clear error status. */
2649 			if ((bgep->chipid.chip_label == 5721) ||
2650 			    (bgep->chipid.chip_label == 5751) ||
2651 			    (bgep->chipid.chip_label == 5752) ||
2652 			    (bgep->chipid.chip_label == 5789) ||
2653 			    (bgep->chipid.chip_label == 5906)) {
2654 				pci_config_put16(bgep->cfg_handle,
2655 				    PCI_CONF_DEV_CTRL, READ_REQ_SIZE_MAX);
2656 				pci_config_put16(bgep->cfg_handle,
2657 				    PCI_CONF_DEV_STUS, DEVICE_ERROR_STUS);
2658 			}
2659 
2660 			if ((bgep->chipid.chip_label == 5723) ||
2661 			    (bgep->chipid.chip_label == 5761)) {
2662 				pci_config_put16(bgep->cfg_handle,
2663 				    PCI_CONF_DEV_CTRL_5723, READ_REQ_SIZE_MAX);
2664 				pci_config_put16(bgep->cfg_handle,
2665 				    PCI_CONF_DEV_STUS_5723, DEVICE_ERROR_STUS);
2666 			}
2667 		}
2668 
2669 		BGE_PCICHK(bgep);
2670 		return (B_TRUE);
2671 
2672 	default:
2673 		bge_reg_put32(bgep, regno, regval);
2674 		return (bge_chip_poll_engine(bgep, regno,
2675 		    STATE_MACHINE_RESET_BIT, 0));
2676 	}
2677 }
2678 
2679 /*
2680  * Various registers that control the chip's internal engines (state
2681  * machines) have an <enable> bit (fortunately, in the same place in
2682  * each such register :-).  To stop the state machine, this bit must
2683  * be written with 0, then polled to see when the state machine has
2684  * actually stopped.
2685  *
2686  * The return value is B_TRUE on success (enable bit cleared), or
2687  * B_FALSE if the state machine didn't stop :(
2688  */
2689 static boolean_t bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno,
2690 						uint32_t morebits);
2691 #pragma	no_inline(bge_chip_disable_engine)
2692 
2693 static boolean_t
2694 bge_chip_disable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2695 {
2696 	uint32_t regval;
2697 
2698 	BGE_TRACE(("bge_chip_disable_engine($%p, 0x%lx, 0x%x)",
2699 	    (void *)bgep, regno, morebits));
2700 
2701 	switch (regno) {
2702 	case FTQ_RESET_REG:
2703 		/*
2704 		 * For Schumacher's bugfix CR6490108
2705 		 */
2706 #ifdef BGE_IPMI_ASF
2707 #ifdef BGE_NETCONSOLE
2708 		if (bgep->asf_enabled)
2709 			return (B_TRUE);
2710 #endif
2711 #endif
2712 		/*
2713 		 * Not quite like the others; it doesn't
2714 		 * have an <enable> bit, but instead we
2715 		 * have to set and then clear all the bits
2716 		 */
2717 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2718 		drv_usecwait(100);
2719 		bge_reg_put32(bgep, regno, 0);
2720 		return (B_TRUE);
2721 
2722 	default:
2723 		regval = bge_reg_get32(bgep, regno);
2724 		regval &= ~STATE_MACHINE_ENABLE_BIT;
2725 		regval &= ~morebits;
2726 		bge_reg_put32(bgep, regno, regval);
2727 		return (bge_chip_poll_engine(bgep, regno,
2728 		    STATE_MACHINE_ENABLE_BIT, 0));
2729 	}
2730 }
2731 
2732 /*
2733  * Various registers that control the chip's internal engines (state
2734  * machines) have an <enable> bit (fortunately, in the same place in
2735  * each such register :-).  To start the state machine, this bit must
2736  * be written with 1, then polled to see when the state machine has
2737  * actually started.
2738  *
2739  * The return value is B_TRUE on success (enable bit set), or
2740  * B_FALSE if the state machine didn't start :(
2741  */
2742 static boolean_t bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno,
2743 					uint32_t morebits);
2744 #pragma	no_inline(bge_chip_enable_engine)
2745 
2746 static boolean_t
2747 bge_chip_enable_engine(bge_t *bgep, bge_regno_t regno, uint32_t morebits)
2748 {
2749 	uint32_t regval;
2750 
2751 	BGE_TRACE(("bge_chip_enable_engine($%p, 0x%lx, 0x%x)",
2752 	    (void *)bgep, regno, morebits));
2753 
2754 	switch (regno) {
2755 	case FTQ_RESET_REG:
2756 #ifdef BGE_IPMI_ASF
2757 #ifdef BGE_NETCONSOLE
2758 		if (bgep->asf_enabled)
2759 			return (B_TRUE);
2760 #endif
2761 #endif
2762 		/*
2763 		 * Not quite like the others; it doesn't
2764 		 * have an <enable> bit, but instead we
2765 		 * have to set and then clear all the bits
2766 		 */
2767 		bge_reg_put32(bgep, regno, ~(uint32_t)0);
2768 		drv_usecwait(100);
2769 		bge_reg_put32(bgep, regno, 0);
2770 		return (B_TRUE);
2771 
2772 	default:
2773 		regval = bge_reg_get32(bgep, regno);
2774 		regval |= STATE_MACHINE_ENABLE_BIT;
2775 		regval |= morebits;
2776 		bge_reg_put32(bgep, regno, regval);
2777 		return (bge_chip_poll_engine(bgep, regno,
2778 		    STATE_MACHINE_ENABLE_BIT, STATE_MACHINE_ENABLE_BIT));
2779 	}
2780 }
2781 
2782 /*
2783  * Reprogram the Ethernet, Transmit, and Receive MAC
2784  * modes to match the param_* variables
2785  */
2786 void bge_sync_mac_modes(bge_t *bgep);
2787 #pragma	no_inline(bge_sync_mac_modes)
2788 
2789 void
2790 bge_sync_mac_modes(bge_t *bgep)
2791 {
2792 	uint32_t macmode;
2793 	uint32_t regval;
2794 
2795 	ASSERT(mutex_owned(bgep->genlock));
2796 
2797 	/*
2798 	 * Reprogram the Ethernet MAC mode ...
2799 	 */
2800 	macmode = regval = bge_reg_get32(bgep, ETHERNET_MAC_MODE_REG);
2801 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2802 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC))
2803 		if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2804 			macmode |= ETHERNET_MODE_LINK_POLARITY;
2805 		else
2806 			macmode &= ~ETHERNET_MODE_LINK_POLARITY;
2807 	else
2808 		macmode |= ETHERNET_MODE_LINK_POLARITY;
2809 	macmode &= ~ETHERNET_MODE_PORTMODE_MASK;
2810 	if ((bgep->chipid.flags & CHIP_FLAG_SERDES) &&
2811 	    (bgep->param_loop_mode != BGE_LOOP_INTERNAL_MAC)) {
2812 		if (DEVICE_5714_SERIES_CHIPSETS(bgep))
2813 			macmode |= ETHERNET_MODE_PORTMODE_GMII;
2814 		else
2815 			macmode |= ETHERNET_MODE_PORTMODE_TBI;
2816 	} else if (bgep->param_link_speed == 10 ||
2817 	    bgep->param_link_speed == 100)
2818 		macmode |= ETHERNET_MODE_PORTMODE_MII;
2819 	else
2820 		macmode |= ETHERNET_MODE_PORTMODE_GMII;
2821 	if (bgep->param_link_duplex == LINK_DUPLEX_HALF)
2822 		macmode |= ETHERNET_MODE_HALF_DUPLEX;
2823 	else
2824 		macmode &= ~ETHERNET_MODE_HALF_DUPLEX;
2825 	if (bgep->param_loop_mode == BGE_LOOP_INTERNAL_MAC)
2826 		macmode |= ETHERNET_MODE_MAC_LOOPBACK;
2827 	else
2828 		macmode &= ~ETHERNET_MODE_MAC_LOOPBACK;
2829 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, macmode);
2830 	BGE_DEBUG(("bge_sync_mac_modes($%p) Ethernet MAC mode 0x%x => 0x%x",
2831 	    (void *)bgep, regval, macmode));
2832 
2833 	/*
2834 	 * ... the Transmit MAC mode ...
2835 	 */
2836 	macmode = regval = bge_reg_get32(bgep, TRANSMIT_MAC_MODE_REG);
2837 	if (bgep->param_link_tx_pause)
2838 		macmode |= TRANSMIT_MODE_FLOW_CONTROL;
2839 	else
2840 		macmode &= ~TRANSMIT_MODE_FLOW_CONTROL;
2841 	bge_reg_put32(bgep, TRANSMIT_MAC_MODE_REG, macmode);
2842 	BGE_DEBUG(("bge_sync_mac_modes($%p) Transmit MAC mode 0x%x => 0x%x",
2843 	    (void *)bgep, regval, macmode));
2844 
2845 	/*
2846 	 * ... and the Receive MAC mode
2847 	 */
2848 	macmode = regval = bge_reg_get32(bgep, RECEIVE_MAC_MODE_REG);
2849 	if (bgep->param_link_rx_pause)
2850 		macmode |= RECEIVE_MODE_FLOW_CONTROL;
2851 	else
2852 		macmode &= ~RECEIVE_MODE_FLOW_CONTROL;
2853 	bge_reg_put32(bgep, RECEIVE_MAC_MODE_REG, macmode);
2854 	BGE_DEBUG(("bge_sync_mac_modes($%p) Receive MAC mode 0x%x => 0x%x",
2855 	    (void *)bgep, regval, macmode));
2856 
2857 	/*
2858 	 * For BCM5785, we need to configure the link status in the MI Status
2859 	 * register with a write command when auto-polling is disabled.
2860 	 */
2861 	if (bgep->chipid.device == DEVICE_ID_5785)
2862 		if (bgep->param_link_speed == 10)
2863 			bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK
2864 			    | MI_STATUS_10MBPS);
2865 		else
2866 			bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
2867 }
2868 
2869 /*
2870  * bge_chip_sync() -- program the chip with the unicast MAC address,
2871  * the multicast hash table, the required level of promiscuity, and
2872  * the current loopback mode ...
2873  */
2874 #ifdef BGE_IPMI_ASF
2875 int bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive);
2876 #else
2877 int bge_chip_sync(bge_t *bgep);
2878 #endif
2879 #pragma	no_inline(bge_chip_sync)
2880 
2881 int
2882 #ifdef BGE_IPMI_ASF
2883 bge_chip_sync(bge_t *bgep, boolean_t asf_keeplive)
2884 #else
2885 bge_chip_sync(bge_t *bgep)
2886 #endif
2887 {
2888 	void (*opfn)(bge_t *bgep, bge_regno_t reg, uint32_t bits);
2889 	boolean_t promisc;
2890 	uint64_t macaddr;
2891 	uint32_t fill = 0;
2892 	int i, j;
2893 	int retval = DDI_SUCCESS;
2894 
2895 	BGE_TRACE(("bge_chip_sync($%p)",
2896 	    (void *)bgep));
2897 
2898 	ASSERT(mutex_owned(bgep->genlock));
2899 
2900 	promisc = B_FALSE;
2901 	fill = ~(uint32_t)0;
2902 
2903 	if (bgep->promisc)
2904 		promisc = B_TRUE;
2905 	else
2906 		fill = (uint32_t)0;
2907 
2908 	/*
2909 	 * If the TX/RX MAC engines are already running, we should stop
2910 	 * them (and reset the RX engine) before changing the parameters.
2911 	 * If they're not running, this will have no effect ...
2912 	 *
2913 	 * NOTE: this is currently disabled by default because stopping
2914 	 * and restarting the Tx engine may cause an outgoing packet in
2915 	 * transit to be truncated.  Also, stopping and restarting the
2916 	 * Rx engine seems to not work correctly on the 5705.  Testing
2917 	 * has not (yet!) revealed any problems with NOT stopping and
2918 	 * restarting these engines (and Broadcom say their drivers don't
2919 	 * do this), but if it is found to cause problems, this variable
2920 	 * can be patched to re-enable the old behaviour ...
2921 	 */
2922 	if (bge_stop_start_on_sync) {
2923 #ifdef BGE_IPMI_ASF
2924 		if (!bgep->asf_enabled) {
2925 			if (!bge_chip_disable_engine(bgep,
2926 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
2927 				retval = DDI_FAILURE;
2928 		} else {
2929 			if (!bge_chip_disable_engine(bgep,
2930 			    RECEIVE_MAC_MODE_REG, 0))
2931 				retval = DDI_FAILURE;
2932 		}
2933 #else
2934 		if (!bge_chip_disable_engine(bgep, RECEIVE_MAC_MODE_REG,
2935 		    RECEIVE_MODE_KEEP_VLAN_TAG))
2936 			retval = DDI_FAILURE;
2937 #endif
2938 		if (!bge_chip_disable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
2939 			retval = DDI_FAILURE;
2940 		if (!bge_chip_reset_engine(bgep, RECEIVE_MAC_MODE_REG))
2941 			retval = DDI_FAILURE;
2942 	}
2943 
2944 	/*
2945 	 * Reprogram the hashed multicast address table ...
2946 	 */
2947 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
2948 		bge_reg_put32(bgep, MAC_HASH_REG(i), 0);
2949 
2950 	for (i = 0; i < BGE_HASH_TABLE_SIZE/32; ++i)
2951 		bge_reg_put32(bgep, MAC_HASH_REG(i),
2952 			bgep->mcast_hash[i] | fill);
2953 
2954 #ifdef BGE_IPMI_ASF
2955 	if (!bgep->asf_enabled || !asf_keeplive) {
2956 #endif
2957 		/*
2958 		 * Transform the MAC address(es) from host to chip format, then
2959 		 * reprogram the transmit random backoff seed and the unicast
2960 		 * MAC address(es) ...
2961 		 */
2962 		for (j = 0; j < MAC_ADDRESS_REGS_MAX; j++) {
2963 			for (i = 0, macaddr = 0ull;
2964 			    i < ETHERADDRL; ++i) {
2965 				macaddr <<= 8;
2966 				macaddr |= bgep->curr_addr[j].addr[i];
2967 			}
2968 			fill += (macaddr >> 16) + (macaddr & 0xffffffff);
2969 			bge_reg_put64(bgep, MAC_ADDRESS_REG(j), macaddr);
2970 
2971 			BGE_DEBUG(("bge_chip_sync($%p) "
2972 			    "setting MAC address %012llx",
2973 			    (void *)bgep, macaddr));
2974 		}
2975 #ifdef BGE_IPMI_ASF
2976 	}
2977 #endif
2978 	/*
2979 	 * Set random seed of backoff interval
2980 	 *   - Writing zero means no backoff interval
2981 	 */
2982 	fill = ((fill >> 20) + (fill >> 10) + fill) & 0x3ff;
2983 	if (fill == 0)
2984 		fill = 1;
2985 	bge_reg_put32(bgep, MAC_TX_RANDOM_BACKOFF_REG, fill);
2986 
2987 	/*
2988 	 * Set or clear the PROMISCUOUS mode bit
2989 	 */
2990 	opfn = promisc ? bge_reg_set32 : bge_reg_clr32;
2991 	(*opfn)(bgep, RECEIVE_MAC_MODE_REG, RECEIVE_MODE_PROMISCUOUS);
2992 
2993 	/*
2994 	 * Sync the rest of the MAC modes too ...
2995 	 */
2996 	bge_sync_mac_modes(bgep);
2997 
2998 	/*
2999 	 * Restart RX/TX MAC engines if required ...
3000 	 */
3001 	if (bgep->bge_chip_state == BGE_CHIP_RUNNING) {
3002 		if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
3003 			retval = DDI_FAILURE;
3004 #ifdef BGE_IPMI_ASF
3005 		if (!bgep->asf_enabled) {
3006 			if (!bge_chip_enable_engine(bgep,
3007 			    RECEIVE_MAC_MODE_REG, RECEIVE_MODE_KEEP_VLAN_TAG))
3008 				retval = DDI_FAILURE;
3009 		} else {
3010 			if (!bge_chip_enable_engine(bgep,
3011 			    RECEIVE_MAC_MODE_REG, 0))
3012 				retval = DDI_FAILURE;
3013 		}
3014 #else
3015 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
3016 		    RECEIVE_MODE_KEEP_VLAN_TAG))
3017 			retval = DDI_FAILURE;
3018 #endif
3019 	}
3020 	return (retval);
3021 }
3022 
3023 /*
3024  * This array defines the sequence of state machine control registers
3025  * in which the <enable> bit must be cleared to bring the chip to a
3026  * clean stop.  Taken from Broadcom document 570X-PG102-R, p116.
3027  */
3028 static bge_regno_t shutdown_engine_regs[] = {
3029 	RECEIVE_MAC_MODE_REG,
3030 	RCV_BD_INITIATOR_MODE_REG,
3031 	RCV_LIST_PLACEMENT_MODE_REG,
3032 	RCV_LIST_SELECTOR_MODE_REG,		/* BCM5704 series only	*/
3033 	RCV_DATA_BD_INITIATOR_MODE_REG,
3034 	RCV_DATA_COMPLETION_MODE_REG,
3035 	RCV_BD_COMPLETION_MODE_REG,
3036 
3037 	SEND_BD_SELECTOR_MODE_REG,
3038 	SEND_BD_INITIATOR_MODE_REG,
3039 	SEND_DATA_INITIATOR_MODE_REG,
3040 	READ_DMA_MODE_REG,
3041 	SEND_DATA_COMPLETION_MODE_REG,
3042 	DMA_COMPLETION_MODE_REG,		/* BCM5704 series only	*/
3043 	SEND_BD_COMPLETION_MODE_REG,
3044 	TRANSMIT_MAC_MODE_REG,
3045 
3046 	HOST_COALESCE_MODE_REG,
3047 	WRITE_DMA_MODE_REG,
3048 	MBUF_CLUSTER_FREE_MODE_REG,		/* BCM5704 series only	*/
3049 	FTQ_RESET_REG,		/* special - see code	*/
3050 	BUFFER_MANAGER_MODE_REG,		/* BCM5704 series only	*/
3051 	MEMORY_ARBITER_MODE_REG,		/* BCM5704 series only	*/
3052 	BGE_REGNO_NONE		/* terminator		*/
3053 };
3054 
3055 #ifndef __sparc
3056 static bge_regno_t quiesce_regs[] = {
3057 	READ_DMA_MODE_REG,
3058 	DMA_COMPLETION_MODE_REG,
3059 	WRITE_DMA_MODE_REG,
3060 	BGE_REGNO_NONE
3061 };
3062 
3063 void bge_chip_stop_nonblocking(bge_t *bgep);
3064 #pragma no_inline(bge_chip_stop_nonblocking)
3065 
3066 /*
3067  * This function is called by bge_quiesce(). We
3068  * turn off all the DMA engines here.
3069  */
3070 void
3071 bge_chip_stop_nonblocking(bge_t *bgep)
3072 {
3073 	bge_regno_t *rbp;
3074 
3075 	/*
3076 	 * Flag that no more activity may be initiated
3077 	 */
3078 	bgep->progress &= ~PROGRESS_READY;
3079 
3080 	rbp = quiesce_regs;
3081 	while (*rbp != BGE_REGNO_NONE) {
3082 		(void) bge_chip_disable_engine(bgep, *rbp, 0);
3083 		++rbp;
3084 	}
3085 
3086 	bgep->bge_chip_state = BGE_CHIP_STOPPED;
3087 }
3088 
3089 #endif
3090 
3091 /*
3092  * bge_chip_stop() -- stop all chip processing
3093  *
3094  * If the <fault> parameter is B_TRUE, we're stopping the chip because
3095  * we've detected a problem internally; otherwise, this is a normal
3096  * (clean) stop (at user request i.e. the last STREAM has been closed).
3097  */
3098 void bge_chip_stop(bge_t *bgep, boolean_t fault);
3099 #pragma	no_inline(bge_chip_stop)
3100 
3101 void
3102 bge_chip_stop(bge_t *bgep, boolean_t fault)
3103 {
3104 	bge_regno_t regno;
3105 	bge_regno_t *rbp;
3106 	boolean_t ok;
3107 
3108 	BGE_TRACE(("bge_chip_stop($%p)",
3109 	    (void *)bgep));
3110 
3111 	ASSERT(mutex_owned(bgep->genlock));
3112 
3113 	rbp = shutdown_engine_regs;
3114 	/*
3115 	 * When driver try to shutdown the BCM5705/5788/5721/5751/
3116 	 * 5752/5714 and 5715 chipsets,the buffer manager and the mem
3117 	 * -ory arbiter should not be disabled.
3118 	 */
3119 	for (ok = B_TRUE; (regno = *rbp) != BGE_REGNO_NONE; ++rbp) {
3120 			if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3121 				ok &= bge_chip_disable_engine(bgep, regno, 0);
3122 			else if ((regno != RCV_LIST_SELECTOR_MODE_REG) &&
3123 			    (regno != DMA_COMPLETION_MODE_REG) &&
3124 			    (regno != MBUF_CLUSTER_FREE_MODE_REG)&&
3125 			    (regno != BUFFER_MANAGER_MODE_REG) &&
3126 			    (regno != MEMORY_ARBITER_MODE_REG))
3127 				ok &= bge_chip_disable_engine(bgep,
3128 				    regno, 0);
3129 	}
3130 
3131 	if (!ok && !fault)
3132 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
3133 
3134 	/*
3135 	 * Finally, disable (all) MAC events & clear the MAC status
3136 	 */
3137 	bge_reg_put32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG, 0);
3138 	bge_reg_put32(bgep, ETHERNET_MAC_STATUS_REG, ~0);
3139 
3140 	/*
3141 	 * if we're stopping the chip because of a detected fault then do
3142 	 * appropriate actions
3143 	 */
3144 	if (fault) {
3145 		if (bgep->bge_chip_state != BGE_CHIP_FAULT) {
3146 			bgep->bge_chip_state = BGE_CHIP_FAULT;
3147 			if (!bgep->manual_reset)
3148 				ddi_fm_service_impact(bgep->devinfo,
3149 				    DDI_SERVICE_LOST);
3150 			if (bgep->bge_dma_error) {
3151 				/*
3152 				 * need to free buffers in case the fault was
3153 				 * due to a memory error in a buffer - got to
3154 				 * do a fair bit of tidying first
3155 				 */
3156 				if (bgep->progress & PROGRESS_KSTATS) {
3157 					bge_fini_kstats(bgep);
3158 					bgep->progress &= ~PROGRESS_KSTATS;
3159 				}
3160 				if (bgep->progress & PROGRESS_INTR) {
3161 					bge_intr_disable(bgep);
3162 					rw_enter(bgep->errlock, RW_WRITER);
3163 					bge_fini_rings(bgep);
3164 					rw_exit(bgep->errlock);
3165 					bgep->progress &= ~PROGRESS_INTR;
3166 				}
3167 				if (bgep->progress & PROGRESS_BUFS) {
3168 					bge_free_bufs(bgep);
3169 					bgep->progress &= ~PROGRESS_BUFS;
3170 				}
3171 				bgep->bge_dma_error = B_FALSE;
3172 			}
3173 		}
3174 	} else
3175 		bgep->bge_chip_state = BGE_CHIP_STOPPED;
3176 }
3177 
3178 /*
3179  * Poll for completion of chip's ROM firmware; also, at least on the
3180  * first time through, find and return the hardware MAC address, if any.
3181  */
3182 static uint64_t bge_poll_firmware(bge_t *bgep);
3183 #pragma	no_inline(bge_poll_firmware)
3184 
3185 static uint64_t
3186 bge_poll_firmware(bge_t *bgep)
3187 {
3188 	uint64_t magic;
3189 	uint64_t mac;
3190 	uint32_t gen, val;
3191 	uint32_t i;
3192 
3193 	/*
3194 	 * Step 19: poll for firmware completion (GENCOMM port set
3195 	 * to the ones complement of T3_MAGIC_NUMBER).
3196 	 *
3197 	 * While we're at it, we also read the MAC address register;
3198 	 * at some stage the firmware will load this with the
3199 	 * factory-set value.
3200 	 *
3201 	 * When both the magic number and the MAC address are set,
3202 	 * we're done; but we impose a time limit of one second
3203 	 * (1000*1000us) in case the firmware fails in some fashion
3204 	 * or the SEEPROM that provides that MAC address isn't fitted.
3205 	 *
3206 	 * After the first time through (chip state != INITIAL), we
3207 	 * don't need the MAC address to be set (we've already got it
3208 	 * or not, from the first time), so we don't wait for it, but
3209 	 * we still have to wait for the T3_MAGIC_NUMBER.
3210 	 *
3211 	 * Note: the magic number is only a 32-bit quantity, but the NIC
3212 	 * memory is 64-bit (and big-endian) internally.  Addressing the
3213 	 * GENCOMM word as "the upper half of a 64-bit quantity" makes
3214 	 * it work correctly on both big- and little-endian hosts.
3215 	 */
3216 	if (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3217 	    MHCR_CHIP_ASIC_REV_5906) {
3218 		for (i = 0; i < 1000; ++i) {
3219 			drv_usecwait(1000);
3220 			val = bge_reg_get32(bgep, VCPU_STATUS_REG);
3221 			if (val & VCPU_INIT_DONE)
3222 				break;
3223 		}
3224 		BGE_DEBUG(("bge_poll_firmware($%p): return after %d loops",
3225 		    (void *)bgep, i));
3226 		mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3227 	} else {
3228 		for (i = 0; i < 1000; ++i) {
3229 			drv_usecwait(1000);
3230 			gen = bge_nic_get64(bgep, NIC_MEM_GENCOMM) >> 32;
3231 			if (i == 0 && DEVICE_5704_SERIES_CHIPSETS(bgep))
3232 				drv_usecwait(100000);
3233 			mac = bge_reg_get64(bgep, MAC_ADDRESS_REG(0));
3234 #ifdef BGE_IPMI_ASF
3235 			if (!bgep->asf_enabled) {
3236 #endif
3237 				if (gen != ~T3_MAGIC_NUMBER)
3238 					continue;
3239 #ifdef BGE_IPMI_ASF
3240 			}
3241 #endif
3242 			if (mac != 0ULL)
3243 				break;
3244 			if (bgep->bge_chip_state != BGE_CHIP_INITIAL)
3245 				break;
3246 		}
3247 	}
3248 
3249 	magic = bge_nic_get64(bgep, NIC_MEM_GENCOMM);
3250 	BGE_DEBUG(("bge_poll_firmware($%p): PXE magic 0x%x after %d loops",
3251 	    (void *)bgep, gen, i));
3252 	BGE_DEBUG(("bge_poll_firmware: MAC %016llx, GENCOMM %016llx",
3253 	    mac, magic));
3254 
3255 	return (mac);
3256 }
3257 
3258 /*
3259  * Maximum times of trying to get the NVRAM access lock
3260  * by calling bge_nvmem_acquire()
3261  */
3262 #define	MAX_TRY_NVMEM_ACQUIRE	10000
3263 
3264 #ifdef BGE_IPMI_ASF
3265 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode);
3266 #else
3267 int bge_chip_reset(bge_t *bgep, boolean_t enable_dma);
3268 #endif
3269 #pragma	no_inline(bge_chip_reset)
3270 
3271 int
3272 #ifdef BGE_IPMI_ASF
3273 bge_chip_reset(bge_t *bgep, boolean_t enable_dma, uint_t asf_mode)
3274 #else
3275 bge_chip_reset(bge_t *bgep, boolean_t enable_dma)
3276 #endif
3277 {
3278 	chip_id_t chipid;
3279 	uint64_t mac;
3280 	uint64_t magic;
3281 	uint32_t modeflags;
3282 	uint32_t mhcr;
3283 	uint32_t sx0;
3284 	uint32_t i, tries;
3285 #ifdef BGE_IPMI_ASF
3286 	uint32_t mailbox;
3287 #endif
3288 	int retval = DDI_SUCCESS;
3289 
3290 	BGE_TRACE(("bge_chip_reset($%p, %d)",
3291 		(void *)bgep, enable_dma));
3292 
3293 	ASSERT(mutex_owned(bgep->genlock));
3294 
3295 	BGE_DEBUG(("bge_chip_reset($%p, %d): current state is %d",
3296 		(void *)bgep, enable_dma, bgep->bge_chip_state));
3297 
3298 	/*
3299 	 * Do we need to stop the chip cleanly before resetting?
3300 	 */
3301 	switch (bgep->bge_chip_state) {
3302 	default:
3303 		_NOTE(NOTREACHED)
3304 		return (DDI_FAILURE);
3305 
3306 	case BGE_CHIP_INITIAL:
3307 	case BGE_CHIP_STOPPED:
3308 	case BGE_CHIP_RESET:
3309 		break;
3310 
3311 	case BGE_CHIP_RUNNING:
3312 	case BGE_CHIP_ERROR:
3313 	case BGE_CHIP_FAULT:
3314 		bge_chip_stop(bgep, B_FALSE);
3315 		break;
3316 	}
3317 
3318 #ifdef BGE_IPMI_ASF
3319 	if (bgep->asf_enabled) {
3320 #ifdef __sparc
3321 		mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3322 			MHCR_ENABLE_TAGGED_STATUS_MODE |
3323 			MHCR_MASK_INTERRUPT_MODE |
3324 			MHCR_MASK_PCI_INT_OUTPUT |
3325 			MHCR_CLEAR_INTERRUPT_INTA |
3326 			MHCR_ENABLE_ENDIAN_WORD_SWAP |
3327 			MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3328 		pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3329 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3330 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG) |
3331 			MEMORY_ARBITER_ENABLE);
3332 #endif
3333 		if (asf_mode == ASF_MODE_INIT) {
3334 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
3335 		} else if (asf_mode == ASF_MODE_SHUTDOWN) {
3336 			bge_asf_pre_reset_operations(bgep, BGE_SHUTDOWN_RESET);
3337 		}
3338 	}
3339 #endif
3340 	/*
3341 	 * Adapted from Broadcom document 570X-PG102-R, pp 102-116.
3342 	 * Updated to reflect Broadcom document 570X-PG104-R, pp 146-159.
3343 	 *
3344 	 * Before reset Core clock,it is
3345 	 * also required to initialize the Memory Arbiter as specified in step9
3346 	 * and Misc Host Control Register as specified in step-13
3347 	 * Step 4-5: reset Core clock & wait for completion
3348 	 * Steps 6-8: are done by bge_chip_cfg_init()
3349 	 * put the T3_MAGIC_NUMBER into the GENCOMM port before reset
3350 	 */
3351 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3352 		retval = DDI_FAILURE;
3353 
3354 	mhcr = MHCR_ENABLE_INDIRECT_ACCESS |
3355 	    MHCR_ENABLE_TAGGED_STATUS_MODE |
3356 	    MHCR_MASK_INTERRUPT_MODE |
3357 	    MHCR_MASK_PCI_INT_OUTPUT |
3358 	    MHCR_CLEAR_INTERRUPT_INTA;
3359 #ifdef  _BIG_ENDIAN
3360 	mhcr |= MHCR_ENABLE_ENDIAN_WORD_SWAP | MHCR_ENABLE_ENDIAN_BYTE_SWAP;
3361 #endif  /* _BIG_ENDIAN */
3362 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MHCR, mhcr);
3363 #ifdef BGE_IPMI_ASF
3364 	if (bgep->asf_enabled)
3365 		bgep->asf_wordswapped = B_FALSE;
3366 #endif
3367 	/*
3368 	 * NVRAM Corruption Workaround
3369 	 */
3370 	for (tries = 0; tries < MAX_TRY_NVMEM_ACQUIRE; tries++)
3371 		if (bge_nvmem_acquire(bgep) != EAGAIN)
3372 			break;
3373 	if (tries >= MAX_TRY_NVMEM_ACQUIRE)
3374 		BGE_DEBUG(("%s: fail to acquire nvram lock",
3375 			bgep->ifname));
3376 
3377 #ifdef BGE_IPMI_ASF
3378 	if (!bgep->asf_enabled) {
3379 #endif
3380 		magic = (uint64_t)T3_MAGIC_NUMBER << 32;
3381 		bge_nic_put64(bgep, NIC_MEM_GENCOMM, magic);
3382 #ifdef BGE_IPMI_ASF
3383 	}
3384 #endif
3385 
3386 	if (!bge_chip_reset_engine(bgep, MISC_CONFIG_REG))
3387 		retval = DDI_FAILURE;
3388 	bge_chip_cfg_init(bgep, &chipid, enable_dma);
3389 
3390 	/*
3391 	 * Step 8a: This may belong elsewhere, but BCM5721 needs
3392 	 * a bit set to avoid a fifo overflow/underflow bug.
3393 	 */
3394 	if ((bgep->chipid.chip_label == 5721) ||
3395 		(bgep->chipid.chip_label == 5751) ||
3396 		(bgep->chipid.chip_label == 5752) ||
3397 		(bgep->chipid.chip_label == 5755) ||
3398 		(bgep->chipid.chip_label == 5756) ||
3399 		(bgep->chipid.chip_label == 5789) ||
3400 		(bgep->chipid.chip_label == 5906))
3401 		bge_reg_set32(bgep, TLP_CONTROL_REG, TLP_DATA_FIFO_PROTECT);
3402 
3403 
3404 	/*
3405 	 * Step 9: enable MAC memory arbiter,bit30 and bit31 of 5714/5715 should
3406 	 * not be changed.
3407 	 */
3408 	if (!bge_chip_enable_engine(bgep, MEMORY_ARBITER_MODE_REG, 0))
3409 		retval = DDI_FAILURE;
3410 
3411 	/*
3412 	 * Steps 10-11: configure PIO endianness options and
3413 	 * enable indirect register access -- already done
3414 	 * Steps 12-13: enable writing to the PCI state & clock
3415 	 * control registers -- not required; we aren't going to
3416 	 * use those features.
3417 	 * Steps 14-15: Configure DMA endianness options.  See
3418 	 * the comments on the setting of the MHCR above.
3419 	 */
3420 #ifdef	_BIG_ENDIAN
3421 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME |
3422 		    MODE_WORD_SWAP_NONFRAME | MODE_BYTE_SWAP_NONFRAME;
3423 #else
3424 	modeflags = MODE_WORD_SWAP_FRAME | MODE_BYTE_SWAP_FRAME;
3425 #endif	/* _BIG_ENDIAN */
3426 #ifdef BGE_IPMI_ASF
3427 	if (bgep->asf_enabled)
3428 		modeflags |= MODE_HOST_STACK_UP;
3429 #endif
3430 	bge_reg_put32(bgep, MODE_CONTROL_REG, modeflags);
3431 
3432 #ifdef BGE_IPMI_ASF
3433 	if (bgep->asf_enabled) {
3434 #ifdef __sparc
3435 		bge_reg_put32(bgep, MEMORY_ARBITER_MODE_REG,
3436 			MEMORY_ARBITER_ENABLE |
3437 			bge_reg_get32(bgep, MEMORY_ARBITER_MODE_REG));
3438 #endif
3439 
3440 #ifdef  BGE_NETCONSOLE
3441 		if (!bgep->asf_newhandshake) {
3442 			if ((asf_mode == ASF_MODE_INIT) ||
3443 			(asf_mode == ASF_MODE_POST_INIT)) {
3444 				bge_asf_post_reset_old_mode(bgep,
3445 					BGE_INIT_RESET);
3446 			} else {
3447 				bge_asf_post_reset_old_mode(bgep,
3448 					BGE_SHUTDOWN_RESET);
3449 			}
3450 		}
3451 #endif
3452 
3453 		/* Wait for NVRAM init */
3454 		i = 0;
3455 		drv_usecwait(5000);
3456 		mailbox = bge_nic_get32(bgep, BGE_FIRMWARE_MAILBOX);
3457 
3458 		while ((mailbox != (uint32_t)
3459 			~BGE_MAGIC_NUM_FIRMWARE_INIT_DONE) &&
3460 			(i < 10000)) {
3461 			drv_usecwait(100);
3462 			mailbox = bge_nic_get32(bgep,
3463 				BGE_FIRMWARE_MAILBOX);
3464 			i++;
3465 		}
3466 
3467 #ifndef BGE_NETCONSOLE
3468 		if (!bgep->asf_newhandshake) {
3469 			if ((asf_mode == ASF_MODE_INIT) ||
3470 				(asf_mode == ASF_MODE_POST_INIT)) {
3471 
3472 				bge_asf_post_reset_old_mode(bgep,
3473 					BGE_INIT_RESET);
3474 			} else {
3475 				bge_asf_post_reset_old_mode(bgep,
3476 					BGE_SHUTDOWN_RESET);
3477 			}
3478 		}
3479 #endif
3480 	}
3481 #endif
3482 	/*
3483 	 * Steps 16-17: poll for firmware completion
3484 	 */
3485 	mac = bge_poll_firmware(bgep);
3486 
3487 	/*
3488 	 * Step 18: enable external memory -- doesn't apply.
3489 	 *
3490 	 * However we take the opportunity to set the MLCR anyway, as
3491 	 * this register also controls the SEEPROM auto-access method
3492 	 * which we may want to use later ...
3493 	 *
3494 	 * The proper value here depends on the way the chip is wired
3495 	 * into the circuit board, as this register *also* controls which
3496 	 * of the "Miscellaneous I/O" pins are driven as outputs and the
3497 	 * values driven onto those pins!
3498 	 *
3499 	 * See also step 74 in the PRM ...
3500 	 */
3501 	bge_reg_put32(bgep, MISC_LOCAL_CONTROL_REG,
3502 	    bgep->chipid.bge_mlcr_default);
3503 	bge_reg_set32(bgep, SERIAL_EEPROM_ADDRESS_REG, SEEPROM_ACCESS_INIT);
3504 
3505 	/*
3506 	 * Step 20: clear the Ethernet MAC mode register
3507 	 */
3508 	bge_reg_put32(bgep, ETHERNET_MAC_MODE_REG, 0);
3509 
3510 	/*
3511 	 * Step 21: restore cache-line-size, latency timer, and
3512 	 * subsystem ID registers to their original values (not
3513 	 * those read into the local structure <chipid>, 'cos
3514 	 * that was after they were cleared by the RESET).
3515 	 *
3516 	 * Note: the Subsystem Vendor/Device ID registers are not
3517 	 * directly writable in config space, so we use the shadow
3518 	 * copy in "Page Zero" of register space to restore them
3519 	 * both in one go ...
3520 	 */
3521 	pci_config_put8(bgep->cfg_handle, PCI_CONF_CACHE_LINESZ,
3522 		bgep->chipid.clsize);
3523 	pci_config_put8(bgep->cfg_handle, PCI_CONF_LATENCY_TIMER,
3524 		bgep->chipid.latency);
3525 	bge_reg_put32(bgep, PCI_CONF_SUBVENID,
3526 		(bgep->chipid.subdev << 16) | bgep->chipid.subven);
3527 
3528 	/*
3529 	 * The SEND INDEX registers should be reset to zero by the
3530 	 * global chip reset; if they're not, there'll be trouble
3531 	 * later on.
3532 	 */
3533 	sx0 = bge_reg_get32(bgep, NIC_DIAG_SEND_INDEX_REG(0));
3534 	if (sx0 != 0) {
3535 		BGE_REPORT((bgep, "SEND INDEX - device didn't RESET"));
3536 		bge_fm_ereport(bgep, DDI_FM_DEVICE_INVAL_STATE);
3537 		retval = DDI_FAILURE;
3538 	}
3539 
3540 	/* Enable MSI code */
3541 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
3542 		bge_reg_set32(bgep, MSI_MODE_REG,
3543 		    MSI_PRI_HIGHEST|MSI_MSI_ENABLE|MSI_ERROR_ATTENTION);
3544 
3545 	/*
3546 	 * On the first time through, save the factory-set MAC address
3547 	 * (if any).  If bge_poll_firmware() above didn't return one
3548 	 * (from a chip register) consider looking in the attached NV
3549 	 * memory device, if any.  Once we have it, we save it in both
3550 	 * register-image (64-bit) and byte-array forms.  All-zero and
3551 	 * all-one addresses are not valid, and we refuse to stash those.
3552 	 */
3553 	if (bgep->bge_chip_state == BGE_CHIP_INITIAL) {
3554 		if (mac == 0ULL)
3555 			mac = bge_get_nvmac(bgep);
3556 		if (mac != 0ULL && mac != ~0ULL) {
3557 			bgep->chipid.hw_mac_addr = mac;
3558 			for (i = ETHERADDRL; i-- != 0; ) {
3559 				bgep->chipid.vendor_addr.addr[i] = (uchar_t)mac;
3560 				mac >>= 8;
3561 			}
3562 			bgep->chipid.vendor_addr.set = B_TRUE;
3563 		}
3564 	}
3565 
3566 #ifdef BGE_IPMI_ASF
3567 	if (bgep->asf_enabled && bgep->asf_newhandshake) {
3568 		if (asf_mode != ASF_MODE_NONE) {
3569 			if ((asf_mode == ASF_MODE_INIT) ||
3570 				(asf_mode == ASF_MODE_POST_INIT)) {
3571 
3572 				bge_asf_post_reset_new_mode(bgep,
3573 					BGE_INIT_RESET);
3574 			} else {
3575 				bge_asf_post_reset_new_mode(bgep,
3576 					BGE_SHUTDOWN_RESET);
3577 			}
3578 		}
3579 	}
3580 #endif
3581 
3582 	/*
3583 	 * Record the new state
3584 	 */
3585 	bgep->chip_resets += 1;
3586 	bgep->bge_chip_state = BGE_CHIP_RESET;
3587 	return (retval);
3588 }
3589 
3590 /*
3591  * bge_chip_start() -- start the chip transmitting and/or receiving,
3592  * including enabling interrupts
3593  */
3594 int bge_chip_start(bge_t *bgep, boolean_t reset_phys);
3595 #pragma	no_inline(bge_chip_start)
3596 
3597 void
3598 bge_chip_coalesce_update(bge_t *bgep)
3599 {
3600 	bge_reg_put32(bgep, SEND_COALESCE_MAX_BD_REG,
3601 	    bgep->chipid.tx_count_norm);
3602 	bge_reg_put32(bgep, SEND_COALESCE_TICKS_REG,
3603 	    bgep->chipid.tx_ticks_norm);
3604 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG,
3605 	    bgep->chipid.rx_count_norm);
3606 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG,
3607 	    bgep->chipid.rx_ticks_norm);
3608 }
3609 
3610 int
3611 bge_chip_start(bge_t *bgep, boolean_t reset_phys)
3612 {
3613 	uint32_t coalmode;
3614 	uint32_t ledctl;
3615 	uint32_t mtu;
3616 	uint32_t maxring;
3617 	uint32_t stats_mask;
3618 	uint32_t dma_wrprio;
3619 	uint64_t ring;
3620 	int retval = DDI_SUCCESS;
3621 
3622 	BGE_TRACE(("bge_chip_start($%p)",
3623 	    (void *)bgep));
3624 
3625 	ASSERT(mutex_owned(bgep->genlock));
3626 	ASSERT(bgep->bge_chip_state == BGE_CHIP_RESET);
3627 
3628 	/*
3629 	 * Taken from Broadcom document 570X-PG102-R, pp 102-116.
3630 	 * The document specifies 95 separate steps to fully
3631 	 * initialise the chip!!!!
3632 	 *
3633 	 * The reset code above has already got us as far as step
3634 	 * 21, so we continue with ...
3635 	 *
3636 	 * Step 22: clear the MAC statistics block
3637 	 * (0x0300-0x0aff in NIC-local memory)
3638 	 */
3639 	if (bgep->chipid.statistic_type == BGE_STAT_BLK)
3640 		bge_nic_zero(bgep, NIC_MEM_STATISTICS,
3641 		    NIC_MEM_STATISTICS_SIZE);
3642 
3643 	/*
3644 	 * Step 23: clear the status block (in host memory)
3645 	 */
3646 	DMA_ZERO(bgep->status_block);
3647 
3648 	/*
3649 	 * Step 24: set DMA read/write control register
3650 	 */
3651 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_PDRWCR,
3652 	    bgep->chipid.bge_dma_rwctrl);
3653 
3654 	/*
3655 	 * Step 25: Configure DMA endianness -- already done (16/17)
3656 	 * Step 26: Configure Host-Based Send Rings
3657 	 * Step 27: Indicate Host Stack Up
3658 	 */
3659 	bge_reg_set32(bgep, MODE_CONTROL_REG,
3660 	    MODE_HOST_SEND_BDS |
3661 	    MODE_HOST_STACK_UP);
3662 
3663 	/*
3664 	 * Step 28: Configure checksum options:
3665 	 *	Solaris supports the hardware default checksum options.
3666 	 *
3667 	 *	Workaround for Incorrect pseudo-header checksum calculation.
3668 	 */
3669 	if (bgep->chipid.flags & CHIP_FLAG_PARTIAL_CSUM)
3670 		bge_reg_set32(bgep, MODE_CONTROL_REG,
3671 		    MODE_SEND_NO_PSEUDO_HDR_CSUM);
3672 
3673 	/*
3674 	 * Step 29: configure Timer Prescaler.  The value is always the
3675 	 * same: the Core Clock frequency in MHz (66), minus 1, shifted
3676 	 * into bits 7-1.  Don't set bit 0, 'cos that's the RESET bit
3677 	 * for the whole chip!
3678 	 */
3679 	bge_reg_put32(bgep, MISC_CONFIG_REG, MISC_CONFIG_DEFAULT);
3680 
3681 	if (DEVICE_5906_SERIES_CHIPSETS(bgep)) {
3682 		drv_usecwait(40);
3683 		/* put PHY into ready state */
3684 		bge_reg_clr32(bgep, MISC_CONFIG_REG, MISC_CONFIG_EPHY_IDDQ);
3685 		(void) bge_reg_get32(bgep, MISC_CONFIG_REG); /* flush */
3686 		drv_usecwait(40);
3687 	}
3688 
3689 	/*
3690 	 * Steps 30-31: Configure MAC local memory pool & DMA pool registers
3691 	 *
3692 	 * If the mbuf_length is specified as 0, we just leave these at
3693 	 * their hardware defaults, rather than explicitly setting them.
3694 	 * As the Broadcom HRM,driver better not change the parameters
3695 	 * when the chipsets is 5705/5788/5721/5751/5714 and 5715.
3696 	 */
3697 	if ((bgep->chipid.mbuf_length != 0) &&
3698 	    (DEVICE_5704_SERIES_CHIPSETS(bgep))) {
3699 			bge_reg_put32(bgep, MBUF_POOL_BASE_REG,
3700 			    bgep->chipid.mbuf_base);
3701 			bge_reg_put32(bgep, MBUF_POOL_LENGTH_REG,
3702 			    bgep->chipid.mbuf_length);
3703 			bge_reg_put32(bgep, DMAD_POOL_BASE_REG,
3704 			    DMAD_POOL_BASE_DEFAULT);
3705 			bge_reg_put32(bgep, DMAD_POOL_LENGTH_REG,
3706 			    DMAD_POOL_LENGTH_DEFAULT);
3707 	}
3708 
3709 	/*
3710 	 * Step 32: configure MAC memory pool watermarks
3711 	 */
3712 	bge_reg_put32(bgep, RDMA_MBUF_LOWAT_REG,
3713 	    bgep->chipid.mbuf_lo_water_rdma);
3714 	bge_reg_put32(bgep, MAC_RX_MBUF_LOWAT_REG,
3715 	    bgep->chipid.mbuf_lo_water_rmac);
3716 	bge_reg_put32(bgep, MBUF_HIWAT_REG,
3717 	    bgep->chipid.mbuf_hi_water);
3718 
3719 	/*
3720 	 * Step 33: configure DMA resource watermarks
3721 	 */
3722 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3723 		bge_reg_put32(bgep, DMAD_POOL_LOWAT_REG,
3724 		    bge_dmad_lo_water);
3725 		bge_reg_put32(bgep, DMAD_POOL_HIWAT_REG,
3726 		    bge_dmad_hi_water);
3727 	}
3728 	bge_reg_put32(bgep, LOWAT_MAX_RECV_FRAMES_REG, bge_lowat_recv_frames);
3729 
3730 	/*
3731 	 * Steps 34-36: enable buffer manager & internal h/w queues
3732 	 */
3733 	if (!bge_chip_enable_engine(bgep, BUFFER_MANAGER_MODE_REG,
3734 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3735 		retval = DDI_FAILURE;
3736 	if (!bge_chip_enable_engine(bgep, FTQ_RESET_REG, 0))
3737 		retval = DDI_FAILURE;
3738 
3739 	/*
3740 	 * Steps 37-39: initialise Receive Buffer (Producer) RCBs
3741 	 */
3742 	bge_reg_putrcb(bgep, STD_RCV_BD_RING_RCB_REG,
3743 	    &bgep->buff[BGE_STD_BUFF_RING].hw_rcb);
3744 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3745 		bge_reg_putrcb(bgep, JUMBO_RCV_BD_RING_RCB_REG,
3746 		    &bgep->buff[BGE_JUMBO_BUFF_RING].hw_rcb);
3747 		bge_reg_putrcb(bgep, MINI_RCV_BD_RING_RCB_REG,
3748 		    &bgep->buff[BGE_MINI_BUFF_RING].hw_rcb);
3749 	}
3750 
3751 	/*
3752 	 * Step 40: set Receive Buffer Descriptor Ring replenish thresholds
3753 	 */
3754 	bge_reg_put32(bgep, STD_RCV_BD_REPLENISH_REG, bge_replenish_std);
3755 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3756 		bge_reg_put32(bgep, JUMBO_RCV_BD_REPLENISH_REG,
3757 		    bge_replenish_jumbo);
3758 		bge_reg_put32(bgep, MINI_RCV_BD_REPLENISH_REG,
3759 		    bge_replenish_mini);
3760 	}
3761 
3762 	/*
3763 	 * Steps 41-43: clear Send Ring Producer Indices and initialise
3764 	 * Send Producer Rings (0x0100-0x01ff in NIC-local memory)
3765 	 */
3766 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3767 		maxring = BGE_SEND_RINGS_MAX;
3768 	else
3769 		maxring = BGE_SEND_RINGS_MAX_5705;
3770 	for (ring = 0; ring < maxring; ++ring) {
3771 		bge_mbx_put(bgep, SEND_RING_HOST_INDEX_REG(ring), 0);
3772 		bge_mbx_put(bgep, SEND_RING_NIC_INDEX_REG(ring), 0);
3773 		bge_nic_putrcb(bgep, NIC_MEM_SEND_RING(ring),
3774 		    &bgep->send[ring].hw_rcb);
3775 	}
3776 
3777 	/*
3778 	 * Steps 44-45: initialise Receive Return Rings
3779 	 * (0x0200-0x02ff in NIC-local memory)
3780 	 */
3781 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3782 		maxring = BGE_RECV_RINGS_MAX;
3783 	else
3784 		maxring = BGE_RECV_RINGS_MAX_5705;
3785 	for (ring = 0; ring < maxring; ++ring)
3786 		bge_nic_putrcb(bgep, NIC_MEM_RECV_RING(ring),
3787 		    &bgep->recv[ring].hw_rcb);
3788 
3789 	/*
3790 	 * Step 46: initialise Receive Buffer (Producer) Ring indexes
3791 	 */
3792 	bge_mbx_put(bgep, RECV_STD_PROD_INDEX_REG, 0);
3793 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3794 		bge_mbx_put(bgep, RECV_JUMBO_PROD_INDEX_REG, 0);
3795 		bge_mbx_put(bgep, RECV_MINI_PROD_INDEX_REG, 0);
3796 	}
3797 	/*
3798 	 * Step 47: configure the MAC unicast address
3799 	 * Step 48: configure the random backoff seed
3800 	 * Step 96: set up multicast filters
3801 	 */
3802 #ifdef BGE_IPMI_ASF
3803 	if (bge_chip_sync(bgep, B_FALSE) == DDI_FAILURE)
3804 #else
3805 	if (bge_chip_sync(bgep) == DDI_FAILURE)
3806 #endif
3807 		retval = DDI_FAILURE;
3808 
3809 	/*
3810 	 * Step 49: configure the MTU
3811 	 */
3812 	mtu = bgep->chipid.ethmax_size+ETHERFCSL+VLAN_TAGSZ;
3813 	bge_reg_put32(bgep, MAC_RX_MTU_SIZE_REG, mtu);
3814 
3815 	/*
3816 	 * Step 50: configure the IPG et al
3817 	 */
3818 	bge_reg_put32(bgep, MAC_TX_LENGTHS_REG, MAC_TX_LENGTHS_DEFAULT);
3819 
3820 	/*
3821 	 * Step 51: configure the default Rx Return Ring
3822 	 */
3823 	bge_reg_put32(bgep, RCV_RULES_CONFIG_REG, RCV_RULES_CONFIG_DEFAULT);
3824 
3825 	/*
3826 	 * Steps 52-54: configure Receive List Placement,
3827 	 * and enable Receive List Placement Statistics
3828 	 */
3829 	bge_reg_put32(bgep, RCV_LP_CONFIG_REG,
3830 	    RCV_LP_CONFIG(bgep->chipid.rx_rings));
3831 	switch (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev)) {
3832 	case MHCR_CHIP_ASIC_REV_5700:
3833 	case MHCR_CHIP_ASIC_REV_5701:
3834 	case MHCR_CHIP_ASIC_REV_5703:
3835 	case MHCR_CHIP_ASIC_REV_5704:
3836 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, ~0);
3837 		break;
3838 	case MHCR_CHIP_ASIC_REV_5705:
3839 		break;
3840 	default:
3841 		stats_mask = bge_reg_get32(bgep, RCV_LP_STATS_ENABLE_MASK_REG);
3842 		stats_mask &= ~RCV_LP_STATS_DISABLE_MACTQ;
3843 		bge_reg_put32(bgep, RCV_LP_STATS_ENABLE_MASK_REG, stats_mask);
3844 		break;
3845 	}
3846 	bge_reg_set32(bgep, RCV_LP_STATS_CONTROL_REG, RCV_LP_STATS_ENABLE);
3847 
3848 	if (bgep->chipid.rx_rings > 1)
3849 		bge_init_recv_rule(bgep);
3850 
3851 	/*
3852 	 * Steps 55-56: enable Send Data Initiator Statistics
3853 	 */
3854 	bge_reg_put32(bgep, SEND_INIT_STATS_ENABLE_MASK_REG, ~0);
3855 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3856 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3857 		    SEND_INIT_STATS_ENABLE | SEND_INIT_STATS_FASTER);
3858 	} else {
3859 		bge_reg_put32(bgep, SEND_INIT_STATS_CONTROL_REG,
3860 		    SEND_INIT_STATS_ENABLE);
3861 	}
3862 	/*
3863 	 * Steps 57-58: stop (?) the Host Coalescing Engine
3864 	 */
3865 	if (!bge_chip_disable_engine(bgep, HOST_COALESCE_MODE_REG, ~0))
3866 		retval = DDI_FAILURE;
3867 
3868 	/*
3869 	 * Steps 59-62: initialise Host Coalescing parameters
3870 	 */
3871 	bge_chip_coalesce_update(bgep);
3872 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3873 		bge_reg_put32(bgep, SEND_COALESCE_INT_BD_REG,
3874 		    bge_tx_count_intr);
3875 		bge_reg_put32(bgep, SEND_COALESCE_INT_TICKS_REG,
3876 		    bge_tx_ticks_intr);
3877 		bge_reg_put32(bgep, RCV_COALESCE_INT_BD_REG,
3878 		    bge_rx_count_intr);
3879 		bge_reg_put32(bgep, RCV_COALESCE_INT_TICKS_REG,
3880 		    bge_rx_ticks_intr);
3881 	}
3882 
3883 	/*
3884 	 * Steps 63-64: initialise status block & statistics
3885 	 * host memory addresses
3886 	 * The statistic block does not exist in some chipsets
3887 	 * Step 65: initialise Statistics Coalescing Tick Counter
3888 	 */
3889 	bge_reg_put64(bgep, STATUS_BLOCK_HOST_ADDR_REG,
3890 	    bgep->status_block.cookie.dmac_laddress);
3891 
3892 	/*
3893 	 * Steps 66-67: initialise status block & statistics
3894 	 * NIC-local memory addresses
3895 	 */
3896 	if (DEVICE_5704_SERIES_CHIPSETS(bgep)) {
3897 		bge_reg_put64(bgep, STATISTICS_HOST_ADDR_REG,
3898 		    bgep->statistics.cookie.dmac_laddress);
3899 		bge_reg_put32(bgep, STATISTICS_TICKS_REG,
3900 		    STATISTICS_TICKS_DEFAULT);
3901 		bge_reg_put32(bgep, STATUS_BLOCK_BASE_ADDR_REG,
3902 		    NIC_MEM_STATUS_BLOCK);
3903 		bge_reg_put32(bgep, STATISTICS_BASE_ADDR_REG,
3904 		    NIC_MEM_STATISTICS);
3905 	}
3906 
3907 	/*
3908 	 * Steps 68-71: start the Host Coalescing Engine, the Receive BD
3909 	 * Completion Engine, the Receive List Placement Engine, and the
3910 	 * Receive List selector.Pay attention:0x3400 is not exist in BCM5714
3911 	 * and BCM5715.
3912 	 */
3913 	if (bgep->chipid.tx_rings <= COALESCE_64_BYTE_RINGS &&
3914 	    bgep->chipid.rx_rings <= COALESCE_64_BYTE_RINGS)
3915 		coalmode = COALESCE_64_BYTE_STATUS;
3916 	else
3917 		coalmode = 0;
3918 	if (!bge_chip_enable_engine(bgep, HOST_COALESCE_MODE_REG, coalmode))
3919 		retval = DDI_FAILURE;
3920 	if (!bge_chip_enable_engine(bgep, RCV_BD_COMPLETION_MODE_REG,
3921 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3922 		retval = DDI_FAILURE;
3923 	if (!bge_chip_enable_engine(bgep, RCV_LIST_PLACEMENT_MODE_REG, 0))
3924 		retval = DDI_FAILURE;
3925 
3926 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3927 		if (!bge_chip_enable_engine(bgep, RCV_LIST_SELECTOR_MODE_REG,
3928 		    STATE_MACHINE_ATTN_ENABLE_BIT))
3929 			retval = DDI_FAILURE;
3930 
3931 	/*
3932 	 * Step 72: Enable MAC DMA engines
3933 	 * Step 73: Clear & enable MAC statistics
3934 	 */
3935 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
3936 	    ETHERNET_MODE_ENABLE_FHDE |
3937 	    ETHERNET_MODE_ENABLE_RDE |
3938 	    ETHERNET_MODE_ENABLE_TDE);
3939 	bge_reg_set32(bgep, ETHERNET_MAC_MODE_REG,
3940 	    ETHERNET_MODE_ENABLE_TX_STATS |
3941 	    ETHERNET_MODE_ENABLE_RX_STATS |
3942 	    ETHERNET_MODE_CLEAR_TX_STATS |
3943 	    ETHERNET_MODE_CLEAR_RX_STATS);
3944 
3945 	/*
3946 	 * Step 74: configure the MLCR (Miscellaneous Local Control
3947 	 * Register); not required, as we set up the MLCR in step 10
3948 	 * (part of the reset code) above.
3949 	 *
3950 	 * Step 75: clear Interrupt Mailbox 0
3951 	 */
3952 	bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG, 0);
3953 
3954 	/*
3955 	 * Steps 76-87: Gentlemen, start your engines ...
3956 	 *
3957 	 * Enable the DMA Completion Engine, the Write DMA Engine,
3958 	 * the Read DMA Engine, Receive Data Completion Engine,
3959 	 * the MBuf Cluster Free Engine, the Send Data Completion Engine,
3960 	 * the Send BD Completion Engine, the Receive BD Initiator Engine,
3961 	 * the Receive Data Initiator Engine, the Send Data Initiator Engine,
3962 	 * the Send BD Initiator Engine, and the Send BD Selector Engine.
3963 	 *
3964 	 * Beware exhaust fumes?
3965 	 */
3966 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3967 		if (!bge_chip_enable_engine(bgep, DMA_COMPLETION_MODE_REG, 0))
3968 			retval = DDI_FAILURE;
3969 	dma_wrprio = (bge_dma_wrprio << DMA_PRIORITY_SHIFT) |
3970 	    ALL_DMA_ATTN_BITS;
3971 	if ((MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3972 	    MHCR_CHIP_ASIC_REV_5755) ||
3973 	    (MHCR_CHIP_ASIC_REV(bgep->chipid.asic_rev) ==
3974 	    MHCR_CHIP_ASIC_REV_5906)) {
3975 		dma_wrprio |= DMA_STATUS_TAG_FIX_CQ12384;
3976 	}
3977 	if (!bge_chip_enable_engine(bgep, WRITE_DMA_MODE_REG,
3978 	    dma_wrprio))
3979 		retval = DDI_FAILURE;
3980 	if (DEVICE_5723_SERIES_CHIPSETS(bgep))
3981 		bge_dma_rdprio = 0;
3982 	if (!bge_chip_enable_engine(bgep, READ_DMA_MODE_REG,
3983 	    (bge_dma_rdprio << DMA_PRIORITY_SHIFT) | ALL_DMA_ATTN_BITS))
3984 		retval = DDI_FAILURE;
3985 	if (!bge_chip_enable_engine(bgep, RCV_DATA_COMPLETION_MODE_REG,
3986 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3987 		retval = DDI_FAILURE;
3988 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
3989 		if (!bge_chip_enable_engine(bgep,
3990 		    MBUF_CLUSTER_FREE_MODE_REG, 0))
3991 			retval = DDI_FAILURE;
3992 	if (!bge_chip_enable_engine(bgep, SEND_DATA_COMPLETION_MODE_REG, 0))
3993 		retval = DDI_FAILURE;
3994 	if (!bge_chip_enable_engine(bgep, SEND_BD_COMPLETION_MODE_REG,
3995 	    STATE_MACHINE_ATTN_ENABLE_BIT))
3996 		retval = DDI_FAILURE;
3997 	if (!bge_chip_enable_engine(bgep, RCV_BD_INITIATOR_MODE_REG,
3998 	    RCV_BD_DISABLED_RING_ATTN))
3999 		retval = DDI_FAILURE;
4000 	if (!bge_chip_enable_engine(bgep, RCV_DATA_BD_INITIATOR_MODE_REG,
4001 	    RCV_DATA_BD_ILL_RING_ATTN))
4002 		retval = DDI_FAILURE;
4003 	if (!bge_chip_enable_engine(bgep, SEND_DATA_INITIATOR_MODE_REG, 0))
4004 		retval = DDI_FAILURE;
4005 	if (!bge_chip_enable_engine(bgep, SEND_BD_INITIATOR_MODE_REG,
4006 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4007 		retval = DDI_FAILURE;
4008 	if (!bge_chip_enable_engine(bgep, SEND_BD_SELECTOR_MODE_REG,
4009 	    STATE_MACHINE_ATTN_ENABLE_BIT))
4010 		retval = DDI_FAILURE;
4011 
4012 	/*
4013 	 * Step 88: download firmware -- doesn't apply
4014 	 * Steps 89-90: enable Transmit & Receive MAC Engines
4015 	 */
4016 	if (!bge_chip_enable_engine(bgep, TRANSMIT_MAC_MODE_REG, 0))
4017 		retval = DDI_FAILURE;
4018 #ifdef BGE_IPMI_ASF
4019 	if (!bgep->asf_enabled) {
4020 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4021 		    RECEIVE_MODE_KEEP_VLAN_TAG))
4022 			retval = DDI_FAILURE;
4023 	} else {
4024 		if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG, 0))
4025 			retval = DDI_FAILURE;
4026 	}
4027 #else
4028 	if (!bge_chip_enable_engine(bgep, RECEIVE_MAC_MODE_REG,
4029 	    RECEIVE_MODE_KEEP_VLAN_TAG))
4030 		retval = DDI_FAILURE;
4031 #endif
4032 
4033 	/*
4034 	 * Step 91: disable auto-polling of PHY status
4035 	 */
4036 	bge_reg_put32(bgep, MI_MODE_REG, MI_MODE_DEFAULT);
4037 
4038 	/*
4039 	 * Step 92: configure D0 power state (not required)
4040 	 * Step 93: initialise LED control register ()
4041 	 */
4042 	ledctl = LED_CONTROL_DEFAULT;
4043 	switch (bgep->chipid.device) {
4044 	case DEVICE_ID_5700:
4045 	case DEVICE_ID_5700x:
4046 	case DEVICE_ID_5701:
4047 		/*
4048 		 * Switch to 5700 (MAC) mode on these older chips
4049 		 */
4050 		ledctl &= ~LED_CONTROL_LED_MODE_MASK;
4051 		ledctl |= LED_CONTROL_LED_MODE_5700;
4052 		break;
4053 
4054 	default:
4055 		break;
4056 	}
4057 	bge_reg_put32(bgep, ETHERNET_MAC_LED_CONTROL_REG, ledctl);
4058 
4059 	/*
4060 	 * Step 94: activate link
4061 	 */
4062 	bge_reg_put32(bgep, MI_STATUS_REG, MI_STATUS_LINK);
4063 
4064 	/*
4065 	 * Step 95: set up physical layer (PHY/SerDes)
4066 	 * restart autoneg (if required)
4067 	 */
4068 	if (reset_phys)
4069 		if (bge_phys_update(bgep) == DDI_FAILURE)
4070 			retval = DDI_FAILURE;
4071 
4072 	/*
4073 	 * Extra step (DSG): hand over all the Receive Buffers to the chip
4074 	 */
4075 	for (ring = 0; ring < BGE_BUFF_RINGS_USED; ++ring)
4076 		bge_mbx_put(bgep, bgep->buff[ring].chip_mbx_reg,
4077 		    bgep->buff[ring].rf_next);
4078 
4079 	/*
4080 	 * MSI bits:The least significant MSI 16-bit word.
4081 	 * ISR will be triggered different.
4082 	 */
4083 	if (bgep->intr_type == DDI_INTR_TYPE_MSI)
4084 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, 0x70);
4085 
4086 	/*
4087 	 * Extra step (DSG): select which interrupts are enabled
4088 	 *
4089 	 * Program the Ethernet MAC engine to signal attention on
4090 	 * Link Change events, then enable interrupts on MAC, DMA,
4091 	 * and FLOW attention signals.
4092 	 */
4093 	bge_reg_set32(bgep, ETHERNET_MAC_EVENT_ENABLE_REG,
4094 	    ETHERNET_EVENT_LINK_INT |
4095 	    ETHERNET_STATUS_PCS_ERROR_INT);
4096 #ifdef BGE_IPMI_ASF
4097 	if (bgep->asf_enabled) {
4098 		bge_reg_set32(bgep, MODE_CONTROL_REG,
4099 		    MODE_INT_ON_FLOW_ATTN |
4100 		    MODE_INT_ON_DMA_ATTN |
4101 		    MODE_HOST_STACK_UP|
4102 		    MODE_INT_ON_MAC_ATTN);
4103 	} else {
4104 #endif
4105 		bge_reg_set32(bgep, MODE_CONTROL_REG,
4106 		    MODE_INT_ON_FLOW_ATTN |
4107 		    MODE_INT_ON_DMA_ATTN |
4108 		    MODE_INT_ON_MAC_ATTN);
4109 #ifdef BGE_IPMI_ASF
4110 	}
4111 #endif
4112 
4113 	/*
4114 	 * Step 97: enable PCI interrupts!!!
4115 	 */
4116 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED)
4117 		bge_cfg_clr32(bgep, PCI_CONF_BGE_MHCR,
4118 		    MHCR_MASK_PCI_INT_OUTPUT);
4119 
4120 	/*
4121 	 * All done!
4122 	 */
4123 	bgep->bge_chip_state = BGE_CHIP_RUNNING;
4124 	return (retval);
4125 }
4126 
4127 
4128 /*
4129  * ========== Hardware interrupt handler ==========
4130  */
4131 
4132 #undef	BGE_DBG
4133 #define	BGE_DBG		BGE_DBG_INT	/* debug flag for this code	*/
4134 
4135 /*
4136  * Sync the status block, then atomically clear the specified bits in
4137  * the <flags-and-tag> field of the status block.
4138  * the <flags> word of the status block, returning the value of the
4139  * <tag> and the <flags> before the bits were cleared.
4140  */
4141 static int bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags);
4142 #pragma	inline(bge_status_sync)
4143 
4144 static int
4145 bge_status_sync(bge_t *bgep, uint64_t bits, uint64_t *flags)
4146 {
4147 	bge_status_t *bsp;
4148 	int retval;
4149 
4150 	BGE_TRACE(("bge_status_sync($%p, 0x%llx)",
4151 	    (void *)bgep, bits));
4152 
4153 	ASSERT(bgep->bge_guard == BGE_GUARD);
4154 
4155 	DMA_SYNC(bgep->status_block, DDI_DMA_SYNC_FORKERNEL);
4156 	retval = bge_check_dma_handle(bgep, bgep->status_block.dma_hdl);
4157 	if (retval != DDI_FM_OK)
4158 		return (retval);
4159 
4160 	bsp = DMA_VPTR(bgep->status_block);
4161 	*flags = bge_atomic_clr64(&bsp->flags_n_tag, bits);
4162 
4163 	BGE_DEBUG(("bge_status_sync($%p, 0x%llx) returning 0x%llx",
4164 	    (void *)bgep, bits, *flags));
4165 
4166 	return (retval);
4167 }
4168 
4169 void bge_wake_factotum(bge_t *bgep);
4170 #pragma	inline(bge_wake_factotum)
4171 
4172 void
4173 bge_wake_factotum(bge_t *bgep)
4174 {
4175 	mutex_enter(bgep->softintrlock);
4176 	if (bgep->factotum_flag == 0) {
4177 		bgep->factotum_flag = 1;
4178 		ddi_trigger_softintr(bgep->factotum_id);
4179 	}
4180 	mutex_exit(bgep->softintrlock);
4181 }
4182 
4183 /*
4184  *	bge_intr() -- handle chip interrupts
4185  */
4186 uint_t bge_intr(caddr_t arg1, caddr_t arg2);
4187 #pragma	no_inline(bge_intr)
4188 
4189 uint_t
4190 bge_intr(caddr_t arg1, caddr_t arg2)
4191 {
4192 	bge_t *bgep = (void *)arg1;		/* private device info	*/
4193 	bge_status_t *bsp;
4194 	uint64_t flags;
4195 	uint32_t regval;
4196 	uint_t result;
4197 	int retval, loop_cnt = 0;
4198 
4199 	BGE_TRACE(("bge_intr($%p) ($%p)", arg1, arg2));
4200 
4201 	/*
4202 	 * GLD v2 checks that s/w setup is complete before passing
4203 	 * interrupts to this routine, thus eliminating the old
4204 	 * (and well-known) race condition around ddi_add_intr()
4205 	 */
4206 	ASSERT(bgep->progress & PROGRESS_HWINT);
4207 
4208 	result = DDI_INTR_UNCLAIMED;
4209 	mutex_enter(bgep->genlock);
4210 
4211 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4212 		/*
4213 		 * Check whether chip's says it's asserting #INTA;
4214 		 * if not, don't process or claim the interrupt.
4215 		 *
4216 		 * Note that the PCI signal is active low, so the
4217 		 * bit is *zero* when the interrupt is asserted.
4218 		 */
4219 		regval = bge_reg_get32(bgep, MISC_LOCAL_CONTROL_REG);
4220 		if (regval & MLCR_INTA_STATE) {
4221 			if (bge_check_acc_handle(bgep, bgep->io_handle)
4222 			    != DDI_FM_OK)
4223 				goto chip_stop;
4224 			mutex_exit(bgep->genlock);
4225 			return (result);
4226 		}
4227 
4228 		/*
4229 		 * Block further PCI interrupts ...
4230 		 */
4231 		bge_reg_set32(bgep, PCI_CONF_BGE_MHCR,
4232 		    MHCR_MASK_PCI_INT_OUTPUT);
4233 
4234 	} else {
4235 		/*
4236 		 * Check MSI status
4237 		 */
4238 		regval = bge_reg_get32(bgep, MSI_STATUS_REG);
4239 		if (regval & MSI_ERROR_ATTENTION) {
4240 			BGE_REPORT((bgep, "msi error attention,"
4241 			    " status=0x%x", regval));
4242 			bge_reg_put32(bgep, MSI_STATUS_REG, regval);
4243 		}
4244 	}
4245 
4246 	result = DDI_INTR_CLAIMED;
4247 
4248 	BGE_DEBUG(("bge_intr($%p) ($%p) regval 0x%08x", arg1, arg2, regval));
4249 
4250 	/*
4251 	 * Sync the status block and grab the flags-n-tag from it.
4252 	 * We count the number of interrupts where there doesn't
4253 	 * seem to have been a DMA update of the status block; if
4254 	 * it *has* been updated, the counter will be cleared in
4255 	 * the while() loop below ...
4256 	 */
4257 	bgep->missed_dmas += 1;
4258 	bsp = DMA_VPTR(bgep->status_block);
4259 	for (loop_cnt = 0; loop_cnt < bge_intr_max_loop; loop_cnt++) {
4260 		if (bgep->bge_chip_state != BGE_CHIP_RUNNING) {
4261 			/*
4262 			 * bge_chip_stop() may have freed dma area etc
4263 			 * while we were in this interrupt handler -
4264 			 * better not call bge_status_sync()
4265 			 */
4266 			(void) bge_check_acc_handle(bgep,
4267 			    bgep->io_handle);
4268 			mutex_exit(bgep->genlock);
4269 			return (DDI_INTR_CLAIMED);
4270 		}
4271 		retval = bge_status_sync(bgep, STATUS_FLAG_UPDATED,
4272 		    &flags);
4273 		if (retval != DDI_FM_OK) {
4274 			bgep->bge_dma_error = B_TRUE;
4275 			goto chip_stop;
4276 		}
4277 
4278 		if (!(flags & STATUS_FLAG_UPDATED))
4279 			break;
4280 
4281 		/*
4282 		 * Tell the chip that we're processing the interrupt
4283 		 */
4284 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4285 		    INTERRUPT_MBOX_DISABLE(flags));
4286 		if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4287 		    DDI_FM_OK)
4288 			goto chip_stop;
4289 
4290 		/*
4291 		 * Drop the mutex while we:
4292 		 * 	Receive any newly-arrived packets
4293 		 *	Recycle any newly-finished send buffers
4294 		 */
4295 		bgep->bge_intr_running = B_TRUE;
4296 		mutex_exit(bgep->genlock);
4297 		bge_receive(bgep, bsp);
4298 		bge_recycle(bgep, bsp);
4299 		mutex_enter(bgep->genlock);
4300 		bgep->bge_intr_running = B_FALSE;
4301 
4302 		/*
4303 		 * Tell the chip we've finished processing, and
4304 		 * give it the tag that we got from the status
4305 		 * block earlier, so that it knows just how far
4306 		 * we've gone.  If it's got more for us to do,
4307 		 * it will now update the status block and try
4308 		 * to assert an interrupt (but we've got the
4309 		 * #INTA blocked at present).  If we see the
4310 		 * update, we'll loop around to do some more.
4311 		 * Eventually we'll get out of here ...
4312 		 */
4313 		bge_mbx_put(bgep, INTERRUPT_MBOX_0_REG,
4314 		    INTERRUPT_MBOX_ENABLE(flags));
4315 		if (bgep->chipid.pci_type == BGE_PCI_E)
4316 			(void) bge_mbx_get(bgep, INTERRUPT_MBOX_0_REG);
4317 		bgep->missed_dmas = 0;
4318 	}
4319 
4320 	/*
4321 	 * Check for exceptional conditions that we need to handle
4322 	 *
4323 	 * Link status changed
4324 	 * Status block not updated
4325 	 */
4326 	if (flags & STATUS_FLAG_LINK_CHANGED)
4327 		bge_wake_factotum(bgep);
4328 
4329 	if (bgep->missed_dmas) {
4330 		/*
4331 		 * Probably due to the internal status tag not
4332 		 * being reset.  Force a status block update now;
4333 		 * this should ensure that we get an update and
4334 		 * a new interrupt.  After that, we should be in
4335 		 * sync again ...
4336 		 */
4337 		BGE_REPORT((bgep, "interrupt: flags 0x%llx - "
4338 		    "not updated?", flags));
4339 		bgep->missed_updates++;
4340 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG,
4341 		    COALESCE_NOW);
4342 
4343 		if (bgep->missed_dmas >= bge_dma_miss_limit) {
4344 			/*
4345 			 * If this happens multiple times in a row,
4346 			 * it means DMA is just not working.  Maybe
4347 			 * the chip's failed, or maybe there's a
4348 			 * problem on the PCI bus or in the host-PCI
4349 			 * bridge (Tomatillo).
4350 			 *
4351 			 * At all events, we want to stop further
4352 			 * interrupts and let the recovery code take
4353 			 * over to see whether anything can be done
4354 			 * about it ...
4355 			 */
4356 			bge_fm_ereport(bgep,
4357 			    DDI_FM_DEVICE_BADINT_LIMIT);
4358 			goto chip_stop;
4359 		}
4360 	}
4361 
4362 	/*
4363 	 * Reenable assertion of #INTA, unless there's a DMA fault
4364 	 */
4365 	if (bgep->intr_type == DDI_INTR_TYPE_FIXED) {
4366 		bge_reg_clr32(bgep, PCI_CONF_BGE_MHCR,
4367 		    MHCR_MASK_PCI_INT_OUTPUT);
4368 		if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4369 		    DDI_FM_OK)
4370 			goto chip_stop;
4371 	}
4372 
4373 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4374 		goto chip_stop;
4375 
4376 	mutex_exit(bgep->genlock);
4377 	return (result);
4378 
4379 chip_stop:
4380 #ifdef BGE_IPMI_ASF
4381 	if (bgep->asf_enabled && bgep->asf_status == ASF_STAT_RUN) {
4382 		/*
4383 		 * We must stop ASF heart beat before
4384 		 * bge_chip_stop(), otherwise some
4385 		 * computers (ex. IBM HS20 blade
4386 		 * server) may crash.
4387 		 */
4388 		bge_asf_update_status(bgep);
4389 		bge_asf_stop_timer(bgep);
4390 		bgep->asf_status = ASF_STAT_STOP;
4391 
4392 		bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4393 		(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4394 	}
4395 #endif
4396 	bge_chip_stop(bgep, B_TRUE);
4397 	(void) bge_check_acc_handle(bgep, bgep->io_handle);
4398 	mutex_exit(bgep->genlock);
4399 	return (result);
4400 }
4401 
4402 /*
4403  * ========== Factotum, implemented as a softint handler ==========
4404  */
4405 
4406 #undef	BGE_DBG
4407 #define	BGE_DBG		BGE_DBG_FACT	/* debug flag for this code	*/
4408 
4409 static void bge_factotum_error_handler(bge_t *bgep);
4410 #pragma	no_inline(bge_factotum_error_handler)
4411 
4412 static void
4413 bge_factotum_error_handler(bge_t *bgep)
4414 {
4415 	uint32_t flow;
4416 	uint32_t rdma;
4417 	uint32_t wdma;
4418 	uint32_t tmac;
4419 	uint32_t rmac;
4420 	uint32_t rxrs;
4421 	uint32_t txrs = 0;
4422 
4423 	ASSERT(mutex_owned(bgep->genlock));
4424 
4425 	/*
4426 	 * Read all the registers that show the possible
4427 	 * reasons for the ERROR bit to be asserted
4428 	 */
4429 	flow = bge_reg_get32(bgep, FLOW_ATTN_REG);
4430 	rdma = bge_reg_get32(bgep, READ_DMA_STATUS_REG);
4431 	wdma = bge_reg_get32(bgep, WRITE_DMA_STATUS_REG);
4432 	tmac = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4433 	rmac = bge_reg_get32(bgep, RECEIVE_MAC_STATUS_REG);
4434 	rxrs = bge_reg_get32(bgep, RX_RISC_STATE_REG);
4435 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4436 		txrs = bge_reg_get32(bgep, TX_RISC_STATE_REG);
4437 
4438 	BGE_DEBUG(("factotum($%p) flow 0x%x rdma 0x%x wdma 0x%x",
4439 	    (void *)bgep, flow, rdma, wdma));
4440 	BGE_DEBUG(("factotum($%p) tmac 0x%x rmac 0x%x rxrs 0x%08x txrs 0x%08x",
4441 	    (void *)bgep, tmac, rmac, rxrs, txrs));
4442 
4443 	/*
4444 	 * For now, just clear all the errors ...
4445 	 */
4446 	if (DEVICE_5704_SERIES_CHIPSETS(bgep))
4447 		bge_reg_put32(bgep, TX_RISC_STATE_REG, ~0);
4448 	bge_reg_put32(bgep, RX_RISC_STATE_REG, ~0);
4449 	bge_reg_put32(bgep, RECEIVE_MAC_STATUS_REG, ~0);
4450 	bge_reg_put32(bgep, WRITE_DMA_STATUS_REG, ~0);
4451 	bge_reg_put32(bgep, READ_DMA_STATUS_REG, ~0);
4452 	bge_reg_put32(bgep, FLOW_ATTN_REG, ~0);
4453 }
4454 
4455 /*
4456  * Handler for hardware link state change.
4457  *
4458  * When this routine is called, the hardware link state has changed
4459  * and the new state is reflected in the param_* variables.  Here
4460  * we must update the softstate and reprogram the MAC to match.
4461  */
4462 static void bge_factotum_link_handler(bge_t *bgep);
4463 #pragma	no_inline(bge_factotum_link_handler)
4464 
4465 static void
4466 bge_factotum_link_handler(bge_t *bgep)
4467 {
4468 	ASSERT(mutex_owned(bgep->genlock));
4469 
4470 	/*
4471 	 * Update the s/w link_state
4472 	 */
4473 	if (bgep->param_link_up)
4474 		bgep->link_state = LINK_STATE_UP;
4475 	else
4476 		bgep->link_state = LINK_STATE_DOWN;
4477 
4478 	/*
4479 	 * Reprogram the MAC modes to match
4480 	 */
4481 	bge_sync_mac_modes(bgep);
4482 }
4483 
4484 static boolean_t bge_factotum_link_check(bge_t *bgep, int *dma_state);
4485 #pragma	no_inline(bge_factotum_link_check)
4486 
4487 static boolean_t
4488 bge_factotum_link_check(bge_t *bgep, int *dma_state)
4489 {
4490 	boolean_t check;
4491 	uint64_t flags;
4492 	uint32_t tmac_status;
4493 
4494 	ASSERT(mutex_owned(bgep->genlock));
4495 
4496 	/*
4497 	 * Get & clear the writable status bits in the Tx status register
4498 	 * (some bits are write-1-to-clear, others are just readonly).
4499 	 */
4500 	tmac_status = bge_reg_get32(bgep, TRANSMIT_MAC_STATUS_REG);
4501 	bge_reg_put32(bgep, TRANSMIT_MAC_STATUS_REG, tmac_status);
4502 
4503 	/*
4504 	 * Get & clear the ERROR and LINK_CHANGED bits from the status block
4505 	 */
4506 	*dma_state = bge_status_sync(bgep, STATUS_FLAG_ERROR |
4507 	    STATUS_FLAG_LINK_CHANGED, &flags);
4508 	if (*dma_state != DDI_FM_OK)
4509 		return (B_FALSE);
4510 
4511 	/*
4512 	 * Clear any errors flagged in the status block ...
4513 	 */
4514 	if (flags & STATUS_FLAG_ERROR)
4515 		bge_factotum_error_handler(bgep);
4516 
4517 	/*
4518 	 * We need to check the link status if:
4519 	 *	the status block says there's been a link change
4520 	 *	or there's any discrepancy between the various
4521 	 *	flags indicating the link state (link_state,
4522 	 *	param_link_up, and the LINK STATE bit in the
4523 	 *	Transmit MAC status register).
4524 	 */
4525 	check = (flags & STATUS_FLAG_LINK_CHANGED) != 0;
4526 	switch (bgep->link_state) {
4527 	case LINK_STATE_UP:
4528 		check |= (bgep->param_link_up == B_FALSE);
4529 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) == 0);
4530 		break;
4531 
4532 	case LINK_STATE_DOWN:
4533 		check |= (bgep->param_link_up != B_FALSE);
4534 		check |= ((tmac_status & TRANSMIT_STATUS_LINK_UP) != 0);
4535 		break;
4536 
4537 	default:
4538 		check = B_TRUE;
4539 		break;
4540 	}
4541 
4542 	/*
4543 	 * If <check> is false, we're sure the link hasn't changed.
4544 	 * If true, however, it's not yet definitive; we have to call
4545 	 * bge_phys_check() to determine whether the link has settled
4546 	 * into a new state yet ... and if it has, then call the link
4547 	 * state change handler.But when the chip is 5700 in Dell 6650
4548 	 * ,even if check is false, the link may have changed.So we
4549 	 * have to call bge_phys_check() to determine the link state.
4550 	 */
4551 	if (check || bgep->chipid.device == DEVICE_ID_5700) {
4552 		check = bge_phys_check(bgep);
4553 		if (check)
4554 			bge_factotum_link_handler(bgep);
4555 	}
4556 
4557 	return (check);
4558 }
4559 
4560 /*
4561  * Factotum routine to check for Tx stall, using the 'watchdog' counter
4562  */
4563 static boolean_t bge_factotum_stall_check(bge_t *bgep);
4564 #pragma	no_inline(bge_factotum_stall_check)
4565 
4566 static boolean_t
4567 bge_factotum_stall_check(bge_t *bgep)
4568 {
4569 	uint32_t dogval;
4570 
4571 	ASSERT(mutex_owned(bgep->genlock));
4572 
4573 	/*
4574 	 * Specific check for Tx stall ...
4575 	 *
4576 	 * The 'watchdog' counter is incremented whenever a packet
4577 	 * is queued, reset to 1 when some (but not all) buffers
4578 	 * are reclaimed, reset to 0 (disabled) when all buffers
4579 	 * are reclaimed, and shifted left here.  If it exceeds the
4580 	 * threshold value, the chip is assumed to have stalled and
4581 	 * is put into the ERROR state.  The factotum will then reset
4582 	 * it on the next pass.
4583 	 *
4584 	 * All of which should ensure that we don't get into a state
4585 	 * where packets are left pending indefinitely!
4586 	 */
4587 	dogval = bge_atomic_shl32(&bgep->watchdog, 1);
4588 	if (dogval < bge_watchdog_count)
4589 		return (B_FALSE);
4590 
4591 #if !defined(BGE_NETCONSOLE)
4592 	BGE_REPORT((bgep, "Tx stall detected, watchdog code 0x%x", dogval));
4593 #endif
4594 	bge_fm_ereport(bgep, DDI_FM_DEVICE_STALL);
4595 	return (B_TRUE);
4596 }
4597 
4598 /*
4599  * The factotum is woken up when there's something to do that we'd rather
4600  * not do from inside a hardware interrupt handler or high-level cyclic.
4601  * Its two main tasks are:
4602  *	reset & restart the chip after an error
4603  *	check the link status whenever necessary
4604  */
4605 uint_t bge_chip_factotum(caddr_t arg);
4606 #pragma	no_inline(bge_chip_factotum)
4607 
4608 uint_t
4609 bge_chip_factotum(caddr_t arg)
4610 {
4611 	bge_t *bgep;
4612 	uint_t result;
4613 	boolean_t error;
4614 	boolean_t linkchg;
4615 	int dma_state;
4616 
4617 	bgep = (void *)arg;
4618 
4619 	BGE_TRACE(("bge_chip_factotum($%p)", (void *)bgep));
4620 
4621 	mutex_enter(bgep->softintrlock);
4622 	if (bgep->factotum_flag == 0) {
4623 		mutex_exit(bgep->softintrlock);
4624 		return (DDI_INTR_UNCLAIMED);
4625 	}
4626 	bgep->factotum_flag = 0;
4627 	mutex_exit(bgep->softintrlock);
4628 
4629 	result = DDI_INTR_CLAIMED;
4630 	error = B_FALSE;
4631 	linkchg = B_FALSE;
4632 
4633 	mutex_enter(bgep->genlock);
4634 	switch (bgep->bge_chip_state) {
4635 	default:
4636 		break;
4637 
4638 	case BGE_CHIP_RUNNING:
4639 		linkchg = bge_factotum_link_check(bgep, &dma_state);
4640 		error = bge_factotum_stall_check(bgep);
4641 		if (dma_state != DDI_FM_OK) {
4642 			bgep->bge_dma_error = B_TRUE;
4643 			error = B_TRUE;
4644 		}
4645 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4646 			error = B_TRUE;
4647 		if (error)
4648 			bgep->bge_chip_state = BGE_CHIP_ERROR;
4649 		break;
4650 
4651 	case BGE_CHIP_ERROR:
4652 		error = B_TRUE;
4653 		break;
4654 
4655 	case BGE_CHIP_FAULT:
4656 		/*
4657 		 * Fault detected, time to reset ...
4658 		 */
4659 		if (bge_autorecover) {
4660 			if (!(bgep->progress & PROGRESS_BUFS)) {
4661 				/*
4662 				 * if we can't allocate the ring buffers,
4663 				 * try later
4664 				 */
4665 				if (bge_alloc_bufs(bgep) != DDI_SUCCESS) {
4666 					mutex_exit(bgep->genlock);
4667 					return (result);
4668 				}
4669 				bgep->progress |= PROGRESS_BUFS;
4670 			}
4671 			if (!(bgep->progress & PROGRESS_INTR)) {
4672 				bge_init_rings(bgep);
4673 				bge_intr_enable(bgep);
4674 				bgep->progress |= PROGRESS_INTR;
4675 			}
4676 			if (!(bgep->progress & PROGRESS_KSTATS)) {
4677 				bge_init_kstats(bgep,
4678 				    ddi_get_instance(bgep->devinfo));
4679 				bgep->progress |= PROGRESS_KSTATS;
4680 			}
4681 
4682 			BGE_REPORT((bgep, "automatic recovery activated"));
4683 
4684 			if (bge_restart(bgep, B_FALSE) != DDI_SUCCESS) {
4685 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4686 				error = B_TRUE;
4687 			}
4688 			if (bge_check_acc_handle(bgep, bgep->cfg_handle) !=
4689 			    DDI_FM_OK) {
4690 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4691 				error = B_TRUE;
4692 			}
4693 			if (bge_check_acc_handle(bgep, bgep->io_handle) !=
4694 			    DDI_FM_OK) {
4695 				bgep->bge_chip_state = BGE_CHIP_ERROR;
4696 				error = B_TRUE;
4697 			}
4698 			if (error == B_FALSE) {
4699 #ifdef BGE_IPMI_ASF
4700 				if (bgep->asf_enabled &&
4701 				    bgep->asf_status != ASF_STAT_RUN) {
4702 					bgep->asf_timeout_id = timeout(
4703 					    bge_asf_heartbeat, (void *)bgep,
4704 					    drv_usectohz(
4705 					    BGE_ASF_HEARTBEAT_INTERVAL));
4706 					bgep->asf_status = ASF_STAT_RUN;
4707 				}
4708 #endif
4709 				if (!bgep->manual_reset) {
4710 					ddi_fm_service_impact(bgep->devinfo,
4711 					    DDI_SERVICE_RESTORED);
4712 				}
4713 			}
4714 		}
4715 		break;
4716 	}
4717 
4718 
4719 	/*
4720 	 * If an error is detected, stop the chip now, marking it as
4721 	 * faulty, so that it will be reset next time through ...
4722 	 *
4723 	 * Note that if intr_running is set, then bge_intr() has dropped
4724 	 * genlock to call bge_receive/bge_recycle. Can't stop the chip at
4725 	 * this point so have to wait until the next time the factotum runs.
4726 	 */
4727 	if (error && !bgep->bge_intr_running) {
4728 #ifdef BGE_IPMI_ASF
4729 		if (bgep->asf_enabled && (bgep->asf_status == ASF_STAT_RUN)) {
4730 			/*
4731 			 * We must stop ASF heart beat before bge_chip_stop(),
4732 			 * otherwise some computers (ex. IBM HS20 blade server)
4733 			 * may crash.
4734 			 */
4735 			bge_asf_update_status(bgep);
4736 			bge_asf_stop_timer(bgep);
4737 			bgep->asf_status = ASF_STAT_STOP;
4738 
4739 			bge_asf_pre_reset_operations(bgep, BGE_INIT_RESET);
4740 			(void) bge_check_acc_handle(bgep, bgep->cfg_handle);
4741 		}
4742 #endif
4743 		bge_chip_stop(bgep, B_TRUE);
4744 		(void) bge_check_acc_handle(bgep, bgep->io_handle);
4745 	}
4746 	mutex_exit(bgep->genlock);
4747 
4748 	/*
4749 	 * If the link state changed, tell the world about it.
4750 	 * Note: can't do this while still holding the mutex.
4751 	 */
4752 	if (bgep->link_update_timer == BGE_LINK_UPDATE_TIMEOUT &&
4753 	    bgep->link_state != LINK_STATE_UNKNOWN)
4754 		linkchg = B_TRUE;
4755 	else if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT &&
4756 	    bgep->link_state == LINK_STATE_DOWN)
4757 		linkchg = B_FALSE;
4758 
4759 	if (linkchg) {
4760 		mac_link_update(bgep->mh, bgep->link_state);
4761 		bgep->link_update_timer = BGE_LINK_UPDATE_DONE;
4762 	}
4763 	if (bgep->manual_reset) {
4764 		bgep->manual_reset = B_FALSE;
4765 	}
4766 
4767 	return (result);
4768 }
4769 
4770 /*
4771  * High-level cyclic handler
4772  *
4773  * This routine schedules a (low-level) softint callback to the
4774  * factotum, and prods the chip to update the status block (which
4775  * will cause a hardware interrupt when complete).
4776  */
4777 void bge_chip_cyclic(void *arg);
4778 #pragma	no_inline(bge_chip_cyclic)
4779 
4780 void
4781 bge_chip_cyclic(void *arg)
4782 {
4783 	bge_t *bgep;
4784 
4785 	bgep = arg;
4786 
4787 	switch (bgep->bge_chip_state) {
4788 	default:
4789 		return;
4790 
4791 	case BGE_CHIP_RUNNING:
4792 		bge_reg_set32(bgep, HOST_COALESCE_MODE_REG, COALESCE_NOW);
4793 		if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
4794 			ddi_fm_service_impact(bgep->devinfo,
4795 			    DDI_SERVICE_UNAFFECTED);
4796 
4797 		if (bgep->link_update_timer < BGE_LINK_UPDATE_TIMEOUT)
4798 			bgep->link_update_timer++;
4799 
4800 		break;
4801 
4802 	case BGE_CHIP_FAULT:
4803 	case BGE_CHIP_ERROR:
4804 		break;
4805 	}
4806 
4807 	bge_wake_factotum(bgep);
4808 }
4809 
4810 
4811 /*
4812  * ========== Ioctl subfunctions ==========
4813  */
4814 
4815 #undef	BGE_DBG
4816 #define	BGE_DBG		BGE_DBG_PPIO	/* debug flag for this code	*/
4817 
4818 #if	BGE_DEBUGGING || BGE_DO_PPIO
4819 
4820 static void bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4821 #pragma	no_inline(bge_chip_peek_cfg)
4822 
4823 static void
4824 bge_chip_peek_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4825 {
4826 	uint64_t regval;
4827 	uint64_t regno;
4828 
4829 	BGE_TRACE(("bge_chip_peek_cfg($%p, $%p)",
4830 	    (void *)bgep, (void *)ppd));
4831 
4832 	regno = ppd->pp_acc_offset;
4833 
4834 	switch (ppd->pp_acc_size) {
4835 	case 1:
4836 		regval = pci_config_get8(bgep->cfg_handle, regno);
4837 		break;
4838 
4839 	case 2:
4840 		regval = pci_config_get16(bgep->cfg_handle, regno);
4841 		break;
4842 
4843 	case 4:
4844 		regval = pci_config_get32(bgep->cfg_handle, regno);
4845 		break;
4846 
4847 	case 8:
4848 		regval = pci_config_get64(bgep->cfg_handle, regno);
4849 		break;
4850 	}
4851 
4852 	ppd->pp_acc_data = regval;
4853 }
4854 
4855 static void bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd);
4856 #pragma	no_inline(bge_chip_poke_cfg)
4857 
4858 static void
4859 bge_chip_poke_cfg(bge_t *bgep, bge_peekpoke_t *ppd)
4860 {
4861 	uint64_t regval;
4862 	uint64_t regno;
4863 
4864 	BGE_TRACE(("bge_chip_poke_cfg($%p, $%p)",
4865 	    (void *)bgep, (void *)ppd));
4866 
4867 	regno = ppd->pp_acc_offset;
4868 	regval = ppd->pp_acc_data;
4869 
4870 	switch (ppd->pp_acc_size) {
4871 	case 1:
4872 		pci_config_put8(bgep->cfg_handle, regno, regval);
4873 		break;
4874 
4875 	case 2:
4876 		pci_config_put16(bgep->cfg_handle, regno, regval);
4877 		break;
4878 
4879 	case 4:
4880 		pci_config_put32(bgep->cfg_handle, regno, regval);
4881 		break;
4882 
4883 	case 8:
4884 		pci_config_put64(bgep->cfg_handle, regno, regval);
4885 		break;
4886 	}
4887 }
4888 
4889 static void bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd);
4890 #pragma	no_inline(bge_chip_peek_reg)
4891 
4892 static void
4893 bge_chip_peek_reg(bge_t *bgep, bge_peekpoke_t *ppd)
4894 {
4895 	uint64_t regval;
4896 	void *regaddr;
4897 
4898 	BGE_TRACE(("bge_chip_peek_reg($%p, $%p)",
4899 	    (void *)bgep, (void *)ppd));
4900 
4901 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
4902 
4903 	switch (ppd->pp_acc_size) {
4904 	case 1:
4905 		regval = ddi_get8(bgep->io_handle, regaddr);
4906 		break;
4907 
4908 	case 2:
4909 		regval = ddi_get16(bgep->io_handle, regaddr);
4910 		break;
4911 
4912 	case 4:
4913 		regval = ddi_get32(bgep->io_handle, regaddr);
4914 		break;
4915 
4916 	case 8:
4917 		regval = ddi_get64(bgep->io_handle, regaddr);
4918 		break;
4919 	}
4920 
4921 	ppd->pp_acc_data = regval;
4922 }
4923 
4924 static void bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd);
4925 #pragma	no_inline(bge_chip_peek_reg)
4926 
4927 static void
4928 bge_chip_poke_reg(bge_t *bgep, bge_peekpoke_t *ppd)
4929 {
4930 	uint64_t regval;
4931 	void *regaddr;
4932 
4933 	BGE_TRACE(("bge_chip_poke_reg($%p, $%p)",
4934 	    (void *)bgep, (void *)ppd));
4935 
4936 	regaddr = PIO_ADDR(bgep, ppd->pp_acc_offset);
4937 	regval = ppd->pp_acc_data;
4938 
4939 	switch (ppd->pp_acc_size) {
4940 	case 1:
4941 		ddi_put8(bgep->io_handle, regaddr, regval);
4942 		break;
4943 
4944 	case 2:
4945 		ddi_put16(bgep->io_handle, regaddr, regval);
4946 		break;
4947 
4948 	case 4:
4949 		ddi_put32(bgep->io_handle, regaddr, regval);
4950 		break;
4951 
4952 	case 8:
4953 		ddi_put64(bgep->io_handle, regaddr, regval);
4954 		break;
4955 	}
4956 	BGE_PCICHK(bgep);
4957 }
4958 
4959 static void bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd);
4960 #pragma	no_inline(bge_chip_peek_nic)
4961 
4962 static void
4963 bge_chip_peek_nic(bge_t *bgep, bge_peekpoke_t *ppd)
4964 {
4965 	uint64_t regoff;
4966 	uint64_t regval;
4967 	void *regaddr;
4968 
4969 	BGE_TRACE(("bge_chip_peek_nic($%p, $%p)",
4970 	    (void *)bgep, (void *)ppd));
4971 
4972 	regoff = ppd->pp_acc_offset;
4973 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
4974 	regoff &= MWBAR_GRANULE_MASK;
4975 	regoff += NIC_MEM_WINDOW_OFFSET;
4976 	regaddr = PIO_ADDR(bgep, regoff);
4977 
4978 	switch (ppd->pp_acc_size) {
4979 	case 1:
4980 		regval = ddi_get8(bgep->io_handle, regaddr);
4981 		break;
4982 
4983 	case 2:
4984 		regval = ddi_get16(bgep->io_handle, regaddr);
4985 		break;
4986 
4987 	case 4:
4988 		regval = ddi_get32(bgep->io_handle, regaddr);
4989 		break;
4990 
4991 	case 8:
4992 		regval = ddi_get64(bgep->io_handle, regaddr);
4993 		break;
4994 	}
4995 
4996 	ppd->pp_acc_data = regval;
4997 }
4998 
4999 static void bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd);
5000 #pragma	no_inline(bge_chip_poke_nic)
5001 
5002 static void
5003 bge_chip_poke_nic(bge_t *bgep, bge_peekpoke_t *ppd)
5004 {
5005 	uint64_t regoff;
5006 	uint64_t regval;
5007 	void *regaddr;
5008 
5009 	BGE_TRACE(("bge_chip_poke_nic($%p, $%p)",
5010 	    (void *)bgep, (void *)ppd));
5011 
5012 	regoff = ppd->pp_acc_offset;
5013 	bge_nic_setwin(bgep, regoff & ~MWBAR_GRANULE_MASK);
5014 	regoff &= MWBAR_GRANULE_MASK;
5015 	regoff += NIC_MEM_WINDOW_OFFSET;
5016 	regaddr = PIO_ADDR(bgep, regoff);
5017 	regval = ppd->pp_acc_data;
5018 
5019 	switch (ppd->pp_acc_size) {
5020 	case 1:
5021 		ddi_put8(bgep->io_handle, regaddr, regval);
5022 		break;
5023 
5024 	case 2:
5025 		ddi_put16(bgep->io_handle, regaddr, regval);
5026 		break;
5027 
5028 	case 4:
5029 		ddi_put32(bgep->io_handle, regaddr, regval);
5030 		break;
5031 
5032 	case 8:
5033 		ddi_put64(bgep->io_handle, regaddr, regval);
5034 		break;
5035 	}
5036 	BGE_PCICHK(bgep);
5037 }
5038 
5039 static void bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5040 #pragma	no_inline(bge_chip_peek_mii)
5041 
5042 static void
5043 bge_chip_peek_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5044 {
5045 	BGE_TRACE(("bge_chip_peek_mii($%p, $%p)",
5046 	    (void *)bgep, (void *)ppd));
5047 
5048 	ppd->pp_acc_data = bge_mii_get16(bgep, ppd->pp_acc_offset/2);
5049 }
5050 
5051 static void bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd);
5052 #pragma	no_inline(bge_chip_poke_mii)
5053 
5054 static void
5055 bge_chip_poke_mii(bge_t *bgep, bge_peekpoke_t *ppd)
5056 {
5057 	BGE_TRACE(("bge_chip_poke_mii($%p, $%p)",
5058 	    (void *)bgep, (void *)ppd));
5059 
5060 	bge_mii_put16(bgep, ppd->pp_acc_offset/2, ppd->pp_acc_data);
5061 }
5062 
5063 #if	BGE_SEE_IO32
5064 
5065 static void bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5066 #pragma	no_inline(bge_chip_peek_seeprom)
5067 
5068 static void
5069 bge_chip_peek_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5070 {
5071 	uint32_t data;
5072 	int err;
5073 
5074 	BGE_TRACE(("bge_chip_peek_seeprom($%p, $%p)",
5075 	    (void *)bgep, (void *)ppd));
5076 
5077 	err = bge_nvmem_rw32(bgep, BGE_SEE_READ, ppd->pp_acc_offset, &data);
5078 	ppd->pp_acc_data = err ? ~0ull : data;
5079 }
5080 
5081 static void bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd);
5082 #pragma	no_inline(bge_chip_poke_seeprom)
5083 
5084 static void
5085 bge_chip_poke_seeprom(bge_t *bgep, bge_peekpoke_t *ppd)
5086 {
5087 	uint32_t data;
5088 
5089 	BGE_TRACE(("bge_chip_poke_seeprom($%p, $%p)",
5090 	    (void *)bgep, (void *)ppd));
5091 
5092 	data = ppd->pp_acc_data;
5093 	(void) bge_nvmem_rw32(bgep, BGE_SEE_WRITE, ppd->pp_acc_offset, &data);
5094 }
5095 #endif	/* BGE_SEE_IO32 */
5096 
5097 #if	BGE_FLASH_IO32
5098 
5099 static void bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5100 #pragma	no_inline(bge_chip_peek_flash)
5101 
5102 static void
5103 bge_chip_peek_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5104 {
5105 	uint32_t data;
5106 	int err;
5107 
5108 	BGE_TRACE(("bge_chip_peek_flash($%p, $%p)",
5109 	    (void *)bgep, (void *)ppd));
5110 
5111 	err = bge_nvmem_rw32(bgep, BGE_FLASH_READ, ppd->pp_acc_offset, &data);
5112 	ppd->pp_acc_data = err ? ~0ull : data;
5113 }
5114 
5115 static void bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd);
5116 #pragma	no_inline(bge_chip_poke_flash)
5117 
5118 static void
5119 bge_chip_poke_flash(bge_t *bgep, bge_peekpoke_t *ppd)
5120 {
5121 	uint32_t data;
5122 
5123 	BGE_TRACE(("bge_chip_poke_flash($%p, $%p)",
5124 	    (void *)bgep, (void *)ppd));
5125 
5126 	data = ppd->pp_acc_data;
5127 	(void) bge_nvmem_rw32(bgep, BGE_FLASH_WRITE,
5128 	    ppd->pp_acc_offset, &data);
5129 }
5130 #endif	/* BGE_FLASH_IO32 */
5131 
5132 static void bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5133 #pragma	no_inline(bge_chip_peek_mem)
5134 
5135 static void
5136 bge_chip_peek_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5137 {
5138 	uint64_t regval;
5139 	void *vaddr;
5140 
5141 	BGE_TRACE(("bge_chip_peek_bge($%p, $%p)",
5142 	    (void *)bgep, (void *)ppd));
5143 
5144 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5145 
5146 	switch (ppd->pp_acc_size) {
5147 	case 1:
5148 		regval = *(uint8_t *)vaddr;
5149 		break;
5150 
5151 	case 2:
5152 		regval = *(uint16_t *)vaddr;
5153 		break;
5154 
5155 	case 4:
5156 		regval = *(uint32_t *)vaddr;
5157 		break;
5158 
5159 	case 8:
5160 		regval = *(uint64_t *)vaddr;
5161 		break;
5162 	}
5163 
5164 	BGE_DEBUG(("bge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p",
5165 	    (void *)bgep, (void *)ppd, regval, vaddr));
5166 
5167 	ppd->pp_acc_data = regval;
5168 }
5169 
5170 static void bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd);
5171 #pragma	no_inline(bge_chip_poke_mem)
5172 
5173 static void
5174 bge_chip_poke_mem(bge_t *bgep, bge_peekpoke_t *ppd)
5175 {
5176 	uint64_t regval;
5177 	void *vaddr;
5178 
5179 	BGE_TRACE(("bge_chip_poke_mem($%p, $%p)",
5180 	    (void *)bgep, (void *)ppd));
5181 
5182 	vaddr = (void *)(uintptr_t)ppd->pp_acc_offset;
5183 	regval = ppd->pp_acc_data;
5184 
5185 	BGE_DEBUG(("bge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p",
5186 	    (void *)bgep, (void *)ppd, regval, vaddr));
5187 
5188 	switch (ppd->pp_acc_size) {
5189 	case 1:
5190 		*(uint8_t *)vaddr = (uint8_t)regval;
5191 		break;
5192 
5193 	case 2:
5194 		*(uint16_t *)vaddr = (uint16_t)regval;
5195 		break;
5196 
5197 	case 4:
5198 		*(uint32_t *)vaddr = (uint32_t)regval;
5199 		break;
5200 
5201 	case 8:
5202 		*(uint64_t *)vaddr = (uint64_t)regval;
5203 		break;
5204 	}
5205 }
5206 
5207 static enum ioc_reply bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5208 					struct iocblk *iocp);
5209 #pragma	no_inline(bge_pp_ioctl)
5210 
5211 static enum ioc_reply
5212 bge_pp_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5213 {
5214 	void (*ppfn)(bge_t *bgep, bge_peekpoke_t *ppd);
5215 	bge_peekpoke_t *ppd;
5216 	dma_area_t *areap;
5217 	uint64_t sizemask;
5218 	uint64_t mem_va;
5219 	uint64_t maxoff;
5220 	boolean_t peek;
5221 
5222 	switch (cmd) {
5223 	default:
5224 		/* NOTREACHED */
5225 		bge_error(bgep, "bge_pp_ioctl: invalid cmd 0x%x", cmd);
5226 		return (IOC_INVAL);
5227 
5228 	case BGE_PEEK:
5229 		peek = B_TRUE;
5230 		break;
5231 
5232 	case BGE_POKE:
5233 		peek = B_FALSE;
5234 		break;
5235 	}
5236 
5237 	/*
5238 	 * Validate format of ioctl
5239 	 */
5240 	if (iocp->ioc_count != sizeof (bge_peekpoke_t))
5241 		return (IOC_INVAL);
5242 	if (mp->b_cont == NULL)
5243 		return (IOC_INVAL);
5244 	ppd = (void *)mp->b_cont->b_rptr;
5245 
5246 	/*
5247 	 * Validate request parameters
5248 	 */
5249 	switch (ppd->pp_acc_space) {
5250 	default:
5251 		return (IOC_INVAL);
5252 
5253 	case BGE_PP_SPACE_CFG:
5254 		/*
5255 		 * Config space
5256 		 */
5257 		sizemask = 8|4|2|1;
5258 		mem_va = 0;
5259 		maxoff = PCI_CONF_HDR_SIZE;
5260 		ppfn = peek ? bge_chip_peek_cfg : bge_chip_poke_cfg;
5261 		break;
5262 
5263 	case BGE_PP_SPACE_REG:
5264 		/*
5265 		 * Memory-mapped I/O space
5266 		 */
5267 		sizemask = 8|4|2|1;
5268 		mem_va = 0;
5269 		maxoff = RIAAR_REGISTER_MAX;
5270 		ppfn = peek ? bge_chip_peek_reg : bge_chip_poke_reg;
5271 		break;
5272 
5273 	case BGE_PP_SPACE_NIC:
5274 		/*
5275 		 * NIC on-chip memory
5276 		 */
5277 		sizemask = 8|4|2|1;
5278 		mem_va = 0;
5279 		maxoff = MWBAR_ONCHIP_MAX;
5280 		ppfn = peek ? bge_chip_peek_nic : bge_chip_poke_nic;
5281 		break;
5282 
5283 	case BGE_PP_SPACE_MII:
5284 		/*
5285 		 * PHY's MII registers
5286 		 * NB: all PHY registers are two bytes, but the
5287 		 * addresses increment in ones (word addressing).
5288 		 * So we scale the address here, then undo the
5289 		 * transformation inside the peek/poke functions.
5290 		 */
5291 		ppd->pp_acc_offset *= 2;
5292 		sizemask = 2;
5293 		mem_va = 0;
5294 		maxoff = (MII_MAXREG+1)*2;
5295 		ppfn = peek ? bge_chip_peek_mii : bge_chip_poke_mii;
5296 		break;
5297 
5298 #if	BGE_SEE_IO32
5299 	case BGE_PP_SPACE_SEEPROM:
5300 		/*
5301 		 * Attached SEEPROM(s), if any.
5302 		 * NB: we use the high-order bits of the 'address' as
5303 		 * a device select to accommodate multiple SEEPROMS,
5304 		 * If each one is the maximum size (64kbytes), this
5305 		 * makes them appear contiguous.  Otherwise, there may
5306 		 * be holes in the mapping.  ENxS doesn't have any
5307 		 * SEEPROMs anyway ...
5308 		 */
5309 		sizemask = 4;
5310 		mem_va = 0;
5311 		maxoff = SEEPROM_DEV_AND_ADDR_MASK;
5312 		ppfn = peek ? bge_chip_peek_seeprom : bge_chip_poke_seeprom;
5313 		break;
5314 #endif	/* BGE_SEE_IO32 */
5315 
5316 #if	BGE_FLASH_IO32
5317 	case BGE_PP_SPACE_FLASH:
5318 		/*
5319 		 * Attached Flash device (if any); a maximum of one device
5320 		 * is currently supported.  But it can be up to 1MB (unlike
5321 		 * the 64k limit on SEEPROMs) so why would you need more ;-)
5322 		 */
5323 		sizemask = 4;
5324 		mem_va = 0;
5325 		maxoff = NVM_FLASH_ADDR_MASK;
5326 		ppfn = peek ? bge_chip_peek_flash : bge_chip_poke_flash;
5327 		break;
5328 #endif	/* BGE_FLASH_IO32 */
5329 
5330 	case BGE_PP_SPACE_BGE:
5331 		/*
5332 		 * BGE data structure!
5333 		 */
5334 		sizemask = 8|4|2|1;
5335 		mem_va = (uintptr_t)bgep;
5336 		maxoff = sizeof (*bgep);
5337 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5338 		break;
5339 
5340 	case BGE_PP_SPACE_STATUS:
5341 	case BGE_PP_SPACE_STATISTICS:
5342 	case BGE_PP_SPACE_TXDESC:
5343 	case BGE_PP_SPACE_TXBUFF:
5344 	case BGE_PP_SPACE_RXDESC:
5345 	case BGE_PP_SPACE_RXBUFF:
5346 		/*
5347 		 * Various DMA_AREAs
5348 		 */
5349 		switch (ppd->pp_acc_space) {
5350 		case BGE_PP_SPACE_TXDESC:
5351 			areap = &bgep->tx_desc;
5352 			break;
5353 		case BGE_PP_SPACE_TXBUFF:
5354 			areap = &bgep->tx_buff[0];
5355 			break;
5356 		case BGE_PP_SPACE_RXDESC:
5357 			areap = &bgep->rx_desc[0];
5358 			break;
5359 		case BGE_PP_SPACE_RXBUFF:
5360 			areap = &bgep->rx_buff[0];
5361 			break;
5362 		case BGE_PP_SPACE_STATUS:
5363 			areap = &bgep->status_block;
5364 			break;
5365 		case BGE_PP_SPACE_STATISTICS:
5366 			if (bgep->chipid.statistic_type == BGE_STAT_BLK)
5367 				areap = &bgep->statistics;
5368 			break;
5369 		}
5370 
5371 		sizemask = 8|4|2|1;
5372 		mem_va = (uintptr_t)areap->mem_va;
5373 		maxoff = areap->alength;
5374 		ppfn = peek ? bge_chip_peek_mem : bge_chip_poke_mem;
5375 		break;
5376 	}
5377 
5378 	switch (ppd->pp_acc_size) {
5379 	default:
5380 		return (IOC_INVAL);
5381 
5382 	case 8:
5383 	case 4:
5384 	case 2:
5385 	case 1:
5386 		if ((ppd->pp_acc_size & sizemask) == 0)
5387 			return (IOC_INVAL);
5388 		break;
5389 	}
5390 
5391 	if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0)
5392 		return (IOC_INVAL);
5393 
5394 	if (ppd->pp_acc_offset >= maxoff)
5395 		return (IOC_INVAL);
5396 
5397 	if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff)
5398 		return (IOC_INVAL);
5399 
5400 	/*
5401 	 * All OK - go do it!
5402 	 */
5403 	ppd->pp_acc_offset += mem_va;
5404 	(*ppfn)(bgep, ppd);
5405 	return (peek ? IOC_REPLY : IOC_ACK);
5406 }
5407 
5408 static enum ioc_reply bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5409 					struct iocblk *iocp);
5410 #pragma	no_inline(bge_diag_ioctl)
5411 
5412 static enum ioc_reply
5413 bge_diag_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5414 {
5415 	ASSERT(mutex_owned(bgep->genlock));
5416 
5417 	switch (cmd) {
5418 	default:
5419 		/* NOTREACHED */
5420 		bge_error(bgep, "bge_diag_ioctl: invalid cmd 0x%x", cmd);
5421 		return (IOC_INVAL);
5422 
5423 	case BGE_DIAG:
5424 		/*
5425 		 * Currently a no-op
5426 		 */
5427 		return (IOC_ACK);
5428 
5429 	case BGE_PEEK:
5430 	case BGE_POKE:
5431 		return (bge_pp_ioctl(bgep, cmd, mp, iocp));
5432 
5433 	case BGE_PHY_RESET:
5434 		return (IOC_RESTART_ACK);
5435 
5436 	case BGE_SOFT_RESET:
5437 	case BGE_HARD_RESET:
5438 		/*
5439 		 * Reset and reinitialise the 570x hardware
5440 		 */
5441 		bgep->bge_chip_state = BGE_CHIP_FAULT;
5442 		ddi_trigger_softintr(bgep->factotum_id);
5443 		(void) bge_restart(bgep, cmd == BGE_HARD_RESET);
5444 		return (IOC_ACK);
5445 	}
5446 
5447 	/* NOTREACHED */
5448 }
5449 
5450 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5451 
5452 static enum ioc_reply bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5453 				    struct iocblk *iocp);
5454 #pragma	no_inline(bge_mii_ioctl)
5455 
5456 static enum ioc_reply
5457 bge_mii_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5458 {
5459 	struct bge_mii_rw *miirwp;
5460 
5461 	/*
5462 	 * Validate format of ioctl
5463 	 */
5464 	if (iocp->ioc_count != sizeof (struct bge_mii_rw))
5465 		return (IOC_INVAL);
5466 	if (mp->b_cont == NULL)
5467 		return (IOC_INVAL);
5468 	miirwp = (void *)mp->b_cont->b_rptr;
5469 
5470 	/*
5471 	 * Validate request parameters ...
5472 	 */
5473 	if (miirwp->mii_reg > MII_MAXREG)
5474 		return (IOC_INVAL);
5475 
5476 	switch (cmd) {
5477 	default:
5478 		/* NOTREACHED */
5479 		bge_error(bgep, "bge_mii_ioctl: invalid cmd 0x%x", cmd);
5480 		return (IOC_INVAL);
5481 
5482 	case BGE_MII_READ:
5483 		miirwp->mii_data = bge_mii_get16(bgep, miirwp->mii_reg);
5484 		return (IOC_REPLY);
5485 
5486 	case BGE_MII_WRITE:
5487 		bge_mii_put16(bgep, miirwp->mii_reg, miirwp->mii_data);
5488 		return (IOC_ACK);
5489 	}
5490 
5491 	/* NOTREACHED */
5492 }
5493 
5494 #if	BGE_SEE_IO32
5495 
5496 static enum ioc_reply bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5497 				    struct iocblk *iocp);
5498 #pragma	no_inline(bge_see_ioctl)
5499 
5500 static enum ioc_reply
5501 bge_see_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5502 {
5503 	struct bge_see_rw *seerwp;
5504 
5505 	/*
5506 	 * Validate format of ioctl
5507 	 */
5508 	if (iocp->ioc_count != sizeof (struct bge_see_rw))
5509 		return (IOC_INVAL);
5510 	if (mp->b_cont == NULL)
5511 		return (IOC_INVAL);
5512 	seerwp = (void *)mp->b_cont->b_rptr;
5513 
5514 	/*
5515 	 * Validate request parameters ...
5516 	 */
5517 	if (seerwp->see_addr & ~SEEPROM_DEV_AND_ADDR_MASK)
5518 		return (IOC_INVAL);
5519 
5520 	switch (cmd) {
5521 	default:
5522 		/* NOTREACHED */
5523 		bge_error(bgep, "bge_see_ioctl: invalid cmd 0x%x", cmd);
5524 		return (IOC_INVAL);
5525 
5526 	case BGE_SEE_READ:
5527 	case BGE_SEE_WRITE:
5528 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5529 		    seerwp->see_addr, &seerwp->see_data);
5530 		return (IOC_REPLY);
5531 	}
5532 
5533 	/* NOTREACHED */
5534 }
5535 
5536 #endif	/* BGE_SEE_IO32 */
5537 
5538 #if	BGE_FLASH_IO32
5539 
5540 static enum ioc_reply bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp,
5541 				    struct iocblk *iocp);
5542 #pragma	no_inline(bge_flash_ioctl)
5543 
5544 static enum ioc_reply
5545 bge_flash_ioctl(bge_t *bgep, int cmd, mblk_t *mp, struct iocblk *iocp)
5546 {
5547 	struct bge_flash_rw *flashrwp;
5548 
5549 	/*
5550 	 * Validate format of ioctl
5551 	 */
5552 	if (iocp->ioc_count != sizeof (struct bge_flash_rw))
5553 		return (IOC_INVAL);
5554 	if (mp->b_cont == NULL)
5555 		return (IOC_INVAL);
5556 	flashrwp = (void *)mp->b_cont->b_rptr;
5557 
5558 	/*
5559 	 * Validate request parameters ...
5560 	 */
5561 	if (flashrwp->flash_addr & ~NVM_FLASH_ADDR_MASK)
5562 		return (IOC_INVAL);
5563 
5564 	switch (cmd) {
5565 	default:
5566 		/* NOTREACHED */
5567 		bge_error(bgep, "bge_flash_ioctl: invalid cmd 0x%x", cmd);
5568 		return (IOC_INVAL);
5569 
5570 	case BGE_FLASH_READ:
5571 	case BGE_FLASH_WRITE:
5572 		iocp->ioc_error = bge_nvmem_rw32(bgep, cmd,
5573 		    flashrwp->flash_addr, &flashrwp->flash_data);
5574 		return (IOC_REPLY);
5575 	}
5576 
5577 	/* NOTREACHED */
5578 }
5579 
5580 #endif	/* BGE_FLASH_IO32 */
5581 
5582 enum ioc_reply bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp,
5583 				struct iocblk *iocp);
5584 #pragma	no_inline(bge_chip_ioctl)
5585 
5586 enum ioc_reply
5587 bge_chip_ioctl(bge_t *bgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp)
5588 {
5589 	int cmd;
5590 
5591 	BGE_TRACE(("bge_chip_ioctl($%p, $%p, $%p, $%p)",
5592 	    (void *)bgep, (void *)wq, (void *)mp, (void *)iocp));
5593 
5594 	ASSERT(mutex_owned(bgep->genlock));
5595 
5596 	cmd = iocp->ioc_cmd;
5597 	switch (cmd) {
5598 	default:
5599 		/* NOTREACHED */
5600 		bge_error(bgep, "bge_chip_ioctl: invalid cmd 0x%x", cmd);
5601 		return (IOC_INVAL);
5602 
5603 	case BGE_DIAG:
5604 	case BGE_PEEK:
5605 	case BGE_POKE:
5606 	case BGE_PHY_RESET:
5607 	case BGE_SOFT_RESET:
5608 	case BGE_HARD_RESET:
5609 #if	BGE_DEBUGGING || BGE_DO_PPIO
5610 		return (bge_diag_ioctl(bgep, cmd, mp, iocp));
5611 #else
5612 		return (IOC_INVAL);
5613 #endif	/* BGE_DEBUGGING || BGE_DO_PPIO */
5614 
5615 	case BGE_MII_READ:
5616 	case BGE_MII_WRITE:
5617 		return (bge_mii_ioctl(bgep, cmd, mp, iocp));
5618 
5619 #if	BGE_SEE_IO32
5620 	case BGE_SEE_READ:
5621 	case BGE_SEE_WRITE:
5622 		return (bge_see_ioctl(bgep, cmd, mp, iocp));
5623 #endif	/* BGE_SEE_IO32 */
5624 
5625 #if	BGE_FLASH_IO32
5626 	case BGE_FLASH_READ:
5627 	case BGE_FLASH_WRITE:
5628 		return (bge_flash_ioctl(bgep, cmd, mp, iocp));
5629 #endif	/* BGE_FLASH_IO32 */
5630 	}
5631 
5632 	/* NOTREACHED */
5633 }
5634 
5635 /* ARGSUSED */
5636 void
5637 bge_chip_blank(void *arg, time_t ticks, uint_t count, int flag)
5638 {
5639 	recv_ring_t *rrp = arg;
5640 	bge_t *bgep = rrp->bgep;
5641 
5642 	mutex_enter(bgep->genlock);
5643 	rrp->poll_flag = flag;
5644 #ifdef NOT_YET
5645 	/*
5646 	 * XXX-Sunay: Since most broadcom cards support only one
5647 	 * interrupt but multiple rx rings, we can't disable the
5648 	 * physical interrupt. This need to be done via capability
5649 	 * negotiation depending on the NIC.
5650 	 */
5651 	bge_reg_put32(bgep, RCV_COALESCE_TICKS_REG, ticks);
5652 	bge_reg_put32(bgep, RCV_COALESCE_MAX_BD_REG, count);
5653 #endif
5654 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5655 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_UNAFFECTED);
5656 	mutex_exit(bgep->genlock);
5657 }
5658 
5659 #ifdef BGE_IPMI_ASF
5660 
5661 uint32_t
5662 bge_nic_read32(bge_t *bgep, bge_regno_t addr)
5663 {
5664 	uint32_t data;
5665 
5666 #ifndef __sparc
5667 	if (!bgep->asf_wordswapped) {
5668 		/* a workaround word swap error */
5669 		if (addr & 4)
5670 			addr = addr - 4;
5671 		else
5672 			addr = addr + 4;
5673 	}
5674 #endif
5675 
5676 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, addr);
5677 	data = pci_config_get32(bgep->cfg_handle, PCI_CONF_BGE_MWDAR);
5678 	pci_config_put32(bgep->cfg_handle, PCI_CONF_BGE_MWBAR, 0);
5679 
5680 	data = LE_32(data);
5681 	return (data);
5682 }
5683 
5684 void
5685 bge_asf_update_status(bge_t *bgep)
5686 {
5687 	uint32_t event;
5688 
5689 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_ALIVE);
5690 	bge_nic_put32(bgep, BGE_CMD_LENGTH_MAILBOX, 4);
5691 	bge_nic_put32(bgep, BGE_CMD_DATA_MAILBOX,   3);
5692 
5693 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5694 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5695 }
5696 
5697 
5698 /*
5699  * The driver is supposed to notify ASF that the OS is still running
5700  * every three seconds, otherwise the management server may attempt
5701  * to reboot the machine.  If it hasn't actually failed, this is
5702  * not a desirable result.  However, this isn't running as a real-time
5703  * thread, and even if it were, it might not be able to generate the
5704  * heartbeat in a timely manner due to system load.  As it isn't a
5705  * significant strain on the machine, we will set the interval to half
5706  * of the required value.
5707  */
5708 void
5709 bge_asf_heartbeat(void *arg)
5710 {
5711 	bge_t *bgep = (bge_t *)arg;
5712 
5713 	mutex_enter(bgep->genlock);
5714 	bge_asf_update_status((bge_t *)bgep);
5715 	if (bge_check_acc_handle(bgep, bgep->io_handle) != DDI_FM_OK)
5716 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5717 	if (bge_check_acc_handle(bgep, bgep->cfg_handle) != DDI_FM_OK)
5718 		ddi_fm_service_impact(bgep->devinfo, DDI_SERVICE_DEGRADED);
5719 	mutex_exit(bgep->genlock);
5720 	((bge_t *)bgep)->asf_timeout_id = timeout(bge_asf_heartbeat, bgep,
5721 	    drv_usectohz(BGE_ASF_HEARTBEAT_INTERVAL));
5722 }
5723 
5724 
5725 void
5726 bge_asf_stop_timer(bge_t *bgep)
5727 {
5728 	timeout_id_t tmp_id = 0;
5729 
5730 	while ((bgep->asf_timeout_id != 0) &&
5731 	    (tmp_id != bgep->asf_timeout_id)) {
5732 		tmp_id = bgep->asf_timeout_id;
5733 		(void) untimeout(tmp_id);
5734 	}
5735 	bgep->asf_timeout_id = 0;
5736 }
5737 
5738 
5739 
5740 /*
5741  * This function should be placed at the earliest position of bge_attach().
5742  */
5743 void
5744 bge_asf_get_config(bge_t *bgep)
5745 {
5746 	uint32_t nicsig;
5747 	uint32_t niccfg;
5748 
5749 	bgep->asf_enabled = B_FALSE;
5750 	nicsig = bge_nic_read32(bgep, BGE_NIC_DATA_SIG_ADDR);
5751 	if (nicsig == BGE_NIC_DATA_SIG) {
5752 		niccfg = bge_nic_read32(bgep, BGE_NIC_DATA_NIC_CFG_ADDR);
5753 		if (niccfg & BGE_NIC_CFG_ENABLE_ASF)
5754 			/*
5755 			 * Here, we don't consider BAXTER, because BGE haven't
5756 			 * supported BAXTER (that is 5752). Also, as I know,
5757 			 * BAXTER doesn't support ASF feature.
5758 			 */
5759 			bgep->asf_enabled = B_TRUE;
5760 		else
5761 			bgep->asf_enabled = B_FALSE;
5762 	} else
5763 		bgep->asf_enabled = B_FALSE;
5764 }
5765 
5766 
5767 void
5768 bge_asf_pre_reset_operations(bge_t *bgep, uint32_t mode)
5769 {
5770 	uint32_t tries;
5771 	uint32_t event;
5772 
5773 	ASSERT(bgep->asf_enabled);
5774 
5775 	/* Issues "pause firmware" command and wait for ACK */
5776 	bge_nic_put32(bgep, BGE_CMD_MAILBOX, BGE_CMD_NICDRV_PAUSE_FW);
5777 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5778 	bge_reg_put32(bgep, RX_RISC_EVENT_REG, event | RRER_ASF_EVENT);
5779 
5780 	event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5781 	tries = 0;
5782 	while ((event & RRER_ASF_EVENT) && (tries < 100)) {
5783 		drv_usecwait(1);
5784 		tries ++;
5785 		event = bge_reg_get32(bgep, RX_RISC_EVENT_REG);
5786 	}
5787 
5788 	bge_nic_put32(bgep, BGE_FIRMWARE_MAILBOX,
5789 	    BGE_MAGIC_NUM_FIRMWARE_INIT_DONE);
5790 
5791 	if (bgep->asf_newhandshake) {
5792 		switch (mode) {
5793 		case BGE_INIT_RESET:
5794 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5795 			    BGE_DRV_STATE_START);
5796 			break;
5797 		case BGE_SHUTDOWN_RESET:
5798 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5799 			    BGE_DRV_STATE_UNLOAD);
5800 			break;
5801 		case BGE_SUSPEND_RESET:
5802 			bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5803 			    BGE_DRV_STATE_SUSPEND);
5804 			break;
5805 		default:
5806 			break;
5807 		}
5808 	}
5809 }
5810 
5811 
5812 void
5813 bge_asf_post_reset_old_mode(bge_t *bgep, uint32_t mode)
5814 {
5815 	switch (mode) {
5816 	case BGE_INIT_RESET:
5817 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5818 		    BGE_DRV_STATE_START);
5819 		break;
5820 	case BGE_SHUTDOWN_RESET:
5821 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5822 		    BGE_DRV_STATE_UNLOAD);
5823 		break;
5824 	case BGE_SUSPEND_RESET:
5825 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5826 		    BGE_DRV_STATE_SUSPEND);
5827 		break;
5828 	default:
5829 		break;
5830 	}
5831 }
5832 
5833 
5834 void
5835 bge_asf_post_reset_new_mode(bge_t *bgep, uint32_t mode)
5836 {
5837 	switch (mode) {
5838 	case BGE_INIT_RESET:
5839 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5840 		    BGE_DRV_STATE_START_DONE);
5841 		break;
5842 	case BGE_SHUTDOWN_RESET:
5843 		bge_nic_put32(bgep, BGE_DRV_STATE_MAILBOX,
5844 		    BGE_DRV_STATE_UNLOAD_DONE);
5845 		break;
5846 	default:
5847 		break;
5848 	}
5849 }
5850 
5851 #endif /* BGE_IPMI_ASF */
5852