1*7c478bd9Sstevel@tonic-gate /*
2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START
3*7c478bd9Sstevel@tonic-gate *
4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
7*7c478bd9Sstevel@tonic-gate * with the License.
8*7c478bd9Sstevel@tonic-gate *
9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions
12*7c478bd9Sstevel@tonic-gate * and limitations under the License.
13*7c478bd9Sstevel@tonic-gate *
14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
19*7c478bd9Sstevel@tonic-gate *
20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END
21*7c478bd9Sstevel@tonic-gate */
22*7c478bd9Sstevel@tonic-gate /*
23*7c478bd9Sstevel@tonic-gate * Copyright (c) 2001 by Sun Microsystems, Inc.
24*7c478bd9Sstevel@tonic-gate * All rights reserved.
25*7c478bd9Sstevel@tonic-gate */
26*7c478bd9Sstevel@tonic-gate
27*7c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
28*7c478bd9Sstevel@tonic-gate
29*7c478bd9Sstevel@tonic-gate #include <sys/promif.h>
30*7c478bd9Sstevel@tonic-gate #include <sys/promimpl.h>
31*7c478bd9Sstevel@tonic-gate
32*7c478bd9Sstevel@tonic-gate /*
33*7c478bd9Sstevel@tonic-gate * This file contains the implementations of all Starfire-specific
34*7c478bd9Sstevel@tonic-gate * promif routines.
35*7c478bd9Sstevel@tonic-gate */
36*7c478bd9Sstevel@tonic-gate
37*7c478bd9Sstevel@tonic-gate /*
38*7c478bd9Sstevel@tonic-gate * Probe all of the devices on a board. The board number is
39*7c478bd9Sstevel@tonic-gate * computed from cpuid. All of the cpus on the board are
40*7c478bd9Sstevel@tonic-gate * brought into OBP's slave idle loop but are not started.
41*7c478bd9Sstevel@tonic-gate * Returns zero for success and non-zero for failure.
42*7c478bd9Sstevel@tonic-gate */
43*7c478bd9Sstevel@tonic-gate int
prom_starfire_add_brd(uint_t cpuid)44*7c478bd9Sstevel@tonic-gate prom_starfire_add_brd(uint_t cpuid)
45*7c478bd9Sstevel@tonic-gate {
46*7c478bd9Sstevel@tonic-gate cell_t ci[5];
47*7c478bd9Sstevel@tonic-gate int rv;
48*7c478bd9Sstevel@tonic-gate
49*7c478bd9Sstevel@tonic-gate ci[0] = p1275_ptr2cell("SUNW,UE10000,add-brd"); /* name */
50*7c478bd9Sstevel@tonic-gate ci[1] = (cell_t)1; /* #argument cells */
51*7c478bd9Sstevel@tonic-gate ci[2] = (cell_t)1; /* #result cells */
52*7c478bd9Sstevel@tonic-gate ci[3] = p1275_uint2cell(cpuid);
53*7c478bd9Sstevel@tonic-gate
54*7c478bd9Sstevel@tonic-gate promif_preprom();
55*7c478bd9Sstevel@tonic-gate rv = p1275_cif_handler(&ci);
56*7c478bd9Sstevel@tonic-gate promif_postprom();
57*7c478bd9Sstevel@tonic-gate
58*7c478bd9Sstevel@tonic-gate return ((rv) ? -1 : p1275_cell2int(ci[4]));
59*7c478bd9Sstevel@tonic-gate }
60*7c478bd9Sstevel@tonic-gate
61*7c478bd9Sstevel@tonic-gate /*
62*7c478bd9Sstevel@tonic-gate * Prune the device tree nodes for all devices on the board
63*7c478bd9Sstevel@tonic-gate * represented by brdnum. Returns zero for success and non-zero
64*7c478bd9Sstevel@tonic-gate * for failure.
65*7c478bd9Sstevel@tonic-gate */
66*7c478bd9Sstevel@tonic-gate int
prom_starfire_rm_brd(uint_t brdnum)67*7c478bd9Sstevel@tonic-gate prom_starfire_rm_brd(uint_t brdnum)
68*7c478bd9Sstevel@tonic-gate {
69*7c478bd9Sstevel@tonic-gate cell_t ci[5];
70*7c478bd9Sstevel@tonic-gate int rv;
71*7c478bd9Sstevel@tonic-gate
72*7c478bd9Sstevel@tonic-gate ci[0] = p1275_ptr2cell("SUNW,UE10000,rm-brd"); /* name */
73*7c478bd9Sstevel@tonic-gate ci[1] = (cell_t)1; /* #argument cells */
74*7c478bd9Sstevel@tonic-gate ci[2] = (cell_t)1; /* #result cells */
75*7c478bd9Sstevel@tonic-gate ci[3] = p1275_uint2cell(brdnum);
76*7c478bd9Sstevel@tonic-gate
77*7c478bd9Sstevel@tonic-gate promif_preprom();
78*7c478bd9Sstevel@tonic-gate rv = p1275_cif_handler(&ci);
79*7c478bd9Sstevel@tonic-gate promif_postprom();
80*7c478bd9Sstevel@tonic-gate
81*7c478bd9Sstevel@tonic-gate return ((rv) ? -1 : p1275_cell2int(ci[4]));
82*7c478bd9Sstevel@tonic-gate }
83*7c478bd9Sstevel@tonic-gate
84*7c478bd9Sstevel@tonic-gate /*
85*7c478bd9Sstevel@tonic-gate * Prepare firmware internal state for the inclusion of the
86*7c478bd9Sstevel@tonic-gate * cpu represented by cpuid. This operation has no effect on
87*7c478bd9Sstevel@tonic-gate * the cpu hardware or behavior in the client.
88*7c478bd9Sstevel@tonic-gate */
89*7c478bd9Sstevel@tonic-gate void
prom_starfire_add_cpu(uint_t cpuid)90*7c478bd9Sstevel@tonic-gate prom_starfire_add_cpu(uint_t cpuid)
91*7c478bd9Sstevel@tonic-gate {
92*7c478bd9Sstevel@tonic-gate cell_t ci[4];
93*7c478bd9Sstevel@tonic-gate
94*7c478bd9Sstevel@tonic-gate ci[0] = p1275_ptr2cell("SUNW,UE10000,add-cpu"); /* name */
95*7c478bd9Sstevel@tonic-gate ci[1] = (cell_t)1; /* #argument cells */
96*7c478bd9Sstevel@tonic-gate ci[2] = (cell_t)0; /* #result cells */
97*7c478bd9Sstevel@tonic-gate ci[3] = p1275_uint2cell(cpuid);
98*7c478bd9Sstevel@tonic-gate
99*7c478bd9Sstevel@tonic-gate promif_preprom();
100*7c478bd9Sstevel@tonic-gate (void) p1275_cif_handler(&ci);
101*7c478bd9Sstevel@tonic-gate promif_postprom();
102*7c478bd9Sstevel@tonic-gate }
103*7c478bd9Sstevel@tonic-gate
104*7c478bd9Sstevel@tonic-gate /*
105*7c478bd9Sstevel@tonic-gate * Prepare firmware internal state for the departure of the cpu
106*7c478bd9Sstevel@tonic-gate * represented by cpuid.
107*7c478bd9Sstevel@tonic-gate */
108*7c478bd9Sstevel@tonic-gate void
prom_starfire_rm_cpu(uint_t cpuid)109*7c478bd9Sstevel@tonic-gate prom_starfire_rm_cpu(uint_t cpuid)
110*7c478bd9Sstevel@tonic-gate {
111*7c478bd9Sstevel@tonic-gate cell_t ci[4];
112*7c478bd9Sstevel@tonic-gate
113*7c478bd9Sstevel@tonic-gate ci[0] = p1275_ptr2cell("SUNW,UE10000,rm-cpu"); /* name */
114*7c478bd9Sstevel@tonic-gate ci[1] = (cell_t)1; /* #argument cells */
115*7c478bd9Sstevel@tonic-gate ci[2] = (cell_t)0; /* #result cells */
116*7c478bd9Sstevel@tonic-gate ci[3] = p1275_uint2cell(cpuid);
117*7c478bd9Sstevel@tonic-gate
118*7c478bd9Sstevel@tonic-gate promif_preprom();
119*7c478bd9Sstevel@tonic-gate (void) p1275_cif_handler(&ci);
120*7c478bd9Sstevel@tonic-gate promif_postprom();
121*7c478bd9Sstevel@tonic-gate }
122*7c478bd9Sstevel@tonic-gate
123*7c478bd9Sstevel@tonic-gate /*
124*7c478bd9Sstevel@tonic-gate * Mark the cpu represented by cpuid as cpu0. Returns zero for
125*7c478bd9Sstevel@tonic-gate * success and non-zero for failure.
126*7c478bd9Sstevel@tonic-gate */
127*7c478bd9Sstevel@tonic-gate int
prom_starfire_move_cpu0(uint_t cpuid)128*7c478bd9Sstevel@tonic-gate prom_starfire_move_cpu0(uint_t cpuid)
129*7c478bd9Sstevel@tonic-gate {
130*7c478bd9Sstevel@tonic-gate cell_t ci[5];
131*7c478bd9Sstevel@tonic-gate int rv;
132*7c478bd9Sstevel@tonic-gate
133*7c478bd9Sstevel@tonic-gate ci[0] = p1275_ptr2cell("SUNW,UE10000,move-cpu0"); /* name */
134*7c478bd9Sstevel@tonic-gate ci[1] = (cell_t)1; /* #argument cells */
135*7c478bd9Sstevel@tonic-gate ci[2] = (cell_t)1; /* #result cells */
136*7c478bd9Sstevel@tonic-gate ci[3] = p1275_uint2cell(cpuid);
137*7c478bd9Sstevel@tonic-gate
138*7c478bd9Sstevel@tonic-gate promif_preprom();
139*7c478bd9Sstevel@tonic-gate rv = p1275_cif_handler(&ci);
140*7c478bd9Sstevel@tonic-gate promif_postprom();
141*7c478bd9Sstevel@tonic-gate
142*7c478bd9Sstevel@tonic-gate return ((rv) ? -1 : p1275_cell2int(ci[4]));
143*7c478bd9Sstevel@tonic-gate }
144*7c478bd9Sstevel@tonic-gate
145*7c478bd9Sstevel@tonic-gate /*
146*7c478bd9Sstevel@tonic-gate * Perform initialization steps required for the console before
147*7c478bd9Sstevel@tonic-gate * moving cpu0. The console uses the bootbus SRAM of cpu0 for both
148*7c478bd9Sstevel@tonic-gate * input and output. The offsets of the console buffers are initialized
149*7c478bd9Sstevel@tonic-gate * for the bootbus SRAM of the new cpu0 represented by cpuid.
150*7c478bd9Sstevel@tonic-gate */
151*7c478bd9Sstevel@tonic-gate void
prom_starfire_init_console(uint_t cpuid)152*7c478bd9Sstevel@tonic-gate prom_starfire_init_console(uint_t cpuid)
153*7c478bd9Sstevel@tonic-gate {
154*7c478bd9Sstevel@tonic-gate cell_t ci[4];
155*7c478bd9Sstevel@tonic-gate
156*7c478bd9Sstevel@tonic-gate ci[0] = p1275_ptr2cell("SUNW,UE10000,init-console"); /* name */
157*7c478bd9Sstevel@tonic-gate ci[1] = (cell_t)1; /* #argument cells */
158*7c478bd9Sstevel@tonic-gate ci[2] = (cell_t)0; /* #result cells */
159*7c478bd9Sstevel@tonic-gate ci[3] = p1275_uint2cell(cpuid);
160*7c478bd9Sstevel@tonic-gate
161*7c478bd9Sstevel@tonic-gate promif_preprom();
162*7c478bd9Sstevel@tonic-gate (void) p1275_cif_handler(&ci);
163*7c478bd9Sstevel@tonic-gate promif_postprom();
164*7c478bd9Sstevel@tonic-gate }
165