1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright (c) 2012, Joyent, Inc. All rights reserved. 25 */ 26 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* Copyright (c) 1988 AT&T */ 33 /* All Rights Reserved */ 34 35 #include "dis_tables.h" 36 37 /* BEGIN CSTYLED */ 38 39 /* 40 * Disassembly begins in dis_distable, which is equivalent to the One-byte 41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 42 * decoding loops then traverse out through the other tables as necessary to 43 * decode a given instruction. 44 * 45 * The behavior of this file can be controlled by one of the following flags: 46 * 47 * DIS_TEXT Include text for disassembly 48 * DIS_MEM Include memory-size calculations 49 * 50 * Either or both of these can be defined. 51 * 52 * This file is not, and will never be, cstyled. If anything, the tables should 53 * be taken out another tab stop or two so nothing overlaps. 54 */ 55 56 /* 57 * These functions must be provided for the consumer to do disassembly. 58 */ 59 #ifdef DIS_TEXT 60 extern char *strncpy(char *, const char *, size_t); 61 extern size_t strlen(const char *); 62 extern int strcmp(const char *, const char *); 63 extern int strncmp(const char *, const char *, size_t); 64 extern size_t strlcat(char *, const char *, size_t); 65 #endif 66 67 68 #define TERM 0 /* used to indicate that the 'indirect' */ 69 /* field terminates - no pointer. */ 70 71 /* Used to decode instructions. */ 72 typedef struct instable { 73 struct instable *it_indirect; /* for decode op codes */ 74 uchar_t it_adrmode; 75 #ifdef DIS_TEXT 76 char it_name[NCPS]; 77 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 78 #endif 79 #ifdef DIS_MEM 80 uint_t it_size:16; 81 #endif 82 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 83 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 84 uint_t it_invalid32:1; /* invalid in IA32 */ 85 uint_t it_stackop:1; /* push/pop stack operation */ 86 } instable_t; 87 88 /* 89 * Instruction formats. 90 */ 91 enum { 92 UNKNOWN, 93 MRw, 94 IMlw, 95 IMw, 96 IR, 97 OA, 98 AO, 99 MS, 100 SM, 101 Mv, 102 Mw, 103 M, /* register or memory */ 104 MG9, /* register or memory in group 9 (prefix optional) */ 105 Mb, /* register or memory, always byte sized */ 106 MO, /* memory only (no registers) */ 107 PREF, 108 SWAPGS_RDTSCP, 109 MONITOR_MWAIT, 110 R, 111 RA, 112 SEG, 113 MR, 114 RM, 115 RM_66r, /* RM, but with a required 0x66 prefix */ 116 IA, 117 MA, 118 SD, 119 AD, 120 SA, 121 D, 122 INM, 123 SO, 124 BD, 125 I, 126 P, 127 V, 128 DSHIFT, /* for double shift that has an 8-bit immediate */ 129 U, 130 OVERRIDE, 131 NORM, /* instructions w/o ModR/M byte, no memory access */ 132 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 133 O, /* for call */ 134 JTAB, /* jump table */ 135 IMUL, /* for 186 iimul instr */ 136 CBW, /* so data16 can be evaluated for cbw and variants */ 137 MvI, /* for 186 logicals */ 138 ENTER, /* for 186 enter instr */ 139 RMw, /* for 286 arpl instr */ 140 Ib, /* for push immediate byte */ 141 F, /* for 287 instructions */ 142 FF, /* for 287 instructions */ 143 FFC, /* for 287 instructions */ 144 DM, /* 16-bit data */ 145 AM, /* 16-bit addr */ 146 LSEG, /* for 3-bit seg reg encoding */ 147 MIb, /* for 386 logicals */ 148 SREG, /* for 386 special registers */ 149 PREFIX, /* a REP instruction prefix */ 150 LOCK, /* a LOCK instruction prefix */ 151 INT3, /* The int 3 instruction, which has a fake operand */ 152 INTx, /* The normal int instruction, with explicit int num */ 153 DSHIFTcl, /* for double shift that implicitly uses %cl */ 154 CWD, /* so data16 can be evaluated for cwd and variants */ 155 RET, /* single immediate 16-bit operand */ 156 MOVZ, /* for movs and movz, with different size operands */ 157 CRC32, /* for crc32, with different size operands */ 158 XADDB, /* for xaddb */ 159 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 160 MOVBE, /* movbe instruction */ 161 162 /* 163 * MMX/SIMD addressing modes. 164 */ 165 166 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 167 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 168 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 169 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 170 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 171 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 172 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 173 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 174 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 175 MMOSH, /* Prefixable MMX mm,imm8 */ 176 MM, /* MMX/SIMD-Int mm/mem -> mm */ 177 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 178 MMSH, /* MMX mm,imm8 */ 179 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 180 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 181 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 182 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 183 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 184 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 185 XMMOM, /* Prefixable SIMD xmm -> mem */ 186 XMMOMS, /* Prefixable SIMD mem -> xmm */ 187 XMM, /* SIMD xmm/mem -> xmm */ 188 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 189 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 190 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 191 XMM3P, /* SIMD xmm -> r32,imm8 */ 192 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 193 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 194 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 195 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 196 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 197 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 198 XMMS, /* SIMD xmm -> xmm/mem */ 199 XMMM, /* SIMD mem -> xmm */ 200 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 201 XMMMS, /* SIMD xmm -> mem */ 202 XMM3MX, /* SIMD r32/mem -> xmm */ 203 XMM3MXS, /* SIMD xmm -> r32/mem */ 204 XMMSH, /* SIMD xmm,imm8 */ 205 XMMXM3, /* SIMD xmm/mem -> r32 */ 206 XMMX3, /* SIMD xmm -> r32 */ 207 XMMXMM, /* SIMD xmm/mem -> mm */ 208 XMMMX, /* SIMD mm -> xmm */ 209 XMMXM, /* SIMD xmm -> mm */ 210 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 211 XMM2I, /* SIMD xmm, imm, imm */ 212 XMMFENCE, /* SIMD lfence or mfence */ 213 XMMSFNC, /* SIMD sfence (none or mem) */ 214 XGETBV_XSETBV, 215 VEX_NONE, /* VEX no operand */ 216 VEX_MO, /* VEX mod_rm -> implicit reg */ 217 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 218 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 219 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 220 VEX_MX, /* VEX mod_rm -> mod_reg */ 221 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 222 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 223 VEX_MR, /* VEX mod_rm -> mod_reg */ 224 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 225 VEX_RX, /* VEX mod_reg -> mod_rm */ 226 VEX_RR, /* VEX mod_rm -> mod_reg */ 227 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 228 VEX_RM, /* VEX mod_reg -> mod_rm */ 229 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 230 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 231 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 232 VMxo, /* VMx instruction with optional prefix */ 233 SVM /* AMD SVM instructions */ 234 }; 235 236 /* 237 * VEX prefixes 238 */ 239 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 240 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 241 242 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 243 244 /* 245 ** Register numbers for the i386 246 */ 247 #define EAX_REGNO 0 248 #define ECX_REGNO 1 249 #define EDX_REGNO 2 250 #define EBX_REGNO 3 251 #define ESP_REGNO 4 252 #define EBP_REGNO 5 253 #define ESI_REGNO 6 254 #define EDI_REGNO 7 255 256 /* 257 * modes for immediate values 258 */ 259 #define MODE_NONE 0 260 #define MODE_IPREL 1 /* signed IP relative value */ 261 #define MODE_SIGNED 2 /* sign extended immediate */ 262 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 263 #define MODE_OFFSET 4 /* offset part of an address */ 264 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 265 266 /* 267 * The letters used in these macros are: 268 * IND - indirect to another to another table 269 * "T" - means to Terminate indirections (this is the final opcode) 270 * "S" - means "operand length suffix required" 271 * "NS" - means "no suffix" which is the operand length suffix of the opcode 272 * "Z" - means instruction size arg required 273 * "u" - means the opcode is invalid in IA32 but valid in amd64 274 * "x" - means the opcode is invalid in amd64, but not IA32 275 * "y" - means the operand size is always 64 bits in 64 bit mode 276 * "p" - means push/pop stack operation 277 */ 278 279 #if defined(DIS_TEXT) && defined(DIS_MEM) 280 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 281 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 282 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 283 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 284 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 285 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 286 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 287 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 288 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 289 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 290 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 291 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 292 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 293 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 294 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 295 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 296 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 297 #elif defined(DIS_TEXT) 298 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 299 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 300 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 301 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 302 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 303 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 304 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 305 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 306 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 307 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 308 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 309 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 310 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 311 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 312 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 313 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 314 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 315 #elif defined(DIS_MEM) 316 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 317 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 318 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 319 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 320 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 321 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 322 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 323 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 324 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 325 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 326 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 327 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 328 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 329 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 330 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 331 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 332 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 333 #else 334 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 335 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 336 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 337 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 338 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 339 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 340 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 341 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 342 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 343 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 344 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 345 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 346 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 347 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 348 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 349 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 350 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 351 #endif 352 353 #ifdef DIS_TEXT 354 /* 355 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 356 */ 357 const char *const dis_addr16[3][8] = { 358 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 359 "(%bx)", 360 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 361 "(%bx)", 362 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 363 "(%bx)", 364 }; 365 366 367 /* 368 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 369 */ 370 const char *const dis_addr32_mode0[16] = { 371 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 372 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 373 }; 374 375 const char *const dis_addr32_mode12[16] = { 376 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 377 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 378 }; 379 380 /* 381 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 382 */ 383 const char *const dis_addr64_mode0[16] = { 384 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 385 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 386 }; 387 const char *const dis_addr64_mode12[16] = { 388 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 389 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 390 }; 391 392 /* 393 * decode for scale from SIB byte 394 */ 395 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 396 397 /* 398 * register decoding for normal references to registers (ie. not addressing) 399 */ 400 const char *const dis_REG8[16] = { 401 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 402 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 403 }; 404 405 const char *const dis_REG8_REX[16] = { 406 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 407 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 408 }; 409 410 const char *const dis_REG16[16] = { 411 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 412 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 413 }; 414 415 const char *const dis_REG32[16] = { 416 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 417 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 418 }; 419 420 const char *const dis_REG64[16] = { 421 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 422 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 423 }; 424 425 const char *const dis_DEBUGREG[16] = { 426 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 427 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 428 }; 429 430 const char *const dis_CONTROLREG[16] = { 431 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 432 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 433 }; 434 435 const char *const dis_TESTREG[16] = { 436 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 437 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 438 }; 439 440 const char *const dis_MMREG[16] = { 441 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 442 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 443 }; 444 445 const char *const dis_XMMREG[16] = { 446 "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", 447 "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15" 448 }; 449 450 const char *const dis_YMMREG[16] = { 451 "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7", 452 "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15" 453 }; 454 455 const char *const dis_SEGREG[16] = { 456 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 457 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 458 }; 459 460 /* 461 * SIMD predicate suffixes 462 */ 463 const char *const dis_PREDSUFFIX[8] = { 464 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 465 }; 466 467 const char *const dis_AVXvgrp7[3][8] = { 468 /*0 1 2 3 4 5 6 7*/ 469 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 470 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 471 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 472 }; 473 474 #endif /* DIS_TEXT */ 475 476 /* 477 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 478 */ 479 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 480 481 /* 482 * "decode table" for pause and clflush instructions 483 */ 484 const instable_t dis_opPause = TNS("pause", NORM); 485 486 /* 487 * Decode table for 0x0F00 opcodes 488 */ 489 const instable_t dis_op0F00[8] = { 490 491 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 492 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 493 }; 494 495 496 /* 497 * Decode table for 0x0F01 opcodes 498 */ 499 const instable_t dis_op0F01[8] = { 500 501 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 502 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 503 }; 504 505 /* 506 * Decode table for 0x0F18 opcodes -- SIMD prefetch 507 */ 508 const instable_t dis_op0F18[8] = { 509 510 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 511 /* [4] */ INVALID, INVALID, INVALID, INVALID, 512 }; 513 514 /* 515 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 516 */ 517 const instable_t dis_op0FAE[8] = { 518 /* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M), 519 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 520 }; 521 522 /* 523 * Decode table for 0x0FBA opcodes 524 */ 525 526 const instable_t dis_op0FBA[8] = { 527 528 /* [0] */ INVALID, INVALID, INVALID, INVALID, 529 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 530 }; 531 532 /* 533 * Decode table for 0x0FC7 opcode (group 9) 534 */ 535 536 const instable_t dis_op0FC7[8] = { 537 538 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, INVALID, 539 /* [4] */ INVALID, INVALID, TNS("vmptrld",MG9), TNS("vmptrst",MG9), 540 }; 541 542 /* 543 * Decode table for 0x0FC7 opcode (group 9) mode 3 544 */ 545 546 const instable_t dis_op0FC7m3[8] = { 547 548 /* [0] */ INVALID, INVALID, INVALID, INVALID, 549 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), INVALID, 550 }; 551 552 /* 553 * Decode table for 0x0FC7 opcode with 0x66 prefix 554 */ 555 556 const instable_t dis_op660FC7[8] = { 557 558 /* [0] */ INVALID, INVALID, INVALID, INVALID, 559 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 560 }; 561 562 /* 563 * Decode table for 0x0FC7 opcode with 0xF3 prefix 564 */ 565 566 const instable_t dis_opF30FC7[8] = { 567 568 /* [0] */ INVALID, INVALID, INVALID, INVALID, 569 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 570 }; 571 572 /* 573 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 574 * 575 *bit pattern: 0000 1111 1100 1reg 576 */ 577 const instable_t dis_op0FC8[4] = { 578 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 579 }; 580 581 /* 582 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 583 */ 584 const instable_t dis_op0F7123[4][8] = { 585 { 586 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 587 /* .4 */ INVALID, INVALID, INVALID, INVALID, 588 }, { 589 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 590 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 591 }, { 592 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 593 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 594 }, { 595 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 596 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 597 } }; 598 599 /* 600 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 601 */ 602 const instable_t dis_opSIMD7123[32] = { 603 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 604 /* .4 */ INVALID, INVALID, INVALID, INVALID, 605 606 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 607 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 608 609 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 610 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 611 612 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 613 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 614 }; 615 616 /* 617 * SIMD instructions have been wedged into the existing IA32 instruction 618 * set through the use of prefixes. That is, while 0xf0 0x58 may be 619 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 620 * instruction - addss. At present, three prefixes have been coopted in 621 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 622 * following tables are used to provide the prefixed instruction names. 623 * The arrays are sparse, but they're fast. 624 */ 625 626 /* 627 * Decode table for SIMD instructions with the address size (0x66) prefix. 628 */ 629 const instable_t dis_opSIMDdata16[256] = { 630 /* [00] */ INVALID, INVALID, INVALID, INVALID, 631 /* [04] */ INVALID, INVALID, INVALID, INVALID, 632 /* [08] */ INVALID, INVALID, INVALID, INVALID, 633 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 634 635 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 636 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 637 /* [18] */ INVALID, INVALID, INVALID, INVALID, 638 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 639 640 /* [20] */ INVALID, INVALID, INVALID, INVALID, 641 /* [24] */ INVALID, INVALID, INVALID, INVALID, 642 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 643 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 644 645 /* [30] */ INVALID, INVALID, INVALID, INVALID, 646 /* [34] */ INVALID, INVALID, INVALID, INVALID, 647 /* [38] */ INVALID, INVALID, INVALID, INVALID, 648 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 649 650 /* [40] */ INVALID, INVALID, INVALID, INVALID, 651 /* [44] */ INVALID, INVALID, INVALID, INVALID, 652 /* [48] */ INVALID, INVALID, INVALID, INVALID, 653 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 654 655 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 656 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 657 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 658 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 659 660 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 661 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 662 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 663 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 664 665 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 666 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 667 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 668 /* [7C] */ INVALID, INVALID, TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 669 670 /* [80] */ INVALID, INVALID, INVALID, INVALID, 671 /* [84] */ INVALID, INVALID, INVALID, INVALID, 672 /* [88] */ INVALID, INVALID, INVALID, INVALID, 673 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 674 675 /* [90] */ INVALID, INVALID, INVALID, INVALID, 676 /* [94] */ INVALID, INVALID, INVALID, INVALID, 677 /* [98] */ INVALID, INVALID, INVALID, INVALID, 678 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 679 680 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 681 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 682 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 683 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 684 685 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 686 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 687 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 688 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 689 690 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 691 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 692 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 693 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 694 695 /* [D0] */ INVALID, TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 696 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 697 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 698 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 699 700 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 701 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 702 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 703 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 704 705 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 706 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 707 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 708 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 709 }; 710 711 const instable_t dis_opAVX660F[256] = { 712 /* [00] */ INVALID, INVALID, INVALID, INVALID, 713 /* [04] */ INVALID, INVALID, INVALID, INVALID, 714 /* [08] */ INVALID, INVALID, INVALID, INVALID, 715 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 716 717 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 718 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 719 /* [18] */ INVALID, INVALID, INVALID, INVALID, 720 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 721 722 /* [20] */ INVALID, INVALID, INVALID, INVALID, 723 /* [24] */ INVALID, INVALID, INVALID, INVALID, 724 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 725 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 726 727 /* [30] */ INVALID, INVALID, INVALID, INVALID, 728 /* [34] */ INVALID, INVALID, INVALID, INVALID, 729 /* [38] */ INVALID, INVALID, INVALID, INVALID, 730 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 731 732 /* [40] */ INVALID, INVALID, INVALID, INVALID, 733 /* [44] */ INVALID, INVALID, INVALID, INVALID, 734 /* [48] */ INVALID, INVALID, INVALID, INVALID, 735 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 736 737 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 738 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 739 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 740 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 741 742 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 743 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 744 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 745 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 746 747 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 748 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 749 /* [78] */ INVALID, INVALID, INVALID, INVALID, 750 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 751 752 /* [80] */ INVALID, INVALID, INVALID, INVALID, 753 /* [84] */ INVALID, INVALID, INVALID, INVALID, 754 /* [88] */ INVALID, INVALID, INVALID, INVALID, 755 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 756 757 /* [90] */ INVALID, INVALID, INVALID, INVALID, 758 /* [94] */ INVALID, INVALID, INVALID, INVALID, 759 /* [98] */ INVALID, INVALID, INVALID, INVALID, 760 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 761 762 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 763 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 764 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 765 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 766 767 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 768 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 769 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 770 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 771 772 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 773 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 774 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 775 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 776 777 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 778 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 779 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 780 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 781 782 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 783 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 784 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 785 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 786 787 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 788 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 789 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 790 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 791 }; 792 793 /* 794 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 795 */ 796 const instable_t dis_opSIMDrepnz[256] = { 797 /* [00] */ INVALID, INVALID, INVALID, INVALID, 798 /* [04] */ INVALID, INVALID, INVALID, INVALID, 799 /* [08] */ INVALID, INVALID, INVALID, INVALID, 800 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 801 802 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), INVALID, INVALID, 803 /* [14] */ INVALID, INVALID, INVALID, INVALID, 804 /* [18] */ INVALID, INVALID, INVALID, INVALID, 805 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 806 807 /* [20] */ INVALID, INVALID, INVALID, INVALID, 808 /* [24] */ INVALID, INVALID, INVALID, INVALID, 809 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 810 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 811 812 /* [30] */ INVALID, INVALID, INVALID, INVALID, 813 /* [34] */ INVALID, INVALID, INVALID, INVALID, 814 /* [38] */ INVALID, INVALID, INVALID, INVALID, 815 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 816 817 /* [40] */ INVALID, INVALID, INVALID, INVALID, 818 /* [44] */ INVALID, INVALID, INVALID, INVALID, 819 /* [48] */ INVALID, INVALID, INVALID, INVALID, 820 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 821 822 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 823 /* [54] */ INVALID, INVALID, INVALID, INVALID, 824 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 825 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 826 827 /* [60] */ INVALID, INVALID, INVALID, INVALID, 828 /* [64] */ INVALID, INVALID, INVALID, INVALID, 829 /* [68] */ INVALID, INVALID, INVALID, INVALID, 830 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 831 832 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 833 /* [74] */ INVALID, INVALID, INVALID, INVALID, 834 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 835 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 836 837 /* [80] */ INVALID, INVALID, INVALID, INVALID, 838 /* [84] */ INVALID, INVALID, INVALID, INVALID, 839 /* [88] */ INVALID, INVALID, INVALID, INVALID, 840 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 841 842 /* [90] */ INVALID, INVALID, INVALID, INVALID, 843 /* [94] */ INVALID, INVALID, INVALID, INVALID, 844 /* [98] */ INVALID, INVALID, INVALID, INVALID, 845 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 846 847 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 848 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 849 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 850 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 851 852 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 853 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 854 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 855 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 856 857 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 858 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 859 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 860 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 861 862 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 863 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 864 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 865 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 866 867 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 868 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 869 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 870 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 871 872 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 873 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 874 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 875 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 876 }; 877 878 const instable_t dis_opAVXF20F[256] = { 879 /* [00] */ INVALID, INVALID, INVALID, INVALID, 880 /* [04] */ INVALID, INVALID, INVALID, INVALID, 881 /* [08] */ INVALID, INVALID, INVALID, INVALID, 882 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 883 884 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 885 /* [14] */ INVALID, INVALID, INVALID, INVALID, 886 /* [18] */ INVALID, INVALID, INVALID, INVALID, 887 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 888 889 /* [20] */ INVALID, INVALID, INVALID, INVALID, 890 /* [24] */ INVALID, INVALID, INVALID, INVALID, 891 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 892 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 893 894 /* [30] */ INVALID, INVALID, INVALID, INVALID, 895 /* [34] */ INVALID, INVALID, INVALID, INVALID, 896 /* [38] */ INVALID, INVALID, INVALID, INVALID, 897 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 898 899 /* [40] */ INVALID, INVALID, INVALID, INVALID, 900 /* [44] */ INVALID, INVALID, INVALID, INVALID, 901 /* [48] */ INVALID, INVALID, INVALID, INVALID, 902 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 903 904 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 905 /* [54] */ INVALID, INVALID, INVALID, INVALID, 906 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 907 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 908 909 /* [60] */ INVALID, INVALID, INVALID, INVALID, 910 /* [64] */ INVALID, INVALID, INVALID, INVALID, 911 /* [68] */ INVALID, INVALID, INVALID, INVALID, 912 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 913 914 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 915 /* [74] */ INVALID, INVALID, INVALID, INVALID, 916 /* [78] */ INVALID, INVALID, INVALID, INVALID, 917 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 918 919 /* [80] */ INVALID, INVALID, INVALID, INVALID, 920 /* [84] */ INVALID, INVALID, INVALID, INVALID, 921 /* [88] */ INVALID, INVALID, INVALID, INVALID, 922 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 923 924 /* [90] */ INVALID, INVALID, INVALID, INVALID, 925 /* [94] */ INVALID, INVALID, INVALID, INVALID, 926 /* [98] */ INVALID, INVALID, INVALID, INVALID, 927 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 928 929 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 930 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 931 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 932 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 933 934 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 935 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 936 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 937 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 938 939 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 940 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 941 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 942 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 943 944 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 945 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 946 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 947 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 948 949 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 950 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 951 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 952 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 953 954 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 955 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 956 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 957 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 958 }; 959 960 /* 961 * Decode table for SIMD instructions with the repz (0xf3) prefix. 962 */ 963 const instable_t dis_opSIMDrepz[256] = { 964 /* [00] */ INVALID, INVALID, INVALID, INVALID, 965 /* [04] */ INVALID, INVALID, INVALID, INVALID, 966 /* [08] */ INVALID, INVALID, INVALID, INVALID, 967 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 968 969 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), INVALID, INVALID, 970 /* [14] */ INVALID, INVALID, INVALID, INVALID, 971 /* [18] */ INVALID, INVALID, INVALID, INVALID, 972 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 973 974 /* [20] */ INVALID, INVALID, INVALID, INVALID, 975 /* [24] */ INVALID, INVALID, INVALID, INVALID, 976 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 977 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 978 979 /* [30] */ INVALID, INVALID, INVALID, INVALID, 980 /* [34] */ INVALID, INVALID, INVALID, INVALID, 981 /* [38] */ INVALID, INVALID, INVALID, INVALID, 982 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 983 984 /* [40] */ INVALID, INVALID, INVALID, INVALID, 985 /* [44] */ INVALID, INVALID, INVALID, INVALID, 986 /* [48] */ INVALID, INVALID, INVALID, INVALID, 987 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 988 989 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 990 /* [54] */ INVALID, INVALID, INVALID, INVALID, 991 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 992 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 993 994 /* [60] */ INVALID, INVALID, INVALID, INVALID, 995 /* [64] */ INVALID, INVALID, INVALID, INVALID, 996 /* [68] */ INVALID, INVALID, INVALID, INVALID, 997 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 998 999 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1000 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1001 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1002 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1003 1004 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1005 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1006 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1008 1009 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1010 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1011 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1012 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1013 1014 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1015 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1016 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1017 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1018 1019 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1020 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1021 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1022 /* [BC] */ INVALID, TS("lzcnt",MRw), INVALID, INVALID, 1023 1024 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1025 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1026 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1028 1029 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1030 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1031 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1033 1034 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1035 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1036 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1037 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1038 1039 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1040 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1041 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1042 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1043 }; 1044 1045 const instable_t dis_opAVXF30F[256] = { 1046 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1047 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1048 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1049 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1050 1051 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1052 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1053 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1054 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1055 1056 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1057 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1058 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1059 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1060 1061 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1062 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1063 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1064 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1065 1066 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1067 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1068 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1069 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1070 1071 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1072 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1073 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1074 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1075 1076 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1077 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1078 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1079 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1080 1081 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1082 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1085 1086 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1087 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1090 1091 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1092 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1095 1096 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1097 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1098 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1100 1101 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1102 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1105 1106 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1107 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1108 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1110 1111 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1112 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1115 1116 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1117 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1118 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1119 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1120 1121 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1122 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1123 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1124 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1125 }; 1126 /* 1127 * The following two tables are used to encode crc32 and movbe 1128 * since they share the same opcodes. 1129 */ 1130 const instable_t dis_op0F38F0[2] = { 1131 /* [00] */ TNS("crc32b",CRC32), 1132 TS("movbe",MOVBE), 1133 }; 1134 1135 const instable_t dis_op0F38F1[2] = { 1136 /* [00] */ TS("crc32",CRC32), 1137 TS("movbe",MOVBE), 1138 }; 1139 1140 const instable_t dis_op0F38[256] = { 1141 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1142 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1143 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1144 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1145 1146 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1147 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1148 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1149 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1150 1151 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 1152 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 1153 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 1154 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1155 1156 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 1157 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 1158 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 1159 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 1160 1161 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 1162 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1163 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1164 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1165 1166 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1167 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1168 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1169 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1170 1171 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1172 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1173 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1174 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1175 1176 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1177 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1178 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1179 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1180 1181 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),INVALID, INVALID, 1182 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1183 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1184 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1185 1186 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1187 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1188 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1189 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1190 1191 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1192 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1193 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1194 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1195 1196 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1197 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1198 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1199 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1200 1201 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1202 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1203 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1204 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1205 1206 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1207 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1208 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 1209 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 1210 1211 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1212 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1213 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1214 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1215 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1216 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1217 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1218 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1219 }; 1220 1221 const instable_t dis_opAVX660F38[256] = { 1222 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 1223 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 1224 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 1225 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 1226 1227 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 1228 /* [14] */ INVALID, INVALID, INVALID, TNSZ("vptest",VEX_RRI,16), 1229 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 1230 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 1231 1232 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 1233 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 1234 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 1235 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 1236 1237 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 1238 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),INVALID, TNSZ("vpcmpgtq",VEX_RMrX,16), 1239 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 1240 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 1241 1242 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 1243 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1244 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1245 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1246 1247 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1248 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1250 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1251 1252 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1253 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1254 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1255 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1256 1257 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1258 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1260 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1261 1262 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1263 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1265 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1266 1267 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1268 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1270 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1271 1272 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1273 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1275 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1276 1277 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1278 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1279 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1280 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1281 1282 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1283 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1285 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1286 1287 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1288 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 1290 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 1291 1292 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1293 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1294 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1295 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1296 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1297 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1298 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1299 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1300 }; 1301 1302 const instable_t dis_op0F3A[256] = { 1303 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1304 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1305 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 1306 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 1307 1308 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1309 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 1310 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1311 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1312 1313 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 1314 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1315 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1316 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1317 1318 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1319 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1320 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1321 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1322 1323 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 1324 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 1325 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1326 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1327 1328 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1329 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1330 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1331 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1332 1333 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 1334 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1335 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1336 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1337 1338 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1339 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1340 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1342 1343 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1344 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1345 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1347 1348 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1349 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1350 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1351 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1352 1353 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1354 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1355 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1356 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1357 1358 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1359 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1360 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1361 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1362 1363 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1364 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1365 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1367 1368 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1369 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1370 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 1372 1373 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1374 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1375 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1376 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1377 1378 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1379 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1380 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1381 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1382 }; 1383 1384 const instable_t dis_opAVX660F3A[256] = { 1385 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1386 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 1387 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 1388 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 1389 1390 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1391 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 1392 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 1393 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 1394 1395 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 1396 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1397 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1398 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1399 1400 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1401 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1402 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1403 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1404 1405 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 1406 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, INVALID, INVALID, 1407 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 1408 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 1409 1410 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1411 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1412 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1413 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1414 1415 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 1416 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1417 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1418 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1419 1420 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1421 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1422 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1423 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1424 1425 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1426 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1427 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1428 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1429 1430 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1431 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1432 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1433 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1434 1435 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1436 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1437 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1438 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1439 1440 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1441 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1442 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1443 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1444 1445 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1446 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1447 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1448 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1449 1450 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1451 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1452 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1453 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 1454 1455 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1456 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1457 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1458 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1459 1460 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1461 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1462 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1463 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1464 }; 1465 1466 /* 1467 * Decode table for 0x0F opcodes 1468 */ 1469 1470 const instable_t dis_op0F[16][16] = { 1471 { 1472 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 1473 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 1474 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 1475 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1476 }, { 1477 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 1478 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 1479 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 1480 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 1481 }, { 1482 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 1483 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 1484 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 1485 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 1486 }, { 1487 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 1488 /* [34] */ TNSx("sysenter",NORM), TNSx("sysexit",NORM), INVALID, INVALID, 1489 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1490 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1491 }, { 1492 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 1493 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 1494 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 1495 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 1496 }, { 1497 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 1498 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 1499 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 1500 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 1501 }, { 1502 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 1503 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 1504 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 1505 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 1506 }, { 1507 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 1508 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 1509 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 1510 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 1511 }, { 1512 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 1513 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 1514 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 1515 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 1516 }, { 1517 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 1518 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 1519 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 1520 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 1521 }, { 1522 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 1523 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 1524 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 1525 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 1526 }, { 1527 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 1528 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 1529 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 1530 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 1531 }, { 1532 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 1533 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 1534 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1535 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1536 }, { 1537 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 1538 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 1539 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 1540 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 1541 }, { 1542 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 1543 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 1544 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 1545 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 1546 }, { 1547 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 1548 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 1549 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 1550 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 1551 } }; 1552 1553 const instable_t dis_opAVX0F[16][16] = { 1554 { 1555 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1556 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1557 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1558 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1559 }, { 1560 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 1561 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 1562 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1563 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1564 }, { 1565 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1566 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1567 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 1568 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 1569 }, { 1570 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1571 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1572 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1573 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1574 }, { 1575 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1576 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1577 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1578 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1579 }, { 1580 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 1581 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 1582 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 1583 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 1584 }, { 1585 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1586 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1587 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1588 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1589 }, { 1590 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1591 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 1592 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1593 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1594 }, { 1595 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1596 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1597 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1598 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1599 }, { 1600 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1601 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1602 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1604 }, { 1605 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1606 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1607 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1608 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 1609 }, { 1610 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1611 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1612 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1613 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1614 }, { 1615 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 1616 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 1617 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1619 }, { 1620 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1621 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1622 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1623 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1624 }, { 1625 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1626 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1627 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1628 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1629 }, { 1630 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1631 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1632 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1633 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1634 } }; 1635 1636 /* 1637 * Decode table for 0x80 opcodes 1638 */ 1639 1640 const instable_t dis_op80[8] = { 1641 1642 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 1643 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 1644 }; 1645 1646 1647 /* 1648 * Decode table for 0x81 opcodes. 1649 */ 1650 1651 const instable_t dis_op81[8] = { 1652 1653 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 1654 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 1655 }; 1656 1657 1658 /* 1659 * Decode table for 0x82 opcodes. 1660 */ 1661 1662 const instable_t dis_op82[8] = { 1663 1664 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 1665 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 1666 }; 1667 /* 1668 * Decode table for 0x83 opcodes. 1669 */ 1670 1671 const instable_t dis_op83[8] = { 1672 1673 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 1674 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 1675 }; 1676 1677 /* 1678 * Decode table for 0xC0 opcodes. 1679 */ 1680 1681 const instable_t dis_opC0[8] = { 1682 1683 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 1684 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 1685 }; 1686 1687 /* 1688 * Decode table for 0xD0 opcodes. 1689 */ 1690 1691 const instable_t dis_opD0[8] = { 1692 1693 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 1694 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 1695 }; 1696 1697 /* 1698 * Decode table for 0xC1 opcodes. 1699 * 186 instruction set 1700 */ 1701 1702 const instable_t dis_opC1[8] = { 1703 1704 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 1705 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 1706 }; 1707 1708 /* 1709 * Decode table for 0xD1 opcodes. 1710 */ 1711 1712 const instable_t dis_opD1[8] = { 1713 1714 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 1715 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 1716 }; 1717 1718 1719 /* 1720 * Decode table for 0xD2 opcodes. 1721 */ 1722 1723 const instable_t dis_opD2[8] = { 1724 1725 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 1726 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 1727 }; 1728 /* 1729 * Decode table for 0xD3 opcodes. 1730 */ 1731 1732 const instable_t dis_opD3[8] = { 1733 1734 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 1735 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 1736 }; 1737 1738 1739 /* 1740 * Decode table for 0xF6 opcodes. 1741 */ 1742 1743 const instable_t dis_opF6[8] = { 1744 1745 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 1746 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 1747 }; 1748 1749 1750 /* 1751 * Decode table for 0xF7 opcodes. 1752 */ 1753 1754 const instable_t dis_opF7[8] = { 1755 1756 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 1757 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 1758 }; 1759 1760 1761 /* 1762 * Decode table for 0xFE opcodes. 1763 */ 1764 1765 const instable_t dis_opFE[8] = { 1766 1767 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 1768 /* [4] */ INVALID, INVALID, INVALID, INVALID, 1769 }; 1770 /* 1771 * Decode table for 0xFF opcodes. 1772 */ 1773 1774 const instable_t dis_opFF[8] = { 1775 1776 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 1777 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 1778 }; 1779 1780 /* for 287 instructions, which are a mess to decode */ 1781 1782 const instable_t dis_opFP1n2[8][8] = { 1783 { 1784 /* bit pattern: 1101 1xxx MODxx xR/M */ 1785 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 1786 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 1787 }, { 1788 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 1789 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 1790 }, { 1791 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 1792 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 1793 }, { 1794 /* [3,0] */ TNS("fildl",M), INVALID, TNS("fistl",M), TNS("fistpl",M), 1795 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 1796 }, { 1797 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 1798 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 1799 }, { 1800 /* [5,0] */ TNSZ("fldl",M,8), INVALID, TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 1801 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 1802 }, { 1803 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 1804 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 1805 }, { 1806 /* [7,0] */ TNSZ("fild",M,2), INVALID, TNSZ("fist",M,2), TNSZ("fistp",M,2), 1807 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 1808 } }; 1809 1810 const instable_t dis_opFP3[8][8] = { 1811 { 1812 /* bit pattern: 1101 1xxx 11xx xREG */ 1813 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 1814 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 1815 }, { 1816 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 1817 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 1818 }, { 1819 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 1820 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 1821 }, { 1822 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 1823 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 1824 }, { 1825 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 1826 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 1827 }, { 1828 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 1829 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 1830 }, { 1831 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 1832 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 1833 }, { 1834 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 1835 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 1836 } }; 1837 1838 const instable_t dis_opFP4[4][8] = { 1839 { 1840 /* bit pattern: 1101 1001 111x xxxx */ 1841 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 1842 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 1843 }, { 1844 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 1845 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 1846 }, { 1847 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 1848 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 1849 }, { 1850 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 1851 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 1852 } }; 1853 1854 const instable_t dis_opFP5[8] = { 1855 /* bit pattern: 1101 1011 111x xxxx */ 1856 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 1857 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 1858 }; 1859 1860 const instable_t dis_opFP6[8] = { 1861 /* bit pattern: 1101 1011 11yy yxxx */ 1862 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 1863 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 1864 }; 1865 1866 const instable_t dis_opFP7[8] = { 1867 /* bit pattern: 1101 1010 11yy yxxx */ 1868 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 1869 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1870 }; 1871 1872 /* 1873 * Main decode table for the op codes. The first two nibbles 1874 * will be used as an index into the table. If there is a 1875 * a need to further decode an instruction, the array to be 1876 * referenced is indicated with the other two entries being 1877 * empty. 1878 */ 1879 1880 const instable_t dis_distable[16][16] = { 1881 { 1882 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 1883 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 1884 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 1885 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 1886 }, { 1887 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 1888 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 1889 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 1890 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 1891 }, { 1892 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 1893 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 1894 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 1895 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 1896 }, { 1897 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 1898 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 1899 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 1900 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 1901 }, { 1902 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 1903 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 1904 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 1905 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 1906 }, { 1907 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 1908 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 1909 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 1910 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 1911 }, { 1912 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw), 1913 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 1914 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 1915 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 1916 }, { 1917 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 1918 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 1919 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 1920 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 1921 }, { 1922 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 1923 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 1924 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 1925 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 1926 }, { 1927 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 1928 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 1929 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 1930 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNSx("sahf",NORM), TNSx("lahf",NORM), 1931 }, { 1932 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 1933 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 1934 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 1935 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 1936 }, { 1937 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 1938 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 1939 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 1940 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 1941 }, { 1942 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 1943 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 1944 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 1945 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 1946 }, { 1947 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 1948 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 1949 1950 /* 287 instructions. Note that although the indirect field */ 1951 /* indicates opFP1n2 for further decoding, this is not necessarily */ 1952 /* the case since the opFP arrays are not partitioned according to key1 */ 1953 /* and key2. opFP1n2 is given only to indicate that we haven't */ 1954 /* finished decoding the instruction. */ 1955 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 1956 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 1957 }, { 1958 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 1959 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 1960 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 1961 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 1962 }, { 1963 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 1964 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 1965 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 1966 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 1967 } }; 1968 1969 /* END CSTYLED */ 1970 1971 /* 1972 * common functions to decode and disassemble an x86 or amd64 instruction 1973 */ 1974 1975 /* 1976 * These are the individual fields of a REX prefix. Note that a REX 1977 * prefix with none of these set is still needed to: 1978 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 1979 * - access the %sil, %dil, %bpl, %spl registers 1980 */ 1981 #define REX_W 0x08 /* 64 bit operand size when set */ 1982 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 1983 #define REX_X 0x02 /* high order bit extension of SIB index field */ 1984 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 1985 1986 /* 1987 * These are the individual fields of a VEX prefix. 1988 */ 1989 #define VEX_R 0x08 /* REX.R in 1's complement form */ 1990 #define VEX_X 0x04 /* REX.X in 1's complement form */ 1991 #define VEX_B 0x02 /* REX.B in 1's complement form */ 1992 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 1993 #define VEX_L 0x04 1994 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 1995 #define VEX_m 0x1F /* VEX m-mmmm field */ 1996 #define VEX_v 0x78 /* VEX register specifier */ 1997 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 1998 1999 /* VEX m-mmmm field, only used by three bytes prefix */ 2000 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 2001 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 2002 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 2003 2004 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 2005 #define VEX_p_66 0x01 2006 #define VEX_p_F3 0x02 2007 #define VEX_p_F2 0x03 2008 2009 /* 2010 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2011 */ 2012 static int isize[] = {1, 2, 4, 4}; 2013 static int isize64[] = {1, 2, 4, 8}; 2014 2015 /* 2016 * Just a bunch of useful macros. 2017 */ 2018 #define WBIT(x) (x & 0x1) /* to get w bit */ 2019 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2020 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2021 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2022 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2023 2024 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2025 2026 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2027 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2028 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2029 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2030 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2031 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2032 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2033 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2034 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2035 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2036 2037 /* 2038 * Get the next byte and separate the op code into the high and low nibbles. 2039 */ 2040 static int 2041 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2042 { 2043 int byte; 2044 2045 /* 2046 * x86 instructions have a maximum length of 15 bytes. Bail out if 2047 * we try to read more. 2048 */ 2049 if (x->d86_len >= 15) 2050 return (x->d86_error = 1); 2051 2052 if (x->d86_error) 2053 return (1); 2054 byte = x->d86_get_byte(x->d86_data); 2055 if (byte < 0) 2056 return (x->d86_error = 1); 2057 x->d86_bytes[x->d86_len++] = byte; 2058 *low = byte & 0xf; /* ----xxxx low 4 bits */ 2059 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 2060 return (0); 2061 } 2062 2063 /* 2064 * Get and decode an SIB (scaled index base) byte 2065 */ 2066 static void 2067 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 2068 { 2069 int byte; 2070 2071 if (x->d86_error) 2072 return; 2073 2074 byte = x->d86_get_byte(x->d86_data); 2075 if (byte < 0) { 2076 x->d86_error = 1; 2077 return; 2078 } 2079 x->d86_bytes[x->d86_len++] = byte; 2080 2081 *base = byte & 0x7; 2082 *index = (byte >> 3) & 0x7; 2083 *ss = (byte >> 6) & 0x3; 2084 } 2085 2086 /* 2087 * Get the byte following the op code and separate it into the 2088 * mode, register, and r/m fields. 2089 */ 2090 static void 2091 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 2092 { 2093 if (x->d86_got_modrm == 0) { 2094 if (x->d86_rmindex == -1) 2095 x->d86_rmindex = x->d86_len; 2096 dtrace_get_SIB(x, mode, reg, r_m); 2097 x->d86_got_modrm = 1; 2098 } 2099 } 2100 2101 /* 2102 * Adjust register selection based on any REX prefix bits present. 2103 */ 2104 /*ARGSUSED*/ 2105 static void 2106 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 2107 { 2108 if (reg != NULL && r_m == NULL) { 2109 if (rex_prefix & REX_B) 2110 *reg += 8; 2111 } else { 2112 if (reg != NULL && (REX_R & rex_prefix) != 0) 2113 *reg += 8; 2114 if (r_m != NULL && (REX_B & rex_prefix) != 0) 2115 *r_m += 8; 2116 } 2117 } 2118 2119 /* 2120 * Adjust register selection based on any VEX prefix bits present. 2121 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 2122 */ 2123 /*ARGSUSED*/ 2124 static void 2125 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 2126 { 2127 if (reg != NULL && r_m == NULL) { 2128 if (!(vex_byte1 & VEX_B)) 2129 *reg += 8; 2130 } else { 2131 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 2132 *reg += 8; 2133 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 2134 *r_m += 8; 2135 } 2136 } 2137 2138 /* 2139 * Get an immediate operand of the given size, with sign extension. 2140 */ 2141 static void 2142 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 2143 { 2144 int i; 2145 int byte; 2146 int valsize; 2147 2148 if (x->d86_numopnds < opindex + 1) 2149 x->d86_numopnds = opindex + 1; 2150 2151 switch (wbit) { 2152 case BYTE_OPND: 2153 valsize = 1; 2154 break; 2155 case LONG_OPND: 2156 if (x->d86_opnd_size == SIZE16) 2157 valsize = 2; 2158 else if (x->d86_opnd_size == SIZE32) 2159 valsize = 4; 2160 else 2161 valsize = 8; 2162 break; 2163 case MM_OPND: 2164 case XMM_OPND: 2165 case YMM_OPND: 2166 case SEG_OPND: 2167 case CONTROL_OPND: 2168 case DEBUG_OPND: 2169 case TEST_OPND: 2170 valsize = size; 2171 break; 2172 case WORD_OPND: 2173 valsize = 2; 2174 break; 2175 } 2176 if (valsize < size) 2177 valsize = size; 2178 2179 if (x->d86_error) 2180 return; 2181 x->d86_opnd[opindex].d86_value = 0; 2182 for (i = 0; i < size; ++i) { 2183 byte = x->d86_get_byte(x->d86_data); 2184 if (byte < 0) { 2185 x->d86_error = 1; 2186 return; 2187 } 2188 x->d86_bytes[x->d86_len++] = byte; 2189 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 2190 } 2191 /* Do sign extension */ 2192 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 2193 for (; i < sizeof (uint64_t); i++) 2194 x->d86_opnd[opindex].d86_value |= 2195 (uint64_t)0xff << (i * 8); 2196 } 2197 #ifdef DIS_TEXT 2198 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2199 x->d86_opnd[opindex].d86_value_size = valsize; 2200 x->d86_imm_bytes += size; 2201 #endif 2202 } 2203 2204 /* 2205 * Get an ip relative operand of the given size, with sign extension. 2206 */ 2207 static void 2208 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 2209 { 2210 dtrace_imm_opnd(x, wbit, size, opindex); 2211 #ifdef DIS_TEXT 2212 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 2213 #endif 2214 } 2215 2216 /* 2217 * Check to see if there is a segment override prefix pending. 2218 * If so, print it in the current 'operand' location and set 2219 * the override flag back to false. 2220 */ 2221 /*ARGSUSED*/ 2222 static void 2223 dtrace_check_override(dis86_t *x, int opindex) 2224 { 2225 #ifdef DIS_TEXT 2226 if (x->d86_seg_prefix) { 2227 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 2228 x->d86_seg_prefix, PFIXLEN); 2229 } 2230 #endif 2231 x->d86_seg_prefix = NULL; 2232 } 2233 2234 2235 /* 2236 * Process a single instruction Register or Memory operand. 2237 * 2238 * mode = addressing mode from ModRM byte 2239 * r_m = r_m (or reg if mode == 3) field from ModRM byte 2240 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 2241 * o = index of operand that we are processing (0, 1 or 2) 2242 * 2243 * the value of reg or r_m must have already been adjusted for any REX prefix. 2244 */ 2245 /*ARGSUSED*/ 2246 static void 2247 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 2248 { 2249 int have_SIB = 0; /* flag presence of scale-index-byte */ 2250 uint_t ss; /* scale-factor from opcode */ 2251 uint_t index; /* index register number */ 2252 uint_t base; /* base register number */ 2253 int dispsize; /* size of displacement in bytes */ 2254 #ifdef DIS_TEXT 2255 char *opnd = x->d86_opnd[opindex].d86_opnd; 2256 #endif 2257 2258 if (x->d86_numopnds < opindex + 1) 2259 x->d86_numopnds = opindex + 1; 2260 2261 if (x->d86_error) 2262 return; 2263 2264 /* 2265 * first handle a simple register 2266 */ 2267 if (mode == REG_ONLY) { 2268 #ifdef DIS_TEXT 2269 switch (wbit) { 2270 case MM_OPND: 2271 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 2272 break; 2273 case XMM_OPND: 2274 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 2275 break; 2276 case YMM_OPND: 2277 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 2278 break; 2279 case SEG_OPND: 2280 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 2281 break; 2282 case CONTROL_OPND: 2283 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 2284 break; 2285 case DEBUG_OPND: 2286 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 2287 break; 2288 case TEST_OPND: 2289 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 2290 break; 2291 case BYTE_OPND: 2292 if (x->d86_rex_prefix == 0) 2293 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 2294 else 2295 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 2296 break; 2297 case WORD_OPND: 2298 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2299 break; 2300 case LONG_OPND: 2301 if (x->d86_opnd_size == SIZE16) 2302 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2303 else if (x->d86_opnd_size == SIZE32) 2304 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 2305 else 2306 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 2307 break; 2308 } 2309 #endif /* DIS_TEXT */ 2310 return; 2311 } 2312 2313 /* 2314 * if symbolic representation, skip override prefix, if any 2315 */ 2316 dtrace_check_override(x, opindex); 2317 2318 /* 2319 * Handle 16 bit memory references first, since they decode 2320 * the mode values more simply. 2321 * mode 1 is r_m + 8 bit displacement 2322 * mode 2 is r_m + 16 bit displacement 2323 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 2324 */ 2325 if (x->d86_addr_size == SIZE16) { 2326 if ((mode == 0 && r_m == 6) || mode == 2) 2327 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 2328 else if (mode == 1) 2329 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 2330 #ifdef DIS_TEXT 2331 if (mode == 0 && r_m == 6) 2332 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2333 else if (mode == 0) 2334 x->d86_opnd[opindex].d86_mode = MODE_NONE; 2335 else 2336 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 2337 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 2338 #endif 2339 return; 2340 } 2341 2342 /* 2343 * 32 and 64 bit addressing modes are more complex since they 2344 * can involve an SIB (scaled index and base) byte to decode. 2345 */ 2346 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) { 2347 have_SIB = 1; 2348 dtrace_get_SIB(x, &ss, &index, &base); 2349 if (x->d86_error) 2350 return; 2351 if (base != 5 || mode != 0) 2352 if (x->d86_rex_prefix & REX_B) 2353 base += 8; 2354 if (x->d86_rex_prefix & REX_X) 2355 index += 8; 2356 } else { 2357 base = r_m; 2358 } 2359 2360 /* 2361 * Compute the displacement size and get its bytes 2362 */ 2363 dispsize = 0; 2364 2365 if (mode == 1) 2366 dispsize = 1; 2367 else if (mode == 2) 2368 dispsize = 4; 2369 else if ((r_m & 7) == EBP_REGNO || 2370 (have_SIB && (base & 7) == EBP_REGNO)) 2371 dispsize = 4; 2372 2373 if (dispsize > 0) { 2374 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 2375 dispsize, opindex); 2376 if (x->d86_error) 2377 return; 2378 } 2379 2380 #ifdef DIS_TEXT 2381 if (dispsize > 0) 2382 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 2383 2384 if (have_SIB == 0) { 2385 if (x->d86_mode == SIZE32) { 2386 if (mode == 0) 2387 (void) strlcat(opnd, dis_addr32_mode0[r_m], 2388 OPLEN); 2389 else 2390 (void) strlcat(opnd, dis_addr32_mode12[r_m], 2391 OPLEN); 2392 } else { 2393 if (mode == 0) { 2394 (void) strlcat(opnd, dis_addr64_mode0[r_m], 2395 OPLEN); 2396 if (r_m == 5) { 2397 x->d86_opnd[opindex].d86_mode = 2398 MODE_RIPREL; 2399 } 2400 } else { 2401 (void) strlcat(opnd, dis_addr64_mode12[r_m], 2402 OPLEN); 2403 } 2404 } 2405 } else { 2406 uint_t need_paren = 0; 2407 char **regs; 2408 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 2409 regs = (char **)dis_REG32; 2410 else 2411 regs = (char **)dis_REG64; 2412 2413 /* 2414 * print the base (if any) 2415 */ 2416 if (base == EBP_REGNO && mode == 0) { 2417 if (index != ESP_REGNO) { 2418 (void) strlcat(opnd, "(", OPLEN); 2419 need_paren = 1; 2420 } 2421 } else { 2422 (void) strlcat(opnd, "(", OPLEN); 2423 (void) strlcat(opnd, regs[base], OPLEN); 2424 need_paren = 1; 2425 } 2426 2427 /* 2428 * print the index (if any) 2429 */ 2430 if (index != ESP_REGNO) { 2431 (void) strlcat(opnd, ",", OPLEN); 2432 (void) strlcat(opnd, regs[index], OPLEN); 2433 (void) strlcat(opnd, dis_scale_factor[ss], OPLEN); 2434 } else 2435 if (need_paren) 2436 (void) strlcat(opnd, ")", OPLEN); 2437 } 2438 #endif 2439 } 2440 2441 /* 2442 * Operand sequence for standard instruction involving one register 2443 * and one register/memory operand. 2444 * wbit indicates a byte(0) or opnd_size(1) operation 2445 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 2446 */ 2447 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 2448 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2449 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2450 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 2451 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 2452 } 2453 2454 /* 2455 * Similar to above, but allows for the two operands to be of different 2456 * classes (ie. wbit). 2457 * wbit is for the r_m operand 2458 * w2 is for the reg operand 2459 */ 2460 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 2461 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2462 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2463 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 2464 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 2465 } 2466 2467 /* 2468 * Similar, but for 2 operands plus an immediate. 2469 * vbit indicates direction 2470 * 0 for "opcode imm, r, r_m" or 2471 * 1 for "opcode imm, r_m, r" 2472 */ 2473 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 2474 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2475 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2476 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 2477 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 2478 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2479 } 2480 2481 /* 2482 * Similar, but for 2 operands plus two immediates. 2483 */ 2484 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 2485 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2486 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2487 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 2488 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 2489 dtrace_imm_opnd(x, wbit, immsize, 1); \ 2490 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2491 } 2492 2493 /* 2494 * 1 operands plus two immediates. 2495 */ 2496 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 2497 dtrace_get_modrm(x, &mode, ®, &r_m); \ 2498 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 2499 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 2500 dtrace_imm_opnd(x, wbit, immsize, 1); \ 2501 dtrace_imm_opnd(x, wbit, immsize, 0); \ 2502 } 2503 2504 /* 2505 * Dissassemble a single x86 or amd64 instruction. 2506 * 2507 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 2508 * for interpreting instructions. 2509 * 2510 * returns non-zero for bad opcode 2511 */ 2512 int 2513 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 2514 { 2515 instable_t *dp; /* decode table being used */ 2516 #ifdef DIS_TEXT 2517 uint_t i; 2518 #endif 2519 #ifdef DIS_MEM 2520 uint_t nomem = 0; 2521 #define NOMEM (nomem = 1) 2522 #else 2523 #define NOMEM /* nothing */ 2524 #endif 2525 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 2526 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 2527 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 2528 uint_t w2; /* wbit value for second operand */ 2529 uint_t vbit; 2530 uint_t mode = 0; /* mode value from ModRM byte */ 2531 uint_t reg; /* reg value from ModRM byte */ 2532 uint_t r_m; /* r_m value from ModRM byte */ 2533 2534 uint_t opcode1; /* high nibble of 1st byte */ 2535 uint_t opcode2; /* low nibble of 1st byte */ 2536 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 2537 uint_t opcode4; /* high nibble of 2nd byte */ 2538 uint_t opcode5; /* low nibble of 2nd byte */ 2539 uint_t opcode6; /* high nibble of 3rd byte */ 2540 uint_t opcode7; /* low nibble of 3rd byte */ 2541 uint_t opcode_bytes = 1; 2542 2543 /* 2544 * legacy prefixes come in 5 flavors, you should have only one of each 2545 */ 2546 uint_t opnd_size_prefix = 0; 2547 uint_t addr_size_prefix = 0; 2548 uint_t segment_prefix = 0; 2549 uint_t lock_prefix = 0; 2550 uint_t rep_prefix = 0; 2551 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 2552 2553 /* 2554 * Intel VEX instruction encoding prefix and fields 2555 */ 2556 2557 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 2558 uint_t vex_prefix = 0; 2559 2560 /* 2561 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 2562 * (for 3 bytes prefix) 2563 */ 2564 uint_t vex_byte1 = 0; 2565 2566 /* 2567 * For 32-bit mode, it should prefetch the next byte to 2568 * distinguish between AVX and les/lds 2569 */ 2570 uint_t vex_prefetch = 0; 2571 2572 uint_t vex_m = 0; 2573 uint_t vex_v = 0; 2574 uint_t vex_p = 0; 2575 uint_t vex_R = 1; 2576 uint_t vex_X = 1; 2577 uint_t vex_B = 1; 2578 uint_t vex_W = 0; 2579 uint_t vex_L; 2580 2581 2582 size_t off; 2583 2584 instable_t dp_mmx; 2585 2586 x->d86_len = 0; 2587 x->d86_rmindex = -1; 2588 x->d86_error = 0; 2589 #ifdef DIS_TEXT 2590 x->d86_numopnds = 0; 2591 x->d86_seg_prefix = NULL; 2592 x->d86_mnem[0] = 0; 2593 for (i = 0; i < 4; ++i) { 2594 x->d86_opnd[i].d86_opnd[0] = 0; 2595 x->d86_opnd[i].d86_prefix[0] = 0; 2596 x->d86_opnd[i].d86_value_size = 0; 2597 x->d86_opnd[i].d86_value = 0; 2598 x->d86_opnd[i].d86_mode = MODE_NONE; 2599 } 2600 #endif 2601 x->d86_rex_prefix = 0; 2602 x->d86_got_modrm = 0; 2603 x->d86_memsize = 0; 2604 2605 if (cpu_mode == SIZE16) { 2606 opnd_size = SIZE16; 2607 addr_size = SIZE16; 2608 } else if (cpu_mode == SIZE32) { 2609 opnd_size = SIZE32; 2610 addr_size = SIZE32; 2611 } else { 2612 opnd_size = SIZE32; 2613 addr_size = SIZE64; 2614 } 2615 2616 /* 2617 * Get one opcode byte and check for zero padding that follows 2618 * jump tables. 2619 */ 2620 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2621 goto error; 2622 2623 if (opcode1 == 0 && opcode2 == 0 && 2624 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 2625 #ifdef DIS_TEXT 2626 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 2627 #endif 2628 goto done; 2629 } 2630 2631 /* 2632 * Gather up legacy x86 prefix bytes. 2633 */ 2634 for (;;) { 2635 uint_t *which_prefix = NULL; 2636 2637 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 2638 2639 switch (dp->it_adrmode) { 2640 case PREFIX: 2641 which_prefix = &rep_prefix; 2642 break; 2643 case LOCK: 2644 which_prefix = &lock_prefix; 2645 break; 2646 case OVERRIDE: 2647 which_prefix = &segment_prefix; 2648 #ifdef DIS_TEXT 2649 x->d86_seg_prefix = (char *)dp->it_name; 2650 #endif 2651 if (dp->it_invalid64 && cpu_mode == SIZE64) 2652 goto error; 2653 break; 2654 case AM: 2655 which_prefix = &addr_size_prefix; 2656 break; 2657 case DM: 2658 which_prefix = &opnd_size_prefix; 2659 break; 2660 } 2661 if (which_prefix == NULL) 2662 break; 2663 *which_prefix = (opcode1 << 4) | opcode2; 2664 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2665 goto error; 2666 } 2667 2668 /* 2669 * Handle amd64 mode PREFIX values. 2670 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 2671 * We might have a REX prefix (opcodes 0x40-0x4f) 2672 */ 2673 if (cpu_mode == SIZE64) { 2674 if (segment_prefix != 0x64 && segment_prefix != 0x65) 2675 segment_prefix = 0; 2676 2677 if (opcode1 == 0x4) { 2678 rex_prefix = (opcode1 << 4) | opcode2; 2679 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2680 goto error; 2681 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 2682 } else if (opcode1 == 0xC && 2683 (opcode2 == 0x4 || opcode2 == 0x5)) { 2684 /* AVX instructions */ 2685 vex_prefix = (opcode1 << 4) | opcode2; 2686 x->d86_rex_prefix = 0x40; 2687 } 2688 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 2689 /* LDS, LES or AVX */ 2690 dtrace_get_modrm(x, &mode, ®, &r_m); 2691 vex_prefetch = 1; 2692 2693 if (mode == REG_ONLY) { 2694 /* AVX */ 2695 vex_prefix = (opcode1 << 4) | opcode2; 2696 x->d86_rex_prefix = 0x40; 2697 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 2698 opcode4 = ((reg << 3) | r_m) & 0x0F; 2699 } 2700 } 2701 2702 if (vex_prefix == VEX_2bytes) { 2703 if (!vex_prefetch) { 2704 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 2705 goto error; 2706 } 2707 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 2708 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 2709 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 2710 vex_p = opcode4 & VEX_p; 2711 /* 2712 * The vex.x and vex.b bits are not defined in two bytes 2713 * mode vex prefix, their default values are 1 2714 */ 2715 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 2716 2717 if (vex_R == 0) 2718 x->d86_rex_prefix |= REX_R; 2719 2720 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2721 goto error; 2722 2723 switch (vex_p) { 2724 case VEX_p_66: 2725 dp = (instable_t *) 2726 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 2727 break; 2728 case VEX_p_F3: 2729 dp = (instable_t *) 2730 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 2731 break; 2732 case VEX_p_F2: 2733 dp = (instable_t *) 2734 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 2735 break; 2736 default: 2737 dp = (instable_t *) 2738 &dis_opAVX0F[opcode1][opcode2]; 2739 2740 } 2741 2742 } else if (vex_prefix == VEX_3bytes) { 2743 if (!vex_prefetch) { 2744 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 2745 goto error; 2746 } 2747 vex_R = (opcode3 & VEX_R) >> 3; 2748 vex_X = (opcode3 & VEX_X) >> 2; 2749 vex_B = (opcode3 & VEX_B) >> 1; 2750 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 2751 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 2752 2753 if (vex_R == 0) 2754 x->d86_rex_prefix |= REX_R; 2755 if (vex_X == 0) 2756 x->d86_rex_prefix |= REX_X; 2757 if (vex_B == 0) 2758 x->d86_rex_prefix |= REX_B; 2759 2760 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 2761 goto error; 2762 vex_W = (opcode5 & VEX_W) >> 3; 2763 vex_L = (opcode6 & VEX_L) >> 2; 2764 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 2765 vex_p = opcode6 & VEX_p; 2766 2767 if (vex_W) 2768 x->d86_rex_prefix |= REX_W; 2769 2770 /* Only these three vex_m values valid; others are reserved */ 2771 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 2772 (vex_m != VEX_m_0F3A)) 2773 goto error; 2774 2775 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 2776 goto error; 2777 2778 switch (vex_p) { 2779 case VEX_p_66: 2780 if (vex_m == VEX_m_0F) { 2781 dp = (instable_t *) 2782 &dis_opAVX660F 2783 [(opcode1 << 4) | opcode2]; 2784 } else if (vex_m == VEX_m_0F38) { 2785 dp = (instable_t *) 2786 &dis_opAVX660F38 2787 [(opcode1 << 4) | opcode2]; 2788 } else if (vex_m == VEX_m_0F3A) { 2789 dp = (instable_t *) 2790 &dis_opAVX660F3A 2791 [(opcode1 << 4) | opcode2]; 2792 } else { 2793 goto error; 2794 } 2795 break; 2796 case VEX_p_F3: 2797 if (vex_m == VEX_m_0F) { 2798 dp = (instable_t *) 2799 &dis_opAVXF30F 2800 [(opcode1 << 4) | opcode2]; 2801 } else { 2802 goto error; 2803 } 2804 break; 2805 case VEX_p_F2: 2806 if (vex_m == VEX_m_0F) { 2807 dp = (instable_t *) 2808 &dis_opAVXF20F 2809 [(opcode1 << 4) | opcode2]; 2810 } else { 2811 goto error; 2812 } 2813 break; 2814 default: 2815 dp = (instable_t *) 2816 &dis_opAVX0F[opcode1][opcode2]; 2817 2818 } 2819 } 2820 if (vex_prefix) { 2821 if (vex_L) 2822 wbit = YMM_OPND; 2823 else 2824 wbit = XMM_OPND; 2825 } 2826 2827 /* 2828 * Deal with selection of operand and address size now. 2829 * Note that the REX.W bit being set causes opnd_size_prefix to be 2830 * ignored. 2831 */ 2832 if (cpu_mode == SIZE64) { 2833 if ((rex_prefix & REX_W) || vex_W) 2834 opnd_size = SIZE64; 2835 else if (opnd_size_prefix) 2836 opnd_size = SIZE16; 2837 2838 if (addr_size_prefix) 2839 addr_size = SIZE32; 2840 } else if (cpu_mode == SIZE32) { 2841 if (opnd_size_prefix) 2842 opnd_size = SIZE16; 2843 if (addr_size_prefix) 2844 addr_size = SIZE16; 2845 } else { 2846 if (opnd_size_prefix) 2847 opnd_size = SIZE32; 2848 if (addr_size_prefix) 2849 addr_size = SIZE32; 2850 } 2851 /* 2852 * The pause instruction - a repz'd nop. This doesn't fit 2853 * with any of the other prefix goop added for SSE, so we'll 2854 * special-case it here. 2855 */ 2856 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 2857 rep_prefix = 0; 2858 dp = (instable_t *)&dis_opPause; 2859 } 2860 2861 /* 2862 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 2863 * byte so we may need to perform a table indirection. 2864 */ 2865 if (dp->it_indirect == (instable_t *)dis_op0F) { 2866 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 2867 goto error; 2868 opcode_bytes = 2; 2869 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 2870 uint_t subcode; 2871 2872 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 2873 goto error; 2874 opcode_bytes = 3; 2875 subcode = ((opcode6 & 0x3) << 1) | 2876 ((opcode7 & 0x8) >> 3); 2877 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 2878 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 2879 dp = (instable_t *)&dis_op0FC8[0]; 2880 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 2881 opcode_bytes = 3; 2882 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 2883 goto error; 2884 if (opnd_size == SIZE16) 2885 opnd_size = SIZE32; 2886 2887 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 2888 #ifdef DIS_TEXT 2889 if (strcmp(dp->it_name, "INVALID") == 0) 2890 goto error; 2891 #endif 2892 switch (dp->it_adrmode) { 2893 case XMMP_66r: 2894 case XMMPRM_66r: 2895 case XMM3PM_66r: 2896 if (opnd_size_prefix == 0) { 2897 goto error; 2898 } 2899 break; 2900 case XMMP_66o: 2901 if (opnd_size_prefix == 0) { 2902 /* SSSE3 MMX instructions */ 2903 dp_mmx = *dp; 2904 dp = &dp_mmx; 2905 dp->it_adrmode = MMOPM_66o; 2906 #ifdef DIS_MEM 2907 dp->it_size = 8; 2908 #endif 2909 } 2910 break; 2911 default: 2912 goto error; 2913 } 2914 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 2915 opcode_bytes = 3; 2916 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 2917 goto error; 2918 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 2919 2920 /* 2921 * Both crc32 and movbe have the same 3rd opcode 2922 * byte of either 0xF0 or 0xF1, so we use another 2923 * indirection to distinguish between the two. 2924 */ 2925 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 2926 dp->it_indirect == (instable_t *)dis_op0F38F1) { 2927 2928 dp = dp->it_indirect; 2929 if (rep_prefix != 0xF2) { 2930 /* It is movbe */ 2931 dp++; 2932 } 2933 } 2934 #ifdef DIS_TEXT 2935 if (strcmp(dp->it_name, "INVALID") == 0) 2936 goto error; 2937 #endif 2938 switch (dp->it_adrmode) { 2939 case RM_66r: 2940 case XMM_66r: 2941 case XMMM_66r: 2942 if (opnd_size_prefix == 0) { 2943 goto error; 2944 } 2945 break; 2946 case XMM_66o: 2947 if (opnd_size_prefix == 0) { 2948 /* SSSE3 MMX instructions */ 2949 dp_mmx = *dp; 2950 dp = &dp_mmx; 2951 dp->it_adrmode = MM; 2952 #ifdef DIS_MEM 2953 dp->it_size = 8; 2954 #endif 2955 } 2956 break; 2957 case CRC32: 2958 if (rep_prefix != 0xF2) { 2959 goto error; 2960 } 2961 rep_prefix = 0; 2962 break; 2963 case MOVBE: 2964 if (rep_prefix != 0x0) { 2965 goto error; 2966 } 2967 break; 2968 default: 2969 goto error; 2970 } 2971 } else { 2972 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 2973 } 2974 } 2975 2976 /* 2977 * If still not at a TERM decode entry, then a ModRM byte 2978 * exists and its fields further decode the instruction. 2979 */ 2980 x->d86_got_modrm = 0; 2981 if (dp->it_indirect != TERM) { 2982 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 2983 if (x->d86_error) 2984 goto error; 2985 reg = opcode3; 2986 2987 /* 2988 * decode 287 instructions (D8-DF) from opcodeN 2989 */ 2990 if (opcode1 == 0xD && opcode2 >= 0x8) { 2991 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 2992 dp = (instable_t *)&dis_opFP5[r_m]; 2993 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 2994 dp = (instable_t *)&dis_opFP7[opcode3]; 2995 else if (opcode2 == 0xB && mode == 0x3) 2996 dp = (instable_t *)&dis_opFP6[opcode3]; 2997 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 2998 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 2999 else if (mode == 0x3) 3000 dp = (instable_t *) 3001 &dis_opFP3[opcode2 - 8][opcode3]; 3002 else 3003 dp = (instable_t *) 3004 &dis_opFP1n2[opcode2 - 8][opcode3]; 3005 } else { 3006 dp = (instable_t *)dp->it_indirect + opcode3; 3007 } 3008 } 3009 3010 /* 3011 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 3012 * (sign extend 32bit to 64 bit) 3013 */ 3014 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 3015 opcode1 == 0x6 && opcode2 == 0x3) 3016 dp = (instable_t *)&dis_opMOVSLD; 3017 3018 /* 3019 * at this point we should have a correct (or invalid) opcode 3020 */ 3021 if (cpu_mode == SIZE64 && dp->it_invalid64 || 3022 cpu_mode != SIZE64 && dp->it_invalid32) 3023 goto error; 3024 if (dp->it_indirect != TERM) 3025 goto error; 3026 3027 /* 3028 * deal with MMX/SSE opcodes which are changed by prefixes 3029 */ 3030 switch (dp->it_adrmode) { 3031 case MMO: 3032 case MMOIMPL: 3033 case MMO3P: 3034 case MMOM3: 3035 case MMOMS: 3036 case MMOPM: 3037 case MMOPRM: 3038 case MMOS: 3039 case XMMO: 3040 case XMMOM: 3041 case XMMOMS: 3042 case XMMOPM: 3043 case XMMOS: 3044 case XMMOMX: 3045 case XMMOX3: 3046 case XMMOXMM: 3047 /* 3048 * This is horrible. Some SIMD instructions take the 3049 * form 0x0F 0x?? ..., which is easily decoded using the 3050 * existing tables. Other SIMD instructions use various 3051 * prefix bytes to overload existing instructions. For 3052 * Example, addps is F0, 58, whereas addss is F3 (repz), 3053 * F0, 58. Presumably someone got a raise for this. 3054 * 3055 * If we see one of the instructions which can be 3056 * modified in this way (if we've got one of the SIMDO* 3057 * address modes), we'll check to see if the last prefix 3058 * was a repz. If it was, we strip the prefix from the 3059 * mnemonic, and we indirect using the dis_opSIMDrepz 3060 * table. 3061 */ 3062 3063 /* 3064 * Calculate our offset in dis_op0F 3065 */ 3066 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 3067 goto error; 3068 3069 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3070 sizeof (instable_t); 3071 3072 /* 3073 * Rewrite if this instruction used one of the magic prefixes. 3074 */ 3075 if (rep_prefix) { 3076 if (rep_prefix == 0xf2) 3077 dp = (instable_t *)&dis_opSIMDrepnz[off]; 3078 else 3079 dp = (instable_t *)&dis_opSIMDrepz[off]; 3080 rep_prefix = 0; 3081 } else if (opnd_size_prefix) { 3082 dp = (instable_t *)&dis_opSIMDdata16[off]; 3083 opnd_size_prefix = 0; 3084 if (opnd_size == SIZE16) 3085 opnd_size = SIZE32; 3086 } 3087 break; 3088 3089 case MG9: 3090 /* 3091 * More horribleness: the group 9 (0xF0 0xC7) instructions are 3092 * allowed an optional prefix of 0x66 or 0xF3. This is similar 3093 * to the SIMD business described above, but with a different 3094 * addressing mode (and an indirect table), so we deal with it 3095 * separately (if similarly). 3096 * 3097 * Intel further complicated this with the release of Ivy Bridge 3098 * where they overloaded these instructions based on the ModR/M 3099 * bytes. The VMX instructions have a mode of 0 since they are 3100 * memory instructions but rdrand instructions have a mode of 3101 * 0b11 (REG_ONLY) because they only operate on registers. While 3102 * there are different prefix formats, for now it is sufficient 3103 * to use a single different table. 3104 */ 3105 3106 /* 3107 * Calculate our offset in dis_op0FC7 (the group 9 table) 3108 */ 3109 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 3110 goto error; 3111 3112 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 3113 sizeof (instable_t); 3114 3115 /* 3116 * If we have a mode of 0b11 then we have to rewrite this. 3117 */ 3118 dtrace_get_modrm(x, &mode, ®, &r_m); 3119 if (mode == REG_ONLY) { 3120 dp = (instable_t *)&dis_op0FC7m3[off]; 3121 break; 3122 } 3123 3124 /* 3125 * Rewrite if this instruction used one of the magic prefixes. 3126 */ 3127 if (rep_prefix) { 3128 if (rep_prefix == 0xf3) 3129 dp = (instable_t *)&dis_opF30FC7[off]; 3130 else 3131 goto error; 3132 rep_prefix = 0; 3133 } else if (opnd_size_prefix) { 3134 dp = (instable_t *)&dis_op660FC7[off]; 3135 opnd_size_prefix = 0; 3136 if (opnd_size == SIZE16) 3137 opnd_size = SIZE32; 3138 } 3139 break; 3140 3141 3142 case MMOSH: 3143 /* 3144 * As with the "normal" SIMD instructions, the MMX 3145 * shuffle instructions are overloaded. These 3146 * instructions, however, are special in that they use 3147 * an extra byte, and thus an extra table. As of this 3148 * writing, they only use the opnd_size prefix. 3149 */ 3150 3151 /* 3152 * Calculate our offset in dis_op0F7123 3153 */ 3154 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 3155 sizeof (dis_op0F7123)) 3156 goto error; 3157 3158 if (opnd_size_prefix) { 3159 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 3160 sizeof (instable_t); 3161 dp = (instable_t *)&dis_opSIMD7123[off]; 3162 opnd_size_prefix = 0; 3163 if (opnd_size == SIZE16) 3164 opnd_size = SIZE32; 3165 } 3166 break; 3167 case MRw: 3168 if (rep_prefix) { 3169 if (rep_prefix == 0xf3) { 3170 3171 /* 3172 * Calculate our offset in dis_op0F 3173 */ 3174 if ((uintptr_t)dp - (uintptr_t)dis_op0F 3175 > sizeof (dis_op0F)) 3176 goto error; 3177 3178 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3179 sizeof (instable_t); 3180 3181 dp = (instable_t *)&dis_opSIMDrepz[off]; 3182 rep_prefix = 0; 3183 } else { 3184 goto error; 3185 } 3186 } 3187 break; 3188 } 3189 3190 /* 3191 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 3192 */ 3193 if (cpu_mode == SIZE64) 3194 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 3195 opnd_size = SIZE64; 3196 3197 #ifdef DIS_TEXT 3198 /* 3199 * At this point most instructions can format the opcode mnemonic 3200 * including the prefixes. 3201 */ 3202 if (lock_prefix) 3203 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 3204 3205 if (rep_prefix == 0xf2) 3206 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 3207 else if (rep_prefix == 0xf3) 3208 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 3209 3210 if (cpu_mode == SIZE64 && addr_size_prefix) 3211 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 3212 3213 if (dp->it_adrmode != CBW && 3214 dp->it_adrmode != CWD && 3215 dp->it_adrmode != XMMSFNC) { 3216 if (strcmp(dp->it_name, "INVALID") == 0) 3217 goto error; 3218 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 3219 if (dp->it_suffix) { 3220 char *types[] = {"", "w", "l", "q"}; 3221 if (opcode_bytes == 2 && opcode4 == 4) { 3222 /* It's a cmovx.yy. Replace the suffix x */ 3223 for (i = 5; i < OPLEN; i++) { 3224 if (x->d86_mnem[i] == '.') 3225 break; 3226 } 3227 x->d86_mnem[i - 1] = *types[opnd_size]; 3228 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 3229 ((opcode6 == 1 && opcode7 == 6) || 3230 (opcode6 == 2 && opcode7 == 2))) { 3231 /* 3232 * To handle PINSRD and PEXTRD 3233 */ 3234 (void) strlcat(x->d86_mnem, "d", OPLEN); 3235 } else { 3236 (void) strlcat(x->d86_mnem, types[opnd_size], 3237 OPLEN); 3238 } 3239 } 3240 } 3241 #endif 3242 3243 /* 3244 * Process operands based on the addressing modes. 3245 */ 3246 x->d86_mode = cpu_mode; 3247 /* 3248 * In vex mode the rex_prefix has no meaning 3249 */ 3250 if (!vex_prefix) 3251 x->d86_rex_prefix = rex_prefix; 3252 x->d86_opnd_size = opnd_size; 3253 x->d86_addr_size = addr_size; 3254 vbit = 0; /* initialize for mem/reg -> reg */ 3255 switch (dp->it_adrmode) { 3256 /* 3257 * amd64 instruction to sign extend 32 bit reg/mem operands 3258 * into 64 bit register values 3259 */ 3260 case MOVSXZ: 3261 #ifdef DIS_TEXT 3262 if (rex_prefix == 0) 3263 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 3264 #endif 3265 dtrace_get_modrm(x, &mode, ®, &r_m); 3266 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3267 x->d86_opnd_size = SIZE64; 3268 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3269 x->d86_opnd_size = opnd_size = SIZE32; 3270 wbit = LONG_OPND; 3271 dtrace_get_operand(x, mode, r_m, wbit, 0); 3272 break; 3273 3274 /* 3275 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 3276 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 3277 * wbit lives in 2nd byte, note that operands 3278 * are different sized 3279 */ 3280 case MOVZ: 3281 if (rex_prefix & REX_W) { 3282 /* target register size = 64 bit */ 3283 x->d86_mnem[5] = 'q'; 3284 } 3285 dtrace_get_modrm(x, &mode, ®, &r_m); 3286 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3287 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3288 x->d86_opnd_size = opnd_size = SIZE16; 3289 wbit = WBIT(opcode5); 3290 dtrace_get_operand(x, mode, r_m, wbit, 0); 3291 break; 3292 case CRC32: 3293 opnd_size = SIZE32; 3294 if (rex_prefix & REX_W) 3295 opnd_size = SIZE64; 3296 x->d86_opnd_size = opnd_size; 3297 3298 dtrace_get_modrm(x, &mode, ®, &r_m); 3299 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3300 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3301 wbit = WBIT(opcode7); 3302 if (opnd_size_prefix) 3303 x->d86_opnd_size = opnd_size = SIZE16; 3304 dtrace_get_operand(x, mode, r_m, wbit, 0); 3305 break; 3306 case MOVBE: 3307 opnd_size = SIZE32; 3308 if (rex_prefix & REX_W) 3309 opnd_size = SIZE64; 3310 x->d86_opnd_size = opnd_size; 3311 3312 dtrace_get_modrm(x, &mode, ®, &r_m); 3313 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3314 wbit = WBIT(opcode7); 3315 if (opnd_size_prefix) 3316 x->d86_opnd_size = opnd_size = SIZE16; 3317 if (wbit) { 3318 /* reg -> mem */ 3319 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3320 dtrace_get_operand(x, mode, r_m, wbit, 1); 3321 } else { 3322 /* mem -> reg */ 3323 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3324 dtrace_get_operand(x, mode, r_m, wbit, 0); 3325 } 3326 break; 3327 3328 /* 3329 * imul instruction, with either 8-bit or longer immediate 3330 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 3331 */ 3332 case IMUL: 3333 wbit = LONG_OPND; 3334 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 3335 OPSIZE(opnd_size, opcode2 == 0x9), 1); 3336 break; 3337 3338 /* memory or register operand to register, with 'w' bit */ 3339 case MRw: 3340 wbit = WBIT(opcode2); 3341 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3342 break; 3343 3344 /* register to memory or register operand, with 'w' bit */ 3345 /* arpl happens to fit here also because it is odd */ 3346 case RMw: 3347 if (opcode_bytes == 2) 3348 wbit = WBIT(opcode5); 3349 else 3350 wbit = WBIT(opcode2); 3351 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3352 break; 3353 3354 /* xaddb instruction */ 3355 case XADDB: 3356 wbit = 0; 3357 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3358 break; 3359 3360 /* MMX register to memory or register operand */ 3361 case MMS: 3362 case MMOS: 3363 #ifdef DIS_TEXT 3364 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3365 #else 3366 wbit = LONG_OPND; 3367 #endif 3368 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 3369 break; 3370 3371 /* MMX register to memory */ 3372 case MMOMS: 3373 dtrace_get_modrm(x, &mode, ®, &r_m); 3374 if (mode == REG_ONLY) 3375 goto error; 3376 wbit = MM_OPND; 3377 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 3378 break; 3379 3380 /* Double shift. Has immediate operand specifying the shift. */ 3381 case DSHIFT: 3382 wbit = LONG_OPND; 3383 dtrace_get_modrm(x, &mode, ®, &r_m); 3384 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3385 dtrace_get_operand(x, mode, r_m, wbit, 2); 3386 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3387 dtrace_imm_opnd(x, wbit, 1, 0); 3388 break; 3389 3390 /* 3391 * Double shift. With no immediate operand, specifies using %cl. 3392 */ 3393 case DSHIFTcl: 3394 wbit = LONG_OPND; 3395 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3396 break; 3397 3398 /* immediate to memory or register operand */ 3399 case IMlw: 3400 wbit = WBIT(opcode2); 3401 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3402 dtrace_get_operand(x, mode, r_m, wbit, 1); 3403 /* 3404 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 3405 */ 3406 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 3407 break; 3408 3409 /* immediate to memory or register operand with the */ 3410 /* 'w' bit present */ 3411 case IMw: 3412 wbit = WBIT(opcode2); 3413 dtrace_get_modrm(x, &mode, ®, &r_m); 3414 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3415 dtrace_get_operand(x, mode, r_m, wbit, 1); 3416 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 3417 break; 3418 3419 /* immediate to register with register in low 3 bits */ 3420 /* of op code */ 3421 case IR: 3422 /* w-bit here (with regs) is bit 3 */ 3423 wbit = opcode2 >>3 & 0x1; 3424 reg = REGNO(opcode2); 3425 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3426 mode = REG_ONLY; 3427 r_m = reg; 3428 dtrace_get_operand(x, mode, r_m, wbit, 1); 3429 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 3430 break; 3431 3432 /* MMX immediate shift of register */ 3433 case MMSH: 3434 case MMOSH: 3435 wbit = MM_OPND; 3436 goto mm_shift; /* in next case */ 3437 3438 /* SIMD immediate shift of register */ 3439 case XMMSH: 3440 wbit = XMM_OPND; 3441 mm_shift: 3442 reg = REGNO(opcode7); 3443 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3444 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 3445 dtrace_imm_opnd(x, wbit, 1, 0); 3446 NOMEM; 3447 break; 3448 3449 /* accumulator to memory operand */ 3450 case AO: 3451 vbit = 1; 3452 /*FALLTHROUGH*/ 3453 3454 /* memory operand to accumulator */ 3455 case OA: 3456 wbit = WBIT(opcode2); 3457 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 3458 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 3459 #ifdef DIS_TEXT 3460 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 3461 #endif 3462 break; 3463 3464 3465 /* segment register to memory or register operand */ 3466 case SM: 3467 vbit = 1; 3468 /*FALLTHROUGH*/ 3469 3470 /* memory or register operand to segment register */ 3471 case MS: 3472 dtrace_get_modrm(x, &mode, ®, &r_m); 3473 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3474 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 3475 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 3476 break; 3477 3478 /* 3479 * rotate or shift instructions, which may shift by 1 or 3480 * consult the cl register, depending on the 'v' bit 3481 */ 3482 case Mv: 3483 vbit = VBIT(opcode2); 3484 wbit = WBIT(opcode2); 3485 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3486 dtrace_get_operand(x, mode, r_m, wbit, 1); 3487 #ifdef DIS_TEXT 3488 if (vbit) { 3489 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 3490 } else { 3491 x->d86_opnd[0].d86_mode = MODE_SIGNED; 3492 x->d86_opnd[0].d86_value_size = 1; 3493 x->d86_opnd[0].d86_value = 1; 3494 } 3495 #endif 3496 break; 3497 /* 3498 * immediate rotate or shift instructions 3499 */ 3500 case MvI: 3501 wbit = WBIT(opcode2); 3502 normal_imm_mem: 3503 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3504 dtrace_get_operand(x, mode, r_m, wbit, 1); 3505 dtrace_imm_opnd(x, wbit, 1, 0); 3506 break; 3507 3508 /* bit test instructions */ 3509 case MIb: 3510 wbit = LONG_OPND; 3511 goto normal_imm_mem; 3512 3513 /* single memory or register operand with 'w' bit present */ 3514 case Mw: 3515 wbit = WBIT(opcode2); 3516 just_mem: 3517 dtrace_get_modrm(x, &mode, ®, &r_m); 3518 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3519 dtrace_get_operand(x, mode, r_m, wbit, 0); 3520 break; 3521 3522 case SWAPGS_RDTSCP: 3523 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 3524 #ifdef DIS_TEXT 3525 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 3526 #endif 3527 NOMEM; 3528 break; 3529 } else if (mode == 3 && r_m == 1) { 3530 #ifdef DIS_TEXT 3531 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 3532 #endif 3533 NOMEM; 3534 break; 3535 } 3536 3537 /*FALLTHROUGH*/ 3538 3539 /* prefetch instruction - memory operand, but no memory acess */ 3540 case PREF: 3541 NOMEM; 3542 /*FALLTHROUGH*/ 3543 3544 /* single memory or register operand */ 3545 case M: 3546 case MG9: 3547 wbit = LONG_OPND; 3548 goto just_mem; 3549 3550 /* single memory or register byte operand */ 3551 case Mb: 3552 wbit = BYTE_OPND; 3553 goto just_mem; 3554 3555 case VMx: 3556 if (mode == 3) { 3557 #ifdef DIS_TEXT 3558 char *vminstr; 3559 3560 switch (r_m) { 3561 case 1: 3562 vminstr = "vmcall"; 3563 break; 3564 case 2: 3565 vminstr = "vmlaunch"; 3566 break; 3567 case 3: 3568 vminstr = "vmresume"; 3569 break; 3570 case 4: 3571 vminstr = "vmxoff"; 3572 break; 3573 default: 3574 goto error; 3575 } 3576 3577 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 3578 #else 3579 if (r_m < 1 || r_m > 4) 3580 goto error; 3581 #endif 3582 3583 NOMEM; 3584 break; 3585 } 3586 /*FALLTHROUGH*/ 3587 case SVM: 3588 if (mode == 3) { 3589 #if DIS_TEXT 3590 char *vinstr; 3591 3592 switch (r_m) { 3593 case 0: 3594 vinstr = "vmrun"; 3595 break; 3596 case 1: 3597 vinstr = "vmmcall"; 3598 break; 3599 case 2: 3600 vinstr = "vmload"; 3601 break; 3602 case 3: 3603 vinstr = "vmsave"; 3604 break; 3605 case 4: 3606 vinstr = "stgi"; 3607 break; 3608 case 5: 3609 vinstr = "clgi"; 3610 break; 3611 case 6: 3612 vinstr = "skinit"; 3613 break; 3614 case 7: 3615 vinstr = "invlpga"; 3616 break; 3617 } 3618 3619 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 3620 #endif 3621 NOMEM; 3622 break; 3623 } 3624 /*FALLTHROUGH*/ 3625 case MONITOR_MWAIT: 3626 if (mode == 3) { 3627 if (r_m == 0) { 3628 #ifdef DIS_TEXT 3629 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 3630 #endif 3631 NOMEM; 3632 break; 3633 } else if (r_m == 1) { 3634 #ifdef DIS_TEXT 3635 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 3636 #endif 3637 NOMEM; 3638 break; 3639 } else { 3640 goto error; 3641 } 3642 } 3643 /*FALLTHROUGH*/ 3644 case XGETBV_XSETBV: 3645 if (mode == 3) { 3646 if (r_m == 0) { 3647 #ifdef DIS_TEXT 3648 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 3649 #endif 3650 NOMEM; 3651 break; 3652 } else if (r_m == 1) { 3653 #ifdef DIS_TEXT 3654 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 3655 #endif 3656 NOMEM; 3657 break; 3658 } else { 3659 goto error; 3660 } 3661 3662 } 3663 /*FALLTHROUGH*/ 3664 case MO: 3665 /* Similar to M, but only memory (no direct registers) */ 3666 wbit = LONG_OPND; 3667 dtrace_get_modrm(x, &mode, ®, &r_m); 3668 if (mode == 3) 3669 goto error; 3670 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 3671 dtrace_get_operand(x, mode, r_m, wbit, 0); 3672 break; 3673 3674 /* move special register to register or reverse if vbit */ 3675 case SREG: 3676 switch (opcode5) { 3677 3678 case 2: 3679 vbit = 1; 3680 /*FALLTHROUGH*/ 3681 case 0: 3682 wbit = CONTROL_OPND; 3683 break; 3684 3685 case 3: 3686 vbit = 1; 3687 /*FALLTHROUGH*/ 3688 case 1: 3689 wbit = DEBUG_OPND; 3690 break; 3691 3692 case 6: 3693 vbit = 1; 3694 /*FALLTHROUGH*/ 3695 case 4: 3696 wbit = TEST_OPND; 3697 break; 3698 3699 } 3700 dtrace_get_modrm(x, &mode, ®, &r_m); 3701 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3702 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 3703 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 3704 NOMEM; 3705 break; 3706 3707 /* 3708 * single register operand with register in the low 3 3709 * bits of op code 3710 */ 3711 case R: 3712 if (opcode_bytes == 2) 3713 reg = REGNO(opcode5); 3714 else 3715 reg = REGNO(opcode2); 3716 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3717 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3718 NOMEM; 3719 break; 3720 3721 /* 3722 * register to accumulator with register in the low 3 3723 * bits of op code, xchg instructions 3724 */ 3725 case RA: 3726 NOMEM; 3727 reg = REGNO(opcode2); 3728 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 3729 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 3730 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 3731 break; 3732 3733 /* 3734 * single segment register operand, with register in 3735 * bits 3-4 of op code byte 3736 */ 3737 case SEG: 3738 NOMEM; 3739 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 3740 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 3741 break; 3742 3743 /* 3744 * single segment register operand, with register in 3745 * bits 3-5 of op code 3746 */ 3747 case LSEG: 3748 NOMEM; 3749 /* long seg reg from opcode */ 3750 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 3751 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 3752 break; 3753 3754 /* memory or register operand to register */ 3755 case MR: 3756 if (vex_prefetch) 3757 x->d86_got_modrm = 1; 3758 wbit = LONG_OPND; 3759 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3760 break; 3761 3762 case RM: 3763 case RM_66r: 3764 wbit = LONG_OPND; 3765 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 3766 break; 3767 3768 /* MMX/SIMD-Int memory or mm reg to mm reg */ 3769 case MM: 3770 case MMO: 3771 #ifdef DIS_TEXT 3772 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3773 #else 3774 wbit = LONG_OPND; 3775 #endif 3776 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 3777 break; 3778 3779 case MMOIMPL: 3780 #ifdef DIS_TEXT 3781 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 3782 #else 3783 wbit = LONG_OPND; 3784 #endif 3785 dtrace_get_modrm(x, &mode, ®, &r_m); 3786 if (mode != REG_ONLY) 3787 goto error; 3788 3789 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3790 dtrace_get_operand(x, mode, r_m, wbit, 0); 3791 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 3792 mode = 0; /* change for memory access size... */ 3793 break; 3794 3795 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 3796 case MMO3P: 3797 wbit = MM_OPND; 3798 goto xmm3p; 3799 case XMM3P: 3800 wbit = XMM_OPND; 3801 xmm3p: 3802 dtrace_get_modrm(x, &mode, ®, &r_m); 3803 if (mode != REG_ONLY) 3804 goto error; 3805 3806 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 3807 1); 3808 NOMEM; 3809 break; 3810 3811 case XMM3PM_66r: 3812 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 3813 1, 0); 3814 break; 3815 3816 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 3817 case MMOPRM: 3818 wbit = LONG_OPND; 3819 w2 = MM_OPND; 3820 goto xmmprm; 3821 case XMMPRM: 3822 case XMMPRM_66r: 3823 wbit = LONG_OPND; 3824 w2 = XMM_OPND; 3825 xmmprm: 3826 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 3827 break; 3828 3829 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 3830 case MMOPM: 3831 case MMOPM_66o: 3832 wbit = w2 = MM_OPND; 3833 goto xmmprm; 3834 3835 /* MMX/SIMD-Int mm reg to r32 */ 3836 case MMOM3: 3837 NOMEM; 3838 dtrace_get_modrm(x, &mode, ®, &r_m); 3839 if (mode != REG_ONLY) 3840 goto error; 3841 wbit = MM_OPND; 3842 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 3843 break; 3844 3845 /* SIMD memory or xmm reg operand to xmm reg */ 3846 case XMM: 3847 case XMM_66o: 3848 case XMM_66r: 3849 case XMMO: 3850 case XMMXIMPL: 3851 wbit = XMM_OPND; 3852 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 3853 3854 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 3855 goto error; 3856 3857 #ifdef DIS_TEXT 3858 /* 3859 * movlps and movhlps share opcodes. They differ in the 3860 * addressing modes allowed for their operands. 3861 * movhps and movlhps behave similarly. 3862 */ 3863 if (mode == REG_ONLY) { 3864 if (strcmp(dp->it_name, "movlps") == 0) 3865 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 3866 else if (strcmp(dp->it_name, "movhps") == 0) 3867 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 3868 } 3869 #endif 3870 if (dp->it_adrmode == XMMXIMPL) 3871 mode = 0; /* change for memory access size... */ 3872 break; 3873 3874 /* SIMD xmm reg to memory or xmm reg */ 3875 case XMMS: 3876 case XMMOS: 3877 case XMMMS: 3878 case XMMOMS: 3879 dtrace_get_modrm(x, &mode, ®, &r_m); 3880 #ifdef DIS_TEXT 3881 if ((strcmp(dp->it_name, "movlps") == 0 || 3882 strcmp(dp->it_name, "movhps") == 0 || 3883 strcmp(dp->it_name, "movntps") == 0) && 3884 mode == REG_ONLY) 3885 goto error; 3886 #endif 3887 wbit = XMM_OPND; 3888 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 3889 break; 3890 3891 /* SIMD memory to xmm reg */ 3892 case XMMM: 3893 case XMMM_66r: 3894 case XMMOM: 3895 wbit = XMM_OPND; 3896 dtrace_get_modrm(x, &mode, ®, &r_m); 3897 #ifdef DIS_TEXT 3898 if (mode == REG_ONLY) { 3899 if (strcmp(dp->it_name, "movhps") == 0) 3900 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 3901 else 3902 goto error; 3903 } 3904 #endif 3905 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 3906 break; 3907 3908 /* SIMD memory or r32 to xmm reg */ 3909 case XMM3MX: 3910 wbit = LONG_OPND; 3911 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 3912 break; 3913 3914 case XMM3MXS: 3915 wbit = LONG_OPND; 3916 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 3917 break; 3918 3919 /* SIMD memory or mm reg to xmm reg */ 3920 case XMMOMX: 3921 /* SIMD mm to xmm */ 3922 case XMMMX: 3923 wbit = MM_OPND; 3924 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 3925 break; 3926 3927 /* SIMD memory or xmm reg to mm reg */ 3928 case XMMXMM: 3929 case XMMOXMM: 3930 case XMMXM: 3931 wbit = XMM_OPND; 3932 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 3933 break; 3934 3935 3936 /* SIMD memory or xmm reg to r32 */ 3937 case XMMXM3: 3938 wbit = XMM_OPND; 3939 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 3940 break; 3941 3942 /* SIMD xmm to r32 */ 3943 case XMMX3: 3944 case XMMOX3: 3945 dtrace_get_modrm(x, &mode, ®, &r_m); 3946 if (mode != REG_ONLY) 3947 goto error; 3948 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 3949 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 3950 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 3951 NOMEM; 3952 break; 3953 3954 /* SIMD predicated memory or xmm reg with/to xmm reg */ 3955 case XMMP: 3956 case XMMP_66r: 3957 case XMMP_66o: 3958 case XMMOPM: 3959 wbit = XMM_OPND; 3960 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 3961 1); 3962 3963 #ifdef DIS_TEXT 3964 /* 3965 * cmpps and cmpss vary their instruction name based 3966 * on the value of imm8. Other XMMP instructions, 3967 * such as shufps, require explicit specification of 3968 * the predicate. 3969 */ 3970 if (dp->it_name[0] == 'c' && 3971 dp->it_name[1] == 'm' && 3972 dp->it_name[2] == 'p' && 3973 strlen(dp->it_name) == 5) { 3974 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 3975 3976 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 3977 goto error; 3978 3979 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 3980 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 3981 OPLEN); 3982 (void) strlcat(x->d86_mnem, 3983 dp->it_name + strlen(dp->it_name) - 2, 3984 OPLEN); 3985 x->d86_opnd[0] = x->d86_opnd[1]; 3986 x->d86_opnd[1] = x->d86_opnd[2]; 3987 x->d86_numopnds = 2; 3988 } 3989 #endif 3990 break; 3991 3992 case XMMX2I: 3993 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 3994 1); 3995 NOMEM; 3996 break; 3997 3998 case XMM2I: 3999 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 4000 NOMEM; 4001 break; 4002 4003 /* immediate operand to accumulator */ 4004 case IA: 4005 wbit = WBIT(opcode2); 4006 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4007 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4008 NOMEM; 4009 break; 4010 4011 /* memory or register operand to accumulator */ 4012 case MA: 4013 wbit = WBIT(opcode2); 4014 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4015 dtrace_get_operand(x, mode, r_m, wbit, 0); 4016 break; 4017 4018 /* si register to di register used to reference memory */ 4019 case SD: 4020 #ifdef DIS_TEXT 4021 dtrace_check_override(x, 0); 4022 x->d86_numopnds = 2; 4023 if (addr_size == SIZE64) { 4024 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 4025 OPLEN); 4026 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 4027 OPLEN); 4028 } else if (addr_size == SIZE32) { 4029 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 4030 OPLEN); 4031 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 4032 OPLEN); 4033 } else { 4034 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4035 OPLEN); 4036 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 4037 OPLEN); 4038 } 4039 #endif 4040 wbit = LONG_OPND; 4041 break; 4042 4043 /* accumulator to di register */ 4044 case AD: 4045 wbit = WBIT(opcode2); 4046 #ifdef DIS_TEXT 4047 dtrace_check_override(x, 1); 4048 x->d86_numopnds = 2; 4049 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 4050 if (addr_size == SIZE64) 4051 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 4052 OPLEN); 4053 else if (addr_size == SIZE32) 4054 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 4055 OPLEN); 4056 else 4057 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 4058 OPLEN); 4059 #endif 4060 break; 4061 4062 /* si register to accumulator */ 4063 case SA: 4064 wbit = WBIT(opcode2); 4065 #ifdef DIS_TEXT 4066 dtrace_check_override(x, 0); 4067 x->d86_numopnds = 2; 4068 if (addr_size == SIZE64) 4069 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 4070 OPLEN); 4071 else if (addr_size == SIZE32) 4072 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 4073 OPLEN); 4074 else 4075 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4076 OPLEN); 4077 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4078 #endif 4079 break; 4080 4081 /* 4082 * single operand, a 16/32 bit displacement 4083 */ 4084 case D: 4085 wbit = LONG_OPND; 4086 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 4087 NOMEM; 4088 break; 4089 4090 /* jmp/call indirect to memory or register operand */ 4091 case INM: 4092 #ifdef DIS_TEXT 4093 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 4094 #endif 4095 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4096 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4097 wbit = LONG_OPND; 4098 break; 4099 4100 /* 4101 * for long jumps and long calls -- a new code segment 4102 * register and an offset in IP -- stored in object 4103 * code in reverse order. Note - not valid in amd64 4104 */ 4105 case SO: 4106 dtrace_check_override(x, 1); 4107 wbit = LONG_OPND; 4108 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 4109 #ifdef DIS_TEXT 4110 x->d86_opnd[1].d86_mode = MODE_SIGNED; 4111 #endif 4112 /* will now get segment operand */ 4113 dtrace_imm_opnd(x, wbit, 2, 0); 4114 break; 4115 4116 /* 4117 * jmp/call. single operand, 8 bit displacement. 4118 * added to current EIP in 'compofff' 4119 */ 4120 case BD: 4121 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 4122 NOMEM; 4123 break; 4124 4125 /* single 32/16 bit immediate operand */ 4126 case I: 4127 wbit = LONG_OPND; 4128 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 4129 break; 4130 4131 /* single 8 bit immediate operand */ 4132 case Ib: 4133 wbit = LONG_OPND; 4134 dtrace_imm_opnd(x, wbit, 1, 0); 4135 break; 4136 4137 case ENTER: 4138 wbit = LONG_OPND; 4139 dtrace_imm_opnd(x, wbit, 2, 0); 4140 dtrace_imm_opnd(x, wbit, 1, 1); 4141 switch (opnd_size) { 4142 case SIZE64: 4143 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 4144 break; 4145 case SIZE32: 4146 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 4147 break; 4148 case SIZE16: 4149 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 4150 break; 4151 } 4152 4153 break; 4154 4155 /* 16-bit immediate operand */ 4156 case RET: 4157 wbit = LONG_OPND; 4158 dtrace_imm_opnd(x, wbit, 2, 0); 4159 break; 4160 4161 /* single 8 bit port operand */ 4162 case P: 4163 dtrace_check_override(x, 0); 4164 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 4165 NOMEM; 4166 break; 4167 4168 /* single operand, dx register (variable port instruction) */ 4169 case V: 4170 x->d86_numopnds = 1; 4171 dtrace_check_override(x, 0); 4172 #ifdef DIS_TEXT 4173 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 4174 #endif 4175 NOMEM; 4176 break; 4177 4178 /* 4179 * The int instruction, which has two forms: 4180 * int 3 (breakpoint) or 4181 * int n, where n is indicated in the subsequent 4182 * byte (format Ib). The int 3 instruction (opcode 0xCC), 4183 * where, although the 3 looks like an operand, 4184 * it is implied by the opcode. It must be converted 4185 * to the correct base and output. 4186 */ 4187 case INT3: 4188 #ifdef DIS_TEXT 4189 x->d86_numopnds = 1; 4190 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4191 x->d86_opnd[0].d86_value_size = 1; 4192 x->d86_opnd[0].d86_value = 3; 4193 #endif 4194 NOMEM; 4195 break; 4196 4197 /* single 8 bit immediate operand */ 4198 case INTx: 4199 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 4200 NOMEM; 4201 break; 4202 4203 /* an unused byte must be discarded */ 4204 case U: 4205 if (x->d86_get_byte(x->d86_data) < 0) 4206 goto error; 4207 x->d86_len++; 4208 NOMEM; 4209 break; 4210 4211 case CBW: 4212 #ifdef DIS_TEXT 4213 if (opnd_size == SIZE16) 4214 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 4215 else if (opnd_size == SIZE32) 4216 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 4217 else 4218 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 4219 #endif 4220 wbit = LONG_OPND; 4221 NOMEM; 4222 break; 4223 4224 case CWD: 4225 #ifdef DIS_TEXT 4226 if (opnd_size == SIZE16) 4227 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 4228 else if (opnd_size == SIZE32) 4229 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 4230 else 4231 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 4232 #endif 4233 wbit = LONG_OPND; 4234 NOMEM; 4235 break; 4236 4237 case XMMSFNC: 4238 /* 4239 * sfence is sfence if mode is REG_ONLY. If mode isn't 4240 * REG_ONLY, mnemonic should be 'clflush'. 4241 */ 4242 dtrace_get_modrm(x, &mode, ®, &r_m); 4243 4244 /* sfence doesn't take operands */ 4245 #ifdef DIS_TEXT 4246 if (mode == REG_ONLY) { 4247 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 4248 } else { 4249 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 4250 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4251 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 4252 NOMEM; 4253 } 4254 #else 4255 if (mode != REG_ONLY) { 4256 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4257 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4258 NOMEM; 4259 } 4260 #endif 4261 break; 4262 4263 /* 4264 * no disassembly, the mnemonic was all there was so go on 4265 */ 4266 case NORM: 4267 if (dp->it_invalid32 && cpu_mode != SIZE64) 4268 goto error; 4269 NOMEM; 4270 /*FALLTHROUGH*/ 4271 case IMPLMEM: 4272 break; 4273 4274 case XMMFENCE: 4275 /* 4276 * XRSTOR and LFENCE share the same opcode but differ in mode 4277 */ 4278 dtrace_get_modrm(x, &mode, ®, &r_m); 4279 4280 if (mode == REG_ONLY) { 4281 /* 4282 * Only the following exact byte sequences are allowed: 4283 * 4284 * 0f ae e8 lfence 4285 * 0f ae f0 mfence 4286 */ 4287 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 4288 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 4289 goto error; 4290 } else { 4291 #ifdef DIS_TEXT 4292 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 4293 #endif 4294 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4295 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 4296 } 4297 break; 4298 4299 /* float reg */ 4300 case F: 4301 #ifdef DIS_TEXT 4302 x->d86_numopnds = 1; 4303 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 4304 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 4305 #endif 4306 NOMEM; 4307 break; 4308 4309 /* float reg to float reg, with ret bit present */ 4310 case FF: 4311 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 4312 /*FALLTHROUGH*/ 4313 case FFC: /* case for vbit always = 0 */ 4314 #ifdef DIS_TEXT 4315 x->d86_numopnds = 2; 4316 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 4317 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 4318 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 4319 #endif 4320 NOMEM; 4321 break; 4322 4323 /* AVX instructions */ 4324 case VEX_MO: 4325 /* op(ModR/M.r/m) */ 4326 x->d86_numopnds = 1; 4327 dtrace_get_modrm(x, &mode, ®, &r_m); 4328 #ifdef DIS_TEXT 4329 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 4330 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 4331 #endif 4332 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4333 dtrace_get_operand(x, mode, r_m, wbit, 0); 4334 break; 4335 case VEX_RMrX: 4336 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 4337 x->d86_numopnds = 3; 4338 dtrace_get_modrm(x, &mode, ®, &r_m); 4339 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4340 4341 if (mode != REG_ONLY) { 4342 if ((dp == &dis_opAVXF20F[0x10]) || 4343 (dp == &dis_opAVXF30F[0x10])) { 4344 /* vmovsd <m64>, <xmm> */ 4345 /* or vmovss <m64>, <xmm> */ 4346 x->d86_numopnds = 2; 4347 goto L_VEX_MX; 4348 } 4349 } 4350 4351 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4352 /* 4353 * VEX prefix uses the 1's complement form to encode the 4354 * XMM/YMM regs 4355 */ 4356 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4357 4358 if ((dp == &dis_opAVXF20F[0x2A]) || 4359 (dp == &dis_opAVXF30F[0x2A])) { 4360 /* 4361 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 4362 * <xmm>, <xmm> 4363 */ 4364 wbit = LONG_OPND; 4365 } 4366 #ifdef DIS_TEXT 4367 else if ((mode == REG_ONLY) && 4368 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 4369 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 4370 } else if ((mode == REG_ONLY) && 4371 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 4372 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 4373 } 4374 #endif 4375 dtrace_get_operand(x, mode, r_m, wbit, 0); 4376 4377 break; 4378 4379 case VEX_RRX: 4380 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 4381 x->d86_numopnds = 3; 4382 4383 dtrace_get_modrm(x, &mode, ®, &r_m); 4384 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4385 4386 if (mode != REG_ONLY) { 4387 if ((dp == &dis_opAVXF20F[0x11]) || 4388 (dp == &dis_opAVXF30F[0x11])) { 4389 /* vmovsd <xmm>, <m64> */ 4390 /* or vmovss <xmm>, <m64> */ 4391 x->d86_numopnds = 2; 4392 goto L_VEX_RM; 4393 } 4394 } 4395 4396 dtrace_get_operand(x, mode, r_m, wbit, 2); 4397 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4398 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4399 break; 4400 4401 case VEX_RMRX: 4402 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 4403 x->d86_numopnds = 4; 4404 4405 dtrace_get_modrm(x, &mode, ®, &r_m); 4406 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4407 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 4408 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 4409 if (dp == &dis_opAVX660F3A[0x18]) { 4410 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 4411 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 4412 } else if ((dp == &dis_opAVX660F3A[0x20]) || 4413 (dp == & dis_opAVX660F[0xC4])) { 4414 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 4415 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 4416 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 4417 } else if (dp == &dis_opAVX660F3A[0x22]) { 4418 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 4419 #ifdef DIS_TEXT 4420 if (vex_W) 4421 x->d86_mnem[6] = 'q'; 4422 #endif 4423 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 4424 } else { 4425 dtrace_get_operand(x, mode, r_m, wbit, 1); 4426 } 4427 4428 /* one byte immediate number */ 4429 dtrace_imm_opnd(x, wbit, 1, 0); 4430 4431 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 4432 if ((dp == &dis_opAVX660F3A[0x4A]) || 4433 (dp == &dis_opAVX660F3A[0x4B]) || 4434 (dp == &dis_opAVX660F3A[0x4C])) { 4435 #ifdef DIS_TEXT 4436 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 4437 #endif 4438 x->d86_opnd[0].d86_mode = MODE_NONE; 4439 #ifdef DIS_TEXT 4440 if (vex_L) 4441 (void) strncpy(x->d86_opnd[0].d86_opnd, 4442 dis_YMMREG[regnum], OPLEN); 4443 else 4444 (void) strncpy(x->d86_opnd[0].d86_opnd, 4445 dis_XMMREG[regnum], OPLEN); 4446 #endif 4447 } 4448 break; 4449 4450 case VEX_MX: 4451 /* ModR/M.reg := op(ModR/M.rm) */ 4452 x->d86_numopnds = 2; 4453 4454 dtrace_get_modrm(x, &mode, ®, &r_m); 4455 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4456 L_VEX_MX: 4457 4458 if ((dp == &dis_opAVXF20F[0xE6]) || 4459 (dp == &dis_opAVX660F[0x5A]) || 4460 (dp == &dis_opAVX660F[0xE6])) { 4461 /* vcvtpd2dq <ymm>, <xmm> */ 4462 /* or vcvtpd2ps <ymm>, <xmm> */ 4463 /* or vcvttpd2dq <ymm>, <xmm> */ 4464 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 4465 dtrace_get_operand(x, mode, r_m, wbit, 0); 4466 } else if ((dp == &dis_opAVXF30F[0xE6]) || 4467 (dp == &dis_opAVX0F[0x5][0xA]) || 4468 (dp == &dis_opAVX660F38[0x13])) { 4469 /* vcvtdq2pd <xmm>, <ymm> */ 4470 /* or vcvtps2pd <xmm>, <ymm> */ 4471 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4472 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 4473 } else if (dp == &dis_opAVX660F[0x6E]) { 4474 /* vmovd/q <reg/mem 32/64>, <xmm> */ 4475 #ifdef DIS_TEXT 4476 if (vex_W) 4477 x->d86_mnem[4] = 'q'; 4478 #endif 4479 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4480 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 4481 } else { 4482 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4483 dtrace_get_operand(x, mode, r_m, wbit, 0); 4484 } 4485 4486 break; 4487 4488 case VEX_MXI: 4489 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 4490 x->d86_numopnds = 3; 4491 4492 dtrace_get_modrm(x, &mode, ®, &r_m); 4493 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4494 4495 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4496 dtrace_get_operand(x, mode, r_m, wbit, 1); 4497 4498 /* one byte immediate number */ 4499 dtrace_imm_opnd(x, wbit, 1, 0); 4500 break; 4501 4502 case VEX_XXI: 4503 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 4504 x->d86_numopnds = 3; 4505 4506 dtrace_get_modrm(x, &mode, ®, &r_m); 4507 #ifdef DIS_TEXT 4508 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 4509 OPLEN); 4510 #endif 4511 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4512 4513 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 4514 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 4515 4516 /* one byte immediate number */ 4517 dtrace_imm_opnd(x, wbit, 1, 0); 4518 break; 4519 4520 case VEX_MR: 4521 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 4522 if (dp == &dis_opAVX660F[0xC5]) { 4523 /* vpextrw <imm8>, <xmm>, <reg> */ 4524 x->d86_numopnds = 2; 4525 vbit = 2; 4526 } else { 4527 x->d86_numopnds = 2; 4528 vbit = 1; 4529 } 4530 4531 dtrace_get_modrm(x, &mode, ®, &r_m); 4532 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4533 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 4534 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 4535 4536 if (vbit == 2) 4537 dtrace_imm_opnd(x, wbit, 1, 0); 4538 4539 break; 4540 4541 case VEX_RRI: 4542 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 4543 x->d86_numopnds = 2; 4544 4545 dtrace_get_modrm(x, &mode, ®, &r_m); 4546 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4547 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4548 dtrace_get_operand(x, mode, r_m, wbit, 0); 4549 break; 4550 4551 case VEX_RX: 4552 /* ModR/M.rm := op(ModR/M.reg) */ 4553 /* vextractf128 || vcvtps2ph */ 4554 if (dp == &dis_opAVX660F3A[0x19] || 4555 dp == &dis_opAVX660F3A[0x1d]) { 4556 x->d86_numopnds = 3; 4557 4558 dtrace_get_modrm(x, &mode, ®, &r_m); 4559 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4560 4561 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 4562 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4563 4564 /* one byte immediate number */ 4565 dtrace_imm_opnd(x, wbit, 1, 0); 4566 break; 4567 } 4568 4569 x->d86_numopnds = 2; 4570 4571 dtrace_get_modrm(x, &mode, ®, &r_m); 4572 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4573 dtrace_get_operand(x, mode, r_m, wbit, 1); 4574 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4575 break; 4576 4577 case VEX_RR: 4578 /* ModR/M.rm := op(ModR/M.reg) */ 4579 x->d86_numopnds = 2; 4580 4581 dtrace_get_modrm(x, &mode, ®, &r_m); 4582 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4583 4584 if (dp == &dis_opAVX660F[0x7E]) { 4585 /* vmovd/q <reg/mem 32/64>, <xmm> */ 4586 #ifdef DIS_TEXT 4587 if (vex_W) 4588 x->d86_mnem[4] = 'q'; 4589 #endif 4590 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 4591 } else 4592 dtrace_get_operand(x, mode, r_m, wbit, 1); 4593 4594 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4595 break; 4596 4597 case VEX_RRi: 4598 /* ModR/M.rm := op(ModR/M.reg, imm) */ 4599 x->d86_numopnds = 3; 4600 4601 dtrace_get_modrm(x, &mode, ®, &r_m); 4602 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4603 4604 #ifdef DIS_TEXT 4605 if (dp == &dis_opAVX660F3A[0x16]) { 4606 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 4607 if (vex_W) 4608 x->d86_mnem[6] = 'q'; 4609 } 4610 #endif 4611 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 4612 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4613 4614 /* one byte immediate number */ 4615 dtrace_imm_opnd(x, wbit, 1, 0); 4616 break; 4617 4618 case VEX_RM: 4619 /* ModR/M.rm := op(ModR/M.reg) */ 4620 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 4621 x->d86_numopnds = 3; 4622 4623 dtrace_get_modrm(x, &mode, ®, &r_m); 4624 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4625 4626 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 4627 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4628 /* one byte immediate number */ 4629 dtrace_imm_opnd(x, wbit, 1, 0); 4630 break; 4631 } 4632 x->d86_numopnds = 2; 4633 4634 dtrace_get_modrm(x, &mode, ®, &r_m); 4635 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4636 L_VEX_RM: 4637 vbit = 1; 4638 dtrace_get_operand(x, mode, r_m, wbit, vbit); 4639 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 4640 4641 break; 4642 4643 case VEX_RRM: 4644 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 4645 x->d86_numopnds = 3; 4646 4647 dtrace_get_modrm(x, &mode, ®, &r_m); 4648 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4649 dtrace_get_operand(x, mode, r_m, wbit, 2); 4650 /* VEX use the 1's complement form encode the XMM/YMM regs */ 4651 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4652 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 4653 break; 4654 4655 case VEX_RMX: 4656 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 4657 x->d86_numopnds = 3; 4658 4659 dtrace_get_modrm(x, &mode, ®, &r_m); 4660 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 4661 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 4662 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 4663 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 4664 break; 4665 4666 case VEX_NONE: 4667 #ifdef DIS_TEXT 4668 if (vex_L) 4669 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 4670 #endif 4671 break; 4672 /* an invalid op code */ 4673 case AM: 4674 case DM: 4675 case OVERRIDE: 4676 case PREFIX: 4677 case UNKNOWN: 4678 NOMEM; 4679 default: 4680 goto error; 4681 } /* end switch */ 4682 if (x->d86_error) 4683 goto error; 4684 4685 done: 4686 #ifdef DIS_MEM 4687 /* 4688 * compute the size of any memory accessed by the instruction 4689 */ 4690 if (x->d86_memsize != 0) { 4691 return (0); 4692 } else if (dp->it_stackop) { 4693 switch (opnd_size) { 4694 case SIZE16: 4695 x->d86_memsize = 2; 4696 break; 4697 case SIZE32: 4698 x->d86_memsize = 4; 4699 break; 4700 case SIZE64: 4701 x->d86_memsize = 8; 4702 break; 4703 } 4704 } else if (nomem || mode == REG_ONLY) { 4705 x->d86_memsize = 0; 4706 4707 } else if (dp->it_size != 0) { 4708 /* 4709 * In 64 bit mode descriptor table entries 4710 * go up to 10 bytes and popf/pushf are always 8 bytes 4711 */ 4712 if (x->d86_mode == SIZE64 && dp->it_size == 6) 4713 x->d86_memsize = 10; 4714 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 4715 (opcode2 == 0xc || opcode2 == 0xd)) 4716 x->d86_memsize = 8; 4717 else 4718 x->d86_memsize = dp->it_size; 4719 4720 } else if (wbit == 0) { 4721 x->d86_memsize = 1; 4722 4723 } else if (wbit == LONG_OPND) { 4724 if (opnd_size == SIZE64) 4725 x->d86_memsize = 8; 4726 else if (opnd_size == SIZE32) 4727 x->d86_memsize = 4; 4728 else 4729 x->d86_memsize = 2; 4730 4731 } else if (wbit == SEG_OPND) { 4732 x->d86_memsize = 4; 4733 4734 } else { 4735 x->d86_memsize = 8; 4736 } 4737 #endif 4738 return (0); 4739 4740 error: 4741 #ifdef DIS_TEXT 4742 (void) strlcat(x->d86_mnem, "undef", OPLEN); 4743 #endif 4744 return (1); 4745 } 4746 4747 #ifdef DIS_TEXT 4748 4749 /* 4750 * Some instructions should have immediate operands printed 4751 * as unsigned integers. We compare against this table. 4752 */ 4753 static char *unsigned_ops[] = { 4754 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 4755 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 4756 0 4757 }; 4758 4759 4760 static int 4761 isunsigned_op(char *opcode) 4762 { 4763 char *where; 4764 int i; 4765 int is_unsigned = 0; 4766 4767 /* 4768 * Work back to start of last mnemonic, since we may have 4769 * prefixes on some opcodes. 4770 */ 4771 where = opcode + strlen(opcode) - 1; 4772 while (where > opcode && *where != ' ') 4773 --where; 4774 if (*where == ' ') 4775 ++where; 4776 4777 for (i = 0; unsigned_ops[i]; ++i) { 4778 if (strncmp(where, unsigned_ops[i], 4779 strlen(unsigned_ops[i]))) 4780 continue; 4781 is_unsigned = 1; 4782 break; 4783 } 4784 return (is_unsigned); 4785 } 4786 4787 /* 4788 * Print a numeric immediate into end of buf, maximum length buflen. 4789 * The immediate may be an address or a displacement. Mask is set 4790 * for address size. If the immediate is a "small negative", or 4791 * if it's a negative displacement of any magnitude, print as -<absval>. 4792 * Respect the "octal" flag. "Small negative" is defined as "in the 4793 * interval [NEG_LIMIT, 0)". 4794 * 4795 * Also, "isunsigned_op()" instructions never print negatives. 4796 * 4797 * Return whether we decided to print a negative value or not. 4798 */ 4799 4800 #define NEG_LIMIT -255 4801 enum {IMM, DISP}; 4802 enum {POS, TRY_NEG}; 4803 4804 static int 4805 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 4806 size_t buflen, int disp, int try_neg) 4807 { 4808 int curlen; 4809 int64_t sv = (int64_t)usv; 4810 int octal = dis->d86_flags & DIS_F_OCTAL; 4811 4812 curlen = strlen(buf); 4813 4814 if (try_neg == TRY_NEG && sv < 0 && 4815 (disp || sv >= NEG_LIMIT) && 4816 !isunsigned_op(dis->d86_mnem)) { 4817 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 4818 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 4819 return (1); 4820 } else { 4821 if (disp == DISP) 4822 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 4823 octal ? "+0%llo" : "+0x%llx", usv & mask); 4824 else 4825 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 4826 octal ? "0%llo" : "0x%llx", usv & mask); 4827 return (0); 4828 4829 } 4830 } 4831 4832 4833 static int 4834 log2(int size) 4835 { 4836 switch (size) { 4837 case 1: return (0); 4838 case 2: return (1); 4839 case 4: return (2); 4840 case 8: return (3); 4841 } 4842 return (0); 4843 } 4844 4845 /* ARGSUSED */ 4846 void 4847 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 4848 size_t buflen) 4849 { 4850 uint64_t reltgt = 0; 4851 uint64_t tgt = 0; 4852 int curlen; 4853 int (*lookup)(void *, uint64_t, char *, size_t); 4854 int i; 4855 int64_t sv; 4856 uint64_t usv, mask, save_mask, save_usv; 4857 static uint64_t masks[] = 4858 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 4859 save_usv = 0; 4860 4861 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 4862 4863 /* 4864 * For PC-relative jumps, the pc is really the next pc after executing 4865 * this instruction, so increment it appropriately. 4866 */ 4867 pc += dis->d86_len; 4868 4869 for (i = 0; i < dis->d86_numopnds; i++) { 4870 d86opnd_t *op = &dis->d86_opnd[i]; 4871 4872 if (i != 0) 4873 (void) strlcat(buf, ",", buflen); 4874 4875 (void) strlcat(buf, op->d86_prefix, buflen); 4876 4877 /* 4878 * sv is for the signed, possibly-truncated immediate or 4879 * displacement; usv retains the original size and 4880 * unsignedness for symbol lookup. 4881 */ 4882 4883 sv = usv = op->d86_value; 4884 4885 /* 4886 * About masks: for immediates that represent 4887 * addresses, the appropriate display size is 4888 * the effective address size of the instruction. 4889 * This includes MODE_OFFSET, MODE_IPREL, and 4890 * MODE_RIPREL. Immediates that are simply 4891 * immediate values should display in the operand's 4892 * size, however, since they don't represent addresses. 4893 */ 4894 4895 /* d86_addr_size is SIZEnn, which is log2(real size) */ 4896 mask = masks[dis->d86_addr_size]; 4897 4898 /* d86_value_size and d86_imm_bytes are in bytes */ 4899 if (op->d86_mode == MODE_SIGNED || 4900 op->d86_mode == MODE_IMPLIED) 4901 mask = masks[log2(op->d86_value_size)]; 4902 4903 switch (op->d86_mode) { 4904 4905 case MODE_NONE: 4906 4907 (void) strlcat(buf, op->d86_opnd, buflen); 4908 break; 4909 4910 case MODE_SIGNED: 4911 case MODE_IMPLIED: 4912 case MODE_OFFSET: 4913 4914 tgt = usv; 4915 4916 if (dis->d86_seg_prefix) 4917 (void) strlcat(buf, dis->d86_seg_prefix, 4918 buflen); 4919 4920 if (op->d86_mode == MODE_SIGNED || 4921 op->d86_mode == MODE_IMPLIED) { 4922 (void) strlcat(buf, "$", buflen); 4923 } 4924 4925 if (print_imm(dis, usv, mask, buf, buflen, 4926 IMM, TRY_NEG) && 4927 (op->d86_mode == MODE_SIGNED || 4928 op->d86_mode == MODE_IMPLIED)) { 4929 4930 /* 4931 * We printed a negative value for an 4932 * immediate that wasn't a 4933 * displacement. Note that fact so we can 4934 * print the positive value as an 4935 * annotation. 4936 */ 4937 4938 save_usv = usv; 4939 save_mask = mask; 4940 } 4941 (void) strlcat(buf, op->d86_opnd, buflen); 4942 4943 break; 4944 4945 case MODE_IPREL: 4946 case MODE_RIPREL: 4947 4948 reltgt = pc + sv; 4949 4950 switch (mode) { 4951 case SIZE16: 4952 reltgt = (uint16_t)reltgt; 4953 break; 4954 case SIZE32: 4955 reltgt = (uint32_t)reltgt; 4956 break; 4957 } 4958 4959 (void) print_imm(dis, usv, mask, buf, buflen, 4960 DISP, TRY_NEG); 4961 4962 if (op->d86_mode == MODE_RIPREL) 4963 (void) strlcat(buf, "(%rip)", buflen); 4964 break; 4965 } 4966 } 4967 4968 /* 4969 * The symbol lookups may result in false positives, 4970 * particularly on object files, where small numbers may match 4971 * the 0-relative non-relocated addresses of symbols. 4972 */ 4973 4974 lookup = dis->d86_sym_lookup; 4975 if (tgt != 0) { 4976 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 4977 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 4978 (void) strlcat(buf, "\t<", buflen); 4979 curlen = strlen(buf); 4980 lookup(dis->d86_data, tgt, buf + curlen, 4981 buflen - curlen); 4982 (void) strlcat(buf, ">", buflen); 4983 } 4984 4985 /* 4986 * If we printed a negative immediate above, print the 4987 * positive in case our heuristic was unhelpful 4988 */ 4989 if (save_usv) { 4990 (void) strlcat(buf, "\t<", buflen); 4991 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 4992 IMM, POS); 4993 (void) strlcat(buf, ">", buflen); 4994 } 4995 } 4996 4997 if (reltgt != 0) { 4998 /* Print symbol or effective address for reltgt */ 4999 5000 (void) strlcat(buf, "\t<", buflen); 5001 curlen = strlen(buf); 5002 lookup(dis->d86_data, reltgt, buf + curlen, 5003 buflen - curlen); 5004 (void) strlcat(buf, ">", buflen); 5005 } 5006 } 5007 5008 #endif /* DIS_TEXT */ 5009