1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#pragma dictionary "PCIEX" 27 28#include <px_err.h> 29 30/* 31 * generic root complex/root port diagnosis rules 32 */ 33 34#define PCIEXFN pciexbus/pciexdev/pciexfn 35#define PCIEXFNHZ pciexbus<>/pciexdev<>/pciexfn<> 36 37#define RC_N 5 38#define RC_T 72h 39 40#define SW_FIT 5000 41#define FW_FIT 5000 42#define HB_FIT 400 43 44#define EPKT_DESC (payloadprop("desc") >> 12) 45#define EPKT_B_BIT (payloadprop("desc") & (1 << 7)) 46#define EPKT_C_BIT (payloadprop("desc") & (1 << 5)) 47#define EPKT_H_BIT (payloadprop("desc") & (1 << 4)) 48 49#define MATCHES_DESC(b, o, p, c, d) \ 50 (EPKT_DESC == (b << 16 | o << 12 | p << 8 | c << 4 | d)) 51 52#define IS_CE (EPKT_C_BIT != 0 && setserdsuffix(EPKT_DESC)) 53#define IS_UE (EPKT_C_BIT == 0) 54#define IS_BLOCKED (EPKT_B_BIT != 0) 55 56#define EPKT(b, o, p, c, d) \ 57 ereport.io.pciex.rc.epkt@hostbridge { MATCHES_DESC(b, o, p, c, d) } 58 59/* Ereport Events */ 60event ereport.io.pciex.rc.epkt@hostbridge {within(5s)}; 61 62/* Internal Events */ 63event error.io.pciex.rc.stall@hostbridge; 64event error.io.pciex.rc.poiscomp@hostbridge; 65event error.io.pciex.nr-d@hostbridge/pciexrc/PCIEXFN; 66event error.io.pciex.badreq-u@hostbridge/pciexrc/PCIEXFN; 67event error.io.pciex.poiscomp-d@hostbridge/pciexrc/PCIEXFN; 68event error.io.pciex.noimpact-d@hostbridge/pciexrc/PCIEXFN; 69event error.io.pciex.lost-d@hostbridge/pciexrc/PCIEXFN; 70event error.io.pciex.degraded-d@hostbridge/pciexrc/PCIEXFN; 71 72/* Upset event */ 73event upset.io.pciex.rc.discard@hostbridge; 74 75/* 76 * Fault Events 77 * Do no retire and FRUs for SW/FW faults 78 */ 79event fault.io.pciex.rc.generic-ue@hostbridge, 80 FITrate=HB_FIT, retire=0, response=0; 81event fault.io.pciex.rc.generic-sw@hostbridge, 82 FITrate=SW_FIT, retire=0, response=0; 83event fault.io.pciex.rc.generic-fw@hostbridge, 84 FITrate=FW_FIT, retire=0, response=0; 85 86/* Serd engine for CE errors */ 87engine serd.io.pciex.rc.generic-ce@hostbridge, N=RC_N, T=RC_T; 88event fault.io.pciex.rc.generic-ce@hostbridge, FITrate=HB_FIT, 89 engine=serd.io.pciex.rc.generic-ce@hostbridge; 90 91/* Fire faults */ 92event fault.io.fire.pciex.device@PCIEXFN, FITrate=1000; 93event fault.io.fire.pci.device@pcibus/pcidev/pcifn, FITrate=1000; 94 95/* Generic Root Complex Software faults */ 96prop fault.io.pciex.rc.generic-sw@hostbridge -> 97 ereport.io.pciex.rc.epkt@hostbridge { 98 MATCHES_DESC(BLOCK_INTR,OP_FIXED,PH_UNKNOWN,CND_ILL,DIR_INGRESS) || 99 MATCHES_DESC(BLOCK_INTR,OP_MSI32,PH_UNKNOWN,CND_ILL,DIR_IRR) || 100 MATCHES_DESC(BLOCK_INTR,OP_PCIEMSG,PH_UNKNOWN,CND_ILL,DIR_INGRESS) 101 }; 102 103/* Generic Root Complex Firmware faults */ 104prop fault.io.pciex.rc.generic-fw@hostbridge -> 105 ereport.io.pciex.rc.epkt@hostbridge { 106 MATCHES_DESC(BLOCK_HOSTBUS,OP_PIO,PH_ADDR,CND_UNMAP,DIR_WRITE) 107 }; 108 109/* Generic Root Complex CE faults */ 110prop fault.io.pciex.rc.generic-ce@hostbridge { IS_CE } -> 111 ereport.io.pciex.rc.epkt@hostbridge; 112 113/* Generic Root Complex UE faults from propagations */ 114event error.io.pciex.rc.generic-ue1@hostbridge; 115event error.io.pciex.rc.generic-ue2@hostbridge; 116 117prop fault.io.pciex.rc.generic-ue@hostbridge -> 118 error.io.pciex.rc.generic-ue1@hostbridge, 119 error.io.pciex.rc.generic-ue2@hostbridge, 120 error.io.pciex.rc.stall@hostbridge, 121 error.io.pciex.rc.poiscomp@hostbridge; 122 123/* Generic Root Complex UE propagations */ 124prop error.io.pciex.rc.generic-ue1@hostbridge { IS_UE && !IS_BLOCKED } -> 125 ereport.io.pciex.rc.epkt@hostbridge { 126 MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_INT,DIR_READ) || 127 MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_INT,DIR_UNKNOWN) || 128 MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_INT,DIR_WRITE) || 129 MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_TO,DIR_READ) || 130 MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_TO,DIR_WRITE) || 131 MATCHES_DESC(BLOCK_HOSTBUS,OP_PIO,PH_DATA,CND_INT,DIR_UNKNOWN) || 132 MATCHES_DESC(BLOCK_HOSTBUS,OP_UNKNOWN,PH_DATA,CND_INT,DIR_UNKNOWN) || 133 MATCHES_DESC(BLOCK_HOSTBUS,OP_UNKNOWN,PH_DATA,CND_INT,DIR_UNKNOWN) || 134 MATCHES_DESC(BLOCK_INTR,OP_MSI32,PH_DATA,CND_INT,DIR_UNKNOWN) || 135 MATCHES_DESC(BLOCK_INTR,OP_MSIQ,PH_DATA,CND_INT,DIR_UNKNOWN) 136 }; 137 138prop error.io.pciex.rc.generic-ue2@hostbridge { IS_UE && !IS_BLOCKED } -> 139 ereport.io.pciex.rc.epkt@hostbridge { 140 MATCHES_DESC(BLOCK_MMU,OP_TBW,PH_ADDR,CND_UNKNOWN,DIR_UNKNOWN) || 141 MATCHES_DESC(BLOCK_MMU,OP_TBW,PH_ADDR,CND_UNMAP,DIR_UNKNOWN) || 142 MATCHES_DESC(BLOCK_MMU,OP_TBW,PH_DATA,CND_INT,DIR_IRR) || 143 MATCHES_DESC(BLOCK_MMU,OP_TBW,PH_UNKNOWN,CND_UNKNOWN,DIR_UNKNOWN) || 144 MATCHES_DESC(BLOCK_MMU,OP_XLAT,PH_DATA,CND_INT,DIR_UNKNOWN) || 145 MATCHES_DESC(BLOCK_PORT,OP_DMA,PH_DATA,CND_INT,DIR_READ) || 146 MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_DATA,CND_INT,DIR_READ) || 147 MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_DATA,CND_INT,DIR_UNKNOWN) || 148 MATCHES_DESC(BLOCK_PORT,OP_UNKNOWN,PH_DATA,CND_INT,DIR_UNKNOWN) || 149 MATCHES_DESC(BLOCK_PORT,OP_UNKNOWN,PH_DATA,CND_INT,DIR_UNKNOWN) 150 }; 151 152/* Errors that will cause a pipe stall and thus a CTO in the fabric */ 153prop error.io.pciex.rc.stall@hostbridge (0) -> 154 error.io.pciex.nr-d@hostbridge/pciexrc<>/PCIEXFNHZ; 155 156prop error.io.pciex.rc.stall@hostbridge { IS_UE && IS_BLOCKED } -> 157 ereport.io.pciex.rc.epkt@hostbridge; 158 159/* 160 * Errors that will send a poisoned data to the fabric 161 * Also the poiscomp-d could represent a fault that a hardened driver 162 * handled and reported a service impact. 163 */ 164prop error.io.pciex.rc.poiscomp@hostbridge (0) -> 165 error.io.pciex.poiscomp-d@hostbridge/pciexrc<>/PCIEXFNHZ, 166 error.io.pciex.noimpact-d@hostbridge/pciexrc<>/PCIEXFNHZ, 167 error.io.pciex.lost-d@hostbridge/pciexrc<>/PCIEXFNHZ, 168 error.io.pciex.degraded-d@hostbridge/pciexrc<>/PCIEXFNHZ; 169 170prop error.io.pciex.rc.poiscomp@hostbridge { IS_UE && !IS_BLOCKED } -> 171 ereport.io.pciex.rc.epkt@hostbridge { 172 MATCHES_DESC(BLOCK_HOSTBUS,OP_DMA,PH_DATA,CND_INT,DIR_READ) 173 }; 174 175prop error.io.pciex.badreq-u@hostbridge/pciexrc/PCIEXFN { IS_UE && !IS_BLOCKED } (0) -> 176 ereport.io.pciex.rc.epkt@hostbridge { 177 MATCHES_DESC(BLOCK_MMU,OP_XLAT,PH_ADDR,CND_UNMAP,DIR_RDWR) || 178 MATCHES_DESC(BLOCK_MMU,OP_XLAT,PH_DATA,CND_INV,DIR_RDWR) || 179 MATCHES_DESC(BLOCK_MMU,OP_XLAT,PH_DATA,CND_PROT,DIR_RDWR) 180 }; 181 182prop upset.io.pciex.rc.discard@hostbridge -> 183 ereport.io.pciex.rc.epkt@hostbridge { 184 MATCHES_DESC(BLOCK_INTR,OP_MSI32,PH_DATA,CND_ILL,DIR_IRR) || 185 MATCHES_DESC(BLOCK_PORT,OP_LINK,PH_FC,CND_TO,DIR_IRR) || 186 MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_INV,DIR_RDWR) || 187 MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_RCA,DIR_WRITE) || 188 MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_RUR,DIR_WRITE) || 189 MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_TO,DIR_READ) || 190 MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_TO,DIR_WRITE) || 191 MATCHES_DESC(BLOCK_PORT,OP_PIO,PH_IRR,CND_UC,DIR_IRR) 192 }; 193 194/* Event queue overflow */ 195#define PROP_PLAT_FRU "FRU" 196#define GET_HB_FRU (confprop(asru(hostbridge), PROP_PLAT_FRU)) 197#define GET_PCIE_FRU (confprop(asru(pciexbus[b]/pciexdev[d]/pciexfn[0]), PROP_PLAT_FRU)) 198#define GET_PCI_FRU (confprop(asru(pcibus[b]/pcidev[d]/pcifn[0]), PROP_PLAT_FRU)) 199 200prop fault.io.fire.pciex.device@pciexbus[b]/pciexdev[d]/pciexfn[0] 201 { 202 /* 203 * Indict PCI-E FRU(s) under this root complex excluding the 204 * one that the Fire ASIC resides on. 205 */ 206 is_under(hostbridge, pciexbus[b]/pciexdev[d]/pciexfn[0]) && 207 (GET_HB_FRU != GET_PCIE_FRU) 208 } (0) -> EPKT(BLOCK_INTR,OP_MSIQ,PH_UNKNOWN,CND_OV,DIR_IRR); 209 210prop fault.io.fire.pci.device@pcibus[b]/pcidev[d]/pcifn[0] 211 { 212 /* 213 * Indict PCI FRU(s) under this root complex excluding the 214 * one that the Fire ASIC resides on. 215 */ 216 is_under(hostbridge, pcibus[b]/pcidev[d]/pcifn[0]) && 217 (GET_HB_FRU != GET_PCI_FRU) 218 } (0) -> EPKT(BLOCK_INTR,OP_MSIQ,PH_UNKNOWN,CND_OV,DIR_IRR); 219