1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* private devlink info interfaces */ 27 28 #ifndef _CFG_LINK_H 29 #define _CFG_LINK_H 30 31 #pragma ident "%Z%%M% %I% %E% SMI" 32 33 #include <devfsadm.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #define SCSI_CFG_LINK_RE "^cfg/c[0-9]+$" 40 #define SBD_CFG_LINK_RE "^cfg/((((N[0-9]+[.])?(SB|IB))?[0-9]+)|[abcd])$" 41 #define USB_CFG_LINK_RE "^cfg/((usb[0-9]+)/([0-9]+)([.]([0-9])+)*)$" 42 #define PCI_CFG_LINK_RE "^cfg/[:alnum:]$" 43 #define IB_CFG_LINK_RE "^cfg/(hca[0-9A-F]+)$" 44 #define SATA_CFG_LINK_RE "^cfg/((sata[0-9]+)/([0-9]+)([.]([0-9])+)*)$" 45 #define PCI_CFG_PATH_LINK_RE \ 46 "^cfg/(.*(pci[0-9]|pcie[0-9]|Slot[0-9]|\\<pci\\>|\\<pcie\\>).*)$" 47 48 #define CFG_DIRNAME "cfg" 49 50 #define PROP_FIRST_CHAS "first-in-chassis" 51 #define PROP_SLOT_NAMES "slot-names" 52 #define PROP_PHYS_SLOT "physical-slot#" 53 #define PROP_DEV_TYPE "device_type" 54 #define PROP_BUS_RANGE "bus-range" 55 #define PROP_SERID "serialid#" 56 #define PROP_REG "reg" 57 #define PROP_AP_NAMES "ap-names" 58 #define PROPVAL_PCIEX "pciex" 59 #define DEVTYPE_PCIE "pcie" 60 #define IOB_PRE "iob" 61 #define AP_PATH_SEP ":" 62 #define AP_PATH_IOB_SEP "." 63 #define IEEE_SUN_ID 0x080020 64 #define APNODE_DEFNAME 0x1 65 #define PCIDEV_NIL ((minor_t)-1) 66 67 /* converts size in bits to a mask covering those bit positions */ 68 #define SIZE2MASK(s) ((1 << (s)) - 1) 69 #define SIZE2MASK64(s) ((1LL << (s)) - 1LL) 70 71 /* 72 * macros for the ieee1275 "reg" property 73 * naming format and semantics: 74 * 75 * REG_<cell>_SIZE_<field> = bit size of <field> in <cell> 76 * REG_<cell>_OFF_<field> = starting bit position of <field> in <cell> 77 * 78 * REG_<cell>_<field>(r) = returns the value of <field> in <cell> using: 79 * (((r) >> REG_<cell>_OFF_<field>) & SIZE2MASK(REG_<cell>_SIZE_<field>)) 80 */ 81 #define REG_PHYSHI_SIZE_PCIDEV 5 82 #define REG_PHYSHI_OFF_PCIDEV 11 83 #define REG_PHYSHI_PCIDEV(r) \ 84 (((r) >> REG_PHYSHI_OFF_PCIDEV) & SIZE2MASK(REG_PHYSHI_SIZE_PCIDEV)) 85 86 /* rp = ptr to 5-tuple int array */ 87 #define REG_PHYSHI_INDEX 0 88 #define REG_PHYSHI(rp) ((rp)[REG_PHYSHI_INDEX]) 89 90 #define REG_PCIDEV(rp) (REG_PHYSHI_PCIDEV(REG_PHYSHI(rp))) 91 92 93 #define DEV "/dev" 94 #define DEV_LEN 4 95 #define DEVICES "/devices" 96 #define DEVICES_LEN 8 97 98 #ifdef __cplusplus 99 } 100 #endif 101 102 #endif /* _CFG_LINK_H */ 103