1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 27 /* All Rights Reserved */ 28 29 /* 30 * Portions of this source code were derived from Berkeley 4.3 BSD 31 * under license from the Regents of the University of California. 32 */ 33 34 #pragma ident "%Z%%M% %I% %E% SMI" 35 36 /* 37 * UNIX machine dependent virtual memory support. 38 */ 39 40 #include <sys/vm.h> 41 #include <sys/exec.h> 42 #include <sys/cmn_err.h> 43 #include <sys/cpu_module.h> 44 #include <sys/cpu.h> 45 #include <sys/elf_SPARC.h> 46 #include <sys/archsystm.h> 47 #include <vm/hat_sfmmu.h> 48 #include <sys/memnode.h> 49 #include <sys/mem_cage.h> 50 #include <vm/vm_dep.h> 51 #include <sys/error.h> 52 #include <sys/machsystm.h> 53 #include <vm/seg_kmem.h> 54 55 uint_t page_colors = 0; 56 uint_t page_colors_mask = 0; 57 uint_t page_coloring_shift = 0; 58 int consistent_coloring; 59 60 uint_t mmu_page_sizes = MMU_PAGE_SIZES; 61 uint_t max_mmu_page_sizes = MMU_PAGE_SIZES; 62 uint_t mmu_hashcnt = MAX_HASHCNT; 63 uint_t max_mmu_hashcnt = MAX_HASHCNT; 64 size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 65 66 /* 67 * A bitmask of the page sizes supported by hardware based upon szc. 68 * The base pagesize (p_szc == 0) must always be supported by the hardware. 69 */ 70 int mmu_exported_pagesize_mask; 71 uint_t mmu_exported_page_sizes; 72 73 uint_t szc_2_userszc[MMU_PAGE_SIZES]; 74 uint_t userszc_2_szc[MMU_PAGE_SIZES]; 75 76 extern uint_t vac_colors_mask; 77 extern int vac_shift; 78 79 hw_pagesize_t hw_page_array[] = { 80 {MMU_PAGESIZE, MMU_PAGESHIFT, MMU_PAGESIZE >> MMU_PAGESHIFT}, 81 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, MMU_PAGESIZE64K >> MMU_PAGESHIFT}, 82 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 83 MMU_PAGESIZE512K >> MMU_PAGESHIFT}, 84 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, MMU_PAGESIZE4M >> MMU_PAGESHIFT}, 85 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, MMU_PAGESIZE32M >> MMU_PAGESHIFT}, 86 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 87 MMU_PAGESIZE256M >> MMU_PAGESHIFT}, 88 {0, 0, 0} 89 }; 90 91 /* 92 * Enable usage of 64k/4M pages for text and 64k pages for initdata for 93 * all sun4v platforms. These variables can be overwritten by the platmod 94 * or the CPU module. User can also change the setting via /etc/system. 95 */ 96 97 int use_text_pgsz64k = 1; 98 int use_text_pgsz4m = 1; 99 int use_initdata_pgsz64k = 1; 100 101 /* 102 * disable_text_largepages and disable_initdata_largepages bitmaks reflect 103 * both unconfigured and undesirable page sizes. Current implementation 104 * supports 64K and 4M page sizes for text and only 64K for data. Rest of 105 * the page sizes are not currently supported, hence disabled below. In 106 * future, when support is added for any other page size, it should be 107 * reflected below. 108 * 109 * Note that these bitmask can be set in platform or CPU specific code to 110 * disable page sizes that should not be used. These variables normally 111 * shouldn't be changed via /etc/system. 112 * 113 * These bitmasks are also updated within hat_init to reflect unsupported 114 * page sizes on a sun4v processor per mmu_exported_pagesize_mask global 115 * variable. 116 */ 117 118 int disable_text_largepages = 119 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M) | (1 << TTE2G) | 120 (1 << TTE16G); 121 int disable_initdata_largepages = 122 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE32M) | (1 << TTE256M) | 123 (1 << TTE2G) | (1 << TTE16G); 124 125 /* 126 * Minimum segment size tunables before 64K or 4M large pages 127 * should be used to map it. 128 */ 129 size_t text_pgsz64k_minsize = MMU_PAGESIZE64K; 130 size_t text_pgsz4m_minsize = MMU_PAGESIZE4M; 131 size_t initdata_pgsz64k_minsize = MMU_PAGESIZE64K; 132 133 size_t max_shm_lpsize = MMU_PAGESIZE4M; 134 135 /* 136 * map_addr_proc() is the routine called when the system is to 137 * choose an address for the user. We will pick an address 138 * range which is just below the current stack limit. The 139 * algorithm used for cache consistency on machines with virtual 140 * address caches is such that offset 0 in the vnode is always 141 * on a shm_alignment'ed aligned address. Unfortunately, this 142 * means that vnodes which are demand paged will not be mapped 143 * cache consistently with the executable images. When the 144 * cache alignment for a given object is inconsistent, the 145 * lower level code must manage the translations so that this 146 * is not seen here (at the cost of efficiency, of course). 147 * 148 * addrp is a value/result parameter. 149 * On input it is a hint from the user to be used in a completely 150 * machine dependent fashion. For MAP_ALIGN, addrp contains the 151 * minimal alignment. 152 * 153 * On output it is NULL if no address can be found in the current 154 * processes address space or else an address that is currently 155 * not mapped for len bytes with a page of red zone on either side. 156 * If vacalign is true, then the selected address will obey the alignment 157 * constraints of a vac machine based on the given off value. 158 */ 159 /*ARGSUSED3*/ 160 void 161 map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign, 162 caddr_t userlimit, struct proc *p, uint_t flags) 163 { 164 struct as *as = p->p_as; 165 caddr_t addr; 166 caddr_t base; 167 size_t slen; 168 uintptr_t align_amount; 169 int allow_largepage_alignment = 1; 170 171 base = p->p_brkbase; 172 if (userlimit < as->a_userlimit) { 173 /* 174 * This happens when a program wants to map something in 175 * a range that's accessible to a program in a smaller 176 * address space. For example, a 64-bit program might 177 * be calling mmap32(2) to guarantee that the returned 178 * address is below 4Gbytes. 179 */ 180 ASSERT(userlimit > base); 181 slen = userlimit - base; 182 } else { 183 slen = p->p_usrstack - base - (((size_t)rctl_enforced_value( 184 rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET) 185 & PAGEMASK); 186 } 187 len = (len + PAGEOFFSET) & PAGEMASK; 188 189 /* 190 * Redzone for each side of the request. This is done to leave 191 * one page unmapped between segments. This is not required, but 192 * it's useful for the user because if their program strays across 193 * a segment boundary, it will catch a fault immediately making 194 * debugging a little easier. 195 */ 196 len += (2 * PAGESIZE); 197 198 /* 199 * If the request is larger than the size of a particular 200 * mmu level, then we use that level to map the request. 201 * But this requires that both the virtual and the physical 202 * addresses be aligned with respect to that level, so we 203 * do the virtual bit of nastiness here. 204 * 205 * For 32-bit processes, only those which have specified 206 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise 207 * we can potentially waste up to 256MB of the 4G process address 208 * space just for alignment. 209 * 210 * XXXQ Should iterate trough hw_page_array here to catch 211 * all supported pagesizes 212 */ 213 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 || 214 ((uintptr_t)*addrp) != 0)) { 215 allow_largepage_alignment = 0; 216 } 217 if ((mmu_page_sizes == max_mmu_page_sizes) && 218 allow_largepage_alignment && 219 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */ 220 align_amount = MMU_PAGESIZE256M; 221 } else if ((mmu_page_sizes == max_mmu_page_sizes) && 222 allow_largepage_alignment && 223 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */ 224 align_amount = MMU_PAGESIZE32M; 225 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */ 226 align_amount = MMU_PAGESIZE4M; 227 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */ 228 align_amount = MMU_PAGESIZE512K; 229 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */ 230 align_amount = MMU_PAGESIZE64K; 231 } else { 232 /* 233 * Align virtual addresses on a 64K boundary to ensure 234 * that ELF shared libraries are mapped with the appropriate 235 * alignment constraints by the run-time linker. 236 */ 237 align_amount = ELF_SPARC_MAXPGSZ; 238 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) && 239 ((uintptr_t)*addrp < align_amount)) 240 align_amount = (uintptr_t)*addrp; 241 } 242 243 /* 244 * 64-bit processes require 1024K alignment of ELF shared libraries. 245 */ 246 if (p->p_model == DATAMODEL_LP64) 247 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ); 248 #ifdef VAC 249 if (vac && vacalign && (align_amount < shm_alignment)) 250 align_amount = shm_alignment; 251 #endif 252 253 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) { 254 align_amount = (uintptr_t)*addrp; 255 } 256 len += align_amount; 257 258 /* 259 * Look for a large enough hole starting below the stack limit. 260 * After finding it, use the upper part. Addition of PAGESIZE is 261 * for the redzone as described above. 262 */ 263 as_purge(as); 264 if (as_gap(as, len, &base, &slen, AH_HI, NULL) == 0) { 265 caddr_t as_addr; 266 267 addr = base + slen - len + PAGESIZE; 268 as_addr = addr; 269 /* 270 * Round address DOWN to the alignment amount, 271 * add the offset, and if this address is less 272 * than the original address, add alignment amount. 273 */ 274 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l))); 275 addr += (long)(off & (align_amount - 1l)); 276 if (addr < as_addr) { 277 addr += align_amount; 278 } 279 280 ASSERT(addr <= (as_addr + align_amount)); 281 ASSERT(((uintptr_t)addr & (align_amount - 1l)) == 282 ((uintptr_t)(off & (align_amount - 1l)))); 283 *addrp = addr; 284 285 } else { 286 *addrp = NULL; /* no more virtual space */ 287 } 288 } 289 290 /* Auto large page tunables. */ 291 int auto_lpg_tlb_threshold = 32; 292 int auto_lpg_minszc = TTE64K; 293 int auto_lpg_maxszc = TTE256M; 294 size_t auto_lpg_heap_default = MMU_PAGESIZE64K; 295 size_t auto_lpg_stack_default = MMU_PAGESIZE64K; 296 size_t auto_lpg_va_default = MMU_PAGESIZE64K; 297 size_t auto_lpg_remap_threshold = 0; /* always remap */ 298 /* 299 * Number of pages in 1 GB. Don't enable automatic large pages if we have 300 * fewer than this many pages. 301 */ 302 pgcnt_t auto_lpg_min_physmem = 1 << (30 - MMU_PAGESHIFT); 303 304 size_t 305 map_pgsz(int maptype, struct proc *p, caddr_t addr, size_t len, int *remap) 306 { 307 uint_t n; 308 size_t pgsz = 0; 309 310 if (remap) 311 *remap = (len > auto_lpg_remap_threshold); 312 313 switch (maptype) { 314 case MAPPGSZ_ISM: 315 n = hat_preferred_pgsz(p->p_as->a_hat, addr, len, maptype); 316 pgsz = hw_page_array[n].hp_size; 317 break; 318 319 case MAPPGSZ_VA: 320 n = hat_preferred_pgsz(p->p_as->a_hat, addr, len, maptype); 321 pgsz = hw_page_array[n].hp_size; 322 if ((pgsz <= MMU_PAGESIZE) || 323 !IS_P2ALIGNED(addr, pgsz) || !IS_P2ALIGNED(len, pgsz)) 324 pgsz = map_pgszva(p, addr, len); 325 break; 326 327 case MAPPGSZ_STK: 328 pgsz = map_pgszstk(p, addr, len); 329 break; 330 331 case MAPPGSZ_HEAP: 332 pgsz = map_pgszheap(p, addr, len); 333 break; 334 } 335 return (pgsz); 336 } 337 338 /* 339 * Platform-dependent page scrub call. 340 * We call hypervisor to scrub the page. 341 */ 342 void 343 pagescrub(page_t *pp, uint_t off, uint_t len) 344 { 345 uint64_t pa, length; 346 347 pa = (uint64_t)(pp->p_pagenum << MMU_PAGESHIFT + off); 348 length = (uint64_t)len; 349 350 (void) mem_scrub(pa, length); 351 } 352 353 void 354 sync_data_memory(caddr_t va, size_t len) 355 { 356 /* Call memory sync function */ 357 mem_sync(va, len); 358 } 359 360 size_t 361 mmu_get_kernel_lpsize(size_t lpsize) 362 { 363 extern int mmu_exported_pagesize_mask; 364 uint_t tte; 365 366 if (lpsize == 0) { 367 /* no setting for segkmem_lpsize in /etc/system: use default */ 368 if (mmu_exported_pagesize_mask & (1 << TTE256M)) { 369 lpsize = MMU_PAGESIZE256M; 370 } else if (mmu_exported_pagesize_mask & (1 << TTE4M)) { 371 lpsize = MMU_PAGESIZE4M; 372 } else if (mmu_exported_pagesize_mask & (1 << TTE64K)) { 373 lpsize = MMU_PAGESIZE64K; 374 } else { 375 lpsize = MMU_PAGESIZE; 376 } 377 378 return (lpsize); 379 } 380 381 for (tte = TTE8K; tte <= TTE256M; tte++) { 382 383 if ((mmu_exported_pagesize_mask & (1 << tte)) == 0) 384 continue; 385 386 if (lpsize == TTEBYTES(tte)) 387 return (lpsize); 388 } 389 390 lpsize = TTEBYTES(TTE8K); 391 return (lpsize); 392 } 393 394 void 395 mmu_init_kcontext() 396 { 397 } 398 399 /*ARGSUSED*/ 400 void 401 mmu_init_kernel_pgsz(struct hat *hat) 402 { 403 } 404 405 #define QUANTUM_SIZE 64 406 407 static vmem_t *contig_mem_slab_arena; 408 static vmem_t *contig_mem_arena; 409 410 uint_t contig_mem_slab_size = MMU_PAGESIZE4M; 411 412 static void * 413 contig_mem_span_alloc(vmem_t *vmp, size_t size, int vmflag) 414 { 415 page_t *ppl; 416 page_t *rootpp; 417 caddr_t addr = NULL; 418 pgcnt_t npages = btopr(size); 419 page_t **ppa; 420 int pgflags; 421 int i = 0; 422 423 424 /* 425 * The import request should be at least 426 * contig_mem_slab_size because that is the 427 * slab arena's quantum. The size can be 428 * further restricted since contiguous 429 * allocations larger than contig_mem_slab_size 430 * are not supported here. 431 */ 432 ASSERT(size == contig_mem_slab_size); 433 434 if ((addr = vmem_xalloc(vmp, size, size, 0, 0, 435 NULL, NULL, vmflag)) == NULL) { 436 return (NULL); 437 } 438 439 /* The address should be slab-size aligned. */ 440 ASSERT(((uintptr_t)addr & (contig_mem_slab_size - 1)) == 0); 441 442 if (page_resv(npages, vmflag & VM_KMFLAGS) == 0) { 443 vmem_xfree(vmp, addr, size); 444 return (NULL); 445 } 446 447 pgflags = PG_EXCL; 448 if ((vmflag & VM_NOSLEEP) == 0) 449 pgflags |= PG_WAIT; 450 if (vmflag & VM_PANIC) 451 pgflags |= PG_PANIC; 452 if (vmflag & VM_PUSHPAGE) 453 pgflags |= PG_PUSHPAGE; 454 455 ppl = page_create_va_large(&kvp, (u_offset_t)(uintptr_t)addr, size, 456 pgflags, &kvseg, addr, NULL); 457 458 if (ppl == NULL) { 459 vmem_xfree(vmp, addr, size); 460 page_unresv(npages); 461 return (NULL); 462 } 463 464 rootpp = ppl; 465 ppa = kmem_zalloc(npages * sizeof (page_t *), KM_SLEEP); 466 while (ppl != NULL) { 467 page_t *pp = ppl; 468 ppa[i++] = pp; 469 page_sub(&ppl, pp); 470 ASSERT(page_iolock_assert(pp)); 471 page_io_unlock(pp); 472 } 473 474 /* 475 * Load the locked entry. It's OK to preload the entry into 476 * the TSB since we now support large mappings in the kernel TSB. 477 */ 478 hat_memload_array(kas.a_hat, (caddr_t)rootpp->p_offset, size, 479 ppa, (PROT_ALL & ~PROT_USER) | HAT_NOSYNC, HAT_LOAD_LOCK); 480 481 for (--i; i >= 0; --i) { 482 (void) page_pp_lock(ppa[i], 0, 1); 483 page_unlock(ppa[i]); 484 } 485 486 kmem_free(ppa, npages * sizeof (page_t *)); 487 return (addr); 488 } 489 490 void 491 contig_mem_span_free(vmem_t *vmp, void *inaddr, size_t size) 492 { 493 page_t *pp; 494 caddr_t addr = inaddr; 495 caddr_t eaddr; 496 pgcnt_t npages = btopr(size); 497 pgcnt_t pgs_left = npages; 498 page_t *rootpp = NULL; 499 500 ASSERT(((uintptr_t)addr & (contig_mem_slab_size - 1)) == 0); 501 502 hat_unload(kas.a_hat, addr, size, HAT_UNLOAD_UNLOCK); 503 504 for (eaddr = addr + size; addr < eaddr; addr += PAGESIZE) { 505 pp = page_lookup(&kvp, (u_offset_t)(uintptr_t)addr, SE_EXCL); 506 if (pp == NULL) 507 panic("contig_mem_span_free: page not found"); 508 509 ASSERT(PAGE_EXCL(pp)); 510 page_pp_unlock(pp, 0, 1); 511 512 if (rootpp == NULL) 513 rootpp = pp; 514 if (--pgs_left == 0) { 515 /* 516 * similar logic to segspt_free_pages, but we know we 517 * have one large page. 518 */ 519 page_destroy_pages(rootpp); 520 } 521 } 522 page_unresv(npages); 523 524 if (vmp != NULL) 525 vmem_xfree(vmp, inaddr, size); 526 } 527 528 static void * 529 contig_vmem_xalloc_aligned_wrapper(vmem_t *vmp, size_t size, int vmflag) 530 { 531 return (vmem_xalloc(vmp, size, size, 0, 0, NULL, NULL, vmflag)); 532 } 533 534 /* 535 * conting_mem_alloc_align allocates real contiguous memory with the specified 536 * alignment upto contig_mem_slab_size. The alignment must be a power of 2. 537 */ 538 void * 539 contig_mem_alloc_align(size_t size, size_t align) 540 { 541 ASSERT(align <= contig_mem_slab_size); 542 543 if ((align & (align - 1)) != 0) 544 return (NULL); 545 546 return (vmem_xalloc(contig_mem_arena, size, align, 0, 0, 547 NULL, NULL, VM_NOSLEEP)); 548 } 549 550 /* 551 * Allocates size aligned contiguous memory upto contig_mem_slab_size. 552 * Size must be a power of 2. 553 */ 554 void * 555 contig_mem_alloc(size_t size) 556 { 557 ASSERT((size & (size - 1)) == 0); 558 return (contig_mem_alloc_align(size, size)); 559 } 560 561 void 562 contig_mem_free(void *vaddr, size_t size) 563 { 564 vmem_xfree(contig_mem_arena, vaddr, size); 565 } 566 567 /* 568 * We create a set of stacked vmem arenas to enable us to 569 * allocate large >PAGESIZE chucks of contiguous Real Address space 570 * This is what the Dynamics TSB support does for TSBs. 571 * The contig_mem_arena import functions are exactly the same as the 572 * TSB kmem_default arena import functions. 573 */ 574 void 575 contig_mem_init(void) 576 { 577 578 contig_mem_slab_arena = vmem_create("contig_mem_slab_arena", NULL, 0, 579 contig_mem_slab_size, contig_vmem_xalloc_aligned_wrapper, 580 vmem_xfree, heap_arena, 0, VM_SLEEP); 581 582 contig_mem_arena = vmem_create("contig_mem_arena", NULL, 0, 583 QUANTUM_SIZE, contig_mem_span_alloc, contig_mem_span_free, 584 contig_mem_slab_arena, 0, VM_SLEEP | VM_BESTFIT); 585 586 } 587