xref: /titanic_41/usr/src/uts/sun4v/sys/mmu.h (revision 2e02daeede04af58a9d4f18f8dfed1fda3ececa1)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_MMU_H
28 #define	_SYS_MMU_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 #ifndef _ASM
37 #include <sys/types.h>
38 #endif
39 #include <sys/hypervisor_api.h>
40 
41 /*
42  * Definitions for the SOFT MMU
43  */
44 
45 #define	FAST_IMMU_MISS_TT	0x64
46 #define	FAST_DMMU_MISS_TT	0x68
47 #define	FAST_PROT_TT		0x6c
48 
49 /*
50  * Constants defining alternate spaces
51  * and register layouts within them,
52  * and a few other interesting assembly constants.
53  */
54 
55 /*
56  * vaddr offsets of various registers
57  */
58 #define	MMU_PCONTEXT		0x08 /* primary context number */
59 #define	MMU_SCONTEXT		0x10 /* secondary context number */
60 
61 #define	MMU_PCONTEXT0		MMU_PCONTEXT	/* primary context# 0 */
62 #define	MMU_PCONTEXT1		0x108		/* primary context# 1 */
63 #define	MMU_SCONTEXT0		MMU_SCONTEXT	/* secondary context# 0 */
64 #define	MMU_SCONTEXT1		0x110		/* secondary context# 1 */
65 
66 /*
67  * Pseudo Synchronous Fault Status Register Layout
68  *
69  * IMMU and DMMU maintain their own pseudo SFSR Register
70  *
71  * +------------------------------------------------+
72  * |       Reserved       |   Context   |     FT    |
73  * +----------------------|-------------------------+
74  *  63                  32 31         16 15         0
75  *
76  */
77 #define	SFSR_FT		0x0000FFFF	/* fault type mask */
78 #define	SFSR_CTX	0xFFFF0000	/* fault context mask */
79 
80 /*
81  * Definition of FT (Fault Type) bit field of sfsr.
82  */
83 #define	FT_NONE		0x00
84 #define	FT_PRIV		MMFSA_F_PRIV	/* privilege violation */
85 #define	FT_SPEC_LD	MMFSA_F_SOPG	/* speculative ld to e page */
86 #define	FT_ATOMIC_NC	MMFSA_F_NCATM	/* atomic to nc page */
87 #define	FT_ILL_ALT	MMFSA_F_INVASI	/* illegal lda/sta */
88 #define	FT_NFO		MMFSA_F_NFO	/* normal access to nfo page */
89 #define	FT_RANGE	MMFSA_F_INVVA	/* dmmu or immu address out of range */
90 #define	FT_NEW_FMISS	MMFSA_F_FMISS	/* fast miss */
91 #define	FT_NEW_FPROT	MMFSA_F_FPROT	/* fast protection */
92 #define	FT_NEW_MISS	MMFSA_F_MISS	/* mmu miss */
93 #define	FT_NEW_INVRA	MMFSA_F_INVRA	/* invalid RA */
94 #define	FT_NEW_PROT	MMFSA_F_PROT	/* protection violation */
95 #define	FT_NEW_PRVACT	MMFSA_F_PRVACT	/* privileged action */
96 #define	FT_NEW_WPT	MMFSA_F_WPT	/* watchpoint hit */
97 #define	FT_NEW_UNALIGN	MMFSA_F_UNALIGN	/* unaligned access */
98 #define	FT_NEW_INVPGSZ	MMFSA_F_INVPGSZ	/* invalid page size */
99 
100 #define	SFSR_FT_SHIFT	0	/* amt. to shift right to get flt type */
101 #define	SFSR_CTX_SHIFT	16	/* to shift right to get context */
102 #define	X_FAULT_TYPE(x)	(((x) & SFSR_FT) >> SFSR_FT_SHIFT)
103 #define	X_FAULT_CTX(x)	(((x) & SFSR_CTX) >> SFSR_CTX_SHIFT)
104 
105 /*
106  * MMU TAG TARGET register Layout
107  *
108  * +---------------+------+-------------------------+
109  * |    context    |  --  | virtual address [63:22] |
110  * +---------------+------+-------------------------+
111  *  63           48 47  42 41                      0
112  *
113  * Some sun4v processors only use a 13-bit context ID, so bits 61-63 will be
114  * zero in that case.  This layout allows us to use the same code for any sun4v
115  * processors, whether they support 13 bit or 16 bit context IDs (or something
116  * in between).
117  */
118 #define	TTARGET_CTX_SHIFT	48
119 #define	TTARGET_VA_SHIFT	22
120 
121 /*
122  * Pseudo MMU TAG ACCESS register Layout
123  *
124  * +-------------------------+------------------+
125  * | virtual address [63:13] |     0     | type |
126  * +-------------------------+------------------+
127  *  63			  13	12      2 1    0
128  *
129  * 16-bit context IDs don't fit into the 13 bit field as they did on sun4u,
130  * so we use a context type, 0 = kernel context, 1 = invalid context,
131  * 2 = user context.
132  */
133 #define	TAGACC_CTX_MASK		0x1FFF
134 #define	TAGACC_SHIFT		13
135 #define	TAGACC_VADDR_MASK	(~TAGACC_CTX_MASK)
136 #define	TAGACC_CTX_LSHIFT	(64 - TAGACC_SHIFT)
137 
138 /*
139  * The kernel always runs in KCONTEXT, and no user mappings
140  * are ever valid in it (so any user access pagefaults).
141  */
142 #define	KCONTEXT	0
143 
144 /*
145  * FLUSH_ADDR is used in the flush instruction to guarantee stores to mmu
146  * registers complete.  It is selected so it won't miss in the tlb.
147  */
148 #define	FLUSH_ADDR	(KERNELBASE + 2 * MMU_PAGESIZE4M)
149 
150 #define	MAX_NCTXS_BITS			16	/* sun4v max. contexts bits */
151 #define	MIN_NCTXS_BITS			2
152 #define	MAX_NCTXS	(1ull << MAX_NCTXS_BITS)
153 
154 /*
155  * MIN_NSHCONTEXTS and MIN_NTSBS are the minimum number of shared contexts
156  * and tsbs necessary for shared context support.
157  */
158 #define	MIN_NSHCONTEXTS			1
159 #define	MIN_NTSBS			4
160 
161 #ifdef	__cplusplus
162 }
163 #endif
164 
165 #endif /* _SYS_MMU_H */
166