1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MACHSYSTM_H 27 #define _SYS_MACHSYSTM_H 28 29 /* 30 * Numerous platform-dependent interfaces that don't seem to belong 31 * in any other header file. 32 * 33 * This file should not be included by code that purports to be 34 * platform-independent. 35 */ 36 37 #ifndef _ASM 38 #include <sys/types.h> 39 #include <sys/scb.h> 40 #include <sys/varargs.h> 41 #include <sys/machparam.h> 42 #include <sys/thread.h> 43 #include <vm/seg_enum.h> 44 #include <sys/processor.h> 45 #include <sys/sunddi.h> 46 #include <sys/memlist.h> 47 #endif /* _ASM */ 48 49 #ifdef __cplusplus 50 extern "C" { 51 #endif 52 53 #ifdef _KERNEL 54 55 #ifndef _ASM 56 /* 57 * The following enum types determine how interrupts are distributed 58 * on a sun4u system. 59 */ 60 enum intr_policies { 61 /* 62 * Target interrupt at the CPU running the add_intrspec 63 * thread. Also used to target all interrupts at the panicing 64 * CPU. 65 */ 66 INTR_CURRENT_CPU = 0, 67 68 /* 69 * Target all interrupts at the boot cpu 70 */ 71 INTR_BOOT_CPU, 72 73 /* 74 * Flat distribution of all interrupts 75 */ 76 INTR_FLAT_DIST, 77 78 /* 79 * Weighted distribution of all interrupts 80 */ 81 INTR_WEIGHTED_DIST 82 }; 83 84 85 /* 86 * Structure that defines the interrupt distribution list. It contains 87 * enough info about the interrupt so that it can callback the parent 88 * nexus driver and retarget the interrupt to a different CPU. 89 */ 90 struct intr_dist { 91 struct intr_dist *next; /* link to next in list */ 92 void (*func)(void *); /* Callback function */ 93 void *arg; /* Nexus parent callback arg 1 */ 94 }; 95 96 /* 97 * Miscellaneous cpu_state changes 98 */ 99 extern void power_down(const char *); 100 extern void do_shutdown(void); 101 102 /* 103 * Number of seconds until power is shut off 104 */ 105 extern int thermal_powerdown_delay; 106 107 108 /* 109 * prom-related 110 */ 111 extern int obpdebug; 112 extern int forthdebug_supported; 113 extern uint_t tba_taken_over; 114 extern void forthdebug_init(void); 115 extern void init_vx_handler(void); 116 extern void kern_preprom(void); 117 extern void kern_postprom(void); 118 119 /* 120 * externally (debugger or prom) initiated panic 121 */ 122 extern struct regs sync_reg_buf; 123 extern uint64_t sync_tt; 124 extern void sync_handler(void); 125 126 /* 127 * Trap-related 128 */ 129 struct regs; 130 extern void trap(struct regs *rp, caddr_t addr, uint32_t type, 131 uint32_t mmu_fsr); 132 extern void *get_tba(void); 133 extern void *set_tba(void *); 134 extern caddr_t set_trap_table(void); 135 extern struct scb trap_table; 136 137 struct panic_trap_info { 138 struct regs *trap_regs; 139 uint_t trap_type; 140 caddr_t trap_addr; 141 uint_t trap_mmu_fsr; 142 }; 143 144 /* 145 * misc. primitives 146 */ 147 #define PROM_CFGHDL_TO_CPUID(x) (x & ~(0xful << 28)) 148 149 extern void debug_flush_windows(void); 150 extern void flush_windows(void); 151 extern int getprocessorid(void); 152 extern void reestablish_curthread(void); 153 154 extern void stphys(uint64_t physaddr, int value); 155 extern int ldphys(uint64_t physaddr); 156 extern void stdphys(uint64_t physaddr, uint64_t value); 157 extern uint64_t lddphys(uint64_t physaddr); 158 159 extern void stphysio(u_longlong_t physaddr, uint_t value); 160 extern uint_t ldphysio(u_longlong_t physaddr); 161 extern void sthphysio(u_longlong_t physaddr, ushort_t value); 162 extern ushort_t ldhphysio(u_longlong_t physaddr); 163 extern void stbphysio(u_longlong_t physaddr, uchar_t value); 164 extern uchar_t ldbphysio(u_longlong_t physaddr); 165 extern void stdphysio(u_longlong_t physaddr, u_longlong_t value); 166 extern u_longlong_t lddphysio(u_longlong_t physaddr); 167 168 extern int pf_is_dmacapable(pfn_t); 169 170 extern int dip_to_cpu_id(dev_info_t *dip, processorid_t *cpu_id); 171 172 extern void set_cmp_error_steering(void); 173 174 /* 175 * SPARCv9 %ver register and field definitions 176 */ 177 178 #define ULTRA_VER_MANUF(x) ((x) >> 48) 179 #define ULTRA_VER_IMPL(x) (((x) >> 32) & 0xFFFF) 180 #define ULTRA_VER_MASK(x) (((x) >> 24) & 0xFF) 181 182 extern uint64_t ultra_getver(void); 183 184 /* 185 * bootup-time 186 */ 187 extern void segnf_init(void); 188 extern void kern_setup1(void); 189 extern void startup(void); 190 extern void post_startup(void); 191 extern void install_va_to_tte(void); 192 extern void setwstate(uint_t); 193 extern void create_va_to_tte(void); 194 extern int memscrub_init(void); 195 196 extern void kcpc_hw_init(void); 197 extern void kcpc_hw_startup_cpu(ushort_t); 198 extern int kcpc_hw_load_pcbe(void); 199 200 /* 201 * Interrupts 202 */ 203 struct cpu; 204 extern struct cpu cpu0; 205 extern struct scb *set_tbr(struct scb *); 206 207 extern uint_t disable_vec_intr(void); 208 extern void enable_vec_intr(uint_t); 209 extern void setintrenable(int); 210 211 extern void intr_dist_add(void (*f)(void *), void *); 212 extern void intr_dist_rem(void (*f)(void *), void *); 213 extern void intr_dist_add_weighted(void (*f)(void *, int32_t, int32_t), void *); 214 extern void intr_dist_rem_weighted(void (*f)(void *, int32_t, int32_t), void *); 215 216 extern uint32_t intr_dist_cpuid(void); 217 extern uint32_t intr_dist_mycpuid(void); 218 219 void intr_dist_cpuid_add_device_weight(uint32_t cpuid, dev_info_t *dip, 220 int32_t weight); 221 void intr_dist_cpuid_rem_device_weight(uint32_t cpuid, dev_info_t *dip); 222 223 extern void intr_redist_all_cpus(void); 224 extern void intr_redist_all_cpus_shutdown(void); 225 226 extern void send_dirint(int, int); 227 extern void setsoftint(uint64_t); 228 extern void setsoftint_tl1(uint64_t, uint64_t); 229 extern void siron(void); 230 extern void sir_on(int); 231 extern void intr_enqueue_req(uint_t pil, uint64_t inum); 232 extern void intr_dequeue_req(uint_t pil, uint64_t inum); 233 extern void wr_clr_softint(uint_t); 234 235 /* 236 * Time- and %tick-related 237 */ 238 extern hrtime_t rdtick(void); 239 extern void tick_write_delta(uint64_t); 240 extern void tickcmpr_set(uint64_t); 241 extern void tickcmpr_reset(void); 242 extern void tickcmpr_disable(void); 243 extern int tickcmpr_disabled(void); 244 extern uint64_t cbe_level14_inum; 245 246 /* 247 * contiguous memory 248 */ 249 extern void *contig_mem_alloc(size_t); 250 extern void *contig_mem_alloc_align(size_t, size_t); 251 extern void contig_mem_free(void *, size_t); 252 253 /* 254 * Caches 255 */ 256 extern int vac; 257 extern int cache; 258 extern int use_mp; 259 extern uint_t vac_mask; 260 extern uint64_t ecache_flushaddr; 261 extern int ecache_alignsize; /* Maximum ecache linesize for struct align */ 262 extern int ecache_setsize; /* Maximum ecache setsize possible */ 263 extern int cpu_setsize; /* Maximum ecache setsize of configured cpus */ 264 265 /* 266 * VM 267 */ 268 extern int do_pg_coloring; 269 extern int use_page_coloring; 270 extern uint_t vac_colors_mask; 271 272 extern caddr_t get_mmfsa_scratchpad(void); 273 extern void set_mmfsa_scratchpad(caddr_t); 274 extern int ndata_alloc_mmfsa(struct memlist *); 275 extern int ndata_alloc_page_freelists(struct memlist *, int); 276 extern int ndata_alloc_dmv(struct memlist *); 277 extern int ndata_alloc_tsbs(struct memlist *, pgcnt_t); 278 extern int ndata_alloc_hat(struct memlist *, pgcnt_t); 279 extern int ndata_alloc_kpm(struct memlist *, pgcnt_t); 280 extern int ndata_alloc_page_mutexs(struct memlist *ndata); 281 282 extern size_t calc_pp_sz(pgcnt_t); 283 extern size_t calc_kpmpp_sz(pgcnt_t); 284 extern size_t calc_hmehash_sz(pgcnt_t); 285 extern size_t calc_pagehash_sz(pgcnt_t); 286 extern size_t calc_free_pagelist_sz(void); 287 288 extern caddr_t alloc_hmehash(caddr_t); 289 extern caddr_t alloc_page_freelists(caddr_t); 290 291 extern size_t page_ctrs_sz(void); 292 extern caddr_t page_ctrs_alloc(caddr_t); 293 extern void page_freelist_coalesce_all(int); 294 extern void ppmapinit(void); 295 extern void hwblkpagecopy(const void *, void *); 296 extern void hw_pa_bcopy32(uint64_t, uint64_t); 297 298 extern int pp_slots; 299 extern int pp_consistent_coloring; 300 301 /* 302 * ppcopy/hwblkpagecopy interaction. See ppage.c. 303 */ 304 #define PPAGE_STORE_VCOLORING 0x1 /* use vcolors to maintain consistency */ 305 #define PPAGE_LOAD_VCOLORING 0x2 /* use vcolors to maintain consistency */ 306 #define PPAGE_STORES_POLLUTE 0x4 /* stores pollute VAC */ 307 #define PPAGE_LOADS_POLLUTE 0x8 /* loads pollute VAC */ 308 309 /* 310 * VIS-accelerated copy/zero 311 */ 312 extern int use_hw_bcopy; 313 extern uint_t hw_copy_limit_1; 314 extern uint_t hw_copy_limit_2; 315 extern uint_t hw_copy_limit_4; 316 extern uint_t hw_copy_limit_8; 317 extern int use_hw_bzero; 318 319 #ifdef CHEETAH 320 #define VIS_COPY_THRESHOLD 256 321 #else 322 #define VIS_COPY_THRESHOLD 900 323 #endif 324 325 /* 326 * MP 327 */ 328 extern void idle_other_cpus(void); 329 extern void resume_other_cpus(void); 330 extern void stop_other_cpus(void); 331 extern void idle_stop_xcall(void); 332 extern void set_idle_cpu(int); 333 extern void unset_idle_cpu(int); 334 extern void mp_cpu_quiesce(struct cpu *); 335 extern int stopcpu_bycpuid(int); 336 337 /* 338 * Panic at TL > 0 339 */ 340 extern uint64_t cpu_pa[]; 341 extern void ptl1_init_cpu(struct cpu *); 342 343 /* 344 * Constants which define the "hole" in the 64-bit sfmmu address space. 345 * These are set to specific values by the CPU module code. 346 */ 347 extern caddr_t hole_start, hole_end; 348 349 /* kpm mapping window */ 350 extern size_t kpm_size; 351 extern uchar_t kpm_size_shift; 352 extern caddr_t kpm_vbase; 353 354 #define INVALID_VADDR(a) (((a) >= hole_start && (a) < hole_end)) 355 #define VA_ADDRESS_SPACE_BITS 64 356 #define RA_ADDRESS_SPACE_BITS 56 357 #define MAX_REAL_ADDRESS (1ull << RA_ADDRESS_SPACE_BITS) 358 #define DEFAULT_VA_ADDRESS_SPACE_BITS 48 /* def. Niagara (broken MD) */ 359 #define PAGESIZE_MASK_BITS 16 360 #define MAX_PAGESIZE_MASK ((1<<PAGESIZE_MASK_BITS) - 1) 361 362 extern void adjust_hw_copy_limits(int); 363 364 struct kdi; 365 366 void cpu_kdi_init(struct kdi *); 367 368 /* 369 * flush instruction and data caches 370 */ 371 void kdi_flush_caches(void); 372 373 struct async_flt; 374 375 /* 376 * take pending fp traps if fpq present 377 * this function is also defined in fpusystm.h 378 */ 379 void syncfpu(void); 380 381 void cpu_faulted_enter(struct cpu *); 382 void cpu_faulted_exit(struct cpu *); 383 384 int cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 385 char *buf, int buflen, int *lenp); 386 int cpu_get_mem_info(uint64_t synd, uint64_t afar, 387 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 388 int *segsp, int *banksp, int *mcidp); 389 size_t cpu_get_name_bufsize(); 390 391 /* 392 * ecache scrub operations 393 */ 394 void cpu_init_cache_scrub(void); 395 396 /* 397 * clock/tick register operations 398 */ 399 void cpu_init_tick_freq(void); 400 401 /* 402 * stick synchronization 403 */ 404 void sticksync_slave(void); 405 void sticksync_master(void); 406 407 #endif /* _ASM */ 408 409 /* 410 * Actions for set_error_enable_tl1 411 */ 412 #define EER_SET_ABSOLUTE 0x0 413 #define EER_SET_SETBITS 0x1 414 #define EER_SET_CLRBITS 0x2 415 416 /* 417 * HVDUMP_SIZE_MAX set as 64k due to limitiation by intrq_alloc() 418 */ 419 420 #define HVDUMP_SIZE_MAX 0x10000 421 #define HVDUMP_SIZE_DEFAULT 0x8000 422 423 /* 424 * HV TOD service retry in usecs 425 */ 426 427 #define HV_TOD_RETRY_THRESH 100 428 #define HV_TOD_WAIT_USEC 5 429 430 /* 431 * Interrupt Queues and Error Queues 432 */ 433 434 #define INTR_CPU_Q 0x3c 435 #define INTR_DEV_Q 0x3d 436 #define CPU_RQ 0x3e 437 #define CPU_NRQ 0x3f 438 #define DEFAULT_CPU_Q_ENTRIES 0x100 439 #define DEFAULT_DEV_Q_ENTRIES 0x100 440 #define INTR_REPORT_SIZE 64 441 442 #ifndef _ASM 443 extern uint64_t cpu_q_entries; 444 extern uint64_t dev_q_entries; 445 extern uint64_t cpu_rq_entries; 446 extern uint64_t cpu_nrq_entries; 447 extern uint64_t ncpu_guest_max; 448 #endif /* _ASM */ 449 450 #endif /* _KERNEL */ 451 452 #ifdef __cplusplus 453 } 454 #endif 455 456 #endif /* _SYS_MACHSYSTM_H */ 457