xref: /titanic_41/usr/src/uts/sun4v/sys/machcpuvar.h (revision 505d05c73a6e56769f263d4803b22eddd168ee24)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_MACHCPUVAR_H
28 #define	_SYS_MACHCPUVAR_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #include <sys/intr.h>
33 #include <sys/clock.h>
34 #include <sys/machparam.h>
35 #include <sys/machpcb.h>
36 #include <sys/privregs.h>
37 #include <sys/machlock.h>
38 
39 #ifdef	__cplusplus
40 extern "C" {
41 #endif
42 
43 #ifndef	_ASM
44 
45 #include <sys/obpdefs.h>
46 #include <sys/async.h>
47 #include <sys/fm/protocol.h>
48 
49 /*
50  * CPU state ptl1_panic save.
51  */
52 typedef struct ptl1_trapregs {
53 	uint32_t	ptl1_tl;
54 	uint32_t	ptl1_tt;
55 	uint64_t	ptl1_tstate;
56 	uint64_t	ptl1_tpc;
57 	uint64_t	ptl1_tnpc;
58 } ptl1_trapregs_t;
59 
60 typedef struct ptl1_gregs {
61 	uint64_t	ptl1_gl;
62 	uint64_t	ptl1_g1;
63 	uint64_t	ptl1_g2;
64 	uint64_t	ptl1_g3;
65 	uint64_t	ptl1_g4;
66 	uint64_t	ptl1_g5;
67 	uint64_t	ptl1_g6;
68 	uint64_t	ptl1_g7;
69 } ptl1_gregs_t;
70 
71 typedef struct ptl1_regs {
72 	ptl1_trapregs_t	ptl1_trap_regs[PTL1_MAXTL];
73 	ptl1_gregs_t	ptl1_gregs[PTL1_MAXGL + 1];
74 	uint64_t	ptl1_tick;
75 	uint64_t	ptl1_dmmu_type;
76 	uint64_t	ptl1_dmmu_addr;
77 	uint64_t	ptl1_dmmu_ctx;
78 	uint64_t	ptl1_immu_type;
79 	uint64_t	ptl1_immu_addr;
80 	uint64_t	ptl1_immu_ctx;
81 	struct rwindow	ptl1_rwindow[MAXWIN];
82 	uint32_t	ptl1_softint;
83 	uint16_t	ptl1_pstate;
84 	uint8_t		ptl1_pil;
85 	uint8_t		ptl1_cwp;
86 	uint8_t		ptl1_wstate;
87 	uint8_t		ptl1_otherwin;
88 	uint8_t		ptl1_cleanwin;
89 	uint8_t		ptl1_cansave;
90 	uint8_t		ptl1_canrestore;
91 } ptl1_regs_t;
92 
93 typedef struct ptl1_state {
94 	ptl1_regs_t	ptl1_regs;
95 	uint32_t	ptl1_entry_count;
96 	uintptr_t	ptl1_stktop;
97 	ulong_t		ptl1_stk[1];
98 } ptl1_state_t;
99 
100 /*
101  * Machine specific fields of the cpu struct
102  * defined in common/sys/cpuvar.h.
103  */
104 struct	machcpu {
105 	struct machpcb	*mpcb;
106 	uint64_t	mpcb_pa;
107 	int		mutex_ready;
108 	int		in_prom;
109 	int		tl1_hdlr;
110 	char		cpu_tstat_flags;	/* tstat flags */
111 	uint16_t	divisor;	/* Estar %tick clock ratio */
112 	uint8_t		intrcnt;	/* number of back-to-back interrupts */
113 	u_longlong_t	tmp1;		/* per-cpu tmps */
114 	u_longlong_t	tmp2;		/*  used in trap processing */
115 
116 	struct intr_req intr_pool[INTR_PENDING_MAX];	/* intr pool */
117 	struct intr_req *intr_head[PIL_LEVELS];		/* intr que heads */
118 	struct intr_req *intr_tail[PIL_LEVELS];		/* intr que tails */
119 	int		intr_pool_added;		/* add'l intr pool */
120 	boolean_t	poke_cpu_outstanding;
121 	/*
122 	 * The cpu module allocates a private data structure for the
123 	 * E$ data, which is needed for the specific cpu type.
124 	 */
125 	void		*cpu_private;		/* ptr to cpu private data */
126 
127 	ptl1_state_t	ptl1_state;
128 
129 	uint64_t	pil_high_start[HIGH_LEVELS];	/* high-level intrs */
130 
131 	/*
132 	 * intrstat[][] is used to keep track of ticks used at a given pil
133 	 * level. intrstat[pil][0] is cumulative and exported via kstats.
134 	 * intrstat[pil][1] is used in intr_get_time() and is private.
135 	 * 2-dimensional array improves cache locality.
136 	 */
137 
138 	uint64_t	intrstat[PIL_MAX+1][2];
139 
140 	int		kwbuf_full;
141 	caddr_t		kwbuf_sp;
142 	struct rwindow	kwbuf;
143 
144 	caddr_t		cpu_q_va;	/* cpu intrq base VA */
145 	caddr_t		dev_q_va;	/* dev intrq base VA */
146 	uint64_t	cpu_q_base_pa;	/* cpu intrq base PA */
147 	uint64_t	cpu_q_size;
148 	uint64_t	dev_q_base_pa;	/* dev intrq base PA */
149 	uint64_t	dev_q_size;
150 	caddr_t		cpu_rq_va;	/* resumable Q base VA */
151 	caddr_t		cpu_nrq_va;	/* nonresumable Q base VA */
152 	uint64_t	cpu_rq_base_pa;	/* resumable Q base PA */
153 	uint64_t	cpu_rq_size;	/* resumable Q size */
154 	uint64_t	cpu_nrq_base_pa;	/* nonresumable Q base PA */
155 	uint64_t	cpu_nrq_size;		/* nonresumable Q size */
156 	caddr_t		mondo_data;		/* send mondo data */
157 	uint64_t	mondo_data_ra;		/* mono data pa */
158 	uint16_t	*cpu_list;		/* uint16_t [NCPU] */
159 	uint64_t	cpu_list_ra;		/* cpu list ra */
160 	id_t		cpu_ipipe;		/* cpu exec unit id */
161 };
162 
163 typedef	struct machcpu	machcpu_t;
164 
165 /*
166  * Macro to access the "cpu private" data structure.
167  */
168 #define	CPU_PRIVATE(cp)		((cp)->cpu_m.cpu_private)
169 
170 /*
171  * The OpenBoot Standalone Interface supplies the kernel with
172  * implementation dependent parameters through the devinfo/property mechanism
173  */
174 #define	MAXSYSNAME	20
175 
176 /*
177  * Used to indicate busy/idle state of a cpu.
178  * msram field will be set with ECACHE_CPU_MIRROR if we are on
179  * mirrored sram module.
180  */
181 #define	ECACHE_CPU_IDLE		0x0		/* CPU is idle */
182 #define	ECACHE_CPU_BUSY		0x1		/* CPU is busy */
183 #define	ECACHE_CPU_MIRROR 	0x2		/* E$ is mirrored */
184 #define	ECACHE_CPU_NON_MIRROR	0x3		/* E$ is not mirrored */
185 
186 /*
187  * A CPU FRU FMRI string minus the unum component.
188  */
189 #define	CPU_FRU_FMRI		FM_FMRI_SCHEME_HC":///" \
190     FM_FMRI_LEGACY_HC"="
191 
192 struct cpu_node {
193 	char	name[MAXSYSNAME];
194 	char	fru_fmri[sizeof (CPU_FRU_FMRI) + UNUM_NAMLEN];
195 	int	cpuid;
196 	dnode_t	nodeid;
197 	uint64_t	clock_freq;
198 	uint_t	tick_nsec_scale;
199 	union {
200 		int	dummy;
201 	}	u_info;
202 	int	ecache_size;
203 	int	ecache_linesize;
204 	int	ecache_associativity;
205 	int	ecache_setsize;
206 	uint64_t	device_id;
207 };
208 
209 extern struct cpu_node cpunodes[];
210 
211 #endif	/* _ASM */
212 
213 #ifdef	__cplusplus
214 }
215 #endif
216 
217 #endif	/* _SYS_MACHCPUVAR_H */
218