xref: /titanic_41/usr/src/uts/sun4v/sys/ldc_impl.h (revision a3c4695861e3f0a8d3706f77ccd53683cca48d67)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _LDC_IMPL_H
28 #define	_LDC_IMPL_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 #include <sys/types.h>
37 #include <sys/ddi.h>
38 #include <sys/sunddi.h>
39 #include <sys/ioctl.h>
40 
41 /* Memory map table entries */
42 #define	LDC_MTBL_ENTRIES	8192	/* 8 K */
43 
44 /* Define LDC Queue info */
45 #define	LDC_PACKET_SHIFT	6
46 #define	LDC_QUEUE_ENTRIES	512
47 #define	LDC_MTU_MSGS		4
48 #define	LDC_QUEUE_SIZE		(LDC_QUEUE_ENTRIES << LDC_PACKET_SHIFT)
49 #define	LDC_DEFAULT_MTU		(LDC_QUEUE_SIZE / LDC_MTU_MSGS)
50 #define	LDC_RXDQ_MULTIPLIER	2
51 
52 /*
53  * LDC Reliable mode - initial packet seqid
54  * - If peer initiated handshake, RDX should contain init_seqid + 1
55  * - If this endpoint initiated handshake first data packet should
56  *   contain the message init_seqid + 1
57  */
58 #define	LDC_INIT_SEQID	0x0
59 
60 /* LDC Message types */
61 #define	LDC_CTRL	0x01	/* Control Pkt */
62 #define	LDC_DATA	0x02	/* Data Pkt */
63 #define	LDC_ERR		0x10	/* Error Pkt */
64 
65 /* LDC Message Subtypes */
66 #define	LDC_INFO	0x01	/* Control/Data/Error info pkt */
67 #define	LDC_ACK		0x02	/* Control/Data ACK */
68 #define	LDC_NACK	0x04	/* Control/Data NACK */
69 
70 /* LDC Control Messages */
71 #define	LDC_VER		0x01	/* Version message */
72 #define	LDC_RTS		0x02	/* Request to Send */
73 #define	LDC_RTR		0x03	/* Ready To Receive */
74 #define	LDC_RDX		0x04	/* Ready for data exchange */
75 
76 #define	LDC_CTRL_MASK	0x0f	/* Mask to read control bits */
77 
78 /* LDC Channel Transport State (tstate) */
79 #define	TS_TXQ_RDY	0x01	/* allocated TX queue */
80 #define	TS_RXQ_RDY	0x02	/* allocated RX queue */
81 #define	TS_INIT		(TS_TXQ_RDY | TS_RXQ_RDY)
82 #define	TS_QCONF_RDY	0x04	/* registered queues with HV */
83 #define	TS_CNEX_RDY	0x08	/* registered channel with cnex */
84 #define	TS_OPEN		(TS_INIT | TS_QCONF_RDY | TS_CNEX_RDY)
85 #define	TS_LINK_READY	0x10	/* both endpts registered Rx queues */
86 #define	TS_READY	(TS_OPEN | TS_LINK_READY)
87 #define	TS_VER_DONE	0x20	/* negotiated version */
88 #define	TS_VREADY	(TS_READY | TS_VER_DONE)
89 #define	TS_HSHAKE_DONE	0x40	/* completed handshake */
90 #define	TS_UP		(TS_READY | TS_VER_DONE | TS_HSHAKE_DONE)
91 
92 #define	TS_IN_RESET	0x100	/* channel is in reset state */
93 
94 /*  LDC Channel Transport Handshake states */
95 #define	TS_SENT_VER	0x01	/* Sent version */
96 #define	TS_SENT_RTS	0x02	/* Sent RTS */
97 #define	TS_RCVD_RTR	0x04	/* Received RTR */
98 #define	TS_SENT_RDX	0x08	/* Sent RDX */
99 #define	TS_RCVD_VER	0x10	/* Received version */
100 #define	TS_RCVD_RTS	0x20	/* Received RTS */
101 #define	TS_SENT_RTR	0x40	/* Sent RTR */
102 #define	TS_RCVD_RDX	0x80	/* Received RDX */
103 
104 /* LDC Interrupt State */
105 #define	LDC_INTR_NONE	0x00	/* No interrupts */
106 #define	LDC_INTR_ACTIVE	0x01	/* Interrupt being processed */
107 #define	LDC_INTR_PEND	0x02	/* Interrupt pending */
108 
109 /* LDC MSG Envelope */
110 #define	LDC_LEN_MASK	0x3F
111 #define	LDC_FRAG_MASK	0xC0
112 
113 #define	LDC_FRAG_START	0x40	/* frag_info = 0x01 */
114 #define	LDC_FRAG_STOP	0x80	/* frag_info = 0x02 */
115 #define	LDC_FRAG_CONT	0x00	/* frag_info = 0x00 */
116 
117 /*
118  * LDC will retry LDC_MAX_RETRIES times when sending or
119  * receiving data or if the HV returns back EWOULDBLOCK.
120  * Between each retry it will wait LDC_DELAY usecs.
121  */
122 #define	LDC_MAX_RETRIES	1000
123 #define	LDC_DELAY	1
124 
125 /* delay(usec) between channel unregister retries in ldc_close() */
126 #define	LDC_CLOSE_DELAY	1
127 
128 /*
129  * LDC Version information
130  */
131 #define	LDC_PAYLOAD_VER_OFF	8	/* offset of version in payload */
132 
133 typedef struct ldc_ver {
134 	uint16_t	major;
135 	uint16_t	minor;
136 } ldc_ver_t;
137 
138 /*
139  * Each guest consists of one or more LDC endpoints represented by a ldc_chan
140  * structure. Each ldc_chan structure points to a ldc_mtbl structure that
141  * contains information about the map table associated with this LDC endpoint.
142  * The map table contains the list of pages being shared by this guest over
143  * this endpoint with the guest at the other end of this endpoint. Each LDC
144  * endpoint also points to a list of memory handles used to bind and export
145  * memory segments from this guest. If a memory segment is bound, it points to
146  * a memory segment structure, which inturn consists of an array of ldc_page
147  * structure for all the pages within that segment. Each ldc_page structure
148  * contains information about the shared page and also points to the
149  * corresponding entry in the map table.
150  *
151  * Each LDC endpoint also points to a list of ldc_dring structures that refer
152  * to both imported and exported descriptor rings. If it is a exported
153  * descriptor ring, it then points to memory handle/memseg corresponding to
154  * the region of memory associated with the descriptor ring.
155  *
156  *     +----------+   +----------+   +----------+
157  *     | ldc_chan |-->| ldc_chan |-->| ldc_chan |-->....
158  *     +----------+   +----------+   +----------+
159  *       |  |  |
160  *       |  |  |
161  *       |  |  |      +-----------+     +-----------+
162  *       |  |  +----->| ldc_dring |---->| ldc_dring |---->......
163  *       |  |         +-----------+     +-----------+
164  *       |  |               |
165  *       |  |               +----------------------------+
166  *       |  |                                            |
167  *       |  |                                            v
168  *       |  |      +----------+     +----------+     +----------+
169  *       |  +----->| ldc_mhdl |---->| ldc_mhdl |---->| ldc_mhdl |---> ....
170  *       |         +----------+     +----------+     +----------+
171  *       v                 |                             |
172  *  +----------+           |    +------------+           |    +------------+
173  *  | ldc_mtbl |--+        +--->| ldc_memseg |-----+     +--->| ldc_memseg |
174  *  +----------+  |             +------------+     |          +------------+
175  *                |                   |            |            |       |
176  *                v                   v            v            |       v
177  *     +--------------+         +----------+  +--------+        |   +--------+
178  *     | ldc_mte_slot |<--------| ldc_page |  | cookie |        |   | cookie |
179  *     +--------------+         +----------+  +--------+        |   +--------+
180  *     | ldc_mte_slot |<--------| ldc_page |  | cookie |        v
181  *     +--------------+         +----------+  +--------+   +----------+
182  *     | ldc_mte_slot |<-----------------------------------| ldc_page |
183  *     +--------------+                                    +----------+
184  *     | ldc_mte_slot |
185  *     +--------------+
186  *     |    ......    |/ +------------+
187  *     +--------------+  |   entry    |
188  *     | ldc_mte_slot |  +------------+
189  *     +--------------+  | inv_cookie |
190  *                     \ +------------+
191  *
192  */
193 
194 /*
195  * Message format of each packet sent over the LDC channel.
196  * Each packet is 64-bytes long.
197  *
198  * Each packet that is sent over LDC can contain either data or acks.
199  * The type will reflect the contents. The len will contain in bytes
200  * the amount of data being sent. In the case of ACKs, the seqid and
201  * data fields will contain the SEQIDs of messages for which ACKs are
202  * being sent.
203  *
204  * Raw pkt format:
205  *
206  *          +------------------------------------------------------+
207  *  0 - 7   |                 data payload                         |
208  *          +------------------------------------------------------+
209  *
210  * Unreliable pkt format:
211  *
212  *          +------------------------------------------------------+
213  *      0   |          seqid          | env  | ctrl | stype | type |
214  *          +------------------------------------------------------+
215  *  1 - 7   |                 data payload                         |
216  *          +------------------------------------------------------+
217  *
218  * Reliable pkt format:
219  *
220  *          +------------------------------------------------------+
221  *      0   |            seqid        | env  | ctrl | stype | type |
222  *          +------------------------------------------------------+
223  *      1   |          ackid          |         unused             |
224  *          +------------------------------------------------------+
225  *  2 - 7   |                 data payload                         |
226  *          +------------------------------------------------------+
227  */
228 
229 typedef struct ldc_msg {
230 	union {
231 		struct {
232 			uint8_t		_type;	/* Message type */
233 			uint8_t		_stype;	/* Message subtype */
234 			uint8_t		_ctrl;	/* Control/Error Message */
235 			uint8_t 	_env;	/* Message Envelope */
236 			uint32_t	_seqid;	/* Sequence ID */
237 
238 			union {
239 				uint8_t	_ud[LDC_PAYLOAD_SIZE_UNRELIABLE];
240 						/* Unreliable data payload */
241 				struct {
242 					uint32_t _unused;	/* unused */
243 					uint32_t _ackid;	/* ACK ID */
244 					uint8_t	_rd[LDC_PAYLOAD_SIZE_RELIABLE];
245 						/* Reliable data payload */
246 				} _rl;
247 			} _data;
248 		} _tpkt;
249 
250 		uint8_t		_raw[LDC_PAYLOAD_SIZE_RAW];
251 	} _pkt;
252 
253 } ldc_msg_t;
254 
255 #define	raw		_pkt._raw
256 #define	type		_pkt._tpkt._type
257 #define	stype		_pkt._tpkt._stype
258 #define	ctrl		_pkt._tpkt._ctrl
259 #define	env		_pkt._tpkt._env
260 #define	seqid		_pkt._tpkt._seqid
261 #define	udata		_pkt._tpkt._data._ud
262 #define	ackid		_pkt._tpkt._data._rl._ackid
263 #define	rdata		_pkt._tpkt._data._rl._rd
264 
265 /*
266  * LDC Map Table Entry (MTE)
267  *
268  *   6    6                               1    1  1
269  *  |3    0|                       psz|   3|   1| 0| 9| 8| 7|6|5|4|      0|
270  *  +------+--------------------------+----+----+--+--+--+--+-+-+-+-------+
271  *  | rsvd |           PFN            | 0  | 0  |CW|CR|IW|IR|X|W|R| pgszc |
272  *  +------+--------------------------+----+----+--+--+--+--+-+-+-+-------+
273  *  |                       hv invalidation cookie                        |
274  *  +---------------------------------------------------------------------+
275  */
276 typedef union {
277 	struct {
278 		uint64_t	_rsvd2:8,	/* <63:56> reserved */
279 				rpfn:43,	/* <55:13> real pfn */
280 				_rsvd1:2,	/* <12:11> reserved */
281 				cw:1,		/* <10> copy write access */
282 				cr:1,		/* <9> copy read perm */
283 				iw:1,		/* <8> iommu write perm */
284 				ir:1,		/* <7> iommu read perm */
285 				x:1,		/* <6> execute perm */
286 				w:1,		/* <5> write perm */
287 				r:1,		/* <4> read perm */
288 				pgszc:4;	/* <3:0> pgsz code */
289 	} mte_bit;
290 
291 	uint64_t 		ll;
292 
293 } ldc_mte_t;
294 
295 #define	mte_rpfn	mte_bit.rpfn
296 #define	mte_cw		mte_bit.cw
297 #define	mte_cr		mte_bit.cr
298 #define	mte_iw		mte_bit.iw
299 #define	mte_ir		mte_bit.ir
300 #define	mte_x		mte_bit.x
301 #define	mte_w		mte_bit.w
302 #define	mte_r		mte_bit.r
303 #define	mte_pgszc	mte_bit.pgszc
304 
305 #define	MTE_BSZS_SHIFT(sz)	((sz) * 3)
306 #define	MTEBYTES(sz)    	(MMU_PAGESIZE << MTE_BSZS_SHIFT(sz))
307 #define	MTEPAGES(sz)    	(1 << MTE_BSZS_SHIFT(sz))
308 #define	MTE_PAGE_SHIFT(sz)	(MMU_PAGESHIFT + MTE_BSZS_SHIFT(sz))
309 #define	MTE_PAGE_OFFSET(sz)	(MTEBYTES(sz) - 1)
310 #define	MTE_PAGEMASK(sz)	(~MTE_PAGE_OFFSET(sz))
311 #define	MTE_PFNMASK(sz)		(~(MTE_PAGE_OFFSET(sz) >> MMU_PAGESHIFT))
312 
313 /*
314  * LDC Map Table Slot
315  */
316 typedef struct ldc_mte_slot {
317 	ldc_mte_t	entry;
318 	uint64_t	cookie;
319 } ldc_mte_slot_t;
320 
321 /*
322  * LDC Memory Map Table
323  *
324  * Each LDC has a memory map table it uses to list all the pages
325  * it exporting to its peer over the channel. This structure
326  * contains information about the map table and is pointed to
327  * by the ldc_chan structure.
328  */
329 typedef struct ldc_mtbl {
330 	kmutex_t		lock;		/* Table lock */
331 	size_t			size;		/* Table size (in bytes) */
332 	uint64_t		next_entry;	/* Next entry to use */
333 	uint64_t		num_entries;	/* Num entries in table */
334 	uint64_t		num_avail;	/* Num of available entries */
335 	boolean_t		contigmem;	/* TRUE=Contig mem alloc'd */
336 	ldc_mte_slot_t		*table;		/* The table itself */
337 } ldc_mtbl_t;
338 
339 /*
340  * LDC page and memory segment information
341  */
342 typedef struct ldc_page {
343 	uintptr_t		raddr;		/* Exported page RA */
344 	uint64_t		offset;		/* Exported page offset */
345 	size_t			size;		/* Exported page size */
346 	uint64_t		index;		/* Index in map table */
347 	ldc_mte_slot_t		*mte;		/* Map table entry */
348 } ldc_page_t;
349 
350 typedef struct ldc_memseg {
351 	caddr_t			vaddr;		/* Exported segment VA */
352 	uintptr_t		raddr;		/* Exported segment VA */
353 	size_t			size;		/* Exported segment size */
354 	uint64_t		npages;		/* Number of pages */
355 	ldc_page_t		*pages;		/* Array of exported pages */
356 	uint32_t		ncookies;	/* Number of cookies */
357 	ldc_mem_cookie_t	*cookies;
358 	uint64_t		next_cookie;	/* Index to next cookie */
359 } ldc_memseg_t;
360 
361 /*
362  * LDC Cookie address format
363  *
364  *   6       6          m+n
365  *  |3|      0|          |                  m|                  0|
366  *  +-+-------+----------+-------------------+-------------------+
367  *  |X| pgszc |   rsvd   |      table_idx    |     page_offset   |
368  *  +-+-------+----------+-------------------+-------------------+
369  */
370 #define	LDC_COOKIE_PGSZC_MASK	0x7
371 #define	LDC_COOKIE_PGSZC_SHIFT	60
372 
373 /*
374  * LDC Memory handle
375  */
376 typedef struct ldc_chan ldc_chan_t;
377 
378 typedef struct ldc_mhdl {
379 	kmutex_t		lock;		/* Mutex for memory handle */
380 	ldc_mstatus_t		status;		/* Memory map status */
381 
382 	uint8_t			mtype;		/* Type of sharing */
383 	uint8_t			perm;		/* Access permissions */
384 	boolean_t		myshadow;	/* TRUE=alloc'd shadow mem */
385 
386 	ldc_chan_t		*ldcp;		/* Pointer to channel struct */
387 	ldc_memseg_t		*memseg;	/* Bound memory segment */
388 	struct ldc_mhdl		*next;		/* Next memory handle */
389 } ldc_mhdl_t;
390 
391 /*
392  * LDC Descriptor rings
393  */
394 
395 typedef struct ldc_dring {
396 	kmutex_t		lock;		/* Desc ring lock */
397 	ldc_mstatus_t		status;		/* Desc ring status */
398 
399 	uint32_t		dsize;		/* Descriptor size */
400 	uint32_t		length;		/* Descriptor ring length */
401 	uint64_t		size;		/* Desc ring size (in bytes) */
402 	caddr_t			base;		/* Descriptor ring base addr */
403 
404 	ldc_chan_t		*ldcp;		/* Pointer to bound channel */
405 	ldc_mem_handle_t	mhdl;		/* Mem handle to desc ring */
406 
407 	struct ldc_dring	*ch_next;	/* Next dring in channel */
408 	struct ldc_dring 	*next;		/* Next dring overall */
409 
410 } ldc_dring_t;
411 
412 
413 /*
414  * Channel specific information is kept in a separate
415  * structure. These are then stored on a array indexed
416  * by the channel number.
417  */
418 struct ldc_chan {
419 	ldc_chan_t	*next;		/* Next channel */
420 
421 	kmutex_t	lock;		/* Channel lock */
422 	uint64_t	id;		/* Channel ID */
423 	ldc_status_t	status;		/* Channel status */
424 	uint32_t	tstate;		/* Channel transport state */
425 	uint32_t	hstate;		/* Channel transport handshake state */
426 
427 	ldc_dev_t	devclass;	/* Associated device class */
428 	uint64_t	devinst;	/* Associated device instance */
429 	ldc_mode_t	mode;		/* Channel mode */
430 
431 	uint64_t	mtu;		/* Max TU size */
432 
433 	ldc_ver_t	version;	/* Channel version */
434 	uint32_t	next_vidx;	/* Next version to match */
435 
436 	uint_t		(*cb)(uint64_t event, caddr_t arg);
437 	caddr_t		cb_arg;		/* Channel callback and arg */
438 	boolean_t	cb_inprogress;	/* Channel callback in progress */
439 	boolean_t	cb_enabled;	/* Channel callbacks are enabled */
440 
441 	uint8_t		tx_intr_state;	/* Tx interrupt state */
442 	uint8_t		rx_intr_state;	/* Rx interrupt state */
443 
444 	kmutex_t	tx_lock;	/* Transmit lock */
445 	uint64_t	tx_q_entries;	/* Num entries in transmit queue */
446 	uint64_t	tx_q_va;	/* Virtual addr of transmit queue */
447 	uint64_t	tx_q_ra;	/* Real addr of transmit queue */
448 	uint64_t	tx_head;	/* Tx queue head */
449 	uint64_t	tx_ackd_head;	/* Tx queue ACKd head (Reliable) */
450 	uint64_t	tx_tail;	/* Tx queue tail */
451 
452 	uint64_t	rx_q_entries;	/* Num entries in receive queue */
453 	uint64_t	rx_q_va;	/* Virtual addr of receive queue */
454 	uint64_t	rx_q_ra;	/* Real addr of receive queue */
455 
456 	uint64_t	rx_dq_entries;	/* Num entries in the data queue */
457 	uint64_t	rx_dq_va;	/* Virtual addr of the data queue */
458 	uint64_t	rx_dq_head;	/* Receive data queue head */
459 	uint64_t	rx_dq_tail;	/* Receive data queue tail */
460 	uint64_t	rx_ack_head;	/* Receive data ACK peek head ptr */
461 
462 	uint64_t	link_state;	/* Underlying HV channel state */
463 
464 	ldc_mtbl_t	*mtbl;		/* Memory table used by channel */
465 	ldc_mhdl_t	*mhdl_list;	/* List of memory handles */
466 	kmutex_t	mlist_lock;	/* Mem handle list lock */
467 
468 	ldc_dring_t	*exp_dring_list; /* Exported desc ring list */
469 	kmutex_t	exp_dlist_lock;	/* Lock for exported desc ring list */
470 	ldc_dring_t	*imp_dring_list; /* Imported desc ring list */
471 	kmutex_t	imp_dlist_lock;	/* Lock for imported desc ring list */
472 
473 	uint8_t		pkt_payload;	/* Size of packet payload */
474 
475 	uint32_t	last_msg_snt;	/* Seqid of last packet sent */
476 	uint32_t	last_ack_rcd;	/* Seqid of last ACK recd */
477 	uint32_t	last_msg_rcd;	/* Seqid of last packet received */
478 
479 	uint32_t	stream_remains;	/* Number of bytes in stream */
480 					/* packet buffer */
481 	uint32_t	stream_offset;	/* Offset into packet buffer for */
482 					/* next read */
483 	uint8_t		*stream_bufferp; /* Stream packet buffer */
484 
485 	int		(*read_p)(ldc_chan_t *ldcp, caddr_t bufferp,
486 				size_t *sizep);
487 	int		(*write_p)(ldc_chan_t *ldcp, caddr_t bufferp,
488 				size_t *sizep);
489 
490 	uint64_t	(*readq_get_state)(ldc_chan_t *ldcp, uint64_t *head,
491 				uint64_t *tail, uint64_t *link_state);
492 
493 	int		(*readq_set_head)(ldc_chan_t *ldcp, uint64_t head);
494 };
495 
496 
497 /*
498  * LDC module soft state structure
499  */
500 typedef struct ldc_soft_state {
501 	kmutex_t 	lock;		/* Protects ldc_soft_state_t  */
502 	ldc_cnex_t	cinfo;		/* channel nexus info */
503 	uint64_t	channel_count;	/* Number of channels */
504 	uint64_t	channels_open;	/* Number of open channels */
505 	ldc_chan_t 	*chan_list;	/* List of LDC endpoints */
506 	ldc_dring_t	*dring_list;	/* Descriptor rings (for export) */
507 
508 	kmem_cache_t	*memhdl_cache;	/* Memory handle cache */
509 	kmem_cache_t	*memseg_cache;	/* Memory segment cache */
510 } ldc_soft_state_t;
511 
512 #ifdef __cplusplus
513 }
514 #endif
515 
516 #endif /* _LDC_IMPL_H */
517