1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 #ifndef _SYS_HYPERVISOR_API_H 27 #define _SYS_HYPERVISOR_API_H 28 29 /* 30 * sun4v Hypervisor API 31 * 32 * Reference: api.pdf Revision 0.12 dated May 12, 2004. 33 * io-api.txt version 1.11 dated 10/19/2004 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* 41 * Trap types 42 */ 43 #define FAST_TRAP 0x80 /* Function # in %o5 */ 44 #define CPU_TICK_NPT 0x81 45 #define CPU_STICK_NPT 0x82 46 #define MMU_MAP_ADDR 0x83 47 #define MMU_UNMAP_ADDR 0x84 48 #define MMU_MAP_TTE 0x86 49 50 #define CORE_TRAP 0xff 51 52 /* 53 * Error returns in %o0. 54 * (Additional result is returned in %o1.) 55 */ 56 #define H_EOK 0 /* Successful return */ 57 #define H_ENOCPU 1 /* Invalid CPU id */ 58 #define H_ENORADDR 2 /* Invalid real address */ 59 #define H_ENOINTR 3 /* Invalid interrupt id */ 60 #define H_EBADPGSZ 4 /* Invalid pagesize encoding */ 61 #define H_EBADTSB 5 /* Invalid TSB description */ 62 #define H_EINVAL 6 /* Invalid argument */ 63 #define H_EBADTRAP 7 /* Invalid function number */ 64 #define H_EBADALIGN 8 /* Invalid address alignment */ 65 #define H_EWOULDBLOCK 9 /* Cannot complete operation */ 66 /* without blocking */ 67 #define H_ENOACCESS 10 /* No access to resource */ 68 #define H_EIO 11 /* I/O error */ 69 #define H_ECPUERROR 12 /* CPU is in error state */ 70 #define H_ENOTSUPPORTED 13 /* Function not supported */ 71 #define H_ENOMAP 14 /* Mapping is not valid, */ 72 /* no translation exists */ 73 #define H_EBUSY 17 /* Resource busy */ 74 #define H_ETOOMANY 15 /* Hard resource limit exceeded */ 75 #define H_ECHANNEL 16 /* Illegal LDC channel */ 76 77 #define H_BREAK -1 /* Console Break */ 78 #define H_HUP -2 /* Console Break */ 79 80 /* 81 * Mondo CPU ID argument processing. 82 */ 83 #define HV_SEND_MONDO_ENTRYDONE 0xffff 84 85 /* 86 * Function numbers for FAST_TRAP. 87 */ 88 #define HV_MACH_EXIT 0x00 89 #define HV_MACH_DESC 0x01 90 #define HV_MACH_SIR 0x02 91 #define MACH_SET_WATCHDOG 0x05 92 93 #define HV_CPU_START 0x10 94 #define HV_CPU_STOP 0x11 95 #define HV_CPU_YIELD 0x12 96 #define HV_CPU_QCONF 0x14 97 #define HV_CPU_STATE 0x17 98 #define HV_CPU_SET_RTBA 0x18 99 100 #define MMU_TSB_CTX0 0x20 101 #define MMU_TSB_CTXNON0 0x21 102 #define MMU_DEMAP_PAGE 0x22 103 #define MMU_DEMAP_CTX 0x23 104 #define MMU_DEMAP_ALL 0x24 105 #define MAP_PERM_ADDR 0x25 106 #define MMU_SET_INFOPTR 0x26 107 #define MMU_ENABLE 0x27 108 #define UNMAP_PERM_ADDR 0x28 109 110 #define HV_MEM_SCRUB 0x31 111 #define HV_MEM_SYNC 0x32 112 113 #define HV_INTR_SEND 0x42 114 115 #define TOD_GET 0x50 116 #define TOD_SET 0x51 117 118 #define CONS_GETCHAR 0x60 119 #define CONS_PUTCHAR 0x61 120 #define CONS_READ 0x62 121 #define CONS_WRITE 0x63 122 123 #define SOFT_STATE_SET 0x70 124 #define SOFT_STATE_GET 0x71 125 126 #define TTRACE_BUF_CONF 0x90 127 #define TTRACE_BUF_INFO 0x91 128 #define TTRACE_ENABLE 0x92 129 #define TTRACE_FREEZE 0x93 130 #define DUMP_BUF_UPDATE 0x94 131 132 #define HVIO_INTR_DEVINO2SYSINO 0xa0 133 #define HVIO_INTR_GETVALID 0xa1 134 #define HVIO_INTR_SETVALID 0xa2 135 #define HVIO_INTR_GETSTATE 0xa3 136 #define HVIO_INTR_SETSTATE 0xa4 137 #define HVIO_INTR_GETTARGET 0xa5 138 #define HVIO_INTR_SETTARGET 0xa6 139 140 #define VINTR_GET_COOKIE 0xa7 141 #define VINTR_SET_COOKIE 0xa8 142 #define VINTR_GET_VALID 0xa9 143 #define VINTR_SET_VALID 0xaa 144 #define VINTR_GET_STATE 0xab 145 #define VINTR_SET_STATE 0xac 146 #define VINTR_GET_TARGET 0xad 147 #define VINTR_SET_TARGET 0xae 148 149 #define LDC_TX_QCONF 0xe0 150 #define LDC_TX_QINFO 0xe1 151 #define LDC_TX_GET_STATE 0xe2 152 #define LDC_TX_SET_QTAIL 0xe3 153 #define LDC_RX_QCONF 0xe4 154 #define LDC_RX_QINFO 0xe5 155 #define LDC_RX_GET_STATE 0xe6 156 #define LDC_RX_SET_QHEAD 0xe7 157 158 #define LDC_SET_MAP_TABLE 0xea 159 #define LDC_GET_MAP_TABLE 0xeb 160 #define LDC_COPY 0xec 161 #define LDC_MAPIN 0xed 162 #define LDC_UNMAP 0xee 163 #define LDC_REVOKE 0xef 164 #define LDC_MAPIN_SIZE_MAX 0x187 165 166 #ifdef SET_MMU_STATS 167 #define MMU_STAT_AREA 0xfc 168 #endif /* SET_MMU_STATS */ 169 170 #define HV_MACH_PRI 0x170 171 #define HV_REBOOT_DATA_SET 0x172 172 173 #define HV_TPM_GET 0x176 174 #define HV_TPM_PUT 0x177 175 176 #define HV_TM_ENABLE 0x180 177 178 #define GUEST_SUSPEND 0x181 179 #define TICK_SET_NPT 0x182 180 #define STICK_SET_NPT 0x183 181 182 #define HV_RA2PA 0x200 183 #define HV_HPRIV 0x201 184 185 /* 186 * Function numbers for CORE_TRAP. 187 */ 188 #define API_SET_VERSION 0x00 189 #define API_PUT_CHAR 0x01 190 #define API_EXIT 0x02 191 #define API_GET_VERSION 0x03 192 193 194 /* 195 * Definitions for MACH_SOFT_STATE routines 196 */ 197 198 #define SIS_NORMAL 0x01 199 #define SIS_TRANSITION 0x02 200 201 /* 202 * Bits for MMU functions flags argument: 203 * arg3 of MMU_MAP_ADDR 204 * arg3 of MMU_DEMAP_CTX 205 * arg2 of MMU_DEMAP_ALL 206 */ 207 #define MAP_DTLB 0x1 208 #define MAP_ITLB 0x2 209 210 211 /* 212 * Interrupt state manipulation definitions. 213 */ 214 215 #define HV_INTR_IDLE_STATE 0 216 #define HV_INTR_RECEIVED_STATE 1 217 #define HV_INTR_DELIVERED_STATE 2 218 219 #define HV_INTR_NOTVALID 0 220 #define HV_INTR_VALID 1 221 222 #ifndef _ASM 223 224 /* 225 * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0. 226 */ 227 typedef struct hv_tsb_info { 228 uint16_t hvtsb_idxpgsz; /* page size used to index TSB */ 229 uint16_t hvtsb_assoc; /* TSB associativity */ 230 uint32_t hvtsb_ntte; /* TSB size (#TTE entries) */ 231 uint32_t hvtsb_ctx_index; /* context reg index */ 232 uint32_t hvtsb_pgszs; /* sizes in use */ 233 uint64_t hvtsb_pa; /* real address of TSB base */ 234 uint64_t hvtsb_rsvd; /* reserved */ 235 } hv_tsb_info_t; 236 237 #define HVTSB_SHARE_INDEX ((uint32_t)-1) 238 239 #ifdef SET_MMU_STATS 240 #ifndef TTE4V_NPGSZ 241 #define TTE4V_NPGSZ 8 242 #endif /* TTE4V_NPGSZ */ 243 /* 244 * MMU statistics structure for MMU_STAT_AREA 245 */ 246 struct mmu_stat_one { 247 uint64_t hit_ctx0[TTE4V_NPGSZ]; 248 uint64_t hit_ctxn0[TTE4V_NPGSZ]; 249 uint64_t tsb_miss; 250 uint64_t tlb_miss; /* miss, no TSB set */ 251 uint64_t map_ctx0[TTE4V_NPGSZ]; 252 uint64_t map_ctxn0[TTE4V_NPGSZ]; 253 }; 254 255 struct mmu_stat { 256 struct mmu_stat_one immu_stat; 257 struct mmu_stat_one dmmu_stat; 258 uint64_t set_ctx0; 259 uint64_t set_ctxn0; 260 }; 261 #endif /* SET_MMU_STATS */ 262 263 #endif /* ! _ASM */ 264 265 /* 266 * CPU States 267 */ 268 #define CPU_STATE_INVALID 0x0 269 #define CPU_STATE_STOPPED 0x1 /* cpu not started */ 270 #define CPU_STATE_RUNNING 0x2 /* cpu running guest code */ 271 #define CPU_STATE_ERROR 0x3 /* cpu is in the error state */ 272 #define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last valid state */ 273 274 /* 275 * MMU fault status area 276 */ 277 278 #define MMFSA_TYPE_ 0x00 /* fault type */ 279 #define MMFSA_ADDR_ 0x08 /* fault address */ 280 #define MMFSA_CTX_ 0x10 /* fault context */ 281 282 #define MMFSA_I_ 0x00 /* start of fields for I */ 283 #define MMFSA_I_TYPE (MMFSA_I_ + MMFSA_TYPE_) /* instruction fault type */ 284 #define MMFSA_I_ADDR (MMFSA_I_ + MMFSA_ADDR_) /* instruction fault address */ 285 #define MMFSA_I_CTX (MMFSA_I_ + MMFSA_CTX_) /* instruction fault context */ 286 287 #define MMFSA_D_ 0x40 /* start of fields for D */ 288 #define MMFSA_D_TYPE (MMFSA_D_ + MMFSA_TYPE_) /* data fault type */ 289 #define MMFSA_D_ADDR (MMFSA_D_ + MMFSA_ADDR_) /* data fault address */ 290 #define MMFSA_D_CTX (MMFSA_D_ + MMFSA_CTX_) /* data fault context */ 291 292 #define MMFSA_F_FMISS 1 /* fast miss */ 293 #define MMFSA_F_FPROT 2 /* fast protection */ 294 #define MMFSA_F_MISS 3 /* mmu miss */ 295 #define MMFSA_F_INVRA 4 /* invalid RA */ 296 #define MMFSA_F_PRIV 5 /* privilege violation */ 297 #define MMFSA_F_PROT 6 /* protection violation */ 298 #define MMFSA_F_NFO 7 /* NFO access */ 299 #define MMFSA_F_SOPG 8 /* so page */ 300 #define MMFSA_F_INVVA 9 /* invalid VA */ 301 #define MMFSA_F_INVASI 10 /* invalid ASI */ 302 #define MMFSA_F_NCATM 11 /* non-cacheable atomic */ 303 #define MMFSA_F_PRVACT 12 /* privileged action */ 304 #define MMFSA_F_WPT 13 /* watchpoint hit */ 305 #define MMFSA_F_UNALIGN 14 /* unaligned access */ 306 #define MMFSA_F_INVPGSZ 15 /* invalid page size */ 307 308 #define MMFSA_SIZE 0x80 /* in bytes, 64 byte aligned */ 309 310 /* 311 * MMU fault status - MMFSA_IFS and MMFSA_DFS 312 */ 313 #define MMFS_FV 0x00000001 314 #define MMFS_OW 0x00000002 315 #define MMFS_W 0x00000004 316 #define MMFS_PR 0x00000008 317 #define MMFS_CT 0x00000030 318 #define MMFS_E 0x00000040 319 #define MMFS_FT 0x00003f80 320 #define MMFS_ME 0x00004000 321 #define MMFS_TM 0x00008000 322 #define MMFS_ASI 0x00ff0000 323 #define MMFS_NF 0x01000000 324 325 /* 326 * DMA sync parameter definitions 327 */ 328 #define HVIO_DMA_SYNC_DIR_TO_DEV 0x01 329 #define HVIO_DMA_SYNC_DIR_FROM_DEV 0x02 330 331 /* 332 * LDC Channel States 333 */ 334 #define LDC_CHANNEL_DOWN 0x0 335 #define LDC_CHANNEL_UP 0x1 336 #define LDC_CHANNEL_RESET 0x2 337 338 /* 339 * LDC mapin table types 340 */ 341 #define LDC_MAPIN_TYPE_REGULAR 0x1 /* 8K page-size table */ 342 #define LDC_MAPIN_TYPE_LARGE 0x2 /* Large page-size table */ 343 344 #ifndef _ASM 345 346 extern uint64_t hv_mmu_map_perm_addr(void *, int, uint64_t, int); 347 extern uint64_t hv_mmu_unmap_perm_addr(void *, int, int); 348 extern uint64_t hv_mach_exit(uint64_t exit_code); 349 extern uint64_t hv_mach_sir(void); 350 351 extern uint64_t hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, 352 uint64_t arg); 353 extern uint64_t hv_cpu_stop(uint64_t cpuid); 354 extern uint64_t hv_cpu_set_rtba(uint64_t *rtba); 355 356 extern uint64_t hv_set_ctx0(uint64_t, uint64_t); 357 extern uint64_t hv_set_ctxnon0(uint64_t, uint64_t); 358 extern uint64_t hv_mmu_fault_area_conf(void *raddr); 359 #ifdef SET_MMU_STATS 360 extern uint64_t hv_mmu_set_stat_area(uint64_t, uint64_t); 361 #endif /* SET_MMU_STATS */ 362 363 extern uint64_t hv_cpu_qconf(int queue, uint64_t paddr, int size); 364 extern uint64_t hv_cpu_yield(void); 365 extern uint64_t hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 366 extern uint64_t hv_mem_scrub(uint64_t real_addr, uint64_t length, 367 uint64_t *scrubbed_len); 368 extern uint64_t hv_mem_sync(uint64_t real_addr, uint64_t length, 369 uint64_t *flushed_len); 370 extern uint64_t hv_tm_enable(uint64_t enable); 371 372 extern uint64_t hv_service_recv(uint64_t s_id, uint64_t buf_pa, 373 uint64_t size, uint64_t *recv_bytes); 374 extern uint64_t hv_service_send(uint64_t s_id, uint64_t buf_pa, 375 uint64_t size, uint64_t *send_bytes); 376 extern uint64_t hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 377 extern uint64_t hv_service_setstatus(uint64_t s_id, uint64_t bits); 378 extern uint64_t hv_service_clrstatus(uint64_t s_id, uint64_t bits); 379 extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep); 380 381 extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *); 382 extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *); 383 extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *); 384 extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *); 385 extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *); 386 extern uint64_t hv_mach_set_watchdog(uint64_t, uint64_t *); 387 388 extern int64_t hv_cnputchar(uint8_t); 389 extern int64_t hv_cngetchar(uint8_t *); 390 extern int64_t hv_cnwrite(uint64_t, uint64_t, uint64_t *); 391 extern int64_t hv_cnread(uint64_t, uint64_t, int64_t *); 392 393 extern uint64_t hv_tod_get(uint64_t *seconds); 394 extern uint64_t hv_tod_set(uint64_t); 395 396 extern uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, 397 uint64_t *sysino); 398 extern uint64_t hvio_intr_getvalid(uint64_t sysino, 399 int *intr_valid_state); 400 extern uint64_t hvio_intr_setvalid(uint64_t sysino, 401 int intr_valid_state); 402 extern uint64_t hvio_intr_getstate(uint64_t sysino, 403 int *intr_state); 404 extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state); 405 extern uint64_t hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid); 406 extern uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid); 407 extern uint64_t hv_soft_state_set(uint64_t state, uint64_t string_ra); 408 extern uint64_t hv_soft_state_get(uint64_t string_ra, uint64_t *state); 409 410 extern uint64_t hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 411 uint64_t nentries); 412 extern uint64_t hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 413 uint64_t *nentries); 414 extern uint64_t hv_ldc_tx_get_state(uint64_t channel, uint64_t *headp, 415 uint64_t *tailp, uint64_t *state); 416 extern uint64_t hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail); 417 extern uint64_t hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 418 uint64_t nentries); 419 extern uint64_t hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 420 uint64_t *nentries); 421 extern uint64_t hv_ldc_rx_get_state(uint64_t channel, uint64_t *headp, 422 uint64_t *tailp, uint64_t *state); 423 extern uint64_t hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head); 424 425 extern uint64_t hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 426 uint64_t tbl_entries); 427 extern uint64_t hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 428 uint64_t *tbl_entries); 429 extern uint64_t hv_ldc_copy(uint64_t channel, uint64_t request, 430 uint64_t cookie, uint64_t raddr, uint64_t length, uint64_t *lengthp); 431 extern uint64_t hv_ldc_mapin(uint64_t channel, uint64_t cookie, 432 uint64_t *raddr, uint64_t *perm); 433 extern uint64_t hv_ldc_unmap(uint64_t raddr); 434 extern uint64_t hv_ldc_revoke(uint64_t channel, uint64_t cookie, 435 uint64_t revoke_cookie); 436 extern uint64_t hv_ldc_mapin_size_max(uint64_t tbl_type, uint64_t *sz); 437 extern uint64_t hv_api_get_version(uint64_t api_group, uint64_t *majorp, 438 uint64_t *minorp); 439 extern uint64_t hv_api_set_version(uint64_t api_group, uint64_t major, 440 uint64_t minor, uint64_t *supported_minor); 441 442 extern uint64_t hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 443 uint64_t *cookie); 444 extern uint64_t hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 445 uint64_t cookie); 446 extern uint64_t hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 447 int *intr_valid_state); 448 extern uint64_t hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 449 int intr_valid_state); 450 extern uint64_t hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 451 int *intr_state); 452 extern uint64_t hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 453 int intr_state); 454 extern uint64_t hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 455 uint32_t *cpuid); 456 extern uint64_t hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 457 uint32_t cpuid); 458 extern uint64_t hv_mach_pri(uint64_t buffer_ra, uint64_t *buffer_sizep); 459 extern uint64_t hv_reboot_data_set(uint64_t buffer_ra, uint64_t buffer_len); 460 461 extern uint64_t hv_guest_suspend(void); 462 extern uint64_t hv_tick_set_npt(uint64_t npt); 463 extern uint64_t hv_stick_set_npt(uint64_t npt); 464 465 #endif /* ! _ASM */ 466 467 468 #ifdef __cplusplus 469 } 470 #endif 471 472 #endif /* _SYS_HYPERVISOR_API_H */ 473