1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_HYPERVISOR_API_H 28 #define _SYS_HYPERVISOR_API_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * sun4v Hypervisor API 34 * 35 * Reference: api.pdf Revision 0.12 dated May 12, 2004. 36 * io-api.txt version 1.11 dated 10/19/2004 37 */ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 44 * Trap types 45 */ 46 #define FAST_TRAP 0x80 /* Function # in %o5 */ 47 #define CPU_TICK_NPT 0x81 48 #define CPU_STICK_NPT 0x82 49 #define MMU_MAP_ADDR 0x83 50 #define MMU_UNMAP_ADDR 0x84 51 52 #define CORE_TRAP 0xff 53 54 /* 55 * Error returns in %o0. 56 * (Additional result is returned in %o1.) 57 */ 58 #define H_EOK 0 /* Successful return */ 59 #define H_ENOCPU 1 /* Invalid CPU id */ 60 #define H_ENORADDR 2 /* Invalid real address */ 61 #define H_ENOINTR 3 /* Invalid interrupt id */ 62 #define H_EBADPGSZ 4 /* Invalid pagesize encoding */ 63 #define H_EBADTSB 5 /* Invalid TSB description */ 64 #define H_EINVAL 6 /* Invalid argument */ 65 #define H_EBADTRAP 7 /* Invalid function number */ 66 #define H_EBADALIGN 8 /* Invalid address alignment */ 67 #define H_EWOULDBLOCK 9 /* Cannot complete operation */ 68 /* without blocking */ 69 #define H_ENOACCESS 10 /* No access to resource */ 70 #define H_EIO 11 /* I/O error */ 71 #define H_ECPUERROR 12 /* CPU is in error state */ 72 #define H_ENOTSUPPORTED 13 /* Function not supported */ 73 #define H_ENOMAP 14 /* Mapping is not valid, */ 74 /* no translation exists */ 75 #define H_EBUSY 17 /* Resource busy */ 76 #define H_ETOOMANY 15 /* Hard resource limit exceeded */ 77 #define H_ECHANNEL 16 /* Illegal LDC channel */ 78 79 #define H_BREAK -1 /* Console Break */ 80 #define H_HUP -2 /* Console Break */ 81 82 /* 83 * Mondo CPU ID argument processing. 84 */ 85 #define HV_SEND_MONDO_ENTRYDONE 0xffff 86 87 /* 88 * Function numbers for FAST_TRAP. 89 */ 90 #define HV_MACH_EXIT 0x00 91 #define HV_MACH_DESC 0x01 92 #define HV_MACH_SIR 0x02 93 #define MACH_SET_WATCHDOG 0x05 94 95 #define HV_CPU_START 0x10 96 #define HV_CPU_STOP 0x11 97 #define HV_CPU_YIELD 0x12 98 #define HV_CPU_QCONF 0x14 99 #define HV_CPU_STATE 0x17 100 #define HV_CPU_SET_RTBA 0x18 101 102 #define MMU_TSB_CTX0 0x20 103 #define MMU_TSB_CTXNON0 0x21 104 #define MMU_DEMAP_PAGE 0x22 105 #define MMU_DEMAP_CTX 0x23 106 #define MMU_DEMAP_ALL 0x24 107 #define MAP_PERM_ADDR 0x25 108 #define MMU_SET_INFOPTR 0x26 109 #define MMU_ENABLE 0x27 110 #define UNMAP_PERM_ADDR 0x28 111 112 #define HV_MEM_SCRUB 0x31 113 #define HV_MEM_SYNC 0x32 114 115 #define HV_INTR_SEND 0x42 116 117 #define TOD_GET 0x50 118 #define TOD_SET 0x51 119 120 #define CONS_GETCHAR 0x60 121 #define CONS_PUTCHAR 0x61 122 123 #define TTRACE_BUF_CONF 0x90 124 #define TTRACE_BUF_INFO 0x91 125 #define TTRACE_ENABLE 0x92 126 #define TTRACE_FREEZE 0x93 127 #define DUMP_BUF_UPDATE 0x94 128 129 #define HVIO_INTR_DEVINO2SYSINO 0xa0 130 #define HVIO_INTR_GETVALID 0xa1 131 #define HVIO_INTR_SETVALID 0xa2 132 #define HVIO_INTR_GETSTATE 0xa3 133 #define HVIO_INTR_SETSTATE 0xa4 134 #define HVIO_INTR_GETTARGET 0xa5 135 #define HVIO_INTR_SETTARGET 0xa6 136 137 #define VINTR_GET_COOKIE 0xa7 138 #define VINTR_SET_COOKIE 0xa8 139 #define VINTR_GET_VALID 0xa9 140 #define VINTR_SET_VALID 0xaa 141 #define VINTR_GET_STATE 0xab 142 #define VINTR_SET_STATE 0xac 143 #define VINTR_GET_TARGET 0xad 144 #define VINTR_SET_TARGET 0xae 145 146 #define LDC_TX_QCONF 0xe0 147 #define LDC_TX_QINFO 0xe1 148 #define LDC_TX_GET_STATE 0xe2 149 #define LDC_TX_SET_QTAIL 0xe3 150 #define LDC_RX_QCONF 0xe4 151 #define LDC_RX_QINFO 0xe5 152 #define LDC_RX_GET_STATE 0xe6 153 #define LDC_RX_SET_QHEAD 0xe7 154 155 #define LDC_SET_MAP_TABLE 0xea 156 #define LDC_GET_MAP_TABLE 0xeb 157 #define LDC_COPY 0xec 158 #define LDC_MAPIN 0xed 159 #define LDC_UNMAP 0xee 160 #define LDC_REVOKE 0xef 161 162 #ifdef SET_MMU_STATS 163 #define MMU_STAT_AREA 0xfc 164 #endif /* SET_MMU_STATS */ 165 166 #define HV_RA2PA 0x200 167 #define HV_HPRIV 0x201 168 169 /* 170 * Function numbers for CORE_TRAP. 171 */ 172 #define API_SET_VERSION 0x00 173 #define API_PUT_CHAR 0x01 174 #define API_EXIT 0x02 175 #define API_GET_VERSION 0x03 176 177 178 /* 179 * Bits for MMU functions flags argument: 180 * arg3 of MMU_MAP_ADDR 181 * arg3 of MMU_DEMAP_CTX 182 * arg2 of MMU_DEMAP_ALL 183 */ 184 #define MAP_DTLB 0x1 185 #define MAP_ITLB 0x2 186 187 188 /* 189 * Interrupt state manipulation definitions. 190 */ 191 192 #define HV_INTR_IDLE_STATE 0 193 #define HV_INTR_RECEIVED_STATE 1 194 #define HV_INTR_DELIVERED_STATE 2 195 196 #define HV_INTR_NOTVALID 0 197 #define HV_INTR_VALID 1 198 199 #ifndef _ASM 200 201 /* 202 * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0. 203 */ 204 typedef struct hv_tsb_info { 205 uint16_t hvtsb_idxpgsz; /* page size used to index TSB */ 206 uint16_t hvtsb_assoc; /* TSB associativity */ 207 uint32_t hvtsb_ntte; /* TSB size (#TTE entries) */ 208 uint32_t hvtsb_ctx_index; /* context reg index */ 209 uint32_t hvtsb_pgszs; /* sizes in use */ 210 uint64_t hvtsb_pa; /* real address of TSB base */ 211 uint64_t hvtsb_rsvd; /* reserved */ 212 } hv_tsb_info_t; 213 214 #define HVTSB_SHARE_INDEX ((uint32_t)-1) 215 216 #ifdef SET_MMU_STATS 217 #ifndef TTE4V_NPGSZ 218 #define TTE4V_NPGSZ 8 219 #endif /* TTE4V_NPGSZ */ 220 /* 221 * MMU statistics structure for MMU_STAT_AREA 222 */ 223 struct mmu_stat_one { 224 uint64_t hit_ctx0[TTE4V_NPGSZ]; 225 uint64_t hit_ctxn0[TTE4V_NPGSZ]; 226 uint64_t tsb_miss; 227 uint64_t tlb_miss; /* miss, no TSB set */ 228 uint64_t map_ctx0[TTE4V_NPGSZ]; 229 uint64_t map_ctxn0[TTE4V_NPGSZ]; 230 }; 231 232 struct mmu_stat { 233 struct mmu_stat_one immu_stat; 234 struct mmu_stat_one dmmu_stat; 235 uint64_t set_ctx0; 236 uint64_t set_ctxn0; 237 }; 238 #endif /* SET_MMU_STATS */ 239 240 #endif /* ! _ASM */ 241 242 /* 243 * CPU States 244 */ 245 #define CPU_STATE_INVALID 0x0 246 #define CPU_STATE_STOPPED 0x1 /* cpu not started */ 247 #define CPU_STATE_RUNNING 0x2 /* cpu running guest code */ 248 #define CPU_STATE_ERROR 0x3 /* cpu is in the error state */ 249 #define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last valid state */ 250 251 /* 252 * MMU fault status area 253 */ 254 255 #define MMFSA_TYPE_ 0x00 /* fault type */ 256 #define MMFSA_ADDR_ 0x08 /* fault address */ 257 #define MMFSA_CTX_ 0x10 /* fault context */ 258 259 #define MMFSA_I_ 0x00 /* start of fields for I */ 260 #define MMFSA_I_TYPE (MMFSA_I_ + MMFSA_TYPE_) /* instruction fault type */ 261 #define MMFSA_I_ADDR (MMFSA_I_ + MMFSA_ADDR_) /* instruction fault address */ 262 #define MMFSA_I_CTX (MMFSA_I_ + MMFSA_CTX_) /* instruction fault context */ 263 264 #define MMFSA_D_ 0x40 /* start of fields for D */ 265 #define MMFSA_D_TYPE (MMFSA_D_ + MMFSA_TYPE_) /* data fault type */ 266 #define MMFSA_D_ADDR (MMFSA_D_ + MMFSA_ADDR_) /* data fault address */ 267 #define MMFSA_D_CTX (MMFSA_D_ + MMFSA_CTX_) /* data fault context */ 268 269 #define MMFSA_F_FMISS 1 /* fast miss */ 270 #define MMFSA_F_FPROT 2 /* fast protection */ 271 #define MMFSA_F_MISS 3 /* mmu miss */ 272 #define MMFSA_F_INVRA 4 /* invalid RA */ 273 #define MMFSA_F_PRIV 5 /* privilege violation */ 274 #define MMFSA_F_PROT 6 /* protection violation */ 275 #define MMFSA_F_NFO 7 /* NFO access */ 276 #define MMFSA_F_SOPG 8 /* so page */ 277 #define MMFSA_F_INVVA 9 /* invalid VA */ 278 #define MMFSA_F_INVASI 10 /* invalid ASI */ 279 #define MMFSA_F_NCATM 11 /* non-cacheable atomic */ 280 #define MMFSA_F_PRVACT 12 /* privileged action */ 281 #define MMFSA_F_WPT 13 /* watchpoint hit */ 282 #define MMFSA_F_UNALIGN 14 /* unaligned access */ 283 #define MMFSA_F_INVPGSZ 15 /* invalid page size */ 284 285 #define MMFSA_SIZE 0x80 /* in bytes, 64 byte aligned */ 286 287 /* 288 * MMU fault status - MMFSA_IFS and MMFSA_DFS 289 */ 290 #define MMFS_FV 0x00000001 291 #define MMFS_OW 0x00000002 292 #define MMFS_W 0x00000004 293 #define MMFS_PR 0x00000008 294 #define MMFS_CT 0x00000030 295 #define MMFS_E 0x00000040 296 #define MMFS_FT 0x00003f80 297 #define MMFS_ME 0x00004000 298 #define MMFS_TM 0x00008000 299 #define MMFS_ASI 0x00ff0000 300 #define MMFS_NF 0x01000000 301 302 /* 303 * DMA sync parameter definitions 304 */ 305 #define HVIO_DMA_SYNC_DIR_TO_DEV 0x01 306 #define HVIO_DMA_SYNC_DIR_FROM_DEV 0x02 307 308 /* 309 * LDC Channel States 310 */ 311 #define LDC_CHANNEL_DOWN 0x0 312 #define LDC_CHANNEL_UP 0x1 313 #define LDC_CHANNEL_RESET 0x2 314 315 #ifndef _ASM 316 317 extern uint64_t hv_mmu_map_perm_addr(void *, int, uint64_t, int); 318 extern uint64_t hv_mmu_unmap_perm_addr(void *, int, int); 319 extern uint64_t hv_mach_exit(uint64_t exit_code); 320 extern uint64_t hv_mach_sir(void); 321 322 extern uint64_t hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, 323 uint64_t arg); 324 extern uint64_t hv_cpu_stop(uint64_t cpuid); 325 extern uint64_t hv_cpu_set_rtba(uint64_t *rtba); 326 327 extern uint64_t hv_set_ctx0(uint64_t, uint64_t); 328 extern uint64_t hv_set_ctxnon0(uint64_t, uint64_t); 329 extern uint64_t hv_mmu_fault_area_conf(void *raddr); 330 #ifdef SET_MMU_STATS 331 extern uint64_t hv_mmu_set_stat_area(uint64_t, uint64_t); 332 #endif /* SET_MMU_STATS */ 333 334 extern uint64_t hv_cpu_qconf(int queue, uint64_t paddr, int size); 335 extern uint64_t hv_cpu_yield(void); 336 extern uint64_t hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 337 extern uint64_t hv_mem_scrub(uint64_t real_addr, uint64_t length, 338 uint64_t *scrubbed_len); 339 extern uint64_t hv_mem_sync(uint64_t real_addr, uint64_t length, 340 uint64_t *flushed_len); 341 342 extern uint64_t hv_service_recv(uint64_t s_id, uint64_t buf_pa, 343 uint64_t size, uint64_t *recv_bytes); 344 extern uint64_t hv_service_send(uint64_t s_id, uint64_t buf_pa, 345 uint64_t size, uint64_t *send_bytes); 346 extern uint64_t hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 347 extern uint64_t hv_service_setstatus(uint64_t s_id, uint64_t bits); 348 extern uint64_t hv_service_clrstatus(uint64_t s_id, uint64_t bits); 349 extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep); 350 351 extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *); 352 extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *); 353 extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *); 354 extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *); 355 extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *); 356 extern uint64_t hv_mach_set_watchdog(uint64_t, uint64_t *); 357 358 extern int64_t hv_cnputchar(uint8_t); 359 extern int64_t hv_cngetchar(uint8_t *); 360 361 extern uint64_t hv_tod_get(uint64_t *seconds); 362 extern uint64_t hv_tod_set(uint64_t); 363 364 extern uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, 365 uint64_t *sysino); 366 extern uint64_t hvio_intr_getvalid(uint64_t sysino, 367 int *intr_valid_state); 368 extern uint64_t hvio_intr_setvalid(uint64_t sysino, 369 int intr_valid_state); 370 extern uint64_t hvio_intr_getstate(uint64_t sysino, 371 int *intr_state); 372 extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state); 373 extern uint64_t hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid); 374 extern uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid); 375 376 extern uint64_t hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 377 uint64_t nentries); 378 extern uint64_t hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 379 uint64_t *nentries); 380 extern uint64_t hv_ldc_tx_get_state(uint64_t channel, uint64_t *headp, 381 uint64_t *tailp, uint64_t *state); 382 extern uint64_t hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail); 383 extern uint64_t hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 384 uint64_t nentries); 385 extern uint64_t hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 386 uint64_t *nentries); 387 extern uint64_t hv_ldc_rx_get_state(uint64_t channel, uint64_t *headp, 388 uint64_t *tailp, uint64_t *state); 389 extern uint64_t hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head); 390 391 extern uint64_t hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 392 uint64_t tbl_entries); 393 extern uint64_t hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 394 uint64_t *tbl_entries); 395 extern uint64_t hv_ldc_copy(uint64_t channel, uint64_t request, 396 uint64_t cookie, uint64_t raddr, uint64_t length, uint64_t *lengthp); 397 extern uint64_t hv_ldc_mapin(uint64_t channel, uint64_t cookie, 398 uint64_t *raddr, uint64_t *perm); 399 extern uint64_t hv_ldc_unmap(uint64_t raddr); 400 extern uint64_t hv_ldc_revoke(uint64_t raddr); 401 extern uint64_t hv_api_get_version(uint64_t api_group, uint64_t *majorp, 402 uint64_t *minorp); 403 extern uint64_t hv_api_set_version(uint64_t api_group, uint64_t major, 404 uint64_t minor, uint64_t *supported_minor); 405 406 extern uint64_t hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 407 uint64_t *cookie); 408 extern uint64_t hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 409 uint64_t cookie); 410 extern uint64_t hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 411 int *intr_valid_state); 412 extern uint64_t hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 413 int intr_valid_state); 414 extern uint64_t hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 415 int *intr_state); 416 extern uint64_t hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 417 int intr_state); 418 extern uint64_t hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 419 uint32_t *cpuid); 420 extern uint64_t hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 421 uint32_t cpuid); 422 423 #endif /* ! _ASM */ 424 425 426 #ifdef __cplusplus 427 } 428 #endif 429 430 #endif /* _SYS_HYPERVISOR_API_H */ 431