1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_HYPERVISOR_API_H 28 #define _SYS_HYPERVISOR_API_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * sun4v Hypervisor API 34 * 35 * Reference: api.pdf Revision 0.12 dated May 12, 2004. 36 * io-api.txt version 1.11 dated 10/19/2004 37 */ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 44 * Trap types 45 */ 46 #define FAST_TRAP 0x80 /* Function # in %o5 */ 47 #define CPU_TICK_NPT 0x81 48 #define CPU_STICK_NPT 0x82 49 #define MMU_MAP_ADDR 0x83 50 #define MMU_UNMAP_ADDR 0x84 51 52 #define CORE_TRAP 0xff 53 54 /* 55 * Error returns in %o0. 56 * (Additional result is returned in %o1.) 57 */ 58 #define H_EOK 0 /* Successful return */ 59 #define H_ENOCPU 1 /* Invalid CPU id */ 60 #define H_ENORADDR 2 /* Invalid real address */ 61 #define H_ENOINTR 3 /* Invalid interrupt id */ 62 #define H_EBADPGSZ 4 /* Invalid pagesize encoding */ 63 #define H_EBADTSB 5 /* Invalid TSB description */ 64 #define H_EINVAL 6 /* Invalid argument */ 65 #define H_EBADTRAP 7 /* Invalid function number */ 66 #define H_EBADALIGN 8 /* Invalid address alignment */ 67 #define H_EWOULDBLOCK 9 /* Cannot complete operation */ 68 /* without blocking */ 69 #define H_ENOACCESS 10 /* No access to resource */ 70 #define H_EIO 11 /* I/O error */ 71 #define H_ECPUERROR 12 /* CPU is in error state */ 72 #define H_ENOTSUPPORTED 13 /* Function not supported */ 73 #define H_ENOMAP 14 /* Mapping is not valid, */ 74 /* no translation exists */ 75 #define H_EBUSY 17 /* Resource busy */ 76 #define H_ETOOMANY 15 /* Hard resource limit exceeded */ 77 #define H_ECHANNEL 16 /* Illegal LDC channel */ 78 79 #define H_BREAK -1 /* Console Break */ 80 #define H_HUP -2 /* Console Break */ 81 82 /* 83 * Mondo CPU ID argument processing. 84 */ 85 #define HV_SEND_MONDO_ENTRYDONE 0xffff 86 87 /* 88 * Function numbers for FAST_TRAP. 89 */ 90 #define HV_MACH_EXIT 0x00 91 #define HV_MACH_DESC 0x01 92 #define HV_MACH_SIR 0x02 93 #define MACH_SET_WATCHDOG 0x05 94 95 #define HV_CPU_START 0x10 96 #define HV_CPU_STOP 0x11 97 #define HV_CPU_YIELD 0x12 98 #define HV_CPU_QCONF 0x14 99 #define HV_CPU_STATE 0x17 100 #define HV_CPU_SET_RTBA 0x18 101 102 #define MMU_TSB_CTX0 0x20 103 #define MMU_TSB_CTXNON0 0x21 104 #define MMU_DEMAP_PAGE 0x22 105 #define MMU_DEMAP_CTX 0x23 106 #define MMU_DEMAP_ALL 0x24 107 #define MAP_PERM_ADDR 0x25 108 #define MMU_SET_INFOPTR 0x26 109 #define MMU_ENABLE 0x27 110 #define UNMAP_PERM_ADDR 0x28 111 112 #define HV_MEM_SCRUB 0x31 113 #define HV_MEM_SYNC 0x32 114 115 #define HV_INTR_SEND 0x42 116 117 #define TOD_GET 0x50 118 #define TOD_SET 0x51 119 120 #define CONS_GETCHAR 0x60 121 #define CONS_PUTCHAR 0x61 122 #define CONS_READ 0x62 123 #define CONS_WRITE 0x63 124 125 #define SOFT_STATE_SET 0x70 126 #define SOFT_STATE_GET 0x71 127 128 #define TTRACE_BUF_CONF 0x90 129 #define TTRACE_BUF_INFO 0x91 130 #define TTRACE_ENABLE 0x92 131 #define TTRACE_FREEZE 0x93 132 #define DUMP_BUF_UPDATE 0x94 133 134 #define HVIO_INTR_DEVINO2SYSINO 0xa0 135 #define HVIO_INTR_GETVALID 0xa1 136 #define HVIO_INTR_SETVALID 0xa2 137 #define HVIO_INTR_GETSTATE 0xa3 138 #define HVIO_INTR_SETSTATE 0xa4 139 #define HVIO_INTR_GETTARGET 0xa5 140 #define HVIO_INTR_SETTARGET 0xa6 141 142 #define VINTR_GET_COOKIE 0xa7 143 #define VINTR_SET_COOKIE 0xa8 144 #define VINTR_GET_VALID 0xa9 145 #define VINTR_SET_VALID 0xaa 146 #define VINTR_GET_STATE 0xab 147 #define VINTR_SET_STATE 0xac 148 #define VINTR_GET_TARGET 0xad 149 #define VINTR_SET_TARGET 0xae 150 151 #define LDC_TX_QCONF 0xe0 152 #define LDC_TX_QINFO 0xe1 153 #define LDC_TX_GET_STATE 0xe2 154 #define LDC_TX_SET_QTAIL 0xe3 155 #define LDC_RX_QCONF 0xe4 156 #define LDC_RX_QINFO 0xe5 157 #define LDC_RX_GET_STATE 0xe6 158 #define LDC_RX_SET_QHEAD 0xe7 159 160 #define LDC_SET_MAP_TABLE 0xea 161 #define LDC_GET_MAP_TABLE 0xeb 162 #define LDC_COPY 0xec 163 #define LDC_MAPIN 0xed 164 #define LDC_UNMAP 0xee 165 #define LDC_REVOKE 0xef 166 167 #ifdef SET_MMU_STATS 168 #define MMU_STAT_AREA 0xfc 169 #endif /* SET_MMU_STATS */ 170 171 #define HV_RA2PA 0x200 172 #define HV_HPRIV 0x201 173 174 /* 175 * Function numbers for CORE_TRAP. 176 */ 177 #define API_SET_VERSION 0x00 178 #define API_PUT_CHAR 0x01 179 #define API_EXIT 0x02 180 #define API_GET_VERSION 0x03 181 182 183 /* 184 * Definitions for MACH_SOFT_STATE routines 185 */ 186 187 #define SIS_NORMAL 0x01 188 #define SIS_TRANSITION 0x02 189 190 /* 191 * Bits for MMU functions flags argument: 192 * arg3 of MMU_MAP_ADDR 193 * arg3 of MMU_DEMAP_CTX 194 * arg2 of MMU_DEMAP_ALL 195 */ 196 #define MAP_DTLB 0x1 197 #define MAP_ITLB 0x2 198 199 200 /* 201 * Interrupt state manipulation definitions. 202 */ 203 204 #define HV_INTR_IDLE_STATE 0 205 #define HV_INTR_RECEIVED_STATE 1 206 #define HV_INTR_DELIVERED_STATE 2 207 208 #define HV_INTR_NOTVALID 0 209 #define HV_INTR_VALID 1 210 211 #ifndef _ASM 212 213 /* 214 * TSB description structure for MMU_TSB_CTX0 and MMU_TSB_CTXNON0. 215 */ 216 typedef struct hv_tsb_info { 217 uint16_t hvtsb_idxpgsz; /* page size used to index TSB */ 218 uint16_t hvtsb_assoc; /* TSB associativity */ 219 uint32_t hvtsb_ntte; /* TSB size (#TTE entries) */ 220 uint32_t hvtsb_ctx_index; /* context reg index */ 221 uint32_t hvtsb_pgszs; /* sizes in use */ 222 uint64_t hvtsb_pa; /* real address of TSB base */ 223 uint64_t hvtsb_rsvd; /* reserved */ 224 } hv_tsb_info_t; 225 226 #define HVTSB_SHARE_INDEX ((uint32_t)-1) 227 228 #ifdef SET_MMU_STATS 229 #ifndef TTE4V_NPGSZ 230 #define TTE4V_NPGSZ 8 231 #endif /* TTE4V_NPGSZ */ 232 /* 233 * MMU statistics structure for MMU_STAT_AREA 234 */ 235 struct mmu_stat_one { 236 uint64_t hit_ctx0[TTE4V_NPGSZ]; 237 uint64_t hit_ctxn0[TTE4V_NPGSZ]; 238 uint64_t tsb_miss; 239 uint64_t tlb_miss; /* miss, no TSB set */ 240 uint64_t map_ctx0[TTE4V_NPGSZ]; 241 uint64_t map_ctxn0[TTE4V_NPGSZ]; 242 }; 243 244 struct mmu_stat { 245 struct mmu_stat_one immu_stat; 246 struct mmu_stat_one dmmu_stat; 247 uint64_t set_ctx0; 248 uint64_t set_ctxn0; 249 }; 250 #endif /* SET_MMU_STATS */ 251 252 #endif /* ! _ASM */ 253 254 /* 255 * CPU States 256 */ 257 #define CPU_STATE_INVALID 0x0 258 #define CPU_STATE_STOPPED 0x1 /* cpu not started */ 259 #define CPU_STATE_RUNNING 0x2 /* cpu running guest code */ 260 #define CPU_STATE_ERROR 0x3 /* cpu is in the error state */ 261 #define CPU_STATE_LAST_PUBLIC CPU_STATE_ERROR /* last valid state */ 262 263 /* 264 * MMU fault status area 265 */ 266 267 #define MMFSA_TYPE_ 0x00 /* fault type */ 268 #define MMFSA_ADDR_ 0x08 /* fault address */ 269 #define MMFSA_CTX_ 0x10 /* fault context */ 270 271 #define MMFSA_I_ 0x00 /* start of fields for I */ 272 #define MMFSA_I_TYPE (MMFSA_I_ + MMFSA_TYPE_) /* instruction fault type */ 273 #define MMFSA_I_ADDR (MMFSA_I_ + MMFSA_ADDR_) /* instruction fault address */ 274 #define MMFSA_I_CTX (MMFSA_I_ + MMFSA_CTX_) /* instruction fault context */ 275 276 #define MMFSA_D_ 0x40 /* start of fields for D */ 277 #define MMFSA_D_TYPE (MMFSA_D_ + MMFSA_TYPE_) /* data fault type */ 278 #define MMFSA_D_ADDR (MMFSA_D_ + MMFSA_ADDR_) /* data fault address */ 279 #define MMFSA_D_CTX (MMFSA_D_ + MMFSA_CTX_) /* data fault context */ 280 281 #define MMFSA_F_FMISS 1 /* fast miss */ 282 #define MMFSA_F_FPROT 2 /* fast protection */ 283 #define MMFSA_F_MISS 3 /* mmu miss */ 284 #define MMFSA_F_INVRA 4 /* invalid RA */ 285 #define MMFSA_F_PRIV 5 /* privilege violation */ 286 #define MMFSA_F_PROT 6 /* protection violation */ 287 #define MMFSA_F_NFO 7 /* NFO access */ 288 #define MMFSA_F_SOPG 8 /* so page */ 289 #define MMFSA_F_INVVA 9 /* invalid VA */ 290 #define MMFSA_F_INVASI 10 /* invalid ASI */ 291 #define MMFSA_F_NCATM 11 /* non-cacheable atomic */ 292 #define MMFSA_F_PRVACT 12 /* privileged action */ 293 #define MMFSA_F_WPT 13 /* watchpoint hit */ 294 #define MMFSA_F_UNALIGN 14 /* unaligned access */ 295 #define MMFSA_F_INVPGSZ 15 /* invalid page size */ 296 297 #define MMFSA_SIZE 0x80 /* in bytes, 64 byte aligned */ 298 299 /* 300 * MMU fault status - MMFSA_IFS and MMFSA_DFS 301 */ 302 #define MMFS_FV 0x00000001 303 #define MMFS_OW 0x00000002 304 #define MMFS_W 0x00000004 305 #define MMFS_PR 0x00000008 306 #define MMFS_CT 0x00000030 307 #define MMFS_E 0x00000040 308 #define MMFS_FT 0x00003f80 309 #define MMFS_ME 0x00004000 310 #define MMFS_TM 0x00008000 311 #define MMFS_ASI 0x00ff0000 312 #define MMFS_NF 0x01000000 313 314 /* 315 * DMA sync parameter definitions 316 */ 317 #define HVIO_DMA_SYNC_DIR_TO_DEV 0x01 318 #define HVIO_DMA_SYNC_DIR_FROM_DEV 0x02 319 320 /* 321 * LDC Channel States 322 */ 323 #define LDC_CHANNEL_DOWN 0x0 324 #define LDC_CHANNEL_UP 0x1 325 #define LDC_CHANNEL_RESET 0x2 326 327 #ifndef _ASM 328 329 extern uint64_t hv_mmu_map_perm_addr(void *, int, uint64_t, int); 330 extern uint64_t hv_mmu_unmap_perm_addr(void *, int, int); 331 extern uint64_t hv_mach_exit(uint64_t exit_code); 332 extern uint64_t hv_mach_sir(void); 333 334 extern uint64_t hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, 335 uint64_t arg); 336 extern uint64_t hv_cpu_stop(uint64_t cpuid); 337 extern uint64_t hv_cpu_set_rtba(uint64_t *rtba); 338 339 extern uint64_t hv_set_ctx0(uint64_t, uint64_t); 340 extern uint64_t hv_set_ctxnon0(uint64_t, uint64_t); 341 extern uint64_t hv_mmu_fault_area_conf(void *raddr); 342 #ifdef SET_MMU_STATS 343 extern uint64_t hv_mmu_set_stat_area(uint64_t, uint64_t); 344 #endif /* SET_MMU_STATS */ 345 346 extern uint64_t hv_cpu_qconf(int queue, uint64_t paddr, int size); 347 extern uint64_t hv_cpu_yield(void); 348 extern uint64_t hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 349 extern uint64_t hv_mem_scrub(uint64_t real_addr, uint64_t length, 350 uint64_t *scrubbed_len); 351 extern uint64_t hv_mem_sync(uint64_t real_addr, uint64_t length, 352 uint64_t *flushed_len); 353 354 extern uint64_t hv_service_recv(uint64_t s_id, uint64_t buf_pa, 355 uint64_t size, uint64_t *recv_bytes); 356 extern uint64_t hv_service_send(uint64_t s_id, uint64_t buf_pa, 357 uint64_t size, uint64_t *send_bytes); 358 extern uint64_t hv_service_getstatus(uint64_t s_id, uint64_t *vreg); 359 extern uint64_t hv_service_setstatus(uint64_t s_id, uint64_t bits); 360 extern uint64_t hv_service_clrstatus(uint64_t s_id, uint64_t bits); 361 extern uint64_t hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep); 362 363 extern uint64_t hv_ttrace_buf_info(uint64_t *, uint64_t *); 364 extern uint64_t hv_ttrace_buf_conf(uint64_t, uint64_t, uint64_t *); 365 extern uint64_t hv_ttrace_enable(uint64_t, uint64_t *); 366 extern uint64_t hv_ttrace_freeze(uint64_t, uint64_t *); 367 extern uint64_t hv_dump_buf_update(uint64_t, uint64_t, uint64_t *); 368 extern uint64_t hv_mach_set_watchdog(uint64_t, uint64_t *); 369 370 extern int64_t hv_cnputchar(uint8_t); 371 extern int64_t hv_cngetchar(uint8_t *); 372 extern int64_t hv_cnwrite(uint64_t, uint64_t, uint64_t *); 373 extern int64_t hv_cnread(uint64_t, uint64_t, int64_t *); 374 375 extern uint64_t hv_tod_get(uint64_t *seconds); 376 extern uint64_t hv_tod_set(uint64_t); 377 378 extern uint64_t hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, 379 uint64_t *sysino); 380 extern uint64_t hvio_intr_getvalid(uint64_t sysino, 381 int *intr_valid_state); 382 extern uint64_t hvio_intr_setvalid(uint64_t sysino, 383 int intr_valid_state); 384 extern uint64_t hvio_intr_getstate(uint64_t sysino, 385 int *intr_state); 386 extern uint64_t hvio_intr_setstate(uint64_t sysino, int intr_state); 387 extern uint64_t hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid); 388 extern uint64_t hvio_intr_settarget(uint64_t sysino, uint32_t cpuid); 389 extern uint64_t hv_soft_state_set(uint64_t state, uint64_t string_ra); 390 extern uint64_t hv_soft_state_get(uint64_t string_ra, uint64_t *state); 391 392 extern uint64_t hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 393 uint64_t nentries); 394 extern uint64_t hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 395 uint64_t *nentries); 396 extern uint64_t hv_ldc_tx_get_state(uint64_t channel, uint64_t *headp, 397 uint64_t *tailp, uint64_t *state); 398 extern uint64_t hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail); 399 extern uint64_t hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 400 uint64_t nentries); 401 extern uint64_t hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 402 uint64_t *nentries); 403 extern uint64_t hv_ldc_rx_get_state(uint64_t channel, uint64_t *headp, 404 uint64_t *tailp, uint64_t *state); 405 extern uint64_t hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head); 406 407 extern uint64_t hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 408 uint64_t tbl_entries); 409 extern uint64_t hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 410 uint64_t *tbl_entries); 411 extern uint64_t hv_ldc_copy(uint64_t channel, uint64_t request, 412 uint64_t cookie, uint64_t raddr, uint64_t length, uint64_t *lengthp); 413 extern uint64_t hv_ldc_mapin(uint64_t channel, uint64_t cookie, 414 uint64_t *raddr, uint64_t *perm); 415 extern uint64_t hv_ldc_unmap(uint64_t raddr); 416 extern uint64_t hv_ldc_revoke(uint64_t channel, uint64_t cookie, 417 uint64_t revoke_cookie); 418 extern uint64_t hv_api_get_version(uint64_t api_group, uint64_t *majorp, 419 uint64_t *minorp); 420 extern uint64_t hv_api_set_version(uint64_t api_group, uint64_t major, 421 uint64_t minor, uint64_t *supported_minor); 422 423 extern uint64_t hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 424 uint64_t *cookie); 425 extern uint64_t hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 426 uint64_t cookie); 427 extern uint64_t hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 428 int *intr_valid_state); 429 extern uint64_t hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 430 int intr_valid_state); 431 extern uint64_t hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 432 int *intr_state); 433 extern uint64_t hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 434 int intr_state); 435 extern uint64_t hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 436 uint32_t *cpuid); 437 extern uint64_t hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 438 uint32_t cpuid); 439 440 #endif /* ! _ASM */ 441 442 443 #ifdef __cplusplus 444 } 445 #endif 446 447 #endif /* _SYS_HYPERVISOR_API_H */ 448