xref: /titanic_41/usr/src/uts/sun4v/os/mach_cpu_states.c (revision e4f5a11d4a234623168c1558fcdf4341e11769e1)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
23  */
24 
25 #include <sys/types.h>
26 #include <sys/systm.h>
27 #include <sys/archsystm.h>
28 #include <sys/t_lock.h>
29 #include <sys/uadmin.h>
30 #include <sys/panic.h>
31 #include <sys/reboot.h>
32 #include <sys/autoconf.h>
33 #include <sys/machsystm.h>
34 #include <sys/promif.h>
35 #include <sys/membar.h>
36 #include <vm/hat_sfmmu.h>
37 #include <sys/cpu_module.h>
38 #include <sys/cpu_sgnblk_defs.h>
39 #include <sys/intreg.h>
40 #include <sys/consdev.h>
41 #include <sys/kdi_impl.h>
42 #include <sys/traptrace.h>
43 #include <sys/hypervisor_api.h>
44 #include <sys/vmsystm.h>
45 #include <sys/dtrace.h>
46 #include <sys/xc_impl.h>
47 #include <sys/callb.h>
48 #include <sys/mdesc.h>
49 #include <sys/mach_descrip.h>
50 #include <sys/wdt.h>
51 #include <sys/soft_state.h>
52 #include <sys/promimpl.h>
53 #include <sys/hsvc.h>
54 #include <sys/ldoms.h>
55 #include <sys/kldc.h>
56 #include <sys/clock_impl.h>
57 #include <sys/suspend.h>
58 #include <sys/dumphdr.h>
59 
60 /*
61  * hvdump_buf_va is a pointer to the currently-configured hvdump_buf.
62  * A value of NULL indicates that this area is not configured.
63  * hvdump_buf_sz is tunable but will be clamped to HVDUMP_SIZE_MAX.
64  */
65 
66 caddr_t hvdump_buf_va;
67 uint64_t hvdump_buf_sz = HVDUMP_SIZE_DEFAULT;
68 static uint64_t hvdump_buf_pa;
69 
70 u_longlong_t panic_tick;
71 
72 extern u_longlong_t gettick();
73 static void reboot_machine(char *);
74 static void update_hvdump_buffer(void);
75 
76 /*
77  * For xt_sync synchronization.
78  */
79 extern uint64_t xc_tick_limit;
80 extern uint64_t xc_tick_jump_limit;
81 extern uint64_t xc_sync_tick_limit;
82 
83 /*
84  * Bring in the cpc PIL_15 handler for panic_enter_hw.
85  */
86 extern uint64_t	cpc_level15_inum;
87 
88 /*
89  * We keep our own copies, used for cache flushing, because we can be called
90  * before cpu_fiximpl().
91  */
92 static int kdi_dcache_size;
93 static int kdi_dcache_linesize;
94 static int kdi_icache_size;
95 static int kdi_icache_linesize;
96 
97 /*
98  * Assembly support for generic modules in sun4v/ml/mach_xc.s
99  */
100 extern void init_mondo_nocheck(xcfunc_t *func, uint64_t arg1, uint64_t arg2);
101 extern void kdi_flush_idcache(int, int, int, int);
102 extern uint64_t get_cpuaddr(uint64_t, uint64_t);
103 
104 
105 #define	BOOT_CMD_MAX_LEN	256	/* power of 2 & 16-byte aligned */
106 #define	BOOT_CMD_BASE		"boot "
107 
108 /*
109  * In an LDoms system we do not save the user's boot args in NVRAM
110  * as is done on legacy systems.  Instead, we format and send a
111  * 'reboot-command' variable to the variable service.  The contents
112  * of the variable are retrieved by OBP and used verbatim for
113  * the next boot.
114  */
115 static void
116 store_boot_cmd(char *args, boolean_t add_boot_str, boolean_t invoke_cb)
117 {
118 	static char	*cmd_buf;
119 	size_t		len = 1;
120 	pnode_t		node;
121 	size_t		base_len = 0;
122 	size_t		args_len;
123 	size_t		args_max;
124 	uint64_t	majornum;
125 	uint64_t	minornum;
126 	uint64_t	buf_pa;
127 	uint64_t	status;
128 
129 	status = hsvc_version(HSVC_GROUP_REBOOT_DATA, &majornum, &minornum);
130 
131 	/*
132 	 * invoke_cb is set to true when we are in a normal shutdown sequence
133 	 * (interrupts are not blocked, the system is not panicking or being
134 	 * suspended). In that case, we can use any method to store the boot
135 	 * command. Otherwise storing the boot command can not be done using
136 	 * a domain service because it can not be safely used in that context.
137 	 */
138 	if ((status != H_EOK) && (invoke_cb == B_FALSE))
139 		return;
140 
141 	cmd_buf = contig_mem_alloc(BOOT_CMD_MAX_LEN);
142 	if (cmd_buf == NULL)
143 		return;
144 
145 	if (add_boot_str) {
146 		(void) strcpy(cmd_buf, BOOT_CMD_BASE);
147 
148 		base_len = strlen(BOOT_CMD_BASE);
149 		len = base_len + 1;
150 	}
151 
152 	if (args != NULL) {
153 		args_len = strlen(args);
154 		args_max = BOOT_CMD_MAX_LEN - len;
155 
156 		if (args_len > args_max) {
157 			cmn_err(CE_WARN, "Reboot command too long (%ld), "
158 			    "truncating command arguments", len + args_len);
159 
160 			args_len = args_max;
161 		}
162 
163 		len += args_len;
164 		(void) strncpy(&cmd_buf[base_len], args, args_len);
165 	}
166 
167 	/*
168 	 * Save the reboot-command with HV, if reboot data group is
169 	 * negotiated. Else save the reboot-command via vars-config domain
170 	 * services on the SP.
171 	 */
172 	if (status == H_EOK) {
173 		buf_pa = va_to_pa(cmd_buf);
174 		status = hv_reboot_data_set(buf_pa, len);
175 		if (status != H_EOK) {
176 			cmn_err(CE_WARN, "Unable to store boot command for "
177 			    "use on reboot with HV: error = 0x%lx", status);
178 		}
179 	} else {
180 		node = prom_optionsnode();
181 		if ((node == OBP_NONODE) || (node == OBP_BADNODE) ||
182 		    prom_setprop(node, "reboot-command", cmd_buf, len) == -1)
183 			cmn_err(CE_WARN, "Unable to store boot command for "
184 			    "use on reboot");
185 	}
186 }
187 
188 
189 /*
190  * Machine dependent code to reboot.
191  *
192  * "bootstr", when non-null, points to a string to be used as the
193  * argument string when rebooting.
194  *
195  * "invoke_cb" is a boolean. It is set to true when mdboot() can safely
196  * invoke CB_CL_MDBOOT callbacks before shutting the system down, i.e. when
197  * we are in a normal shutdown sequence (interrupts are not blocked, the
198  * system is not panic'ing or being suspended).
199  */
200 /*ARGSUSED*/
201 void
202 mdboot(int cmd, int fcn, char *bootstr, boolean_t invoke_cb)
203 {
204 	extern void pm_cfb_check_and_powerup(void);
205 
206 	/*
207 	 * XXX - rconsvp is set to NULL to ensure that output messages
208 	 * are sent to the underlying "hardware" device using the
209 	 * monitor's printf routine since we are in the process of
210 	 * either rebooting or halting the machine.
211 	 */
212 	rconsvp = NULL;
213 
214 	switch (fcn) {
215 	case AD_HALT:
216 		/*
217 		 * LDoms: By storing a no-op command
218 		 * in the 'reboot-command' variable we cause OBP
219 		 * to ignore the setting of 'auto-boot?' after
220 		 * it completes the reset.  This causes the system
221 		 * to stop at the ok prompt.
222 		 */
223 		if (domaining_enabled())
224 			store_boot_cmd("noop", B_FALSE, invoke_cb);
225 		break;
226 
227 	case AD_POWEROFF:
228 		break;
229 
230 	default:
231 		if (bootstr == NULL) {
232 			switch (fcn) {
233 
234 			case AD_FASTREBOOT:
235 			case AD_BOOT:
236 				bootstr = "";
237 				break;
238 
239 			case AD_IBOOT:
240 				bootstr = "-a";
241 				break;
242 
243 			case AD_SBOOT:
244 				bootstr = "-s";
245 				break;
246 
247 			case AD_SIBOOT:
248 				bootstr = "-sa";
249 				break;
250 			default:
251 				cmn_err(CE_WARN,
252 				    "mdboot: invalid function %d", fcn);
253 				bootstr = "";
254 				break;
255 			}
256 		}
257 
258 		/*
259 		 * If LDoms is running, we must save the boot string
260 		 * before we enter restricted mode.  This is possible
261 		 * only if we are not being called from panic.
262 		 */
263 		if (domaining_enabled())
264 			store_boot_cmd(bootstr, B_TRUE, invoke_cb);
265 	}
266 
267 	/*
268 	 * At a high interrupt level we can't:
269 	 *	1) bring up the console
270 	 * or
271 	 *	2) wait for pending interrupts prior to redistribution
272 	 *	   to the current CPU
273 	 *
274 	 * so we do them now.
275 	 */
276 	pm_cfb_check_and_powerup();
277 
278 	/* make sure there are no more changes to the device tree */
279 	devtree_freeze();
280 
281 	if (invoke_cb)
282 		(void) callb_execute_class(CB_CL_MDBOOT, NULL);
283 
284 	/*
285 	 * Clear any unresolved UEs from memory.
286 	 */
287 	page_retire_mdboot();
288 
289 	/*
290 	 * stop other cpus which also raise our priority. since there is only
291 	 * one active cpu after this, and our priority will be too high
292 	 * for us to be preempted, we're essentially single threaded
293 	 * from here on out.
294 	 */
295 	stop_other_cpus();
296 
297 	/*
298 	 * try and reset leaf devices.  reset_leaves() should only
299 	 * be called when there are no other threads that could be
300 	 * accessing devices
301 	 */
302 	reset_leaves();
303 
304 	watchdog_clear();
305 
306 	if (fcn == AD_HALT) {
307 		mach_set_soft_state(SIS_TRANSITION,
308 		    &SOLARIS_SOFT_STATE_HALT_MSG);
309 		halt((char *)NULL);
310 	} else if (fcn == AD_POWEROFF) {
311 		mach_set_soft_state(SIS_TRANSITION,
312 		    &SOLARIS_SOFT_STATE_POWER_MSG);
313 		power_down(NULL);
314 	} else {
315 		mach_set_soft_state(SIS_TRANSITION,
316 		    &SOLARIS_SOFT_STATE_REBOOT_MSG);
317 		reboot_machine(bootstr);
318 	}
319 	/* MAYBE REACHED */
320 }
321 
322 /* mdpreboot - may be called prior to mdboot while root fs still mounted */
323 /*ARGSUSED*/
324 void
325 mdpreboot(int cmd, int fcn, char *bootstr)
326 {
327 }
328 
329 /*
330  * Halt the machine and then reboot with the device
331  * and arguments specified in bootstr.
332  */
333 static void
334 reboot_machine(char *bootstr)
335 {
336 	flush_windows();
337 	stop_other_cpus();		/* send stop signal to other CPUs */
338 	prom_printf("rebooting...\n");
339 	/*
340 	 * For platforms that use CPU signatures, we
341 	 * need to set the signature block to OS and
342 	 * the state to exiting for all the processors.
343 	 */
344 	CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_REBOOT, -1);
345 	prom_reboot(bootstr);
346 	/*NOTREACHED*/
347 }
348 
349 /*
350  * We use the x-trap mechanism and idle_stop_xcall() to stop the other CPUs.
351  * Once in panic_idle() they raise spl, record their location, and spin.
352  */
353 static void
354 panic_idle(void)
355 {
356 	(void) spl7();
357 
358 	debug_flush_windows();
359 	(void) setjmp(&curthread->t_pcb);
360 
361 	CPU->cpu_m.in_prom = 1;
362 	membar_stld();
363 
364 	dumpsys_helper();
365 
366 	for (;;)
367 		;
368 }
369 
370 /*
371  * Force the other CPUs to trap into panic_idle(), and then remove them
372  * from the cpu_ready_set so they will no longer receive cross-calls.
373  */
374 /*ARGSUSED*/
375 void
376 panic_stopcpus(cpu_t *cp, kthread_t *t, int spl)
377 {
378 	cpuset_t cps;
379 	int i;
380 
381 	(void) splzs();
382 	CPUSET_ALL_BUT(cps, cp->cpu_id);
383 	xt_some(cps, (xcfunc_t *)idle_stop_xcall, (uint64_t)&panic_idle, NULL);
384 
385 	for (i = 0; i < NCPU; i++) {
386 		if (i != cp->cpu_id && CPU_XCALL_READY(i)) {
387 			int ntries = 0x10000;
388 
389 			while (!cpu[i]->cpu_m.in_prom && ntries) {
390 				DELAY(50);
391 				ntries--;
392 			}
393 
394 			if (!cpu[i]->cpu_m.in_prom)
395 				printf("panic: failed to stop cpu%d\n", i);
396 
397 			cpu[i]->cpu_flags &= ~CPU_READY;
398 			cpu[i]->cpu_flags |= CPU_QUIESCED;
399 			CPUSET_DEL(cpu_ready_set, cpu[i]->cpu_id);
400 		}
401 	}
402 }
403 
404 /*
405  * Platform callback following each entry to panicsys().  If we've panicked at
406  * level 14, we examine t_panic_trap to see if a fatal trap occurred.  If so,
407  * we disable further %tick_cmpr interrupts.  If not, an explicit call to panic
408  * was made and so we re-enqueue an interrupt request structure to allow
409  * further level 14 interrupts to be processed once we lower PIL.  This allows
410  * us to handle panics from the deadman() CY_HIGH_LEVEL cyclic.
411  *
412  * In case we panic at level 15, ensure that the cpc handler has been
413  * reinstalled otherwise we could run the risk of hitting a missing interrupt
414  * handler when this thread drops PIL and the cpc counter overflows.
415  */
416 void
417 panic_enter_hw(int spl)
418 {
419 	uint_t opstate;
420 
421 	if (!panic_tick) {
422 		panic_tick = gettick();
423 		if (mach_htraptrace_enable) {
424 			uint64_t prev_freeze;
425 
426 			/*  there are no possible error codes for this hcall */
427 			(void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL,
428 			    &prev_freeze);
429 		}
430 #ifdef TRAPTRACE
431 		TRAPTRACE_FREEZE;
432 #endif
433 	}
434 
435 	mach_set_soft_state(SIS_TRANSITION, &SOLARIS_SOFT_STATE_PANIC_MSG);
436 
437 	if (spl == ipltospl(PIL_14)) {
438 		opstate = disable_vec_intr();
439 
440 		if (curthread->t_panic_trap != NULL) {
441 			tickcmpr_disable();
442 			intr_dequeue_req(PIL_14, cbe_level14_inum);
443 		} else {
444 			if (!tickcmpr_disabled())
445 				intr_enqueue_req(PIL_14, cbe_level14_inum);
446 			/*
447 			 * Clear SOFTINT<14>, SOFTINT<0> (TICK_INT)
448 			 * and SOFTINT<16> (STICK_INT) to indicate
449 			 * that the current level 14 has been serviced.
450 			 */
451 			wr_clr_softint((1 << PIL_14) |
452 			    TICK_INT_MASK | STICK_INT_MASK);
453 		}
454 
455 		enable_vec_intr(opstate);
456 	} else if (spl == ipltospl(PIL_15)) {
457 		opstate = disable_vec_intr();
458 		intr_enqueue_req(PIL_15, cpc_level15_inum);
459 		wr_clr_softint(1 << PIL_15);
460 		enable_vec_intr(opstate);
461 	}
462 }
463 
464 /*
465  * Miscellaneous hardware-specific code to execute after panicstr is set
466  * by the panic code: we also print and record PTL1 panic information here.
467  */
468 /*ARGSUSED*/
469 void
470 panic_quiesce_hw(panic_data_t *pdp)
471 {
472 	extern uint_t getpstate(void);
473 	extern void setpstate(uint_t);
474 
475 	/*
476 	 * Turn off TRAPTRACE and save the current %tick value in panic_tick.
477 	 */
478 	if (!panic_tick) {
479 		panic_tick = gettick();
480 		if (mach_htraptrace_enable) {
481 			uint64_t prev_freeze;
482 
483 			/*  there are no possible error codes for this hcall */
484 			(void) hv_ttrace_freeze((uint64_t)TRAP_TFREEZE_ALL,
485 			    &prev_freeze);
486 		}
487 #ifdef TRAPTRACE
488 		TRAPTRACE_FREEZE;
489 #endif
490 	}
491 	/*
492 	 * For Platforms that use CPU signatures, we
493 	 * need to set the signature block to OS, the state to
494 	 * exiting, and the substate to panic for all the processors.
495 	 */
496 	CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_PANIC, -1);
497 
498 	update_hvdump_buffer();
499 
500 	/*
501 	 * Disable further ECC errors from the bus nexus.
502 	 */
503 	(void) bus_func_invoke(BF_TYPE_ERRDIS);
504 
505 	/*
506 	 * Redirect all interrupts to the current CPU.
507 	 */
508 	intr_redist_all_cpus_shutdown();
509 
510 	/*
511 	 * This call exists solely to support dumps to network
512 	 * devices after sync from OBP.
513 	 *
514 	 * If we came here via the sync callback, then on some
515 	 * platforms, interrupts may have arrived while we were
516 	 * stopped in OBP.  OBP will arrange for those interrupts to
517 	 * be redelivered if you say "go", but not if you invoke a
518 	 * client callback like 'sync'.	 For some dump devices
519 	 * (network swap devices), we need interrupts to be
520 	 * delivered in order to dump, so we have to call the bus
521 	 * nexus driver to reset the interrupt state machines.
522 	 */
523 	(void) bus_func_invoke(BF_TYPE_RESINTR);
524 
525 	setpstate(getpstate() | PSTATE_IE);
526 }
527 
528 /*
529  * Platforms that use CPU signatures need to set the signature block to OS and
530  * the state to exiting for all CPUs. PANIC_CONT indicates that we're about to
531  * write the crash dump, which tells the SSP/SMS to begin a timeout routine to
532  * reboot the machine if the dump never completes.
533  */
534 /*ARGSUSED*/
535 void
536 panic_dump_hw(int spl)
537 {
538 	CPU_SIGNATURE(OS_SIG, SIGST_EXIT, SIGSUBST_DUMP, -1);
539 }
540 
541 /*
542  * for ptl1_panic
543  */
544 void
545 ptl1_init_cpu(struct cpu *cpu)
546 {
547 	ptl1_state_t *pstate = &cpu->cpu_m.ptl1_state;
548 
549 	/*CONSTCOND*/
550 	if (sizeof (struct cpu) + PTL1_SSIZE > CPU_ALLOC_SIZE) {
551 		panic("ptl1_init_cpu: not enough space left for ptl1_panic "
552 		    "stack, sizeof (struct cpu) = %lu",
553 		    (unsigned long)sizeof (struct cpu));
554 	}
555 
556 	pstate->ptl1_stktop = (uintptr_t)cpu + CPU_ALLOC_SIZE;
557 	cpu_pa[cpu->cpu_id] = va_to_pa(cpu);
558 }
559 
560 void
561 ptl1_panic_handler(ptl1_state_t *pstate)
562 {
563 	static const char *ptl1_reasons[] = {
564 #ifdef	PTL1_PANIC_DEBUG
565 		"trap for debug purpose",	/* PTL1_BAD_DEBUG */
566 #else
567 		"unknown trap",			/* PTL1_BAD_DEBUG */
568 #endif
569 		"register window trap",		/* PTL1_BAD_WTRAP */
570 		"kernel MMU miss",		/* PTL1_BAD_KMISS */
571 		"kernel protection fault",	/* PTL1_BAD_KPROT_FAULT */
572 		"ISM MMU miss",			/* PTL1_BAD_ISM */
573 		"kernel MMU trap",		/* PTL1_BAD_MMUTRAP */
574 		"kernel trap handler state",	/* PTL1_BAD_TRAP */
575 		"floating point trap",		/* PTL1_BAD_FPTRAP */
576 #ifdef	DEBUG
577 		"pointer to intr_vec",		/* PTL1_BAD_INTR_VEC */
578 #else
579 		"unknown trap",			/* PTL1_BAD_INTR_VEC */
580 #endif
581 #ifdef	TRAPTRACE
582 		"TRACE_PTR state",		/* PTL1_BAD_TRACE_PTR */
583 #else
584 		"unknown trap",			/* PTL1_BAD_TRACE_PTR */
585 #endif
586 		"stack overflow",		/* PTL1_BAD_STACK */
587 		"DTrace flags",			/* PTL1_BAD_DTRACE_FLAGS */
588 		"attempt to steal locked ctx",  /* PTL1_BAD_CTX_STEAL */
589 		"CPU ECC error loop",		/* PTL1_BAD_ECC */
590 		"unexpected error from hypervisor call", /* PTL1_BAD_HCALL */
591 		"unexpected global level(%gl)", /* PTL1_BAD_GL */
592 		"Watchdog Reset", 		/* PTL1_BAD_WATCHDOG */
593 		"unexpected RED mode trap", 	/* PTL1_BAD_RED */
594 		"return value EINVAL from hcall: "\
595 		    "UNMAP_PERM_ADDR",	/* PTL1_BAD_HCALL_UNMAP_PERM_EINVAL */
596 		"return value ENOMAP from hcall: "\
597 		    "UNMAP_PERM_ADDR", /* PTL1_BAD_HCALL_UNMAP_PERM_ENOMAP */
598 		"error raising a TSB exception", /* PTL1_BAD_RAISE_TSBEXCP */
599 		"missing shared TSB"	/* PTL1_NO_SCDTSB8K */
600 	};
601 
602 	uint_t reason = pstate->ptl1_regs.ptl1_gregs[0].ptl1_g1;
603 	uint_t tl = pstate->ptl1_regs.ptl1_trap_regs[0].ptl1_tl;
604 	struct panic_trap_info ti = { 0 };
605 
606 	/*
607 	 * Use trap_info for a place holder to call panic_savetrap() and
608 	 * panic_showtrap() to save and print out ptl1_panic information.
609 	 */
610 	if (curthread->t_panic_trap == NULL)
611 		curthread->t_panic_trap = &ti;
612 
613 	if (reason < sizeof (ptl1_reasons) / sizeof (ptl1_reasons[0]))
614 		panic("bad %s at TL %u", ptl1_reasons[reason], tl);
615 	else
616 		panic("ptl1_panic reason 0x%x at TL %u", reason, tl);
617 }
618 
619 void
620 clear_watchdog_on_exit(void)
621 {
622 	if (watchdog_enabled && watchdog_activated) {
623 		prom_printf("Debugging requested; hardware watchdog "
624 		    "suspended.\n");
625 		(void) watchdog_suspend();
626 	}
627 }
628 
629 /*
630  * Restore the watchdog timer when returning from a debugger
631  * after a panic or L1-A and resume watchdog pat.
632  */
633 void
634 restore_watchdog_on_entry()
635 {
636 	watchdog_resume();
637 }
638 
639 int
640 kdi_watchdog_disable(void)
641 {
642 	watchdog_suspend();
643 
644 	return (0);
645 }
646 
647 void
648 kdi_watchdog_restore(void)
649 {
650 	watchdog_resume();
651 }
652 
653 void
654 mach_dump_buffer_init(void)
655 {
656 	uint64_t  ret, minsize = 0;
657 
658 	if (hvdump_buf_sz > HVDUMP_SIZE_MAX)
659 		hvdump_buf_sz = HVDUMP_SIZE_MAX;
660 
661 	hvdump_buf_va = contig_mem_alloc_align(hvdump_buf_sz, PAGESIZE);
662 	if (hvdump_buf_va == NULL)
663 		return;
664 
665 	hvdump_buf_pa = va_to_pa(hvdump_buf_va);
666 
667 	ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz,
668 	    &minsize);
669 
670 	if (ret != H_EOK) {
671 		contig_mem_free(hvdump_buf_va, hvdump_buf_sz);
672 		hvdump_buf_va = NULL;
673 		cmn_err(CE_NOTE, "!Error in setting up hvstate"
674 		    "dump buffer. Error = 0x%lx, size = 0x%lx,"
675 		    "buf_pa = 0x%lx", ret, hvdump_buf_sz,
676 		    hvdump_buf_pa);
677 
678 		if (ret == H_EINVAL) {
679 			cmn_err(CE_NOTE, "!Buffer size too small."
680 			    "Available buffer size = 0x%lx,"
681 			    "Minimum buffer size required = 0x%lx",
682 			    hvdump_buf_sz, minsize);
683 		}
684 	}
685 }
686 
687 
688 static void
689 update_hvdump_buffer(void)
690 {
691 	uint64_t ret, dummy_val;
692 
693 	if (hvdump_buf_va == NULL)
694 		return;
695 
696 	ret = hv_dump_buf_update(hvdump_buf_pa, hvdump_buf_sz,
697 	    &dummy_val);
698 	if (ret != H_EOK) {
699 		cmn_err(CE_NOTE, "!Cannot update hvstate dump"
700 		    "buffer. Error = 0x%lx", ret);
701 	}
702 }
703 
704 
705 static int
706 getintprop(pnode_t node, char *name, int deflt)
707 {
708 	int	value;
709 
710 	switch (prom_getproplen(node, name)) {
711 	case 0:
712 		value = 1;	/* boolean properties */
713 		break;
714 
715 	case sizeof (int):
716 		(void) prom_getprop(node, name, (caddr_t)&value);
717 		break;
718 
719 	default:
720 		value = deflt;
721 		break;
722 	}
723 
724 	return (value);
725 }
726 
727 /*
728  * Called by setcpudelay
729  */
730 void
731 cpu_init_tick_freq(void)
732 {
733 	md_t *mdp;
734 	mde_cookie_t rootnode;
735 	int		listsz;
736 	mde_cookie_t	*listp = NULL;
737 	int	num_nodes;
738 	uint64_t stick_prop;
739 
740 	if (broken_md_flag) {
741 		sys_tick_freq = cpunodes[CPU->cpu_id].clock_freq;
742 		return;
743 	}
744 
745 	if ((mdp = md_get_handle()) == NULL)
746 		panic("stick_frequency property not found in MD");
747 
748 	rootnode = md_root_node(mdp);
749 	ASSERT(rootnode != MDE_INVAL_ELEM_COOKIE);
750 
751 	num_nodes = md_node_count(mdp);
752 
753 	ASSERT(num_nodes > 0);
754 	listsz = num_nodes * sizeof (mde_cookie_t);
755 	listp = (mde_cookie_t *)prom_alloc((caddr_t)0, listsz, 0);
756 
757 	if (listp == NULL)
758 		panic("cannot allocate list for MD properties");
759 
760 	num_nodes = md_scan_dag(mdp, rootnode, md_find_name(mdp, "platform"),
761 	    md_find_name(mdp, "fwd"), listp);
762 
763 	ASSERT(num_nodes == 1);
764 
765 	if (md_get_prop_val(mdp, *listp, "stick-frequency", &stick_prop) != 0)
766 		panic("stick_frequency property not found in MD");
767 
768 	sys_tick_freq = stick_prop;
769 
770 	prom_free((caddr_t)listp, listsz);
771 	(void) md_fini_handle(mdp);
772 }
773 
774 int shipit(int n, uint64_t cpu_list_ra);
775 
776 #ifdef DEBUG
777 #define	SEND_MONDO_STATS	1
778 #endif
779 
780 #ifdef SEND_MONDO_STATS
781 uint32_t x_one_stimes[64];
782 uint32_t x_one_ltimes[16];
783 uint32_t x_set_stimes[64];
784 uint32_t x_set_ltimes[16];
785 uint32_t x_set_cpus[NCPU];
786 #endif
787 
788 void
789 send_one_mondo(int cpuid)
790 {
791 	int retries, stat;
792 	uint64_t starttick, endtick, tick, lasttick;
793 	struct machcpu	*mcpup = &(CPU->cpu_m);
794 
795 	CPU_STATS_ADDQ(CPU, sys, xcalls, 1);
796 	starttick = lasttick = gettick();
797 	mcpup->cpu_list[0] = (uint16_t)cpuid;
798 	stat = shipit(1, mcpup->cpu_list_ra);
799 	endtick = starttick + xc_tick_limit;
800 	retries = 0;
801 	while (stat != H_EOK) {
802 		if (stat != H_EWOULDBLOCK) {
803 			if (panic_quiesce)
804 				return;
805 			if (stat == H_ECPUERROR)
806 				cmn_err(CE_PANIC, "send_one_mondo: "
807 				    "cpuid: 0x%x has been marked in "
808 				    "error", cpuid);
809 			else
810 				cmn_err(CE_PANIC, "send_one_mondo: "
811 				    "unexpected hypervisor error 0x%x "
812 				    "while sending a mondo to cpuid: "
813 				    "0x%x", stat, cpuid);
814 		}
815 		tick = gettick();
816 		/*
817 		 * If there is a big jump between the current tick
818 		 * count and lasttick, we have probably hit a break
819 		 * point.  Adjust endtick accordingly to avoid panic.
820 		 */
821 		if (tick > (lasttick + xc_tick_jump_limit))
822 			endtick += (tick - lasttick);
823 		lasttick = tick;
824 		if (tick > endtick) {
825 			if (panic_quiesce)
826 				return;
827 			cmn_err(CE_PANIC, "send mondo timeout "
828 			    "(target 0x%x) [retries: 0x%x hvstat: 0x%x]",
829 			    cpuid, retries, stat);
830 		}
831 		drv_usecwait(1);
832 		stat = shipit(1, mcpup->cpu_list_ra);
833 		retries++;
834 	}
835 #ifdef SEND_MONDO_STATS
836 	{
837 		uint64_t n = gettick() - starttick;
838 		if (n < 8192)
839 			x_one_stimes[n >> 7]++;
840 		else if (n < 15*8192)
841 			x_one_ltimes[n >> 13]++;
842 		else
843 			x_one_ltimes[0xf]++;
844 	}
845 #endif
846 }
847 
848 void
849 send_mondo_set(cpuset_t set)
850 {
851 	uint64_t starttick, endtick, tick, lasttick;
852 	uint_t largestid, smallestid;
853 	int i, j;
854 	int ncpuids = 0;
855 	int shipped = 0;
856 	int retries = 0;
857 	struct machcpu	*mcpup = &(CPU->cpu_m);
858 
859 	ASSERT(!CPUSET_ISNULL(set));
860 	CPUSET_BOUNDS(set, smallestid, largestid);
861 	if (smallestid == CPUSET_NOTINSET) {
862 		return;
863 	}
864 
865 	starttick = lasttick = gettick();
866 	endtick = starttick + xc_tick_limit;
867 
868 	/*
869 	 * Assemble CPU list for HV argument. We already know
870 	 * smallestid and largestid are members of set.
871 	 */
872 	mcpup->cpu_list[ncpuids++] = (uint16_t)smallestid;
873 	if (largestid != smallestid) {
874 		for (i = smallestid+1; i <= largestid-1; i++) {
875 			if (CPU_IN_SET(set, i)) {
876 				mcpup->cpu_list[ncpuids++] = (uint16_t)i;
877 			}
878 		}
879 		mcpup->cpu_list[ncpuids++] = (uint16_t)largestid;
880 	}
881 
882 	do {
883 		int stat;
884 
885 		stat = shipit(ncpuids, mcpup->cpu_list_ra);
886 		if (stat == H_EOK) {
887 			shipped += ncpuids;
888 			break;
889 		}
890 
891 		/*
892 		 * Either not all CPU mondos were sent, or an
893 		 * error occurred. CPUs that were sent mondos
894 		 * have their CPU IDs overwritten in cpu_list.
895 		 * Reset cpu_list so that it only holds those
896 		 * CPU IDs that still need to be sent.
897 		 */
898 		for (i = 0, j = 0; i < ncpuids; i++) {
899 			if (mcpup->cpu_list[i] == HV_SEND_MONDO_ENTRYDONE) {
900 				shipped++;
901 			} else {
902 				mcpup->cpu_list[j++] = mcpup->cpu_list[i];
903 			}
904 		}
905 		ncpuids = j;
906 
907 		/*
908 		 * Now handle possible errors returned
909 		 * from hypervisor.
910 		 */
911 		if (stat == H_ECPUERROR) {
912 			int errorcpus;
913 
914 			if (!panic_quiesce)
915 				cmn_err(CE_CONT, "send_mondo_set: cpuid(s) ");
916 
917 			/*
918 			 * Remove any CPUs in the error state from
919 			 * cpu_list. At this point cpu_list only
920 			 * contains the CPU IDs for mondos not
921 			 * succesfully sent.
922 			 */
923 			for (i = 0, errorcpus = 0; i < ncpuids; i++) {
924 				uint64_t state = CPU_STATE_INVALID;
925 				uint16_t id = mcpup->cpu_list[i];
926 
927 				(void) hv_cpu_state(id, &state);
928 				if (state == CPU_STATE_ERROR) {
929 					if (!panic_quiesce)
930 						cmn_err(CE_CONT, "0x%x ", id);
931 					errorcpus++;
932 				} else if (errorcpus > 0) {
933 					mcpup->cpu_list[i - errorcpus] =
934 					    mcpup->cpu_list[i];
935 				}
936 			}
937 			ncpuids -= errorcpus;
938 
939 			if (!panic_quiesce) {
940 				if (errorcpus == 0) {
941 					cmn_err(CE_CONT, "<none> have been "
942 					    "marked in error\n");
943 					cmn_err(CE_PANIC, "send_mondo_set: "
944 					    "hypervisor returned "
945 					    "H_ECPUERROR but no CPU in "
946 					    "cpu_list in error state");
947 				} else {
948 					cmn_err(CE_CONT, "have been marked in "
949 					    "error\n");
950 					cmn_err(CE_PANIC, "send_mondo_set: "
951 					    "CPU(s) in error state");
952 				}
953 			}
954 		} else if (stat != H_EWOULDBLOCK) {
955 			if (panic_quiesce)
956 				return;
957 			/*
958 			 * For all other errors, panic.
959 			 */
960 			cmn_err(CE_CONT, "send_mondo_set: unexpected "
961 			    "hypervisor error 0x%x while sending a "
962 			    "mondo to cpuid(s):", stat);
963 			for (i = 0; i < ncpuids; i++) {
964 				cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]);
965 			}
966 			cmn_err(CE_CONT, "\n");
967 			cmn_err(CE_PANIC, "send_mondo_set: unexpected "
968 			    "hypervisor error");
969 		}
970 
971 		tick = gettick();
972 		/*
973 		 * If there is a big jump between the current tick
974 		 * count and lasttick, we have probably hit a break
975 		 * point.  Adjust endtick accordingly to avoid panic.
976 		 */
977 		if (tick > (lasttick + xc_tick_jump_limit))
978 			endtick += (tick - lasttick);
979 		lasttick = tick;
980 		if (tick > endtick) {
981 			if (panic_quiesce)
982 				return;
983 			cmn_err(CE_CONT, "send mondo timeout "
984 			    "[retries: 0x%x]  cpuids: ", retries);
985 			for (i = 0; i < ncpuids; i++)
986 				cmn_err(CE_CONT, " 0x%x", mcpup->cpu_list[i]);
987 			cmn_err(CE_CONT, "\n");
988 			cmn_err(CE_PANIC, "send_mondo_set: timeout");
989 		}
990 
991 		while (gettick() < (tick + sys_clock_mhz))
992 			;
993 		retries++;
994 	} while (ncpuids > 0);
995 
996 	CPU_STATS_ADDQ(CPU, sys, xcalls, shipped);
997 
998 #ifdef SEND_MONDO_STATS
999 	{
1000 		uint64_t n = gettick() - starttick;
1001 		if (n < 8192)
1002 			x_set_stimes[n >> 7]++;
1003 		else if (n < 15*8192)
1004 			x_set_ltimes[n >> 13]++;
1005 		else
1006 			x_set_ltimes[0xf]++;
1007 	}
1008 	x_set_cpus[shipped]++;
1009 #endif
1010 }
1011 
1012 void
1013 syncfpu(void)
1014 {
1015 }
1016 
1017 void
1018 sticksync_slave(void)
1019 {
1020 	suspend_sync_tick_stick_npt();
1021 }
1022 
1023 void
1024 sticksync_master(void)
1025 {}
1026 
1027 void
1028 cpu_init_cache_scrub(void)
1029 {
1030 	mach_set_soft_state(SIS_NORMAL, &SOLARIS_SOFT_STATE_RUN_MSG);
1031 }
1032 
1033 int
1034 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data)
1035 {
1036 	int ret, watched;
1037 
1038 	watched = watch_disable_addr((void *)addr, 4, S_WRITE);
1039 	ret = dtrace_blksuword32(addr, data, 0);
1040 	if (watched)
1041 		watch_enable_addr((void *)addr, 4, S_WRITE);
1042 
1043 	return (ret);
1044 }
1045 
1046 int
1047 dtrace_blksuword32(uintptr_t addr, uint32_t *data, int tryagain)
1048 {
1049 	if (suword32((void *)addr, *data) == -1)
1050 		return (tryagain ? dtrace_blksuword32_err(addr, data) : -1);
1051 	dtrace_flush_sec(addr);
1052 
1053 	return (0);
1054 }
1055 
1056 /*ARGSUSED*/
1057 void
1058 cpu_faulted_enter(struct cpu *cp)
1059 {
1060 }
1061 
1062 /*ARGSUSED*/
1063 void
1064 cpu_faulted_exit(struct cpu *cp)
1065 {
1066 }
1067 
1068 static int
1069 kdi_cpu_ready_iter(int (*cb)(int, void *), void *arg)
1070 {
1071 	int rc, i;
1072 
1073 	for (rc = 0, i = 0; i < NCPU; i++) {
1074 		if (CPU_IN_SET(cpu_ready_set, i))
1075 			rc += cb(i, arg);
1076 	}
1077 
1078 	return (rc);
1079 }
1080 
1081 /*
1082  * Sends a cross-call to a specified processor.  The caller assumes
1083  * responsibility for repetition of cross-calls, as appropriate (MARSA for
1084  * debugging).
1085  */
1086 static int
1087 kdi_xc_one(int cpuid, void (*func)(uintptr_t, uintptr_t), uintptr_t arg1,
1088     uintptr_t arg2)
1089 {
1090 	int stat;
1091 	struct machcpu	*mcpup;
1092 	uint64_t cpuaddr_reg = 0, cpuaddr_scr = 0;
1093 
1094 	mcpup = &(((cpu_t *)get_cpuaddr(cpuaddr_reg, cpuaddr_scr))->cpu_m);
1095 
1096 	/*
1097 	 * if (idsr_busy())
1098 	 *	return (KDI_XC_RES_ERR);
1099 	 */
1100 
1101 	init_mondo_nocheck((xcfunc_t *)func, arg1, arg2);
1102 
1103 	mcpup->cpu_list[0] = (uint16_t)cpuid;
1104 	stat = shipit(1, mcpup->cpu_list_ra);
1105 
1106 	if (stat == 0)
1107 		return (KDI_XC_RES_OK);
1108 	else
1109 		return (KDI_XC_RES_NACK);
1110 }
1111 
1112 static void
1113 kdi_tickwait(clock_t nticks)
1114 {
1115 	clock_t endtick = gettick() + nticks;
1116 
1117 	while (gettick() < endtick)
1118 		;
1119 }
1120 
1121 static void
1122 kdi_cpu_init(int dcache_size, int dcache_linesize, int icache_size,
1123     int icache_linesize)
1124 {
1125 	kdi_dcache_size = dcache_size;
1126 	kdi_dcache_linesize = dcache_linesize;
1127 	kdi_icache_size = icache_size;
1128 	kdi_icache_linesize = icache_linesize;
1129 }
1130 
1131 /* used directly by kdi_read/write_phys */
1132 void
1133 kdi_flush_caches(void)
1134 {
1135 	/* Not required on sun4v architecture. */
1136 }
1137 
1138 /*ARGSUSED*/
1139 int
1140 kdi_get_stick(uint64_t *stickp)
1141 {
1142 	return (-1);
1143 }
1144 
1145 void
1146 cpu_kdi_init(kdi_t *kdi)
1147 {
1148 	kdi->kdi_flush_caches = kdi_flush_caches;
1149 	kdi->mkdi_cpu_init = kdi_cpu_init;
1150 	kdi->mkdi_cpu_ready_iter = kdi_cpu_ready_iter;
1151 	kdi->mkdi_xc_one = kdi_xc_one;
1152 	kdi->mkdi_tickwait = kdi_tickwait;
1153 	kdi->mkdi_get_stick = kdi_get_stick;
1154 }
1155 
1156 uint64_t	soft_state_message_ra[SOLARIS_SOFT_STATE_MSG_CNT];
1157 static uint64_t	soft_state_saved_state = (uint64_t)-1;
1158 static int	soft_state_initialized = 0;
1159 static uint64_t soft_state_sup_minor;		/* Supported minor number */
1160 static hsvc_info_t soft_state_hsvc = {
1161 			HSVC_REV_1, NULL, HSVC_GROUP_SOFT_STATE, 1, 0, NULL };
1162 
1163 
1164 static void
1165 sun4v_system_claim(void)
1166 {
1167 	lbolt_debug_entry();
1168 
1169 	watchdog_suspend();
1170 	kldc_debug_enter();
1171 	/*
1172 	 * For "mdb -K", set soft state to debugging
1173 	 */
1174 	if (soft_state_saved_state == -1) {
1175 		mach_get_soft_state(&soft_state_saved_state,
1176 		    &SOLARIS_SOFT_STATE_SAVED_MSG);
1177 	}
1178 	/*
1179 	 * check again as the read above may or may not have worked and if
1180 	 * it didn't then soft state will still be -1
1181 	 */
1182 	if (soft_state_saved_state != -1) {
1183 		mach_set_soft_state(SIS_TRANSITION,
1184 		    &SOLARIS_SOFT_STATE_DEBUG_MSG);
1185 	}
1186 }
1187 
1188 static void
1189 sun4v_system_release(void)
1190 {
1191 	watchdog_resume();
1192 	/*
1193 	 * For "mdb -K", set soft_state state back to original state on exit
1194 	 */
1195 	if (soft_state_saved_state != -1) {
1196 		mach_set_soft_state(soft_state_saved_state,
1197 		    &SOLARIS_SOFT_STATE_SAVED_MSG);
1198 		soft_state_saved_state = -1;
1199 	}
1200 
1201 	lbolt_debug_return();
1202 }
1203 
1204 void
1205 plat_kdi_init(kdi_t *kdi)
1206 {
1207 	kdi->pkdi_system_claim = sun4v_system_claim;
1208 	kdi->pkdi_system_release = sun4v_system_release;
1209 }
1210 
1211 /*
1212  * Routine to return memory information associated
1213  * with a physical address and syndrome.
1214  */
1215 /* ARGSUSED */
1216 int
1217 cpu_get_mem_info(uint64_t synd, uint64_t afar,
1218     uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep,
1219     int *segsp, int *banksp, int *mcidp)
1220 {
1221 	return (ENOTSUP);
1222 }
1223 
1224 /*
1225  * This routine returns the size of the kernel's FRU name buffer.
1226  */
1227 size_t
1228 cpu_get_name_bufsize()
1229 {
1230 	return (UNUM_NAMLEN);
1231 }
1232 
1233 /*
1234  * This routine is a more generic interface to cpu_get_mem_unum(),
1235  * that may be used by other modules (e.g. mm).
1236  */
1237 /* ARGSUSED */
1238 int
1239 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar,
1240     char *buf, int buflen, int *lenp)
1241 {
1242 	return (ENOTSUP);
1243 }
1244 
1245 /* ARGSUSED */
1246 int
1247 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp)
1248 {
1249 	return (ENOTSUP);
1250 }
1251 
1252 /* ARGSUSED */
1253 int
1254 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp)
1255 {
1256 	return (ENOTSUP);
1257 }
1258 
1259 /*
1260  * xt_sync - wait for previous x-traps to finish
1261  */
1262 void
1263 xt_sync(cpuset_t cpuset)
1264 {
1265 	union {
1266 		uint8_t volatile byte[NCPU];
1267 		uint64_t volatile xword[NCPU / 8];
1268 	} cpu_sync;
1269 	uint64_t starttick, endtick, tick, lasttick, traptrace_id;
1270 	uint_t largestid, smallestid;
1271 	int i, j;
1272 
1273 	kpreempt_disable();
1274 	CPUSET_DEL(cpuset, CPU->cpu_id);
1275 	CPUSET_AND(cpuset, cpu_ready_set);
1276 
1277 	CPUSET_BOUNDS(cpuset, smallestid, largestid);
1278 	if (smallestid == CPUSET_NOTINSET)
1279 		goto out;
1280 
1281 	/*
1282 	 * Sun4v uses a queue for receiving mondos. Successful
1283 	 * transmission of a mondo only indicates that the mondo
1284 	 * has been written into the queue.
1285 	 *
1286 	 * We use an array of bytes to let each cpu to signal back
1287 	 * to the cross trap sender that the cross trap has been
1288 	 * executed. Set the byte to 1 before sending the cross trap
1289 	 * and wait until other cpus reset it to 0.
1290 	 */
1291 	bzero((void *)&cpu_sync, NCPU);
1292 	cpu_sync.byte[smallestid] = 1;
1293 	if (largestid != smallestid) {
1294 		for (i = (smallestid + 1); i <= (largestid - 1); i++)
1295 			if (CPU_IN_SET(cpuset, i))
1296 				cpu_sync.byte[i] = 1;
1297 		cpu_sync.byte[largestid] = 1;
1298 	}
1299 
1300 	/*
1301 	 * To help debug xt_sync panic, each mondo is uniquely identified
1302 	 * by passing the tick value, traptrace_id as the second mondo
1303 	 * argument to xt_some which is logged in CPU's mondo queue,
1304 	 * traptrace buffer and the panic message.
1305 	 */
1306 	traptrace_id = gettick();
1307 	xt_some(cpuset, (xcfunc_t *)xt_sync_tl1,
1308 	    (uint64_t)cpu_sync.byte, traptrace_id);
1309 
1310 	starttick = lasttick = gettick();
1311 	endtick = starttick + xc_sync_tick_limit;
1312 
1313 	for (i = (smallestid / 8); i <= (largestid / 8); i++) {
1314 		while (cpu_sync.xword[i] != 0) {
1315 			tick = gettick();
1316 			/*
1317 			 * If there is a big jump between the current tick
1318 			 * count and lasttick, we have probably hit a break
1319 			 * point. Adjust endtick accordingly to avoid panic.
1320 			 */
1321 			if (tick > (lasttick + xc_tick_jump_limit)) {
1322 				endtick += (tick - lasttick);
1323 			}
1324 			lasttick = tick;
1325 			if (tick > endtick) {
1326 				if (panic_quiesce)
1327 					goto out;
1328 				cmn_err(CE_CONT, "Cross trap sync timeout:  "
1329 				    "at cpu_sync.xword[%d]: 0x%lx "
1330 				    "cpu_sync.byte: 0x%lx "
1331 				    "starttick: 0x%lx endtick: 0x%lx "
1332 				    "traptrace_id = 0x%lx\n",
1333 				    i, cpu_sync.xword[i],
1334 				    (uint64_t)cpu_sync.byte,
1335 				    starttick, endtick, traptrace_id);
1336 				cmn_err(CE_CONT, "CPUIDs:");
1337 				for (j = (i * 8); j <= largestid; j++) {
1338 					if (cpu_sync.byte[j] != 0)
1339 						cmn_err(CE_CONT, " 0x%x", j);
1340 				}
1341 				cmn_err(CE_PANIC, "xt_sync: timeout");
1342 			}
1343 		}
1344 	}
1345 
1346 out:
1347 	kpreempt_enable();
1348 }
1349 
1350 #define	QFACTOR		200
1351 /*
1352  * Recalculate the values of the cross-call timeout variables based
1353  * on the value of the 'inter-cpu-latency' property of the platform node.
1354  * The property sets the number of nanosec to wait for a cross-call
1355  * to be acknowledged.  Other timeout variables are derived from it.
1356  *
1357  * N.B. This implementation is aware of the internals of xc_init()
1358  * and updates many of the same variables.
1359  */
1360 void
1361 recalc_xc_timeouts(void)
1362 {
1363 	typedef union {
1364 		uint64_t whole;
1365 		struct {
1366 			uint_t high;
1367 			uint_t low;
1368 		} half;
1369 	} u_number;
1370 
1371 	/* See x_call.c for descriptions of these extern variables. */
1372 	extern uint64_t xc_tick_limit_scale;
1373 	extern uint64_t xc_mondo_time_limit;
1374 	extern uint64_t xc_func_time_limit;
1375 	extern uint64_t xc_scale;
1376 	extern uint64_t xc_mondo_multiplier;
1377 	extern uint_t   nsec_shift;
1378 
1379 	/* Temp versions of the target variables */
1380 	uint64_t tick_limit;
1381 	uint64_t tick_jump_limit;
1382 	uint64_t mondo_time_limit;
1383 	uint64_t func_time_limit;
1384 	uint64_t scale;
1385 
1386 	uint64_t latency;	/* nanoseconds */
1387 	uint64_t maxfreq;
1388 	uint64_t tick_limit_save = xc_tick_limit;
1389 	uint64_t sync_tick_limit_save = xc_sync_tick_limit;
1390 	uint_t   tick_scale;
1391 	uint64_t top;
1392 	uint64_t bottom;
1393 	u_number tk;
1394 
1395 	md_t *mdp;
1396 	int nrnode;
1397 	mde_cookie_t *platlist;
1398 
1399 	/*
1400 	 * Look up the 'inter-cpu-latency' (optional) property in the
1401 	 * platform node of the MD.  The units are nanoseconds.
1402 	 */
1403 	if ((mdp = md_get_handle()) == NULL) {
1404 		cmn_err(CE_WARN, "recalc_xc_timeouts: "
1405 		    "Unable to initialize machine description");
1406 		return;
1407 	}
1408 
1409 	nrnode = md_alloc_scan_dag(mdp,
1410 	    md_root_node(mdp), "platform", "fwd", &platlist);
1411 
1412 	ASSERT(nrnode == 1);
1413 	if (nrnode < 1) {
1414 		cmn_err(CE_WARN, "recalc_xc_timeouts: platform node missing");
1415 		goto done;
1416 	}
1417 	if (md_get_prop_val(mdp, platlist[0],
1418 	    "inter-cpu-latency", &latency) == -1)
1419 		goto done;
1420 
1421 	/*
1422 	 * clock.h defines an assembly-language macro
1423 	 * (NATIVE_TIME_TO_NSEC_SCALE) to convert from %stick
1424 	 * units to nanoseconds.  Since the inter-cpu-latency
1425 	 * units are nanoseconds and the xc_* variables require
1426 	 * %stick units, we need the inverse of that function.
1427 	 * The trick is to perform the calculation without
1428 	 * floating point, but also without integer truncation
1429 	 * or overflow.  To understand the calculation below,
1430 	 * please read the discussion of the macro in clock.h.
1431 	 * Since this new code will be invoked infrequently,
1432 	 * we can afford to implement it in C.
1433 	 *
1434 	 * tick_scale is the reciprocal of nsec_scale which is
1435 	 * calculated at startup in setcpudelay().  The calc
1436 	 * of tick_limit parallels that of NATIVE_TIME_TO_NSEC_SCALE
1437 	 * except we use tick_scale instead of nsec_scale and
1438 	 * C instead of assembler.
1439 	 */
1440 	tick_scale = (uint_t)(((u_longlong_t)sys_tick_freq
1441 	    << (32 - nsec_shift)) / NANOSEC);
1442 
1443 	tk.whole = latency;
1444 	top = ((uint64_t)tk.half.high << 4) * tick_scale;
1445 	bottom = (((uint64_t)tk.half.low << 4) * (uint64_t)tick_scale) >> 32;
1446 	tick_limit = top + bottom;
1447 
1448 	/*
1449 	 * xc_init() calculated 'maxfreq' by looking at all the cpus,
1450 	 * and used it to derive some of the timeout variables that we
1451 	 * recalculate below.  We can back into the original value by
1452 	 * using the inverse of one of those calculations.
1453 	 */
1454 	maxfreq = xc_mondo_time_limit / xc_scale;
1455 
1456 	/*
1457 	 * Don't allow the new timeout (xc_tick_limit) to fall below
1458 	 * the system tick frequency (stick).  Allowing the timeout
1459 	 * to be set more tightly than this empirically determined
1460 	 * value may cause panics.
1461 	 */
1462 	tick_limit = tick_limit < sys_tick_freq ? sys_tick_freq : tick_limit;
1463 
1464 	tick_jump_limit = tick_limit / 32;
1465 	tick_limit *= xc_tick_limit_scale;
1466 
1467 	/*
1468 	 * Recalculate xc_scale since it is used in a callback function
1469 	 * (xc_func_timeout_adj) to adjust two of the timeouts dynamically.
1470 	 * Make the change in xc_scale proportional to the change in
1471 	 * xc_tick_limit.
1472 	 */
1473 	scale = (xc_scale * tick_limit + sys_tick_freq / 2) / tick_limit_save;
1474 	if (scale == 0)
1475 		scale = 1;
1476 
1477 	mondo_time_limit = maxfreq * scale;
1478 	func_time_limit = mondo_time_limit * xc_mondo_multiplier;
1479 
1480 	/*
1481 	 * Don't modify the timeouts if nothing has changed.  Else,
1482 	 * stuff the variables with the freshly calculated (temp)
1483 	 * variables.  This minimizes the window where the set of
1484 	 * values could be inconsistent.
1485 	 */
1486 	if (tick_limit != xc_tick_limit) {
1487 		xc_tick_limit = tick_limit;
1488 		xc_tick_jump_limit = tick_jump_limit;
1489 		xc_scale = scale;
1490 		xc_mondo_time_limit = mondo_time_limit;
1491 		xc_func_time_limit = func_time_limit;
1492 	}
1493 
1494 done:
1495 	/*
1496 	 * Increase the timeout limit for xt_sync() cross calls.
1497 	 */
1498 	xc_sync_tick_limit = xc_tick_limit * (cpu_q_entries / QFACTOR);
1499 	xc_sync_tick_limit = xc_sync_tick_limit < xc_tick_limit ?
1500 	    xc_tick_limit : xc_sync_tick_limit;
1501 
1502 	/*
1503 	 * Force the new values to be used for future cross calls.
1504 	 * This is necessary only when we increase the timeouts.
1505 	 */
1506 	if ((xc_tick_limit > tick_limit_save) || (xc_sync_tick_limit >
1507 	    sync_tick_limit_save)) {
1508 		cpuset_t cpuset = cpu_ready_set;
1509 		xt_sync(cpuset);
1510 	}
1511 
1512 	if (nrnode > 0)
1513 		md_free_scan_dag(mdp, &platlist);
1514 	(void) md_fini_handle(mdp);
1515 }
1516 
1517 void
1518 mach_soft_state_init(void)
1519 {
1520 	int		i;
1521 	uint64_t	ra;
1522 
1523 	/*
1524 	 * Try to register soft_state api. If it fails, soft_state api has not
1525 	 * been implemented in the firmware, so do not bother to setup
1526 	 * soft_state in the kernel.
1527 	 */
1528 	if ((i = hsvc_register(&soft_state_hsvc, &soft_state_sup_minor)) != 0) {
1529 		return;
1530 	}
1531 	for (i = 0; i < SOLARIS_SOFT_STATE_MSG_CNT; i++) {
1532 		ASSERT(strlen((const char *)(void *)
1533 		    soft_state_message_strings + i) < SSM_SIZE);
1534 		if ((ra = va_to_pa(
1535 		    (void *)(soft_state_message_strings + i))) == -1ll) {
1536 			return;
1537 		}
1538 		soft_state_message_ra[i] = ra;
1539 	}
1540 	/*
1541 	 * Tell OBP that we are supporting Guest State
1542 	 */
1543 	prom_sun4v_soft_state_supported();
1544 	soft_state_initialized = 1;
1545 }
1546 
1547 void
1548 mach_set_soft_state(uint64_t state, uint64_t *string_ra)
1549 {
1550 	uint64_t	rc;
1551 
1552 	if (soft_state_initialized && *string_ra) {
1553 		rc = hv_soft_state_set(state, *string_ra);
1554 		if (rc != H_EOK) {
1555 			cmn_err(CE_WARN,
1556 			    "hv_soft_state_set returned %ld\n", rc);
1557 		}
1558 	}
1559 }
1560 
1561 void
1562 mach_get_soft_state(uint64_t *state, uint64_t *string_ra)
1563 {
1564 	uint64_t	rc;
1565 
1566 	if (soft_state_initialized && *string_ra) {
1567 		rc = hv_soft_state_get(*string_ra, state);
1568 		if (rc != H_EOK) {
1569 			cmn_err(CE_WARN,
1570 			    "hv_soft_state_get returned %ld\n", rc);
1571 			*state = -1;
1572 		}
1573 	}
1574 }
1575