1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29#if !defined(lint) 30#include "assym.h" 31#endif /* !lint */ 32#include <sys/asm_linkage.h> 33#include <sys/privregs.h> 34#include <sys/sun4asi.h> 35#include <sys/machasi.h> 36#include <sys/hypervisor_api.h> 37#include <sys/machtrap.h> 38#include <sys/machthread.h> 39#include <sys/pcb.h> 40#include <sys/pte.h> 41#include <sys/mmu.h> 42#include <sys/machpcb.h> 43#include <sys/async.h> 44#include <sys/intreg.h> 45#include <sys/scb.h> 46#include <sys/psr_compat.h> 47#include <sys/syscall.h> 48#include <sys/machparam.h> 49#include <sys/traptrace.h> 50#include <vm/hat_sfmmu.h> 51#include <sys/archsystm.h> 52#include <sys/utrap.h> 53#include <sys/clock.h> 54#include <sys/intr.h> 55#include <sys/fpu/fpu_simulator.h> 56#include <vm/seg_spt.h> 57 58/* 59 * WARNING: If you add a fast trap handler which can be invoked by a 60 * non-privileged user, you may have to use the FAST_TRAP_DONE macro 61 * instead of "done" instruction to return back to the user mode. See 62 * comments for the "fast_trap_done" entry point for more information. 63 * 64 * An alternate FAST_TRAP_DONE_CHK_INTR macro should be used for the 65 * cases where you always want to process any pending interrupts before 66 * returning back to the user mode. 67 */ 68#define FAST_TRAP_DONE \ 69 ba,a fast_trap_done 70 71#define FAST_TRAP_DONE_CHK_INTR \ 72 ba,a fast_trap_done_chk_intr 73 74/* 75 * SPARC V9 Trap Table 76 * 77 * Most of the trap handlers are made from common building 78 * blocks, and some are instantiated multiple times within 79 * the trap table. So, I build a bunch of macros, then 80 * populate the table using only the macros. 81 * 82 * Many macros branch to sys_trap. Its calling convention is: 83 * %g1 kernel trap handler 84 * %g2, %g3 args for above 85 * %g4 desire %pil 86 */ 87 88#ifdef TRAPTRACE 89 90/* 91 * Tracing macro. Adds two instructions if TRAPTRACE is defined. 92 */ 93#define TT_TRACE(label) \ 94 ba label ;\ 95 rd %pc, %g7 96#define TT_TRACE_INS 2 97 98#define TT_TRACE_L(label) \ 99 ba label ;\ 100 rd %pc, %l4 ;\ 101 clr %l4 102#define TT_TRACE_L_INS 3 103 104#else 105 106#define TT_TRACE(label) 107#define TT_TRACE_INS 0 108 109#define TT_TRACE_L(label) 110#define TT_TRACE_L_INS 0 111 112#endif 113 114/* 115 * This macro is used to update per cpu mmu stats in perf critical 116 * paths. It is only enabled in debug kernels or if SFMMU_STAT_GATHER 117 * is defined. 118 */ 119#if defined(DEBUG) || defined(SFMMU_STAT_GATHER) 120#define HAT_PERCPU_DBSTAT(stat) \ 121 mov stat, %g1 ;\ 122 ba stat_mmu ;\ 123 rd %pc, %g7 124#else 125#define HAT_PERCPU_DBSTAT(stat) 126#endif /* DEBUG || SFMMU_STAT_GATHER */ 127 128/* 129 * This first set are funneled to trap() with %tt as the type. 130 * Trap will then either panic or send the user a signal. 131 */ 132/* 133 * NOT is used for traps that just shouldn't happen. 134 * It comes in both single and quadruple flavors. 135 */ 136#if !defined(lint) 137 .global trap 138#endif /* !lint */ 139#define NOT \ 140 TT_TRACE(trace_gen) ;\ 141 set trap, %g1 ;\ 142 rdpr %tt, %g3 ;\ 143 ba,pt %xcc, sys_trap ;\ 144 sub %g0, 1, %g4 ;\ 145 .align 32 146#define NOT4 NOT; NOT; NOT; NOT 147 148#define NOTP \ 149 TT_TRACE(trace_gen) ;\ 150 ba,pt %xcc, ptl1_panic ;\ 151 mov PTL1_BAD_TRAP, %g1 ;\ 152 .align 32 153#define NOTP4 NOTP; NOTP; NOTP; NOTP 154 155/* 156 * RED is for traps that use the red mode handler. 157 * We should never see these either. 158 */ 159#define RED NOT 160/* 161 * BAD is used for trap vectors we don't have a kernel 162 * handler for. 163 * It also comes in single and quadruple versions. 164 */ 165#define BAD NOT 166#define BAD4 NOT4 167 168#define DONE \ 169 done; \ 170 .align 32 171 172/* 173 * TRAP vectors to the trap() function. 174 * It's main use is for user errors. 175 */ 176#if !defined(lint) 177 .global trap 178#endif /* !lint */ 179#define TRAP(arg) \ 180 TT_TRACE(trace_gen) ;\ 181 set trap, %g1 ;\ 182 mov arg, %g3 ;\ 183 ba,pt %xcc, sys_trap ;\ 184 sub %g0, 1, %g4 ;\ 185 .align 32 186 187/* 188 * SYSCALL is used for system calls on both ILP32 and LP64 kernels 189 * depending on the "which" parameter (should be either syscall_trap 190 * or syscall_trap32). 191 */ 192#define SYSCALL(which) \ 193 TT_TRACE(trace_gen) ;\ 194 set (which), %g1 ;\ 195 ba,pt %xcc, sys_trap ;\ 196 sub %g0, 1, %g4 ;\ 197 .align 32 198 199/* 200 * GOTO just jumps to a label. 201 * It's used for things that can be fixed without going thru sys_trap. 202 */ 203#define GOTO(label) \ 204 .global label ;\ 205 ba,a label ;\ 206 .empty ;\ 207 .align 32 208 209/* 210 * GOTO_TT just jumps to a label. 211 * correctable ECC error traps at level 0 and 1 will use this macro. 212 * It's used for things that can be fixed without going thru sys_trap. 213 */ 214#define GOTO_TT(label, ttlabel) \ 215 .global label ;\ 216 TT_TRACE(ttlabel) ;\ 217 ba,a label ;\ 218 .empty ;\ 219 .align 32 220 221/* 222 * Privileged traps 223 * Takes breakpoint if privileged, calls trap() if not. 224 */ 225#define PRIV(label) \ 226 rdpr %tstate, %g1 ;\ 227 btst TSTATE_PRIV, %g1 ;\ 228 bnz label ;\ 229 rdpr %tt, %g3 ;\ 230 set trap, %g1 ;\ 231 ba,pt %xcc, sys_trap ;\ 232 sub %g0, 1, %g4 ;\ 233 .align 32 234 235 236/* 237 * DTrace traps. 238 */ 239#define DTRACE_FASTTRAP \ 240 .global dtrace_fasttrap_probe ;\ 241 .global dtrace_fasttrap_probe_ptr ;\ 242 sethi %hi(dtrace_fasttrap_probe_ptr), %g4 ;\ 243 ldn [%g4 + %lo(dtrace_fasttrap_probe_ptr)], %g4 ;\ 244 set dtrace_fasttrap_probe, %g1 ;\ 245 brnz,pn %g4, user_trap ;\ 246 sub %g0, 1, %g4 ;\ 247 FAST_TRAP_DONE ;\ 248 .align 32 249 250#define DTRACE_PID \ 251 .global dtrace_pid_probe ;\ 252 set dtrace_pid_probe, %g1 ;\ 253 ba,pt %xcc, user_trap ;\ 254 sub %g0, 1, %g4 ;\ 255 .align 32 256 257#define DTRACE_RETURN \ 258 .global dtrace_return_probe ;\ 259 set dtrace_return_probe, %g1 ;\ 260 ba,pt %xcc, user_trap ;\ 261 sub %g0, 1, %g4 ;\ 262 .align 32 263 264/* 265 * REGISTER WINDOW MANAGEMENT MACROS 266 */ 267 268/* 269 * various convenient units of padding 270 */ 271#define SKIP(n) .skip 4*(n) 272 273/* 274 * CLEAN_WINDOW is the simple handler for cleaning a register window. 275 */ 276#define CLEAN_WINDOW \ 277 TT_TRACE_L(trace_win) ;\ 278 rdpr %cleanwin, %l0; inc %l0; wrpr %l0, %cleanwin ;\ 279 clr %l0; clr %l1; clr %l2; clr %l3 ;\ 280 clr %l4; clr %l5; clr %l6; clr %l7 ;\ 281 clr %o0; clr %o1; clr %o2; clr %o3 ;\ 282 clr %o4; clr %o5; clr %o6; clr %o7 ;\ 283 retry; .align 128 284 285#if !defined(lint) 286 287/* 288 * If we get an unresolved tlb miss while in a window handler, the fault 289 * handler will resume execution at the last instruction of the window 290 * hander, instead of delivering the fault to the kernel. Spill handlers 291 * use this to spill windows into the wbuf. 292 * 293 * The mixed handler works by checking %sp, and branching to the correct 294 * handler. This is done by branching back to label 1: for 32b frames, 295 * or label 2: for 64b frames; which implies the handler order is: 32b, 296 * 64b, mixed. The 1: and 2: labels are offset into the routines to 297 * allow the branchs' delay slots to contain useful instructions. 298 */ 299 300/* 301 * SPILL_32bit spills a 32-bit-wide kernel register window. It 302 * assumes that the kernel context and the nucleus context are the 303 * same. The stack pointer is required to be eight-byte aligned even 304 * though this code only needs it to be four-byte aligned. 305 */ 306#define SPILL_32bit(tail) \ 307 srl %sp, 0, %sp ;\ 3081: st %l0, [%sp + 0] ;\ 309 st %l1, [%sp + 4] ;\ 310 st %l2, [%sp + 8] ;\ 311 st %l3, [%sp + 12] ;\ 312 st %l4, [%sp + 16] ;\ 313 st %l5, [%sp + 20] ;\ 314 st %l6, [%sp + 24] ;\ 315 st %l7, [%sp + 28] ;\ 316 st %i0, [%sp + 32] ;\ 317 st %i1, [%sp + 36] ;\ 318 st %i2, [%sp + 40] ;\ 319 st %i3, [%sp + 44] ;\ 320 st %i4, [%sp + 48] ;\ 321 st %i5, [%sp + 52] ;\ 322 st %i6, [%sp + 56] ;\ 323 st %i7, [%sp + 60] ;\ 324 TT_TRACE_L(trace_win) ;\ 325 saved ;\ 326 retry ;\ 327 SKIP(31-19-TT_TRACE_L_INS) ;\ 328 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 329 .empty 330 331/* 332 * SPILL_32bit_asi spills a 32-bit-wide register window into a 32-bit 333 * wide address space via the designated asi. It is used to spill 334 * non-kernel windows. The stack pointer is required to be eight-byte 335 * aligned even though this code only needs it to be four-byte 336 * aligned. 337 */ 338#define SPILL_32bit_asi(asi_num, tail) \ 339 srl %sp, 0, %sp ;\ 3401: sta %l0, [%sp + %g0]asi_num ;\ 341 mov 4, %g1 ;\ 342 sta %l1, [%sp + %g1]asi_num ;\ 343 mov 8, %g2 ;\ 344 sta %l2, [%sp + %g2]asi_num ;\ 345 mov 12, %g3 ;\ 346 sta %l3, [%sp + %g3]asi_num ;\ 347 add %sp, 16, %g4 ;\ 348 sta %l4, [%g4 + %g0]asi_num ;\ 349 sta %l5, [%g4 + %g1]asi_num ;\ 350 sta %l6, [%g4 + %g2]asi_num ;\ 351 sta %l7, [%g4 + %g3]asi_num ;\ 352 add %g4, 16, %g4 ;\ 353 sta %i0, [%g4 + %g0]asi_num ;\ 354 sta %i1, [%g4 + %g1]asi_num ;\ 355 sta %i2, [%g4 + %g2]asi_num ;\ 356 sta %i3, [%g4 + %g3]asi_num ;\ 357 add %g4, 16, %g4 ;\ 358 sta %i4, [%g4 + %g0]asi_num ;\ 359 sta %i5, [%g4 + %g1]asi_num ;\ 360 sta %i6, [%g4 + %g2]asi_num ;\ 361 sta %i7, [%g4 + %g3]asi_num ;\ 362 TT_TRACE_L(trace_win) ;\ 363 saved ;\ 364 retry ;\ 365 SKIP(31-25-TT_TRACE_L_INS) ;\ 366 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 367 .empty 368 369#define SPILL_32bit_tt1(asi_num, tail) \ 370 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 371 .empty ;\ 372 .align 128 373 374 375/* 376 * FILL_32bit fills a 32-bit-wide kernel register window. It assumes 377 * that the kernel context and the nucleus context are the same. The 378 * stack pointer is required to be eight-byte aligned even though this 379 * code only needs it to be four-byte aligned. 380 */ 381#define FILL_32bit(tail) \ 382 srl %sp, 0, %sp ;\ 3831: TT_TRACE_L(trace_win) ;\ 384 ld [%sp + 0], %l0 ;\ 385 ld [%sp + 4], %l1 ;\ 386 ld [%sp + 8], %l2 ;\ 387 ld [%sp + 12], %l3 ;\ 388 ld [%sp + 16], %l4 ;\ 389 ld [%sp + 20], %l5 ;\ 390 ld [%sp + 24], %l6 ;\ 391 ld [%sp + 28], %l7 ;\ 392 ld [%sp + 32], %i0 ;\ 393 ld [%sp + 36], %i1 ;\ 394 ld [%sp + 40], %i2 ;\ 395 ld [%sp + 44], %i3 ;\ 396 ld [%sp + 48], %i4 ;\ 397 ld [%sp + 52], %i5 ;\ 398 ld [%sp + 56], %i6 ;\ 399 ld [%sp + 60], %i7 ;\ 400 restored ;\ 401 retry ;\ 402 SKIP(31-19-TT_TRACE_L_INS) ;\ 403 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 404 .empty 405 406/* 407 * FILL_32bit_asi fills a 32-bit-wide register window from a 32-bit 408 * wide address space via the designated asi. It is used to fill 409 * non-kernel windows. The stack pointer is required to be eight-byte 410 * aligned even though this code only needs it to be four-byte 411 * aligned. 412 */ 413#define FILL_32bit_asi(asi_num, tail) \ 414 srl %sp, 0, %sp ;\ 4151: TT_TRACE_L(trace_win) ;\ 416 mov 4, %g1 ;\ 417 lda [%sp + %g0]asi_num, %l0 ;\ 418 mov 8, %g2 ;\ 419 lda [%sp + %g1]asi_num, %l1 ;\ 420 mov 12, %g3 ;\ 421 lda [%sp + %g2]asi_num, %l2 ;\ 422 lda [%sp + %g3]asi_num, %l3 ;\ 423 add %sp, 16, %g4 ;\ 424 lda [%g4 + %g0]asi_num, %l4 ;\ 425 lda [%g4 + %g1]asi_num, %l5 ;\ 426 lda [%g4 + %g2]asi_num, %l6 ;\ 427 lda [%g4 + %g3]asi_num, %l7 ;\ 428 add %g4, 16, %g4 ;\ 429 lda [%g4 + %g0]asi_num, %i0 ;\ 430 lda [%g4 + %g1]asi_num, %i1 ;\ 431 lda [%g4 + %g2]asi_num, %i2 ;\ 432 lda [%g4 + %g3]asi_num, %i3 ;\ 433 add %g4, 16, %g4 ;\ 434 lda [%g4 + %g0]asi_num, %i4 ;\ 435 lda [%g4 + %g1]asi_num, %i5 ;\ 436 lda [%g4 + %g2]asi_num, %i6 ;\ 437 lda [%g4 + %g3]asi_num, %i7 ;\ 438 restored ;\ 439 retry ;\ 440 SKIP(31-25-TT_TRACE_L_INS) ;\ 441 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 442 .empty 443 444 445/* 446 * SPILL_64bit spills a 64-bit-wide kernel register window. It 447 * assumes that the kernel context and the nucleus context are the 448 * same. The stack pointer is required to be eight-byte aligned. 449 */ 450#define SPILL_64bit(tail) \ 4512: stx %l0, [%sp + V9BIAS64 + 0] ;\ 452 stx %l1, [%sp + V9BIAS64 + 8] ;\ 453 stx %l2, [%sp + V9BIAS64 + 16] ;\ 454 stx %l3, [%sp + V9BIAS64 + 24] ;\ 455 stx %l4, [%sp + V9BIAS64 + 32] ;\ 456 stx %l5, [%sp + V9BIAS64 + 40] ;\ 457 stx %l6, [%sp + V9BIAS64 + 48] ;\ 458 stx %l7, [%sp + V9BIAS64 + 56] ;\ 459 stx %i0, [%sp + V9BIAS64 + 64] ;\ 460 stx %i1, [%sp + V9BIAS64 + 72] ;\ 461 stx %i2, [%sp + V9BIAS64 + 80] ;\ 462 stx %i3, [%sp + V9BIAS64 + 88] ;\ 463 stx %i4, [%sp + V9BIAS64 + 96] ;\ 464 stx %i5, [%sp + V9BIAS64 + 104] ;\ 465 stx %i6, [%sp + V9BIAS64 + 112] ;\ 466 stx %i7, [%sp + V9BIAS64 + 120] ;\ 467 TT_TRACE_L(trace_win) ;\ 468 saved ;\ 469 retry ;\ 470 SKIP(31-18-TT_TRACE_L_INS) ;\ 471 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 472 .empty 473 474#define SPILL_64bit_ktt1(tail) \ 475 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 476 .empty ;\ 477 .align 128 478 479#define SPILL_mixed_ktt1(tail) \ 480 btst 1, %sp ;\ 481 bz,a,pt %xcc, fault_32bit_/**/tail ;\ 482 srl %sp, 0, %sp ;\ 483 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 484 .empty ;\ 485 .align 128 486 487/* 488 * SPILL_64bit_asi spills a 64-bit-wide register window into a 64-bit 489 * wide address space via the designated asi. It is used to spill 490 * non-kernel windows. The stack pointer is required to be eight-byte 491 * aligned. 492 */ 493#define SPILL_64bit_asi(asi_num, tail) \ 494 mov 0 + V9BIAS64, %g1 ;\ 4952: stxa %l0, [%sp + %g1]asi_num ;\ 496 mov 8 + V9BIAS64, %g2 ;\ 497 stxa %l1, [%sp + %g2]asi_num ;\ 498 mov 16 + V9BIAS64, %g3 ;\ 499 stxa %l2, [%sp + %g3]asi_num ;\ 500 mov 24 + V9BIAS64, %g4 ;\ 501 stxa %l3, [%sp + %g4]asi_num ;\ 502 add %sp, 32, %g5 ;\ 503 stxa %l4, [%g5 + %g1]asi_num ;\ 504 stxa %l5, [%g5 + %g2]asi_num ;\ 505 stxa %l6, [%g5 + %g3]asi_num ;\ 506 stxa %l7, [%g5 + %g4]asi_num ;\ 507 add %g5, 32, %g5 ;\ 508 stxa %i0, [%g5 + %g1]asi_num ;\ 509 stxa %i1, [%g5 + %g2]asi_num ;\ 510 stxa %i2, [%g5 + %g3]asi_num ;\ 511 stxa %i3, [%g5 + %g4]asi_num ;\ 512 add %g5, 32, %g5 ;\ 513 stxa %i4, [%g5 + %g1]asi_num ;\ 514 stxa %i5, [%g5 + %g2]asi_num ;\ 515 stxa %i6, [%g5 + %g3]asi_num ;\ 516 stxa %i7, [%g5 + %g4]asi_num ;\ 517 TT_TRACE_L(trace_win) ;\ 518 saved ;\ 519 retry ;\ 520 SKIP(31-25-TT_TRACE_L_INS) ;\ 521 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 522 .empty 523 524#define SPILL_64bit_tt1(asi_num, tail) \ 525 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 526 .empty ;\ 527 .align 128 528 529/* 530 * FILL_64bit fills a 64-bit-wide kernel register window. It assumes 531 * that the kernel context and the nucleus context are the same. The 532 * stack pointer is required to be eight-byte aligned. 533 */ 534#define FILL_64bit(tail) \ 5352: TT_TRACE_L(trace_win) ;\ 536 ldx [%sp + V9BIAS64 + 0], %l0 ;\ 537 ldx [%sp + V9BIAS64 + 8], %l1 ;\ 538 ldx [%sp + V9BIAS64 + 16], %l2 ;\ 539 ldx [%sp + V9BIAS64 + 24], %l3 ;\ 540 ldx [%sp + V9BIAS64 + 32], %l4 ;\ 541 ldx [%sp + V9BIAS64 + 40], %l5 ;\ 542 ldx [%sp + V9BIAS64 + 48], %l6 ;\ 543 ldx [%sp + V9BIAS64 + 56], %l7 ;\ 544 ldx [%sp + V9BIAS64 + 64], %i0 ;\ 545 ldx [%sp + V9BIAS64 + 72], %i1 ;\ 546 ldx [%sp + V9BIAS64 + 80], %i2 ;\ 547 ldx [%sp + V9BIAS64 + 88], %i3 ;\ 548 ldx [%sp + V9BIAS64 + 96], %i4 ;\ 549 ldx [%sp + V9BIAS64 + 104], %i5 ;\ 550 ldx [%sp + V9BIAS64 + 112], %i6 ;\ 551 ldx [%sp + V9BIAS64 + 120], %i7 ;\ 552 restored ;\ 553 retry ;\ 554 SKIP(31-18-TT_TRACE_L_INS) ;\ 555 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 556 .empty 557 558/* 559 * FILL_64bit_asi fills a 64-bit-wide register window from a 64-bit 560 * wide address space via the designated asi. It is used to fill 561 * non-kernel windows. The stack pointer is required to be eight-byte 562 * aligned. 563 */ 564#define FILL_64bit_asi(asi_num, tail) \ 565 mov V9BIAS64 + 0, %g1 ;\ 5662: TT_TRACE_L(trace_win) ;\ 567 ldxa [%sp + %g1]asi_num, %l0 ;\ 568 mov V9BIAS64 + 8, %g2 ;\ 569 ldxa [%sp + %g2]asi_num, %l1 ;\ 570 mov V9BIAS64 + 16, %g3 ;\ 571 ldxa [%sp + %g3]asi_num, %l2 ;\ 572 mov V9BIAS64 + 24, %g4 ;\ 573 ldxa [%sp + %g4]asi_num, %l3 ;\ 574 add %sp, 32, %g5 ;\ 575 ldxa [%g5 + %g1]asi_num, %l4 ;\ 576 ldxa [%g5 + %g2]asi_num, %l5 ;\ 577 ldxa [%g5 + %g3]asi_num, %l6 ;\ 578 ldxa [%g5 + %g4]asi_num, %l7 ;\ 579 add %g5, 32, %g5 ;\ 580 ldxa [%g5 + %g1]asi_num, %i0 ;\ 581 ldxa [%g5 + %g2]asi_num, %i1 ;\ 582 ldxa [%g5 + %g3]asi_num, %i2 ;\ 583 ldxa [%g5 + %g4]asi_num, %i3 ;\ 584 add %g5, 32, %g5 ;\ 585 ldxa [%g5 + %g1]asi_num, %i4 ;\ 586 ldxa [%g5 + %g2]asi_num, %i5 ;\ 587 ldxa [%g5 + %g3]asi_num, %i6 ;\ 588 ldxa [%g5 + %g4]asi_num, %i7 ;\ 589 restored ;\ 590 retry ;\ 591 SKIP(31-25-TT_TRACE_L_INS) ;\ 592 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 593 .empty 594 595 596#endif /* !lint */ 597 598/* 599 * SPILL_mixed spills either size window, depending on 600 * whether %sp is even or odd, to a 32-bit address space. 601 * This may only be used in conjunction with SPILL_32bit/ 602 * FILL_64bit. 603 * Clear upper 32 bits of %sp if it is odd. 604 * We won't need to clear them in 64 bit kernel. 605 */ 606#define SPILL_mixed \ 607 btst 1, %sp ;\ 608 bz,a,pt %xcc, 1b ;\ 609 srl %sp, 0, %sp ;\ 610 ba,pt %xcc, 2b ;\ 611 nop ;\ 612 .align 128 613 614/* 615 * FILL_mixed(ASI) fills either size window, depending on 616 * whether %sp is even or odd, from a 32-bit address space. 617 * This may only be used in conjunction with FILL_32bit/ 618 * FILL_64bit. New versions of FILL_mixed_{tt1,asi} would be 619 * needed for use with FILL_{32,64}bit_{tt1,asi}. Particular 620 * attention should be paid to the instructions that belong 621 * in the delay slots of the branches depending on the type 622 * of fill handler being branched to. 623 * Clear upper 32 bits of %sp if it is odd. 624 * We won't need to clear them in 64 bit kernel. 625 */ 626#define FILL_mixed \ 627 btst 1, %sp ;\ 628 bz,a,pt %xcc, 1b ;\ 629 srl %sp, 0, %sp ;\ 630 ba,pt %xcc, 2b ;\ 631 nop ;\ 632 .align 128 633 634 635/* 636 * SPILL_32clean/SPILL_64clean spill 32-bit and 64-bit register windows, 637 * respectively, into the address space via the designated asi. The 638 * unbiased stack pointer is required to be eight-byte aligned (even for 639 * the 32-bit case even though this code does not require such strict 640 * alignment). 641 * 642 * With SPARC v9 the spill trap takes precedence over the cleanwin trap 643 * so when cansave == 0, canrestore == 6, and cleanwin == 6 the next save 644 * will cause cwp + 2 to be spilled but will not clean cwp + 1. That 645 * window may contain kernel data so in user_rtt we set wstate to call 646 * these spill handlers on the first user spill trap. These handler then 647 * spill the appropriate window but also back up a window and clean the 648 * window that didn't get a cleanwin trap. 649 */ 650#define SPILL_32clean(asi_num, tail) \ 651 srl %sp, 0, %sp ;\ 652 sta %l0, [%sp + %g0]asi_num ;\ 653 mov 4, %g1 ;\ 654 sta %l1, [%sp + %g1]asi_num ;\ 655 mov 8, %g2 ;\ 656 sta %l2, [%sp + %g2]asi_num ;\ 657 mov 12, %g3 ;\ 658 sta %l3, [%sp + %g3]asi_num ;\ 659 add %sp, 16, %g4 ;\ 660 sta %l4, [%g4 + %g0]asi_num ;\ 661 sta %l5, [%g4 + %g1]asi_num ;\ 662 sta %l6, [%g4 + %g2]asi_num ;\ 663 sta %l7, [%g4 + %g3]asi_num ;\ 664 add %g4, 16, %g4 ;\ 665 sta %i0, [%g4 + %g0]asi_num ;\ 666 sta %i1, [%g4 + %g1]asi_num ;\ 667 sta %i2, [%g4 + %g2]asi_num ;\ 668 sta %i3, [%g4 + %g3]asi_num ;\ 669 add %g4, 16, %g4 ;\ 670 sta %i4, [%g4 + %g0]asi_num ;\ 671 sta %i5, [%g4 + %g1]asi_num ;\ 672 sta %i6, [%g4 + %g2]asi_num ;\ 673 sta %i7, [%g4 + %g3]asi_num ;\ 674 TT_TRACE_L(trace_win) ;\ 675 b .spill_clean ;\ 676 mov WSTATE_USER32, %g7 ;\ 677 SKIP(31-25-TT_TRACE_L_INS) ;\ 678 ba,a,pt %xcc, fault_32bit_/**/tail ;\ 679 .empty 680 681#define SPILL_64clean(asi_num, tail) \ 682 mov 0 + V9BIAS64, %g1 ;\ 683 stxa %l0, [%sp + %g1]asi_num ;\ 684 mov 8 + V9BIAS64, %g2 ;\ 685 stxa %l1, [%sp + %g2]asi_num ;\ 686 mov 16 + V9BIAS64, %g3 ;\ 687 stxa %l2, [%sp + %g3]asi_num ;\ 688 mov 24 + V9BIAS64, %g4 ;\ 689 stxa %l3, [%sp + %g4]asi_num ;\ 690 add %sp, 32, %g5 ;\ 691 stxa %l4, [%g5 + %g1]asi_num ;\ 692 stxa %l5, [%g5 + %g2]asi_num ;\ 693 stxa %l6, [%g5 + %g3]asi_num ;\ 694 stxa %l7, [%g5 + %g4]asi_num ;\ 695 add %g5, 32, %g5 ;\ 696 stxa %i0, [%g5 + %g1]asi_num ;\ 697 stxa %i1, [%g5 + %g2]asi_num ;\ 698 stxa %i2, [%g5 + %g3]asi_num ;\ 699 stxa %i3, [%g5 + %g4]asi_num ;\ 700 add %g5, 32, %g5 ;\ 701 stxa %i4, [%g5 + %g1]asi_num ;\ 702 stxa %i5, [%g5 + %g2]asi_num ;\ 703 stxa %i6, [%g5 + %g3]asi_num ;\ 704 stxa %i7, [%g5 + %g4]asi_num ;\ 705 TT_TRACE_L(trace_win) ;\ 706 b .spill_clean ;\ 707 mov WSTATE_USER64, %g7 ;\ 708 SKIP(31-25-TT_TRACE_L_INS) ;\ 709 ba,a,pt %xcc, fault_64bit_/**/tail ;\ 710 .empty 711 712 713/* 714 * Floating point disabled. 715 */ 716#define FP_DISABLED_TRAP \ 717 TT_TRACE(trace_gen) ;\ 718 ba,pt %xcc,.fp_disabled ;\ 719 nop ;\ 720 .align 32 721 722/* 723 * Floating point exceptions. 724 */ 725#define FP_IEEE_TRAP \ 726 TT_TRACE(trace_gen) ;\ 727 ba,pt %xcc,.fp_ieee_exception ;\ 728 nop ;\ 729 .align 32 730 731#define FP_TRAP \ 732 TT_TRACE(trace_gen) ;\ 733 ba,pt %xcc,.fp_exception ;\ 734 nop ;\ 735 .align 32 736 737#if !defined(lint) 738 739/* 740 * ECACHE_ECC error traps at level 0 and level 1 741 */ 742#define ECACHE_ECC(table_name) \ 743 .global table_name ;\ 744table_name: ;\ 745 membar #Sync ;\ 746 set trap, %g1 ;\ 747 rdpr %tt, %g3 ;\ 748 ba,pt %xcc, sys_trap ;\ 749 sub %g0, 1, %g4 ;\ 750 .align 32 751 752#endif /* !lint */ 753 754/* 755 * illegal instruction trap 756 */ 757#define ILLTRAP_INSTR \ 758 membar #Sync ;\ 759 TT_TRACE(trace_gen) ;\ 760 or %g0, P_UTRAP4, %g2 ;\ 761 or %g0, T_UNIMP_INSTR, %g3 ;\ 762 sethi %hi(.check_v9utrap), %g4 ;\ 763 jmp %g4 + %lo(.check_v9utrap) ;\ 764 nop ;\ 765 .align 32 766 767/* 768 * tag overflow trap 769 */ 770#define TAG_OVERFLOW \ 771 TT_TRACE(trace_gen) ;\ 772 or %g0, P_UTRAP10, %g2 ;\ 773 or %g0, T_TAG_OVERFLOW, %g3 ;\ 774 sethi %hi(.check_v9utrap), %g4 ;\ 775 jmp %g4 + %lo(.check_v9utrap) ;\ 776 nop ;\ 777 .align 32 778 779/* 780 * divide by zero trap 781 */ 782#define DIV_BY_ZERO \ 783 TT_TRACE(trace_gen) ;\ 784 or %g0, P_UTRAP11, %g2 ;\ 785 or %g0, T_IDIV0, %g3 ;\ 786 sethi %hi(.check_v9utrap), %g4 ;\ 787 jmp %g4 + %lo(.check_v9utrap) ;\ 788 nop ;\ 789 .align 32 790 791/* 792 * trap instruction for V9 user trap handlers 793 */ 794#define TRAP_INSTR \ 795 TT_TRACE(trace_gen) ;\ 796 or %g0, T_SOFTWARE_TRAP, %g3 ;\ 797 sethi %hi(.check_v9utrap), %g4 ;\ 798 jmp %g4 + %lo(.check_v9utrap) ;\ 799 nop ;\ 800 .align 32 801#define TRP4 TRAP_INSTR; TRAP_INSTR; TRAP_INSTR; TRAP_INSTR 802 803/* 804 * LEVEL_INTERRUPT is for level N interrupts. 805 * VECTOR_INTERRUPT is for the vector trap. 806 */ 807#define LEVEL_INTERRUPT(level) \ 808 .global tt_pil/**/level ;\ 809tt_pil/**/level: ;\ 810 ba,pt %xcc, pil_interrupt ;\ 811 mov level, %g4 ;\ 812 .align 32 813 814#define LEVEL14_INTERRUPT \ 815 ba pil14_interrupt ;\ 816 mov PIL_14, %g4 ;\ 817 .align 32 818 819#define CPU_MONDO \ 820 ba,a,pt %xcc, cpu_mondo ;\ 821 .align 32 822 823#define DEV_MONDO \ 824 ba,a,pt %xcc, dev_mondo ;\ 825 .align 32 826 827/* 828 * MMU Trap Handlers. 829 */ 830#define SFSR_CTX_SHIFT 16 831 832#define IMMU_EXCEPTION \ 833 MMU_FAULT_STATUS_AREA(%g3) ;\ 834 rdpr %tpc, %g2 ;\ 835 ldx [%g3 + MMFSA_I_TYPE], %g1 ;\ 836 ldx [%g3 + MMFSA_I_CTX], %g3 ;\ 837 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 838 or %g3, %g1, %g3 ;\ 839 ba,pt %xcc, .mmu_exception_end ;\ 840 mov T_INSTR_EXCEPTION, %g1 ;\ 841 .align 32 842 843#define DMMU_EXCEPTION \ 844 MMU_FAULT_STATUS_AREA(%g3) ;\ 845 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\ 846 ldx [%g3 + MMFSA_D_TYPE], %g1 ;\ 847 ldx [%g3 + MMFSA_D_CTX], %g3 ;\ 848 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 849 or %g3, %g1, %g3 ;\ 850 ba,pt %xcc, .mmu_exception_end ;\ 851 mov T_DATA_EXCEPTION, %g1 ;\ 852 .align 32 853 854#define DMMU_EXC_AG_PRIV \ 855 MMU_FAULT_STATUS_AREA(%g3) ;\ 856 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\ 857 /* Fault type not available in MMU fault status area */ ;\ 858 mov MMFSA_F_PRVACT, %g1 ;\ 859 ldx [%g3 + MMFSA_D_CTX], %g3 ;\ 860 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 861 ba,pt %xcc, .mmu_priv_exception ;\ 862 or %g3, %g1, %g3 ;\ 863 .align 32 864 865#define DMMU_EXC_AG_NOT_ALIGNED \ 866 MMU_FAULT_STATUS_AREA(%g3) ;\ 867 ldx [%g3 + MMFSA_D_ADDR], %g2 ;\ 868 /* Fault type not available in MMU fault status area */ ;\ 869 mov MMFSA_F_UNALIGN, %g1 ;\ 870 ldx [%g3 + MMFSA_D_CTX], %g3 ;\ 871 sllx %g3, SFSR_CTX_SHIFT, %g3 ;\ 872 ba,pt %xcc, .mmu_exception_not_aligned ;\ 873 or %g3, %g1, %g3 ;\ 874 .align 32 875/* 876 * SPARC V9 IMPL. DEP. #109(1) and (2) and #110(1) and (2) 877 */ 878 879#define DMMU_EXC_LDDF_NOT_ALIGNED \ 880 ba,a,pt %xcc, .dmmu_exc_lddf_not_aligned ;\ 881 .align 32 882#define DMMU_EXC_STDF_NOT_ALIGNED \ 883 ba,a,pt %xcc, .dmmu_exc_stdf_not_aligned ;\ 884 .align 32 885 886#if TAGACC_CTX_MASK != CTXREG_CTX_MASK 887#error "TAGACC_CTX_MASK != CTXREG_CTX_MASK" 888#endif 889 890#if defined(cscope) 891/* 892 * Define labels to direct cscope quickly to labels that 893 * are generated by macro expansion of DTLB_MISS(). 894 */ 895 .global tt0_dtlbmiss 896tt0_dtlbmiss: 897 .global tt1_dtlbmiss 898tt1_dtlbmiss: 899 nop 900#endif 901 902/* 903 * Data miss handler (must be exactly 32 instructions) 904 * 905 * This handler is invoked only if the hypervisor has been instructed 906 * not to do any TSB walk. 907 * 908 * Kernel and invalid context cases are handled by the sfmmu_kdtlb_miss 909 * handler. 910 * 911 * User TLB miss handling depends upon whether a user process has one or 912 * two TSBs. User TSB information (physical base and size code) is kept 913 * in two dedicated scratchpad registers. Absence of a user TSB (primarily 914 * second TSB) is indicated by a negative value (-1) in that register. 915 */ 916 917#define DTLB_MISS(table_name) ;\ 918 .global table_name/**/_dtlbmiss ;\ 919table_name/**/_dtlbmiss: ;\ 920 HAT_PERCPU_DBSTAT(TSBMISS_DTLBMISS) /* 3 instr ifdef DEBUG */ ;\ 921 MMU_FAULT_STATUS_AREA(%g7) ;\ 922 ldx [%g7 + MMFSA_D_ADDR], %g2 /* address */ ;\ 923 ldx [%g7 + MMFSA_D_CTX], %g3 /* g3 = ctx */ ;\ 924 or %g2, %g3, %g2 /* XXXQ temp */ ;\ 925 cmp %g3, INVALID_CONTEXT ;\ 926 ble,pn %xcc, sfmmu_kdtlb_miss ;\ 927 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 928 mov SCRATCHPAD_UTSBREG2, %g1 ;\ 929 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\ 930 brgez,pn %g1, sfmmu_udtlb_slowpath /* brnach if 2 TSBs */ ;\ 931 nop ;\ 932 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\ 933 ba,pt %xcc, sfmmu_udtlb_fastpath /* no 4M TSB, miss */ ;\ 934 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 935 .align 128 936 937 938#if defined(cscope) 939/* 940 * Define labels to direct cscope quickly to labels that 941 * are generated by macro expansion of ITLB_MISS(). 942 */ 943 .global tt0_itlbmiss 944tt0_itlbmiss: 945 .global tt1_itlbmiss 946tt1_itlbmiss: 947 nop 948#endif 949 950/* 951 * Instruction miss handler. 952 * 953 * This handler is invoked only if the hypervisor has been instructed 954 * not to do any TSB walk. 955 * 956 * ldda instructions will have their ASI patched 957 * by sfmmu_patch_ktsb at runtime. 958 * MUST be EXACTLY 32 instructions or we'll break. 959 */ 960 961#define ITLB_MISS(table_name) \ 962 .global table_name/**/_itlbmiss ;\ 963table_name/**/_itlbmiss: ;\ 964 HAT_PERCPU_DBSTAT(TSBMISS_ITLBMISS) /* 3 instr ifdef DEBUG */ ;\ 965 MMU_FAULT_STATUS_AREA(%g7) ;\ 966 ldx [%g7 + MMFSA_I_ADDR], %g2 /* g2 = address */ ;\ 967 ldx [%g7 + MMFSA_I_CTX], %g3 /* g3 = ctx */ ;\ 968 or %g2, %g3, %g2 /* XXXQ temp */ ;\ 969 cmp %g3, INVALID_CONTEXT ;\ 970 ble,pn %xcc, sfmmu_kitlb_miss ;\ 971 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 972 mov SCRATCHPAD_UTSBREG2, %g1 ;\ 973 ldxa [%g1]ASI_SCRATCHPAD, %g1 /* get 2nd tsbreg */ ;\ 974 brgez,pn %g1, sfmmu_uitlb_slowpath /* branch if 2 TSBS */ ;\ 975 nop ;\ 976 GET_1ST_TSBE_PTR(%g2, %g1, %g4, %g5) /* 11 instr */ ;\ 977 ba,pt %xcc, sfmmu_uitlb_fastpath /* no 4M TSB, miss */ ;\ 978 srlx %g2, TAG_VALO_SHIFT, %g7 /* g7 = tsb tag */ ;\ 979 .align 128 980 981#define DTSB_MISS \ 982 GOTO_TT(sfmmu_slow_dmmu_miss,trace_dmmu) 983 984#define ITSB_MISS \ 985 GOTO_TT(sfmmu_slow_immu_miss,trace_immu) 986 987/* 988 * This macro is the first level handler for fast protection faults. 989 * It first demaps the tlb entry which generated the fault and then 990 * attempts to set the modify bit on the hash. It needs to be 991 * exactly 32 instructions. 992 */ 993#define DTLB_PROT \ 994 MMU_FAULT_STATUS_AREA(%g7) ;\ 995 ldx [%g7 + MMFSA_D_ADDR], %g2 /* address */ ;\ 996 ldx [%g7 + MMFSA_D_CTX], %g3 /* %g3 = ctx */ ;\ 997 or %g2, %g3, %g2 /* XXXQ temp */ ;\ 998 /* ;\ 999 * g2 = tag access register ;\ 1000 * g3 = ctx number ;\ 1001 */ ;\ 1002 TT_TRACE(trace_dataprot) /* 2 instr ifdef TRAPTRACE */ ;\ 1003 /* clobbers g1 and g6 XXXQ? */ ;\ 1004 brnz,pt %g3, sfmmu_uprot_trap /* user trap */ ;\ 1005 nop ;\ 1006 ba,a,pt %xcc, sfmmu_kprot_trap /* kernel trap */ ;\ 1007 .align 128 1008 1009#define DMMU_EXCEPTION_TL1 ;\ 1010 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1011 .align 32 1012 1013#define MISALIGN_ADDR_TL1 ;\ 1014 ba,a,pt %xcc, mmu_trap_tl1 ;\ 1015 .align 32 1016 1017/* 1018 * Trace a tsb hit 1019 * g1 = tsbe pointer (in/clobbered) 1020 * g2 = tag access register (in) 1021 * g3 - g4 = scratch (clobbered) 1022 * g5 = tsbe data (in) 1023 * g6 = scratch (clobbered) 1024 * g7 = pc we jumped here from (in) 1025 * ttextra = value to OR in to trap type (%tt) (in) 1026 */ 1027#ifdef TRAPTRACE 1028#define TRACE_TSBHIT(ttextra) \ 1029 membar #Sync ;\ 1030 sethi %hi(FLUSH_ADDR), %g6 ;\ 1031 flush %g6 ;\ 1032 TRACE_PTR(%g3, %g6) ;\ 1033 GET_TRACE_TICK(%g6) ;\ 1034 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi ;\ 1035 stna %g2, [%g3 + TRAP_ENT_SP]%asi /* tag access */ ;\ 1036 stna %g5, [%g3 + TRAP_ENT_F1]%asi /* tsb data */ ;\ 1037 rdpr %tnpc, %g6 ;\ 1038 stna %g6, [%g3 + TRAP_ENT_F2]%asi ;\ 1039 stna %g1, [%g3 + TRAP_ENT_F3]%asi /* tsb pointer */ ;\ 1040 stna %g0, [%g3 + TRAP_ENT_F4]%asi ;\ 1041 rdpr %tpc, %g6 ;\ 1042 stna %g6, [%g3 + TRAP_ENT_TPC]%asi ;\ 1043 TRACE_SAVE_TL_GL_REGS(%g3, %g6) ;\ 1044 rdpr %tt, %g6 ;\ 1045 or %g6, (ttextra), %g1 ;\ 1046 stha %g1, [%g3 + TRAP_ENT_TT]%asi ;\ 1047 MMU_FAULT_STATUS_AREA(%g4) ;\ 1048 ldx [%g4 + MMFSA_I_ADDR], %g1 ;\ 1049 ldx [%g4 + MMFSA_D_ADDR], %g4 ;\ 1050 cmp %g6, FAST_IMMU_MISS_TT ;\ 1051 move %icc, %g1, %g4 ;\ 1052 cmp %g6, T_INSTR_MMU_MISS ;\ 1053 move %icc, %g1, %g4 ;\ 1054 stxa %g4, [%g3 + TRAP_ENT_TSTATE]%asi /* fault addr */ ;\ 1055 MMU_FAULT_STATUS_AREA(%g4) ;\ 1056 ldx [%g4 + MMFSA_I_CTX], %g1 ;\ 1057 ldx [%g4 + MMFSA_D_CTX], %g4 ;\ 1058 cmp %g6, FAST_IMMU_MISS_TT ;\ 1059 move %icc, %g1, %g4 ;\ 1060 cmp %g6, T_INSTR_MMU_MISS ;\ 1061 move %icc, %g1, %g4 ;\ 1062 stna %g4, [%g3 + TRAP_ENT_TR]%asi ;\ 1063 TRACE_NEXT(%g3, %g4, %g6) 1064#else 1065#define TRACE_TSBHIT(ttextra) 1066#endif 1067 1068 1069#if defined(lint) 1070 1071struct scb trap_table; 1072struct scb scb; /* trap_table/scb are the same object */ 1073 1074#else /* lint */ 1075 1076/* 1077 * ======================================================================= 1078 * SPARC V9 TRAP TABLE 1079 * 1080 * The trap table is divided into two halves: the first half is used when 1081 * taking traps when TL=0; the second half is used when taking traps from 1082 * TL>0. Note that handlers in the second half of the table might not be able 1083 * to make the same assumptions as handlers in the first half of the table. 1084 * 1085 * Worst case trap nesting so far: 1086 * 1087 * at TL=0 client issues software trap requesting service 1088 * at TL=1 nucleus wants a register window 1089 * at TL=2 register window clean/spill/fill takes a TLB miss 1090 * at TL=3 processing TLB miss 1091 * at TL=4 handle asynchronous error 1092 * 1093 * Note that a trap from TL=4 to TL=5 places Spitfire in "RED mode". 1094 * 1095 * ======================================================================= 1096 */ 1097 .section ".text" 1098 .align 4 1099 .global trap_table, scb, trap_table0, trap_table1, etrap_table 1100 .type trap_table, #function 1101 .type trap_table0, #function 1102 .type trap_table1, #function 1103 .type scb, #function 1104trap_table: 1105scb: 1106trap_table0: 1107 /* hardware traps */ 1108 NOT; /* 000 reserved */ 1109 RED; /* 001 power on reset */ 1110 RED; /* 002 watchdog reset */ 1111 RED; /* 003 externally initiated reset */ 1112 RED; /* 004 software initiated reset */ 1113 RED; /* 005 red mode exception */ 1114 NOT; NOT; /* 006 - 007 reserved */ 1115 IMMU_EXCEPTION; /* 008 instruction access exception */ 1116 ITSB_MISS; /* 009 instruction access MMU miss */ 1117 NOT; /* 00A reserved */ 1118 NOT; NOT4; /* 00B - 00F reserved */ 1119 ILLTRAP_INSTR; /* 010 illegal instruction */ 1120 TRAP(T_PRIV_INSTR); /* 011 privileged opcode */ 1121 NOT; /* 012 unimplemented LDD */ 1122 NOT; /* 013 unimplemented STD */ 1123 NOT4; NOT4; NOT4; /* 014 - 01F reserved */ 1124 FP_DISABLED_TRAP; /* 020 fp disabled */ 1125 FP_IEEE_TRAP; /* 021 fp exception ieee 754 */ 1126 FP_TRAP; /* 022 fp exception other */ 1127 TAG_OVERFLOW; /* 023 tag overflow */ 1128 CLEAN_WINDOW; /* 024 - 027 clean window */ 1129 DIV_BY_ZERO; /* 028 division by zero */ 1130 NOT; /* 029 internal processor error */ 1131 NOT; NOT; NOT4; /* 02A - 02F reserved */ 1132 DMMU_EXCEPTION; /* 030 data access exception */ 1133 DTSB_MISS; /* 031 data access MMU miss */ 1134 NOT; /* 032 reserved */ 1135 NOT; /* 033 data access protection */ 1136 DMMU_EXC_AG_NOT_ALIGNED; /* 034 mem address not aligned */ 1137 DMMU_EXC_LDDF_NOT_ALIGNED; /* 035 LDDF mem address not aligned */ 1138 DMMU_EXC_STDF_NOT_ALIGNED; /* 036 STDF mem address not aligned */ 1139 DMMU_EXC_AG_PRIV; /* 037 privileged action */ 1140 NOT; /* 038 LDQF mem address not aligned */ 1141 NOT; /* 039 STQF mem address not aligned */ 1142 NOT; NOT; NOT4; /* 03A - 03F reserved */ 1143 NOT; /* 040 async data error */ 1144 LEVEL_INTERRUPT(1); /* 041 interrupt level 1 */ 1145 LEVEL_INTERRUPT(2); /* 042 interrupt level 2 */ 1146 LEVEL_INTERRUPT(3); /* 043 interrupt level 3 */ 1147 LEVEL_INTERRUPT(4); /* 044 interrupt level 4 */ 1148 LEVEL_INTERRUPT(5); /* 045 interrupt level 5 */ 1149 LEVEL_INTERRUPT(6); /* 046 interrupt level 6 */ 1150 LEVEL_INTERRUPT(7); /* 047 interrupt level 7 */ 1151 LEVEL_INTERRUPT(8); /* 048 interrupt level 8 */ 1152 LEVEL_INTERRUPT(9); /* 049 interrupt level 9 */ 1153 LEVEL_INTERRUPT(10); /* 04A interrupt level 10 */ 1154 LEVEL_INTERRUPT(11); /* 04B interrupt level 11 */ 1155 LEVEL_INTERRUPT(12); /* 04C interrupt level 12 */ 1156 LEVEL_INTERRUPT(13); /* 04D interrupt level 13 */ 1157 LEVEL14_INTERRUPT; /* 04E interrupt level 14 */ 1158 LEVEL_INTERRUPT(15); /* 04F interrupt level 15 */ 1159 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F reserved */ 1160 NOT; /* 060 interrupt vector */ 1161 GOTO(kmdb_trap); /* 061 PA watchpoint */ 1162 GOTO(kmdb_trap); /* 062 VA watchpoint */ 1163 NOT; /* 063 reserved */ 1164 ITLB_MISS(tt0); /* 064 instruction access MMU miss */ 1165 DTLB_MISS(tt0); /* 068 data access MMU miss */ 1166 DTLB_PROT; /* 06C data access protection */ 1167 NOT; /* 070 reserved */ 1168 NOT; /* 071 reserved */ 1169 NOT; /* 072 reserved */ 1170 NOT; /* 073 reserved */ 1171 NOT4; NOT4 /* 074 - 07B reserved */ 1172 CPU_MONDO; /* 07C cpu_mondo */ 1173 DEV_MONDO; /* 07D dev_mondo */ 1174 GOTO_TT(resumable_error, trace_gen); /* 07E resumable error */ 1175 GOTO_TT(nonresumable_error, trace_gen); /* 07F non-reasumable error */ 1176 NOT4; /* 080 spill 0 normal */ 1177 SPILL_32bit_asi(ASI_AIUP,sn0); /* 084 spill 1 normal */ 1178 SPILL_64bit_asi(ASI_AIUP,sn0); /* 088 spill 2 normal */ 1179 SPILL_32clean(ASI_AIUP,sn0); /* 08C spill 3 normal */ 1180 SPILL_64clean(ASI_AIUP,sn0); /* 090 spill 4 normal */ 1181 SPILL_32bit(not); /* 094 spill 5 normal */ 1182 SPILL_64bit(not); /* 098 spill 6 normal */ 1183 SPILL_mixed; /* 09C spill 7 normal */ 1184 NOT4; /* 0A0 spill 0 other */ 1185 SPILL_32bit_asi(ASI_AIUS,so0); /* 0A4 spill 1 other */ 1186 SPILL_64bit_asi(ASI_AIUS,so0); /* 0A8 spill 2 other */ 1187 SPILL_32bit_asi(ASI_AIUS,so0); /* 0AC spill 3 other */ 1188 SPILL_64bit_asi(ASI_AIUS,so0); /* 0B0 spill 4 other */ 1189 NOT4; /* 0B4 spill 5 other */ 1190 NOT4; /* 0B8 spill 6 other */ 1191 NOT4; /* 0BC spill 7 other */ 1192 NOT4; /* 0C0 fill 0 normal */ 1193 FILL_32bit_asi(ASI_AIUP,fn0); /* 0C4 fill 1 normal */ 1194 FILL_64bit_asi(ASI_AIUP,fn0); /* 0C8 fill 2 normal */ 1195 FILL_32bit_asi(ASI_AIUP,fn0); /* 0CC fill 3 normal */ 1196 FILL_64bit_asi(ASI_AIUP,fn0); /* 0D0 fill 4 normal */ 1197 FILL_32bit(not); /* 0D4 fill 5 normal */ 1198 FILL_64bit(not); /* 0D8 fill 6 normal */ 1199 FILL_mixed; /* 0DC fill 7 normal */ 1200 NOT4; /* 0E0 fill 0 other */ 1201 NOT4; /* 0E4 fill 1 other */ 1202 NOT4; /* 0E8 fill 2 other */ 1203 NOT4; /* 0EC fill 3 other */ 1204 NOT4; /* 0F0 fill 4 other */ 1205 NOT4; /* 0F4 fill 5 other */ 1206 NOT4; /* 0F8 fill 6 other */ 1207 NOT4; /* 0FC fill 7 other */ 1208 /* user traps */ 1209 GOTO(syscall_trap_4x); /* 100 old system call */ 1210 TRAP(T_BREAKPOINT); /* 101 user breakpoint */ 1211 TRAP(T_DIV0); /* 102 user divide by zero */ 1212 GOTO(.flushw); /* 103 flush windows */ 1213 GOTO(.clean_windows); /* 104 clean windows */ 1214 BAD; /* 105 range check ?? */ 1215 GOTO(.fix_alignment); /* 106 do unaligned references */ 1216 BAD; /* 107 unused */ 1217 SYSCALL(syscall_trap32); /* 108 ILP32 system call on LP64 */ 1218 GOTO(set_trap0_addr); /* 109 set trap0 address */ 1219 BAD; BAD; BAD4; /* 10A - 10F unused */ 1220 TRP4; TRP4; TRP4; TRP4; /* 110 - 11F V9 user trap handlers */ 1221 GOTO(.getcc); /* 120 get condition codes */ 1222 GOTO(.setcc); /* 121 set condition codes */ 1223 GOTO(.getpsr); /* 122 get psr */ 1224 GOTO(.setpsr); /* 123 set psr (some fields) */ 1225 GOTO(get_timestamp); /* 124 get timestamp */ 1226 GOTO(get_virtime); /* 125 get lwp virtual time */ 1227 PRIV(self_xcall); /* 126 self xcall */ 1228 GOTO(get_hrestime); /* 127 get hrestime */ 1229 BAD; /* 128 ST_SETV9STACK */ 1230 GOTO(.getlgrp); /* 129 get lgrpid */ 1231 BAD; BAD; BAD4; /* 12A - 12F unused */ 1232 BAD4; BAD4; /* 130 - 137 unused */ 1233 DTRACE_PID; /* 138 dtrace pid tracing provider */ 1234 DTRACE_FASTTRAP; /* 139 dtrace fasttrap provider */ 1235 DTRACE_RETURN; /* 13A dtrace pid return probe */ 1236 BAD; BAD4; /* 13B - 13F unused */ 1237 SYSCALL(syscall_trap) /* 140 LP64 system call */ 1238 BAD; /* 141 unused */ 1239#ifdef DEBUG_USER_TRAPTRACECTL 1240 GOTO(.traptrace_freeze); /* 142 freeze traptrace */ 1241 GOTO(.traptrace_unfreeze); /* 143 unfreeze traptrace */ 1242#else 1243 BAD; BAD; /* 142 - 143 unused */ 1244#endif 1245 BAD4; BAD4; BAD4; /* 144 - 14F unused */ 1246 BAD4; BAD4; BAD4; BAD4; /* 150 - 15F unused */ 1247 BAD4; BAD4; BAD4; BAD4; /* 160 - 16F unused */ 1248 BAD; /* 170 - unused */ 1249 BAD; /* 171 - unused */ 1250 BAD; BAD; /* 172 - 173 unused */ 1251 BAD4; BAD4; /* 174 - 17B unused */ 1252#ifdef PTL1_PANIC_DEBUG 1253 mov PTL1_BAD_DEBUG, %g1; GOTO(ptl1_panic); 1254 /* 17C test ptl1_panic */ 1255#else 1256 BAD; /* 17C unused */ 1257#endif /* PTL1_PANIC_DEBUG */ 1258 PRIV(kmdb_trap); /* 17D kmdb enter (L1-A) */ 1259 PRIV(kmdb_trap); /* 17E kmdb breakpoint */ 1260 PRIV(obp_bpt); /* 17F obp breakpoint */ 1261 /* reserved */ 1262 NOT4; NOT4; NOT4; NOT4; /* 180 - 18F reserved */ 1263 NOT4; NOT4; NOT4; NOT4; /* 190 - 19F reserved */ 1264 NOT4; NOT4; NOT4; NOT4; /* 1A0 - 1AF reserved */ 1265 NOT4; NOT4; NOT4; NOT4; /* 1B0 - 1BF reserved */ 1266 NOT4; NOT4; NOT4; NOT4; /* 1C0 - 1CF reserved */ 1267 NOT4; NOT4; NOT4; NOT4; /* 1D0 - 1DF reserved */ 1268 NOT4; NOT4; NOT4; NOT4; /* 1E0 - 1EF reserved */ 1269 NOT4; NOT4; NOT4; NOT4; /* 1F0 - 1FF reserved */ 1270 .size trap_table0, (.-trap_table0) 1271trap_table1: 1272 NOT4; NOT4; /* 000 - 007 unused */ 1273 NOT; /* 008 instruction access exception */ 1274 ITSB_MISS; /* 009 instruction access MMU miss */ 1275 NOT; /* 00A reserved */ 1276 NOT; NOT4; /* 00B - 00F unused */ 1277 NOT4; NOT4; NOT4; NOT4; /* 010 - 01F unused */ 1278 NOT4; /* 020 - 023 unused */ 1279 CLEAN_WINDOW; /* 024 - 027 clean window */ 1280 NOT4; NOT4; /* 028 - 02F unused */ 1281 DMMU_EXCEPTION_TL1; /* 030 data access exception */ 1282 DTSB_MISS; /* 031 data access MMU miss */ 1283 NOT; /* 032 reserved */ 1284 NOT; /* 033 unused */ 1285 MISALIGN_ADDR_TL1; /* 034 mem address not aligned */ 1286 NOT; NOT; NOT; NOT4; NOT4 /* 035 - 03F unused */ 1287 NOT4; NOT4; NOT4; NOT4; /* 040 - 04F unused */ 1288 NOT4; NOT4; NOT4; NOT4; /* 050 - 05F unused */ 1289 NOT; /* 060 unused */ 1290 GOTO(kmdb_trap_tl1); /* 061 PA watchpoint */ 1291 GOTO(kmdb_trap_tl1); /* 062 VA watchpoint */ 1292 NOT; /* 063 reserved */ 1293 ITLB_MISS(tt1); /* 064 instruction access MMU miss */ 1294 DTLB_MISS(tt1); /* 068 data access MMU miss */ 1295 DTLB_PROT; /* 06C data access protection */ 1296 NOT; /* 070 reserved */ 1297 NOT; /* 071 reserved */ 1298 NOT; /* 072 reserved */ 1299 NOT; /* 073 reserved */ 1300 NOT4; NOT4; NOT4; /* 074 - 07F reserved */ 1301 NOTP4; /* 080 spill 0 normal */ 1302 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 084 spill 1 normal */ 1303 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 088 spill 2 normal */ 1304 SPILL_32bit_tt1(ASI_AIUP,sn1); /* 08C spill 3 normal */ 1305 SPILL_64bit_tt1(ASI_AIUP,sn1); /* 090 spill 4 normal */ 1306 NOTP4; /* 094 spill 5 normal */ 1307 SPILL_64bit_ktt1(sk); /* 098 spill 6 normal */ 1308 SPILL_mixed_ktt1(sk); /* 09C spill 7 normal */ 1309 NOTP4; /* 0A0 spill 0 other */ 1310 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0A4 spill 1 other */ 1311 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0A8 spill 2 other */ 1312 SPILL_32bit_tt1(ASI_AIUS,so1); /* 0AC spill 3 other */ 1313 SPILL_64bit_tt1(ASI_AIUS,so1); /* 0B0 spill 4 other */ 1314 NOTP4; /* 0B4 spill 5 other */ 1315 NOTP4; /* 0B8 spill 6 other */ 1316 NOTP4; /* 0BC spill 7 other */ 1317 NOT4; /* 0C0 fill 0 normal */ 1318 NOT4; /* 0C4 fill 1 normal */ 1319 NOT4; /* 0C8 fill 2 normal */ 1320 NOT4; /* 0CC fill 3 normal */ 1321 NOT4; /* 0D0 fill 4 normal */ 1322 NOT4; /* 0D4 fill 5 normal */ 1323 NOT4; /* 0D8 fill 6 normal */ 1324 NOT4; /* 0DC fill 7 normal */ 1325 NOT4; NOT4; NOT4; NOT4; /* 0E0 - 0EF unused */ 1326 NOT4; NOT4; NOT4; NOT4; /* 0F0 - 0FF unused */ 1327/* 1328 * Code running at TL>0 does not use soft traps, so 1329 * we can truncate the table here. 1330 * However: 1331 * sun4v uses (hypervisor) ta instructions at TL > 0, so 1332 * provide a safety net for now. 1333 */ 1334 /* soft traps */ 1335 BAD4; BAD4; BAD4; BAD4; /* 100 - 10F unused */ 1336 BAD4; BAD4; BAD4; BAD4; /* 110 - 11F unused */ 1337 BAD4; BAD4; BAD4; BAD4; /* 120 - 12F unused */ 1338 BAD4; BAD4; BAD4; BAD4; /* 130 - 13F unused */ 1339 BAD4; BAD4; BAD4; BAD4; /* 140 - 14F unused */ 1340 BAD4; BAD4; BAD4; BAD4; /* 150 - 15F unused */ 1341 BAD4; BAD4; BAD4; BAD4; /* 160 - 16F unused */ 1342 BAD4; BAD4; BAD4; BAD4; /* 170 - 17F unused */ 1343 /* reserved */ 1344 NOT4; NOT4; NOT4; NOT4; /* 180 - 18F reserved */ 1345 NOT4; NOT4; NOT4; NOT4; /* 190 - 19F reserved */ 1346 NOT4; NOT4; NOT4; NOT4; /* 1A0 - 1AF reserved */ 1347 NOT4; NOT4; NOT4; NOT4; /* 1B0 - 1BF reserved */ 1348 NOT4; NOT4; NOT4; NOT4; /* 1C0 - 1CF reserved */ 1349 NOT4; NOT4; NOT4; NOT4; /* 1D0 - 1DF reserved */ 1350 NOT4; NOT4; NOT4; NOT4; /* 1E0 - 1EF reserved */ 1351 NOT4; NOT4; NOT4; NOT4; /* 1F0 - 1FF reserved */ 1352etrap_table: 1353 .size trap_table1, (.-trap_table1) 1354 .size trap_table, (.-trap_table) 1355 .size scb, (.-scb) 1356 1357/* 1358 * We get to exec_fault in the case of an instruction miss and tte 1359 * has no execute bit set. We go to tl0 to handle it. 1360 * 1361 * g1 = tsbe pointer (in/clobbered) 1362 * g2 = tag access register (in) 1363 * g3 - g4 = scratch (clobbered) 1364 * g5 = tsbe data (in) 1365 * g6 = scratch (clobbered) 1366 * g7 = pc we jumped here from (in) 1367 */ 1368 ALTENTRY(exec_fault) 1369 TRACE_TSBHIT(TT_MMU_EXEC) 1370 MMU_FAULT_STATUS_AREA(%g4) 1371 ldx [%g4 + MMFSA_I_ADDR], %g2 /* g2 = address */ 1372 ldx [%g4 + MMFSA_I_CTX], %g3 /* g3 = ctx */ 1373 srlx %g2, MMU_PAGESHIFT, %g2 ! align address to page boundry 1374 sllx %g2, MMU_PAGESHIFT, %g2 1375 or %g2, %g3, %g2 /* XXXQ temp */ 1376 mov T_INSTR_MMU_MISS, %g3 ! arg2 = traptype 1377 set trap, %g1 1378 ba,pt %xcc, sys_trap 1379 mov -1, %g4 1380 1381.mmu_exception_not_aligned: 1382 /* %g2 = sfar, %g3 = sfsr */ 1383 rdpr %tstate, %g1 1384 btst TSTATE_PRIV, %g1 1385 bnz,pn %icc, 2f 1386 nop 1387 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1388 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1389 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1390 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1391 brz,pt %g5, 2f 1392 nop 1393 ldn [%g5 + P_UTRAP15], %g5 ! unaligned utrap? 1394 brz,pn %g5, 2f 1395 nop 1396 btst 1, %sp 1397 bz,pt %xcc, 1f ! 32 bit user program 1398 nop 1399 ba,pt %xcc, .setup_v9utrap ! 64 bit user program 1400 nop 14011: 1402 ba,pt %xcc, .setup_utrap 1403 or %g2, %g0, %g7 14042: 1405 ba,pt %xcc, .mmu_exception_end 1406 mov T_ALIGNMENT, %g1 1407 1408.mmu_priv_exception: 1409 rdpr %tstate, %g1 1410 btst TSTATE_PRIV, %g1 1411 bnz,pn %icc, 1f 1412 nop 1413 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1414 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1415 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1416 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1417 brz,pt %g5, 1f 1418 nop 1419 ldn [%g5 + P_UTRAP16], %g5 1420 brnz,pt %g5, .setup_v9utrap 1421 nop 14221: 1423 mov T_PRIV_INSTR, %g1 1424 1425.mmu_exception_end: 1426 CPU_INDEX(%g4, %g5) 1427 set cpu_core, %g5 1428 sllx %g4, CPU_CORE_SHIFT, %g4 1429 add %g4, %g5, %g4 1430 lduh [%g4 + CPUC_DTRACE_FLAGS], %g5 1431 andcc %g5, CPU_DTRACE_NOFAULT, %g0 1432 bz 1f 1433 or %g5, CPU_DTRACE_BADADDR, %g5 1434 stuh %g5, [%g4 + CPUC_DTRACE_FLAGS] 1435 done 1436 14371: 1438 sllx %g3, 32, %g3 1439 or %g3, %g1, %g3 1440 set trap, %g1 1441 ba,pt %xcc, sys_trap 1442 sub %g0, 1, %g4 1443 1444.fp_disabled: 1445 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1446 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1447 rdpr %tstate, %g4 1448 btst TSTATE_PRIV, %g4 1449 bnz,a,pn %icc, ptl1_panic 1450 mov PTL1_BAD_FPTRAP, %g1 1451 1452 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1453 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1454 brz,a,pt %g5, 2f 1455 nop 1456 ldn [%g5 + P_UTRAP7], %g5 ! fp_disabled utrap? 1457 brz,a,pn %g5, 2f 1458 nop 1459 btst 1, %sp 1460 bz,a,pt %xcc, 1f ! 32 bit user program 1461 nop 1462 ba,a,pt %xcc, .setup_v9utrap ! 64 bit user program 1463 nop 14641: 1465 ba,pt %xcc, .setup_utrap 1466 or %g0, %g0, %g7 14672: 1468 set fp_disabled, %g1 1469 ba,pt %xcc, sys_trap 1470 sub %g0, 1, %g4 1471 1472.fp_ieee_exception: 1473 rdpr %tstate, %g1 1474 btst TSTATE_PRIV, %g1 1475 bnz,a,pn %icc, ptl1_panic 1476 mov PTL1_BAD_FPTRAP, %g1 1477 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1478 stx %fsr, [%g1 + CPU_TMP1] 1479 ldx [%g1 + CPU_TMP1], %g2 1480 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1481 ldn [%g1 + T_PROCP], %g1 ! load proc pointer 1482 ldn [%g1 + P_UTRAPS], %g5 ! are there utraps? 1483 brz,a,pt %g5, 1f 1484 nop 1485 ldn [%g5 + P_UTRAP8], %g5 1486 brnz,a,pt %g5, .setup_v9utrap 1487 nop 14881: 1489 set _fp_ieee_exception, %g1 1490 ba,pt %xcc, sys_trap 1491 sub %g0, 1, %g4 1492 1493/* 1494 * Register Inputs: 1495 * %g5 user trap handler 1496 * %g7 misaligned addr - for alignment traps only 1497 */ 1498.setup_utrap: 1499 set trap, %g1 ! setup in case we go 1500 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1501 sub %g0, 1, %g4 ! the save instruction below 1502 1503 /* 1504 * If the DTrace pid provider is single stepping a copied-out 1505 * instruction, t->t_dtrace_step will be set. In that case we need 1506 * to abort the single-stepping (since execution of the instruction 1507 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1508 */ 1509 save %sp, -SA(MINFRAME32), %sp ! window for trap handler 1510 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1511 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1512 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1513 rdpr %tnpc, %l2 ! arg1 == tnpc 1514 brz,pt %g2, 1f 1515 rdpr %tpc, %l1 ! arg0 == tpc 1516 1517 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1518 ldn [%g1 + T_DTRACE_NPC], %l2 ! arg1 = t->t_dtrace_npc (step) 1519 brz,pt %g2, 1f 1520 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1521 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 15221: 1523 mov %g7, %l3 ! arg2 == misaligned address 1524 1525 rdpr %tstate, %g1 ! cwp for trap handler 1526 rdpr %cwp, %g4 1527 bclr TSTATE_CWP_MASK, %g1 1528 wrpr %g1, %g4, %tstate 1529 wrpr %g0, %g5, %tnpc ! trap handler address 1530 FAST_TRAP_DONE 1531 /* NOTREACHED */ 1532 1533.check_v9utrap: 1534 rdpr %tstate, %g1 1535 btst TSTATE_PRIV, %g1 1536 bnz,a,pn %icc, 3f 1537 nop 1538 CPU_ADDR(%g4, %g1) ! load CPU struct addr 1539 ldn [%g4 + CPU_THREAD], %g5 ! load thread pointer 1540 ldn [%g5 + T_PROCP], %g5 ! load proc pointer 1541 ldn [%g5 + P_UTRAPS], %g5 ! are there utraps? 1542 1543 cmp %g3, T_SOFTWARE_TRAP 1544 bne,a,pt %icc, 1f 1545 nop 1546 1547 brz,pt %g5, 3f ! if p_utraps == NULL goto trap() 1548 rdpr %tt, %g3 ! delay - get actual hw trap type 1549 1550 sub %g3, 254, %g1 ! UT_TRAP_INSTRUCTION_16 = p_utraps[18] 1551 ba,pt %icc, 2f 1552 smul %g1, CPTRSIZE, %g2 15531: 1554 brz,a,pt %g5, 3f ! if p_utraps == NULL goto trap() 1555 nop 1556 1557 cmp %g3, T_UNIMP_INSTR 1558 bne,a,pt %icc, 2f 1559 nop 1560 1561 mov 1, %g1 1562 st %g1, [%g4 + CPU_TL1_HDLR] ! set CPU_TL1_HDLR 1563 rdpr %tpc, %g1 ! ld trapping instruction using 1564 lduwa [%g1]ASI_AIUP, %g1 ! "AS IF USER" ASI which could fault 1565 st %g0, [%g4 + CPU_TL1_HDLR] ! clr CPU_TL1_HDLR 1566 1567 sethi %hi(0xc1c00000), %g4 ! setup mask for illtrap instruction 1568 andcc %g1, %g4, %g4 ! and instruction with mask 1569 bnz,a,pt %icc, 3f ! if %g4 == zero, %g1 is an ILLTRAP 1570 nop ! fall thru to setup 15712: 1572 ldn [%g5 + %g2], %g5 1573 brnz,a,pt %g5, .setup_v9utrap 1574 nop 15753: 1576 set trap, %g1 1577 ba,pt %xcc, sys_trap 1578 sub %g0, 1, %g4 1579 /* NOTREACHED */ 1580 1581/* 1582 * Register Inputs: 1583 * %g5 user trap handler 1584 */ 1585.setup_v9utrap: 1586 set trap, %g1 ! setup in case we go 1587 mov T_FLUSH_PCB, %g3 ! through sys_trap on 1588 sub %g0, 1, %g4 ! the save instruction below 1589 1590 /* 1591 * If the DTrace pid provider is single stepping a copied-out 1592 * instruction, t->t_dtrace_step will be set. In that case we need 1593 * to abort the single-stepping (since execution of the instruction 1594 * was interrupted) and use the value of t->t_dtrace_npc as the %npc. 1595 */ 1596 save %sp, -SA(MINFRAME64), %sp ! window for trap handler 1597 CPU_ADDR(%g1, %g4) ! load CPU struct addr 1598 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1599 ldub [%g1 + T_DTRACE_STEP], %g2 ! load t->t_dtrace_step 1600 rdpr %tnpc, %l7 ! arg1 == tnpc 1601 brz,pt %g2, 1f 1602 rdpr %tpc, %l6 ! arg0 == tpc 1603 1604 ldub [%g1 + T_DTRACE_AST], %g2 ! load t->t_dtrace_ast 1605 ldn [%g1 + T_DTRACE_NPC], %l7 ! arg1 == t->t_dtrace_npc (step) 1606 brz,pt %g2, 1f 1607 st %g0, [%g1 + T_DTRACE_FT] ! zero all pid provider flags 1608 stub %g2, [%g1 + T_ASTFLAG] ! aston(t) if t->t_dtrace_ast 16091: 1610 rdpr %tstate, %g2 ! cwp for trap handler 1611 rdpr %cwp, %g4 1612 bclr TSTATE_CWP_MASK, %g2 1613 wrpr %g2, %g4, %tstate 1614 1615 ldn [%g1 + T_PROCP], %g4 ! load proc pointer 1616 ldn [%g4 + P_AS], %g4 ! load as pointer 1617 ldn [%g4 + A_USERLIMIT], %g4 ! load as userlimit 1618 cmp %l7, %g4 ! check for single-step set 1619 bne,pt %xcc, 4f 1620 nop 1621 ldn [%g1 + T_LWP], %g1 ! load klwp pointer 1622 ld [%g1 + PCB_STEP], %g4 ! load single-step flag 1623 cmp %g4, STEP_ACTIVE ! step flags set in pcb? 1624 bne,pt %icc, 4f 1625 nop 1626 stn %g5, [%g1 + PCB_TRACEPC] ! save trap handler addr in pcb 1627 mov %l7, %g4 ! on entry to precise user trap 1628 add %l6, 4, %l7 ! handler, %l6 == pc, %l7 == npc 1629 ! at time of trap 1630 wrpr %g0, %g4, %tnpc ! generate FLTBOUNDS, 1631 ! %g4 == userlimit 1632 FAST_TRAP_DONE 1633 /* NOTREACHED */ 16344: 1635 wrpr %g0, %g5, %tnpc ! trap handler address 1636 FAST_TRAP_DONE_CHK_INTR 1637 /* NOTREACHED */ 1638 1639.fp_exception: 1640 CPU_ADDR(%g1, %g4) 1641 stx %fsr, [%g1 + CPU_TMP1] 1642 ldx [%g1 + CPU_TMP1], %g2 1643 1644 /* 1645 * Cheetah takes unfinished_FPop trap for certain range of operands 1646 * to the "fitos" instruction. Instead of going through the slow 1647 * software emulation path, we try to simulate the "fitos" instruction 1648 * via "fitod" and "fdtos" provided the following conditions are met: 1649 * 1650 * fpu_exists is set (if DEBUG) 1651 * not in privileged mode 1652 * ftt is unfinished_FPop 1653 * NXM IEEE trap is not enabled 1654 * instruction at %tpc is "fitos" 1655 * 1656 * Usage: 1657 * %g1 per cpu address 1658 * %g2 %fsr 1659 * %g6 user instruction 1660 * 1661 * Note that we can take a memory access related trap while trying 1662 * to fetch the user instruction. Therefore, we set CPU_TL1_HDLR 1663 * flag to catch those traps and let the SFMMU code deal with page 1664 * fault and data access exception. 1665 */ 1666#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 1667 sethi %hi(fpu_exists), %g7 1668 ld [%g7 + %lo(fpu_exists)], %g7 1669 brz,pn %g7, .fp_exception_cont 1670 nop 1671#endif 1672 rdpr %tstate, %g7 ! branch if in privileged mode 1673 btst TSTATE_PRIV, %g7 1674 bnz,pn %xcc, .fp_exception_cont 1675 srl %g2, FSR_FTT_SHIFT, %g7 ! extract ftt from %fsr 1676 and %g7, (FSR_FTT>>FSR_FTT_SHIFT), %g7 1677 cmp %g7, FTT_UNFIN 1678 set FSR_TEM_NX, %g5 1679 bne,pn %xcc, .fp_exception_cont ! branch if NOT unfinished_FPop 1680 andcc %g2, %g5, %g0 1681 bne,pn %xcc, .fp_exception_cont ! branch if FSR_TEM_NX enabled 1682 rdpr %tpc, %g5 ! get faulting PC 1683 1684 or %g0, 1, %g7 1685 st %g7, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 1686 lda [%g5]ASI_USER, %g6 ! get user's instruction 1687 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 1688 1689 set FITOS_INSTR_MASK, %g7 1690 and %g6, %g7, %g7 1691 set FITOS_INSTR, %g5 1692 cmp %g7, %g5 1693 bne,pn %xcc, .fp_exception_cont ! branch if not FITOS_INSTR 1694 nop 1695 1696 /* 1697 * This is unfinished FPops trap for "fitos" instruction. We 1698 * need to simulate "fitos" via "fitod" and "fdtos" instruction 1699 * sequence. 1700 * 1701 * We need a temporary FP register to do the conversion. Since 1702 * both source and destination operands for the "fitos" instruction 1703 * have to be within %f0-%f31, we use an FP register from the upper 1704 * half to guarantee that it won't collide with the source or the 1705 * dest operand. However, we do have to save and restore its value. 1706 * 1707 * We use %d62 as a temporary FP register for the conversion and 1708 * branch to appropriate instruction within the conversion tables 1709 * based upon the rs2 and rd values. 1710 */ 1711 1712 std %d62, [%g1 + CPU_TMP1] ! save original value 1713 1714 srl %g6, FITOS_RS2_SHIFT, %g7 1715 and %g7, FITOS_REG_MASK, %g7 1716 set _fitos_fitod_table, %g4 1717 sllx %g7, 2, %g7 1718 jmp %g4 + %g7 1719 ba,pt %xcc, _fitos_fitod_done 1720 .empty 1721 1722_fitos_fitod_table: 1723 fitod %f0, %d62 1724 fitod %f1, %d62 1725 fitod %f2, %d62 1726 fitod %f3, %d62 1727 fitod %f4, %d62 1728 fitod %f5, %d62 1729 fitod %f6, %d62 1730 fitod %f7, %d62 1731 fitod %f8, %d62 1732 fitod %f9, %d62 1733 fitod %f10, %d62 1734 fitod %f11, %d62 1735 fitod %f12, %d62 1736 fitod %f13, %d62 1737 fitod %f14, %d62 1738 fitod %f15, %d62 1739 fitod %f16, %d62 1740 fitod %f17, %d62 1741 fitod %f18, %d62 1742 fitod %f19, %d62 1743 fitod %f20, %d62 1744 fitod %f21, %d62 1745 fitod %f22, %d62 1746 fitod %f23, %d62 1747 fitod %f24, %d62 1748 fitod %f25, %d62 1749 fitod %f26, %d62 1750 fitod %f27, %d62 1751 fitod %f28, %d62 1752 fitod %f29, %d62 1753 fitod %f30, %d62 1754 fitod %f31, %d62 1755_fitos_fitod_done: 1756 1757 /* 1758 * Now convert data back into single precision 1759 */ 1760 srl %g6, FITOS_RD_SHIFT, %g7 1761 and %g7, FITOS_REG_MASK, %g7 1762 set _fitos_fdtos_table, %g4 1763 sllx %g7, 2, %g7 1764 jmp %g4 + %g7 1765 ba,pt %xcc, _fitos_fdtos_done 1766 .empty 1767 1768_fitos_fdtos_table: 1769 fdtos %d62, %f0 1770 fdtos %d62, %f1 1771 fdtos %d62, %f2 1772 fdtos %d62, %f3 1773 fdtos %d62, %f4 1774 fdtos %d62, %f5 1775 fdtos %d62, %f6 1776 fdtos %d62, %f7 1777 fdtos %d62, %f8 1778 fdtos %d62, %f9 1779 fdtos %d62, %f10 1780 fdtos %d62, %f11 1781 fdtos %d62, %f12 1782 fdtos %d62, %f13 1783 fdtos %d62, %f14 1784 fdtos %d62, %f15 1785 fdtos %d62, %f16 1786 fdtos %d62, %f17 1787 fdtos %d62, %f18 1788 fdtos %d62, %f19 1789 fdtos %d62, %f20 1790 fdtos %d62, %f21 1791 fdtos %d62, %f22 1792 fdtos %d62, %f23 1793 fdtos %d62, %f24 1794 fdtos %d62, %f25 1795 fdtos %d62, %f26 1796 fdtos %d62, %f27 1797 fdtos %d62, %f28 1798 fdtos %d62, %f29 1799 fdtos %d62, %f30 1800 fdtos %d62, %f31 1801_fitos_fdtos_done: 1802 1803 ldd [%g1 + CPU_TMP1], %d62 ! restore %d62 1804 1805#if DEBUG 1806 /* 1807 * Update FPop_unfinished trap kstat 1808 */ 1809 set fpustat+FPUSTAT_UNFIN_KSTAT, %g7 1810 ldx [%g7], %g5 18111: 1812 add %g5, 1, %g6 1813 1814 casxa [%g7] ASI_N, %g5, %g6 1815 cmp %g5, %g6 1816 bne,a,pn %xcc, 1b 1817 or %g0, %g6, %g5 1818 1819 /* 1820 * Update fpu_sim_fitos kstat 1821 */ 1822 set fpuinfo+FPUINFO_FITOS_KSTAT, %g7 1823 ldx [%g7], %g5 18241: 1825 add %g5, 1, %g6 1826 1827 casxa [%g7] ASI_N, %g5, %g6 1828 cmp %g5, %g6 1829 bne,a,pn %xcc, 1b 1830 or %g0, %g6, %g5 1831#endif /* DEBUG */ 1832 1833 FAST_TRAP_DONE 1834 1835.fp_exception_cont: 1836 /* 1837 * Let _fp_exception deal with simulating FPop instruction. 1838 * Note that we need to pass %fsr in %g2 (already read above). 1839 */ 1840 1841 set _fp_exception, %g1 1842 ba,pt %xcc, sys_trap 1843 sub %g0, 1, %g4 1844 1845 1846/* 1847 * Register windows 1848 */ 1849 1850/* 1851 * FILL_32bit_flushw/FILL_64bit_flushw fills a 32/64-bit-wide register window 1852 * from a 32/64-bit * wide address space via the designated asi. 1853 * It is used to fill windows in user_flushw to avoid going above TL 2. 1854 */ 1855/* TODO: Use the faster FILL based on FILL_32bit_asi/FILL_64bit_asi */ 1856#define FILL_32bit_flushw(asi_num) \ 1857 mov asi_num, %asi ;\ 1858 rdpr %cwp, %g2 ;\ 1859 sub %g2, 1, %g2 ;\ 1860 wrpr %g2, %cwp ;\ 18611: srl %sp, 0, %sp ;\ 1862 lda [%sp + 0]%asi, %l0 ;\ 1863 lda [%sp + 4]%asi, %l1 ;\ 1864 lda [%sp + 8]%asi, %l2 ;\ 1865 lda [%sp + 12]%asi, %l3 ;\ 1866 lda [%sp + 16]%asi, %l4 ;\ 1867 lda [%sp + 20]%asi, %l5 ;\ 1868 lda [%sp + 24]%asi, %l6 ;\ 1869 lda [%sp + 28]%asi, %l7 ;\ 1870 lda [%sp + 32]%asi, %i0 ;\ 1871 lda [%sp + 36]%asi, %i1 ;\ 1872 lda [%sp + 40]%asi, %i2 ;\ 1873 lda [%sp + 44]%asi, %i3 ;\ 1874 lda [%sp + 48]%asi, %i4 ;\ 1875 lda [%sp + 52]%asi, %i5 ;\ 1876 lda [%sp + 56]%asi, %i6 ;\ 1877 lda [%sp + 60]%asi, %i7 ;\ 1878 restored ;\ 1879 add %g2, 1, %g2 ;\ 1880 wrpr %g2, %cwp 1881 1882#define FILL_64bit_flushw(asi_num) \ 1883 mov asi_num, %asi ;\ 1884 rdpr %cwp, %g2 ;\ 1885 sub %g2, 1, %g2 ;\ 1886 wrpr %g2, %cwp ;\ 1887 ldxa [%sp + V9BIAS64 + 0]%asi, %l0 ;\ 1888 ldxa [%sp + V9BIAS64 + 8]%asi, %l1 ;\ 1889 ldxa [%sp + V9BIAS64 + 16]%asi, %l2 ;\ 1890 ldxa [%sp + V9BIAS64 + 24]%asi, %l3 ;\ 1891 ldxa [%sp + V9BIAS64 + 32]%asi, %l4 ;\ 1892 ldxa [%sp + V9BIAS64 + 40]%asi, %l5 ;\ 1893 ldxa [%sp + V9BIAS64 + 48]%asi, %l6 ;\ 1894 ldxa [%sp + V9BIAS64 + 56]%asi, %l7 ;\ 1895 ldxa [%sp + V9BIAS64 + 64]%asi, %i0 ;\ 1896 ldxa [%sp + V9BIAS64 + 72]%asi, %i1 ;\ 1897 ldxa [%sp + V9BIAS64 + 80]%asi, %i2 ;\ 1898 ldxa [%sp + V9BIAS64 + 88]%asi, %i3 ;\ 1899 ldxa [%sp + V9BIAS64 + 96]%asi, %i4 ;\ 1900 ldxa [%sp + V9BIAS64 + 104]%asi, %i5 ;\ 1901 ldxa [%sp + V9BIAS64 + 112]%asi, %i6 ;\ 1902 ldxa [%sp + V9BIAS64 + 120]%asi, %i7 ;\ 1903 restored ;\ 1904 add %g2, 1, %g2 ;\ 1905 wrpr %g2, %cwp 1906 1907.flushw: 1908 rdpr %tnpc, %g1 1909 wrpr %g1, %tpc 1910 add %g1, 4, %g1 1911 wrpr %g1, %tnpc 1912 set trap, %g1 1913 mov T_FLUSH_PCB, %g3 1914 ba,pt %xcc, sys_trap 1915 sub %g0, 1, %g4 1916 1917.clean_windows: 1918 set trap, %g1 1919 mov T_FLUSH_PCB, %g3 1920 sub %g0, 1, %g4 1921 save 1922 flushw 1923 rdpr %canrestore, %g2 1924 brnz %g2, 1f 1925 nop 1926 rdpr %wstate, %g2 1927 btst 1, %g2 1928 beq 2f 1929 nop 1930 FILL_32bit_flushw(ASI_AIUP) 1931 ba,a 1f 1932 .empty 19332: 1934 FILL_64bit_flushw(ASI_AIUP) 19351: 1936 restore 1937 wrpr %g0, %g0, %cleanwin ! no clean windows 1938 1939 CPU_ADDR(%g4, %g5) 1940 ldn [%g4 + CPU_MPCB], %g4 1941 brz,a,pn %g4, 1f 1942 nop 1943 ld [%g4 + MPCB_WSTATE], %g5 1944 add %g5, WSTATE_CLEAN_OFFSET, %g5 1945 wrpr %g0, %g5, %wstate 19461: FAST_TRAP_DONE 1947 1948/* 1949 * .spill_clean: clean the previous window, restore the wstate, and 1950 * "done". 1951 * 1952 * Entry: %g7 contains new wstate 1953 */ 1954.spill_clean: 1955 sethi %hi(nwin_minus_one), %g5 1956 ld [%g5 + %lo(nwin_minus_one)], %g5 ! %g5 = nwin - 1 1957 rdpr %cwp, %g6 ! %g6 = %cwp 1958 deccc %g6 ! %g6-- 1959 movneg %xcc, %g5, %g6 ! if (%g6<0) %g6 = nwin-1 1960 wrpr %g6, %cwp 1961 TT_TRACE_L(trace_win) 1962 clr %l0 1963 clr %l1 1964 clr %l2 1965 clr %l3 1966 clr %l4 1967 clr %l5 1968 clr %l6 1969 clr %l7 1970 wrpr %g0, %g7, %wstate 1971 saved 1972 retry ! restores correct %cwp 1973 1974.fix_alignment: 1975 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 1976 ldn [%g1 + CPU_THREAD], %g1 ! load thread pointer 1977 ldn [%g1 + T_PROCP], %g1 1978 mov 1, %g2 1979 stb %g2, [%g1 + P_FIXALIGNMENT] 1980 FAST_TRAP_DONE 1981 1982#define STDF_REG(REG, ADDR, TMP) \ 1983 sll REG, 3, REG ;\ 1984mark1: set start1, TMP ;\ 1985 jmp REG + TMP ;\ 1986 nop ;\ 1987start1: ba,pt %xcc, done1 ;\ 1988 std %f0, [ADDR + CPU_TMP1] ;\ 1989 ba,pt %xcc, done1 ;\ 1990 std %f32, [ADDR + CPU_TMP1] ;\ 1991 ba,pt %xcc, done1 ;\ 1992 std %f2, [ADDR + CPU_TMP1] ;\ 1993 ba,pt %xcc, done1 ;\ 1994 std %f34, [ADDR + CPU_TMP1] ;\ 1995 ba,pt %xcc, done1 ;\ 1996 std %f4, [ADDR + CPU_TMP1] ;\ 1997 ba,pt %xcc, done1 ;\ 1998 std %f36, [ADDR + CPU_TMP1] ;\ 1999 ba,pt %xcc, done1 ;\ 2000 std %f6, [ADDR + CPU_TMP1] ;\ 2001 ba,pt %xcc, done1 ;\ 2002 std %f38, [ADDR + CPU_TMP1] ;\ 2003 ba,pt %xcc, done1 ;\ 2004 std %f8, [ADDR + CPU_TMP1] ;\ 2005 ba,pt %xcc, done1 ;\ 2006 std %f40, [ADDR + CPU_TMP1] ;\ 2007 ba,pt %xcc, done1 ;\ 2008 std %f10, [ADDR + CPU_TMP1] ;\ 2009 ba,pt %xcc, done1 ;\ 2010 std %f42, [ADDR + CPU_TMP1] ;\ 2011 ba,pt %xcc, done1 ;\ 2012 std %f12, [ADDR + CPU_TMP1] ;\ 2013 ba,pt %xcc, done1 ;\ 2014 std %f44, [ADDR + CPU_TMP1] ;\ 2015 ba,pt %xcc, done1 ;\ 2016 std %f14, [ADDR + CPU_TMP1] ;\ 2017 ba,pt %xcc, done1 ;\ 2018 std %f46, [ADDR + CPU_TMP1] ;\ 2019 ba,pt %xcc, done1 ;\ 2020 std %f16, [ADDR + CPU_TMP1] ;\ 2021 ba,pt %xcc, done1 ;\ 2022 std %f48, [ADDR + CPU_TMP1] ;\ 2023 ba,pt %xcc, done1 ;\ 2024 std %f18, [ADDR + CPU_TMP1] ;\ 2025 ba,pt %xcc, done1 ;\ 2026 std %f50, [ADDR + CPU_TMP1] ;\ 2027 ba,pt %xcc, done1 ;\ 2028 std %f20, [ADDR + CPU_TMP1] ;\ 2029 ba,pt %xcc, done1 ;\ 2030 std %f52, [ADDR + CPU_TMP1] ;\ 2031 ba,pt %xcc, done1 ;\ 2032 std %f22, [ADDR + CPU_TMP1] ;\ 2033 ba,pt %xcc, done1 ;\ 2034 std %f54, [ADDR + CPU_TMP1] ;\ 2035 ba,pt %xcc, done1 ;\ 2036 std %f24, [ADDR + CPU_TMP1] ;\ 2037 ba,pt %xcc, done1 ;\ 2038 std %f56, [ADDR + CPU_TMP1] ;\ 2039 ba,pt %xcc, done1 ;\ 2040 std %f26, [ADDR + CPU_TMP1] ;\ 2041 ba,pt %xcc, done1 ;\ 2042 std %f58, [ADDR + CPU_TMP1] ;\ 2043 ba,pt %xcc, done1 ;\ 2044 std %f28, [ADDR + CPU_TMP1] ;\ 2045 ba,pt %xcc, done1 ;\ 2046 std %f60, [ADDR + CPU_TMP1] ;\ 2047 ba,pt %xcc, done1 ;\ 2048 std %f30, [ADDR + CPU_TMP1] ;\ 2049 ba,pt %xcc, done1 ;\ 2050 std %f62, [ADDR + CPU_TMP1] ;\ 2051done1: 2052 2053#define LDDF_REG(REG, ADDR, TMP) \ 2054 sll REG, 3, REG ;\ 2055mark2: set start2, TMP ;\ 2056 jmp REG + TMP ;\ 2057 nop ;\ 2058start2: ba,pt %xcc, done2 ;\ 2059 ldd [ADDR + CPU_TMP1], %f0 ;\ 2060 ba,pt %xcc, done2 ;\ 2061 ldd [ADDR + CPU_TMP1], %f32 ;\ 2062 ba,pt %xcc, done2 ;\ 2063 ldd [ADDR + CPU_TMP1], %f2 ;\ 2064 ba,pt %xcc, done2 ;\ 2065 ldd [ADDR + CPU_TMP1], %f34 ;\ 2066 ba,pt %xcc, done2 ;\ 2067 ldd [ADDR + CPU_TMP1], %f4 ;\ 2068 ba,pt %xcc, done2 ;\ 2069 ldd [ADDR + CPU_TMP1], %f36 ;\ 2070 ba,pt %xcc, done2 ;\ 2071 ldd [ADDR + CPU_TMP1], %f6 ;\ 2072 ba,pt %xcc, done2 ;\ 2073 ldd [ADDR + CPU_TMP1], %f38 ;\ 2074 ba,pt %xcc, done2 ;\ 2075 ldd [ADDR + CPU_TMP1], %f8 ;\ 2076 ba,pt %xcc, done2 ;\ 2077 ldd [ADDR + CPU_TMP1], %f40 ;\ 2078 ba,pt %xcc, done2 ;\ 2079 ldd [ADDR + CPU_TMP1], %f10 ;\ 2080 ba,pt %xcc, done2 ;\ 2081 ldd [ADDR + CPU_TMP1], %f42 ;\ 2082 ba,pt %xcc, done2 ;\ 2083 ldd [ADDR + CPU_TMP1], %f12 ;\ 2084 ba,pt %xcc, done2 ;\ 2085 ldd [ADDR + CPU_TMP1], %f44 ;\ 2086 ba,pt %xcc, done2 ;\ 2087 ldd [ADDR + CPU_TMP1], %f14 ;\ 2088 ba,pt %xcc, done2 ;\ 2089 ldd [ADDR + CPU_TMP1], %f46 ;\ 2090 ba,pt %xcc, done2 ;\ 2091 ldd [ADDR + CPU_TMP1], %f16 ;\ 2092 ba,pt %xcc, done2 ;\ 2093 ldd [ADDR + CPU_TMP1], %f48 ;\ 2094 ba,pt %xcc, done2 ;\ 2095 ldd [ADDR + CPU_TMP1], %f18 ;\ 2096 ba,pt %xcc, done2 ;\ 2097 ldd [ADDR + CPU_TMP1], %f50 ;\ 2098 ba,pt %xcc, done2 ;\ 2099 ldd [ADDR + CPU_TMP1], %f20 ;\ 2100 ba,pt %xcc, done2 ;\ 2101 ldd [ADDR + CPU_TMP1], %f52 ;\ 2102 ba,pt %xcc, done2 ;\ 2103 ldd [ADDR + CPU_TMP1], %f22 ;\ 2104 ba,pt %xcc, done2 ;\ 2105 ldd [ADDR + CPU_TMP1], %f54 ;\ 2106 ba,pt %xcc, done2 ;\ 2107 ldd [ADDR + CPU_TMP1], %f24 ;\ 2108 ba,pt %xcc, done2 ;\ 2109 ldd [ADDR + CPU_TMP1], %f56 ;\ 2110 ba,pt %xcc, done2 ;\ 2111 ldd [ADDR + CPU_TMP1], %f26 ;\ 2112 ba,pt %xcc, done2 ;\ 2113 ldd [ADDR + CPU_TMP1], %f58 ;\ 2114 ba,pt %xcc, done2 ;\ 2115 ldd [ADDR + CPU_TMP1], %f28 ;\ 2116 ba,pt %xcc, done2 ;\ 2117 ldd [ADDR + CPU_TMP1], %f60 ;\ 2118 ba,pt %xcc, done2 ;\ 2119 ldd [ADDR + CPU_TMP1], %f30 ;\ 2120 ba,pt %xcc, done2 ;\ 2121 ldd [ADDR + CPU_TMP1], %f62 ;\ 2122done2: 2123 2124.lddf_exception_not_aligned: 2125 /* %g2 = sfar, %g3 = sfsr */ 2126 mov %g2, %g5 ! stash sfar 2127#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2128 sethi %hi(fpu_exists), %g2 ! check fpu_exists 2129 ld [%g2 + %lo(fpu_exists)], %g2 2130 brz,a,pn %g2, 4f 2131 nop 2132#endif 2133 CPU_ADDR(%g1, %g4) 2134 or %g0, 1, %g4 2135 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2136 2137 rdpr %tpc, %g2 2138 lda [%g2]ASI_AIUP, %g6 ! get the user's lddf instruction 2139 srl %g6, 23, %g1 ! using ldda or not? 2140 and %g1, 1, %g1 2141 brz,a,pt %g1, 2f ! check for ldda instruction 2142 nop 2143 srl %g6, 13, %g1 ! check immflag 2144 and %g1, 1, %g1 2145 rdpr %tstate, %g2 ! %tstate in %g2 2146 brnz,a,pn %g1, 1f 2147 srl %g2, 31, %g1 ! get asi from %tstate 2148 srl %g6, 5, %g1 ! get asi from instruction 2149 and %g1, 0xFF, %g1 ! imm_asi field 21501: 2151 cmp %g1, ASI_P ! primary address space 2152 be,a,pt %icc, 2f 2153 nop 2154 cmp %g1, ASI_PNF ! primary no fault address space 2155 be,a,pt %icc, 2f 2156 nop 2157 cmp %g1, ASI_S ! secondary address space 2158 be,a,pt %icc, 2f 2159 nop 2160 cmp %g1, ASI_SNF ! secondary no fault address space 2161 bne,a,pn %icc, 3f 2162 nop 21632: 2164 lduwa [%g5]ASI_USER, %g7 ! get first half of misaligned data 2165 add %g5, 4, %g5 ! increment misaligned data address 2166 lduwa [%g5]ASI_USER, %g5 ! get second half of misaligned data 2167 2168 sllx %g7, 32, %g7 2169 or %g5, %g7, %g5 ! combine data 2170 CPU_ADDR(%g7, %g1) ! save data on a per-cpu basis 2171 stx %g5, [%g7 + CPU_TMP1] ! save in cpu_tmp1 2172 2173 srl %g6, 25, %g3 ! %g6 has the instruction 2174 and %g3, 0x1F, %g3 ! %g3 has rd 2175 LDDF_REG(%g3, %g7, %g4) 2176 2177 CPU_ADDR(%g1, %g4) 2178 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2179 FAST_TRAP_DONE 21803: 2181 CPU_ADDR(%g1, %g4) 2182 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 21834: 2184 set T_USER, %g3 ! trap type in %g3 2185 or %g3, T_LDDF_ALIGN, %g3 2186 mov %g5, %g2 ! misaligned vaddr in %g2 2187 set fpu_trap, %g1 ! goto C for the little and 2188 ba,pt %xcc, sys_trap ! no fault little asi's 2189 sub %g0, 1, %g4 2190 2191.stdf_exception_not_aligned: 2192 /* %g2 = sfar, %g3 = sfsr */ 2193 mov %g2, %g5 2194 2195#if defined(DEBUG) || defined(NEED_FPU_EXISTS) 2196 sethi %hi(fpu_exists), %g7 ! check fpu_exists 2197 ld [%g7 + %lo(fpu_exists)], %g3 2198 brz,a,pn %g3, 4f 2199 nop 2200#endif 2201 CPU_ADDR(%g1, %g4) 2202 or %g0, 1, %g4 2203 st %g4, [%g1 + CPU_TL1_HDLR] ! set tl1_hdlr flag 2204 2205 rdpr %tpc, %g2 2206 lda [%g2]ASI_AIUP, %g6 ! get the user's stdf instruction 2207 2208 srl %g6, 23, %g1 ! using stda or not? 2209 and %g1, 1, %g1 2210 brz,a,pt %g1, 2f ! check for stda instruction 2211 nop 2212 srl %g6, 13, %g1 ! check immflag 2213 and %g1, 1, %g1 2214 rdpr %tstate, %g2 ! %tstate in %g2 2215 brnz,a,pn %g1, 1f 2216 srl %g2, 31, %g1 ! get asi from %tstate 2217 srl %g6, 5, %g1 ! get asi from instruction 2218 and %g1, 0xff, %g1 ! imm_asi field 22191: 2220 cmp %g1, ASI_P ! primary address space 2221 be,a,pt %icc, 2f 2222 nop 2223 cmp %g1, ASI_S ! secondary address space 2224 bne,a,pn %icc, 3f 2225 nop 22262: 2227 srl %g6, 25, %g6 2228 and %g6, 0x1F, %g6 ! %g6 has rd 2229 CPU_ADDR(%g7, %g1) 2230 STDF_REG(%g6, %g7, %g4) ! STDF_REG(REG, ADDR, TMP) 2231 2232 ldx [%g7 + CPU_TMP1], %g6 2233 srlx %g6, 32, %g7 2234 stuwa %g7, [%g5]ASI_USER ! first half 2235 add %g5, 4, %g5 ! increment misaligned data address 2236 stuwa %g6, [%g5]ASI_USER ! second half 2237 2238 CPU_ADDR(%g1, %g4) 2239 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 2240 FAST_TRAP_DONE 22413: 2242 CPU_ADDR(%g1, %g4) 2243 st %g0, [%g1 + CPU_TL1_HDLR] ! clear tl1_hdlr flag 22444: 2245 set T_USER, %g3 ! trap type in %g3 2246 or %g3, T_STDF_ALIGN, %g3 2247 mov %g5, %g2 ! misaligned vaddr in %g2 2248 set fpu_trap, %g1 ! goto C for the little and 2249 ba,pt %xcc, sys_trap ! nofault little asi's 2250 sub %g0, 1, %g4 2251 2252#ifdef DEBUG_USER_TRAPTRACECTL 2253 2254.traptrace_freeze: 2255 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2256 TT_TRACE_L(trace_win) 2257 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2258 set trap_freeze, %g1 2259 mov 1, %g2 2260 st %g2, [%g1] 2261 FAST_TRAP_DONE 2262 2263.traptrace_unfreeze: 2264 set trap_freeze, %g1 2265 st %g0, [%g1] 2266 mov %l0, %g1 ; mov %l1, %g2 ; mov %l2, %g3 ; mov %l4, %g4 2267 TT_TRACE_L(trace_win) 2268 mov %g4, %l4 ; mov %g3, %l2 ; mov %g2, %l1 ; mov %g1, %l0 2269 FAST_TRAP_DONE 2270 2271#endif /* DEBUG_USER_TRAPTRACECTL */ 2272 2273.getcc: 2274 CPU_ADDR(%g1, %g2) 2275 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2276 rdpr %tstate, %g3 ! get tstate 2277 srlx %g3, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2278 set PSR_ICC, %g2 2279 and %o0, %g2, %o0 ! mask out the rest 2280 srl %o0, PSR_ICC_SHIFT, %o0 ! right justify 2281 wrpr %g0, 0, %gl 2282 mov %o0, %g1 ! move ccr to normal %g1 2283 wrpr %g0, 1, %gl 2284 ! cannot assume globals retained their values after increasing %gl 2285 CPU_ADDR(%g1, %g2) 2286 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2287 FAST_TRAP_DONE 2288 2289.setcc: 2290 CPU_ADDR(%g1, %g2) 2291 stx %o0, [%g1 + CPU_TMP1] ! save %o0 2292 wrpr %g0, 0, %gl 2293 mov %g1, %o0 2294 wrpr %g0, 1, %gl 2295 ! cannot assume globals retained their values after increasing %gl 2296 CPU_ADDR(%g1, %g2) 2297 sll %o0, PSR_ICC_SHIFT, %g2 2298 set PSR_ICC, %g3 2299 and %g2, %g3, %g2 ! mask out rest 2300 sllx %g2, PSR_TSTATE_CC_SHIFT, %g2 2301 rdpr %tstate, %g3 ! get tstate 2302 srl %g3, 0, %g3 ! clear upper word 2303 or %g3, %g2, %g3 ! or in new bits 2304 wrpr %g3, %tstate 2305 ldx [%g1 + CPU_TMP1], %o0 ! restore %o0 2306 FAST_TRAP_DONE 2307 2308/* 2309 * getpsr(void) 2310 * Note that the xcc part of the ccr is not provided. 2311 * The V8 code shows why the V9 trap is not faster: 2312 * #define GETPSR_TRAP() \ 2313 * mov %psr, %i0; jmp %l2; rett %l2+4; nop; 2314 */ 2315 2316 .type .getpsr, #function 2317.getpsr: 2318 rdpr %tstate, %g1 ! get tstate 2319 srlx %g1, PSR_TSTATE_CC_SHIFT, %o0 ! shift ccr to V8 psr 2320 set PSR_ICC, %g2 2321 and %o0, %g2, %o0 ! mask out the rest 2322 2323 rd %fprs, %g1 ! get fprs 2324 and %g1, FPRS_FEF, %g2 ! mask out dirty upper/lower 2325 sllx %g2, PSR_FPRS_FEF_SHIFT, %g2 ! shift fef to V8 psr.ef 2326 or %o0, %g2, %o0 ! or result into psr.ef 2327 2328 set V9_PSR_IMPLVER, %g2 ! SI assigned impl/ver: 0xef 2329 or %o0, %g2, %o0 ! or psr.impl/ver 2330 FAST_TRAP_DONE 2331 SET_SIZE(.getpsr) 2332 2333/* 2334 * setpsr(newpsr) 2335 * Note that there is no support for ccr.xcc in the V9 code. 2336 */ 2337 2338 .type .setpsr, #function 2339.setpsr: 2340 rdpr %tstate, %g1 ! get tstate 2341! setx TSTATE_V8_UBITS, %g2 2342 or %g0, CCR_ICC, %g3 2343 sllx %g3, TSTATE_CCR_SHIFT, %g2 2344 2345 andn %g1, %g2, %g1 ! zero current user bits 2346 set PSR_ICC, %g2 2347 and %g2, %o0, %g2 ! clear all but psr.icc bits 2348 sllx %g2, PSR_TSTATE_CC_SHIFT, %g3 ! shift to tstate.ccr.icc 2349 wrpr %g1, %g3, %tstate ! write tstate 2350 2351 set PSR_EF, %g2 2352 and %g2, %o0, %g2 ! clear all but fp enable bit 2353 srlx %g2, PSR_FPRS_FEF_SHIFT, %g4 ! shift ef to V9 fprs.fef 2354 wr %g0, %g4, %fprs ! write fprs 2355 2356 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 2357 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2358 ldn [%g2 + T_LWP], %g3 ! load klwp pointer 2359 ldn [%g3 + LWP_FPU], %g2 ! get lwp_fpu pointer 2360 stuw %g4, [%g2 + FPU_FPRS] ! write fef value to fpu_fprs 2361 srlx %g4, 2, %g4 ! shift fef value to bit 0 2362 stub %g4, [%g2 + FPU_EN] ! write fef value to fpu_en 2363 FAST_TRAP_DONE 2364 SET_SIZE(.setpsr) 2365 2366/* 2367 * getlgrp 2368 * get home lgrpid on which the calling thread is currently executing. 2369 */ 2370 .type .getlgrp, #function 2371.getlgrp: 2372 ! Thanks for the incredibly helpful comments 2373 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2374 ld [%g1 + CPU_ID], %o0 ! load cpu_id 2375 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2376 ldn [%g2 + T_LPL], %g2 ! load lpl pointer 2377 ld [%g2 + LPL_LGRPID], %g1 ! load lpl_lgrpid 2378 sra %g1, 0, %o1 2379 FAST_TRAP_DONE 2380 SET_SIZE(.getlgrp) 2381 2382/* 2383 * Entry for old 4.x trap (trap 0). 2384 */ 2385 ENTRY_NP(syscall_trap_4x) 2386 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2387 ldn [%g1 + CPU_THREAD], %g2 ! load thread pointer 2388 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2389 ld [%g2 + PCB_TRAP0], %g2 ! lwp->lwp_pcb.pcb_trap0addr 2390 brz,pn %g2, 1f ! has it been set? 2391 st %l0, [%g1 + CPU_TMP1] ! delay - save some locals 2392 st %l1, [%g1 + CPU_TMP2] 2393 rdpr %tnpc, %l1 ! save old tnpc 2394 wrpr %g0, %g2, %tnpc ! setup tnpc 2395 2396 mov %g1, %l0 ! save CPU struct addr 2397 wrpr %g0, 0, %gl 2398 mov %l1, %g6 ! pass tnpc to user code in %g6 2399 wrpr %g0, 1, %gl 2400 ld [%l0 + CPU_TMP2], %l1 ! restore locals 2401 ld [%l0 + CPU_TMP1], %l0 2402 FAST_TRAP_DONE_CHK_INTR 24031: 2404 ! 2405 ! check for old syscall mmap which is the only different one which 2406 ! must be the same. Others are handled in the compatibility library. 2407 ! 2408 mov %g1, %l0 ! save CPU struct addr 2409 wrpr %g0, 0, %gl 2410 cmp %g1, OSYS_mmap ! compare to old 4.x mmap 2411 movz %icc, SYS_mmap, %g1 2412 wrpr %g0, 1, %gl 2413 ld [%l0 + CPU_TMP1], %l0 2414 SYSCALL(syscall_trap32) 2415 SET_SIZE(syscall_trap_4x) 2416 2417/* 2418 * Handler for software trap 9. 2419 * Set trap0 emulation address for old 4.x system call trap. 2420 * XXX - this should be a system call. 2421 */ 2422 ENTRY_NP(set_trap0_addr) 2423 CPU_ADDR(%g1, %g2) ! load CPU struct addr to %g1 using %g2 2424 st %l0, [%g1 + CPU_TMP1] ! save some locals 2425 st %l1, [%g1 + CPU_TMP2] 2426 mov %g1, %l0 ! preserve CPU addr 2427 wrpr %g0, 0, %gl 2428 mov %g1, %l1 2429 wrpr %g0, 1, %gl 2430 ! cannot assume globals retained their values after increasing %gl 2431 ldn [%l0 + CPU_THREAD], %g2 ! load thread pointer 2432 ldn [%g2 + T_LWP], %g2 ! load klwp pointer 2433 andn %l1, 3, %l1 ! force alignment 2434 st %l1, [%g2 + PCB_TRAP0] ! lwp->lwp_pcb.pcb_trap0addr 2435 ld [%l0 + CPU_TMP2], %l1 ! restore locals 2436 ld [%l0 + CPU_TMP1], %l0 2437 FAST_TRAP_DONE 2438 SET_SIZE(set_trap0_addr) 2439 2440/* 2441 * mmu_trap_tl1 2442 * trap handler for unexpected mmu traps. 2443 * simply checks if the trap was a user lddf/stdf alignment trap, in which 2444 * case we go to fpu_trap or a user trap from the window handler, in which 2445 * case we go save the state on the pcb. Otherwise, we go to ptl1_panic. 2446 */ 2447 .type mmu_trap_tl1, #function 2448mmu_trap_tl1: 2449#ifdef TRAPTRACE 2450 TRACE_PTR(%g5, %g6) 2451 GET_TRACE_TICK(%g6) 2452 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2453 TRACE_SAVE_TL_GL_REGS(%g5, %g6) 2454 rdpr %tt, %g6 2455 stha %g6, [%g5 + TRAP_ENT_TT]%asi 2456 rdpr %tstate, %g6 2457 stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi 2458 stna %sp, [%g5 + TRAP_ENT_SP]%asi 2459 stna %g0, [%g5 + TRAP_ENT_TR]%asi 2460 rdpr %tpc, %g6 2461 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2462 MMU_FAULT_STATUS_AREA(%g6) 2463 ldx [%g6 + MMFSA_D_ADDR], %g6 2464 stna %g6, [%g5 + TRAP_ENT_F1]%asi ! MMU fault address 2465 CPU_PADDR(%g7, %g6); 2466 add %g7, CPU_TL1_HDLR, %g7 2467 lda [%g7]ASI_MEM, %g6 2468 stna %g6, [%g5 + TRAP_ENT_F2]%asi 2469 MMU_FAULT_STATUS_AREA(%g6) 2470 ldx [%g6 + MMFSA_D_TYPE], %g7 ! XXXQ should be a MMFSA_F_ constant? 2471 ldx [%g6 + MMFSA_D_CTX], %g6 2472 sllx %g6, SFSR_CTX_SHIFT, %g6 2473 or %g6, %g7, %g6 2474 stna %g6, [%g5 + TRAP_ENT_F3]%asi ! MMU context/type 2475 set 0xdeadbeef, %g6 2476 stna %g6, [%g5 + TRAP_ENT_F4]%asi 2477 TRACE_NEXT(%g5, %g6, %g7) 2478#endif /* TRAPTRACE */ 2479 CPU_PADDR(%g7, %g6); 2480 add %g7, CPU_TL1_HDLR, %g7 ! %g7 = &cpu_m.tl1_hdlr (PA) 2481 lda [%g7]ASI_MEM, %g6 2482 brz,a,pt %g6, 1f 2483 nop 2484 sta %g0, [%g7]ASI_MEM 2485 ! XXXQ need to setup registers for sfmmu_mmu_trap? 2486 ba,a,pt %xcc, sfmmu_mmu_trap ! handle page faults 24871: 2488 rdpr %tpc, %g7 2489 /* in user_rtt? */ 2490 set rtt_fill_start, %g6 2491 cmp %g7, %g6 2492 blu,pn %xcc, 6f 2493 .empty 2494 set rtt_fill_end, %g6 2495 cmp %g7, %g6 2496 bgeu,pn %xcc, 6f 2497 nop 2498 set fault_rtt_fn1, %g7 2499 ba,a 7f 25006: 2501 ! check to see if the trap pc is in a window spill/fill handling 2502 rdpr %tpc, %g7 2503 /* tpc should be in the trap table */ 2504 set trap_table, %g6 2505 cmp %g7, %g6 2506 blu,a,pn %xcc, ptl1_panic 2507 mov PTL1_BAD_MMUTRAP, %g1 2508 set etrap_table, %g6 2509 cmp %g7, %g6 2510 bgeu,a,pn %xcc, ptl1_panic 2511 mov PTL1_BAD_MMUTRAP, %g1 2512 ! pc is inside the trap table, convert to trap type 2513 srl %g7, 5, %g6 ! XXXQ need #define 2514 and %g6, 0x1ff, %g6 ! XXXQ need #define 2515 ! and check for a window trap type 2516 and %g6, WTRAP_TTMASK, %g6 2517 cmp %g6, WTRAP_TYPE 2518 bne,a,pn %xcc, ptl1_panic 2519 mov PTL1_BAD_MMUTRAP, %g1 2520 andn %g7, WTRAP_ALIGN, %g7 /* 128 byte aligned */ 2521 add %g7, WTRAP_FAULTOFF, %g7 2522 25237: 2524 ! Arguments are passed in the global set active after the 2525 ! 'done' instruction. Before switching sets, must save 2526 ! the calculated next pc 2527 wrpr %g0, %g7, %tnpc 2528 wrpr %g0, 1, %gl 2529 rdpr %tt, %g5 2530 cmp %g5, T_ALIGNMENT 2531 MMU_FAULT_STATUS_AREA(%g4) 2532 ldx [%g4 + MMFSA_D_ADDR], %g6 2533 done 2534 SET_SIZE(mmu_trap_tl1) 2535 2536/* 2537 * Several traps use kmdb_trap and kmdb_trap_tl1 as their handlers. These 2538 * traps are valid only when kmdb is loaded. When the debugger is active, 2539 * the code below is rewritten to transfer control to the appropriate 2540 * debugger entry points. 2541 */ 2542 .global kmdb_trap 2543 .align 8 2544kmdb_trap: 2545 ba,a trap_table0 2546 jmp %g1 + 0 2547 nop 2548 2549 .global kmdb_trap_tl1 2550 .align 8 2551kmdb_trap_tl1: 2552 ba,a trap_table0 2553 jmp %g1 + 0 2554 nop 2555 2556/* 2557 * This entry is copied from OBP's trap table during boot. 2558 */ 2559 .global obp_bpt 2560 .align 8 2561obp_bpt: 2562 NOT 2563 2564 2565 2566#ifdef TRAPTRACE 2567/* 2568 * TRAPTRACE support. 2569 * labels here are branched to with "rd %pc, %g7" in the delay slot. 2570 * Return is done by "jmp %g7 + 4". 2571 */ 2572 2573trace_dmmu: 2574 TRACE_PTR(%g3, %g6) 2575 GET_TRACE_TICK(%g6) 2576 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2577 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2578 rdpr %tt, %g6 2579 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2580 rdpr %tstate, %g6 2581 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2582 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2583 rdpr %tpc, %g6 2584 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2585 MMU_FAULT_STATUS_AREA(%g6) 2586 ldx [%g6 + MMFSA_D_ADDR], %g4 2587 stxa %g4, [%g3 + TRAP_ENT_TR]%asi 2588 ldx [%g6 + MMFSA_D_CTX], %g4 2589 stxa %g4, [%g3 + TRAP_ENT_F1]%asi 2590 ldx [%g6 + MMFSA_D_TYPE], %g4 2591 stxa %g4, [%g3 + TRAP_ENT_F2]%asi 2592 stxa %g6, [%g3 + TRAP_ENT_F3]%asi 2593 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2594 TRACE_NEXT(%g3, %g4, %g5) 2595 jmp %g7 + 4 2596 nop 2597 2598trace_immu: 2599 TRACE_PTR(%g3, %g6) 2600 GET_TRACE_TICK(%g6) 2601 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2602 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2603 rdpr %tt, %g6 2604 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2605 rdpr %tstate, %g6 2606 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2607 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2608 rdpr %tpc, %g6 2609 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2610 MMU_FAULT_STATUS_AREA(%g6) 2611 ldx [%g6 + MMFSA_I_ADDR], %g4 2612 stxa %g4, [%g3 + TRAP_ENT_TR]%asi 2613 ldx [%g6 + MMFSA_I_CTX], %g4 2614 stxa %g4, [%g3 + TRAP_ENT_F1]%asi 2615 ldx [%g6 + MMFSA_I_TYPE], %g4 2616 stxa %g4, [%g3 + TRAP_ENT_F2]%asi 2617 stxa %g6, [%g3 + TRAP_ENT_F3]%asi 2618 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2619 TRACE_NEXT(%g3, %g4, %g5) 2620 jmp %g7 + 4 2621 nop 2622 2623trace_gen: 2624 TRACE_PTR(%g3, %g6) 2625 GET_TRACE_TICK(%g6) 2626 stxa %g6, [%g3 + TRAP_ENT_TICK]%asi 2627 TRACE_SAVE_TL_GL_REGS(%g3, %g6) 2628 rdpr %tt, %g6 2629 stha %g6, [%g3 + TRAP_ENT_TT]%asi 2630 rdpr %tstate, %g6 2631 stxa %g6, [%g3 + TRAP_ENT_TSTATE]%asi 2632 stna %sp, [%g3 + TRAP_ENT_SP]%asi 2633 rdpr %tpc, %g6 2634 stna %g6, [%g3 + TRAP_ENT_TPC]%asi 2635 stna %g0, [%g3 + TRAP_ENT_TR]%asi 2636 stna %g0, [%g3 + TRAP_ENT_F1]%asi 2637 stna %g0, [%g3 + TRAP_ENT_F2]%asi 2638 stna %g0, [%g3 + TRAP_ENT_F3]%asi 2639 stna %g0, [%g3 + TRAP_ENT_F4]%asi 2640 TRACE_NEXT(%g3, %g4, %g5) 2641 jmp %g7 + 4 2642 nop 2643 2644trace_win: 2645 TRACE_WIN_INFO(0, %l0, %l1, %l2) 2646 ! Keep the locals as clean as possible, caller cleans %l4 2647 clr %l2 2648 clr %l1 2649 jmp %l4 + 4 2650 clr %l0 2651 2652/* 2653 * Trace a tsb hit 2654 * g1 = tsbe pointer (in/clobbered) 2655 * g2 = tag access register (in) 2656 * g3 - g4 = scratch (clobbered) 2657 * g5 = tsbe data (in) 2658 * g6 = scratch (clobbered) 2659 * g7 = pc we jumped here from (in) 2660 */ 2661 2662 ! Do not disturb %g5, it will be used after the trace 2663 ALTENTRY(trace_tsbhit) 2664 TRACE_TSBHIT(0) 2665 jmp %g7 + 4 2666 nop 2667 2668/* 2669 * Trace a TSB miss 2670 * 2671 * g1 = tsb8k pointer (in) 2672 * g2 = tag access register (in) 2673 * g3 = tsb4m pointer (in) 2674 * g4 = tsbe tag (in/clobbered) 2675 * g5 - g6 = scratch (clobbered) 2676 * g7 = pc we jumped here from (in) 2677 */ 2678 .global trace_tsbmiss 2679trace_tsbmiss: 2680 membar #Sync 2681 sethi %hi(FLUSH_ADDR), %g6 2682 flush %g6 2683 TRACE_PTR(%g5, %g6) 2684 GET_TRACE_TICK(%g6) 2685 stxa %g6, [%g5 + TRAP_ENT_TICK]%asi 2686 stna %g2, [%g5 + TRAP_ENT_SP]%asi ! tag access 2687 stna %g4, [%g5 + TRAP_ENT_F1]%asi ! XXX? tsb tag 2688 rdpr %tnpc, %g6 2689 stna %g6, [%g5 + TRAP_ENT_F2]%asi 2690 stna %g1, [%g5 + TRAP_ENT_F3]%asi ! tsb8k pointer 2691 srlx %g1, 32, %g6 2692 stna %g6, [%g5 + TRAP_ENT_F4]%asi ! huh? 2693 rdpr %tpc, %g6 2694 stna %g6, [%g5 + TRAP_ENT_TPC]%asi 2695 TRACE_SAVE_TL_GL_REGS(%g5, %g6) 2696 rdpr %tt, %g6 2697 or %g6, TT_MMU_MISS, %g4 2698 stha %g4, [%g5 + TRAP_ENT_TT]%asi 2699 MMU_FAULT_STATUS_AREA(%g4) 2700 cmp %g6, FAST_IMMU_MISS_TT 2701 be,a %icc, 1f 2702 ldx [%g4 + MMFSA_I_ADDR], %g6 2703 cmp %g6, T_INSTR_MMU_MISS 2704 be,a %icc, 1f 2705 ldx [%g4 + MMFSA_I_ADDR], %g6 2706 ldx [%g4 + MMFSA_D_ADDR], %g6 27071: stxa %g6, [%g5 + TRAP_ENT_TSTATE]%asi ! tag target 2708 stna %g3, [%g5 + TRAP_ENT_TR]%asi ! tsb4m pointer 2709 TRACE_NEXT(%g5, %g4, %g6) 2710 jmp %g7 + 4 2711 nop 2712 2713/* 2714 * g2 = tag access register (in) 2715 * g3 = ctx number (in) 2716 */ 2717trace_dataprot: 2718 membar #Sync 2719 sethi %hi(FLUSH_ADDR), %g6 2720 flush %g6 2721 TRACE_PTR(%g1, %g6) 2722 GET_TRACE_TICK(%g6) 2723 stxa %g6, [%g1 + TRAP_ENT_TICK]%asi 2724 rdpr %tpc, %g6 2725 stna %g6, [%g1 + TRAP_ENT_TPC]%asi 2726 rdpr %tstate, %g6 2727 stxa %g6, [%g1 + TRAP_ENT_TSTATE]%asi 2728 stna %g2, [%g1 + TRAP_ENT_SP]%asi ! tag access reg 2729 stna %g0, [%g1 + TRAP_ENT_TR]%asi 2730 stna %g0, [%g1 + TRAP_ENT_F1]%asi 2731 stna %g0, [%g1 + TRAP_ENT_F2]%asi 2732 stna %g0, [%g1 + TRAP_ENT_F3]%asi 2733 stna %g0, [%g1 + TRAP_ENT_F4]%asi 2734 TRACE_SAVE_TL_GL_REGS(%g1, %g6) 2735 rdpr %tt, %g6 2736 stha %g6, [%g1 + TRAP_ENT_TT]%asi 2737 TRACE_NEXT(%g1, %g4, %g5) 2738 jmp %g7 + 4 2739 nop 2740 2741#endif /* TRAPTRACE */ 2742 2743.dmmu_exc_lddf_not_aligned: 2744 MMU_FAULT_STATUS_AREA(%g3) 2745 ldx [%g3 + MMFSA_D_ADDR], %g2 2746 /* Fault type not available in MMU fault status area */ 2747 mov MMFSA_F_UNALIGN, %g1 2748 ldx [%g3 + MMFSA_D_CTX], %g3 2749 sllx %g3, SFSR_CTX_SHIFT, %g3 2750 btst 1, %sp 2751 bnz,pt %xcc, .lddf_exception_not_aligned 2752 or %g3, %g1, %g3 2753 ba,a,pt %xcc, .mmu_exception_not_aligned 2754 2755.dmmu_exc_stdf_not_aligned: 2756 MMU_FAULT_STATUS_AREA(%g3) 2757 ldx [%g3 + MMFSA_D_ADDR], %g2 2758 /* Fault type not available in MMU fault status area */ 2759 mov MMFSA_F_UNALIGN, %g1 2760 ldx [%g3 + MMFSA_D_CTX], %g3 2761 sllx %g3, SFSR_CTX_SHIFT, %g3 2762 btst 1, %sp 2763 bnz,pt %xcc, .stdf_exception_not_aligned 2764 or %g3, %g1, %g3 2765 ba,a,pt %xcc, .mmu_exception_not_aligned 2766 2767/* 2768 * expects offset into tsbmiss area in %g1 and return pc in %g7 2769 */ 2770stat_mmu: 2771 CPU_INDEX(%g5, %g6) 2772 sethi %hi(tsbmiss_area), %g6 2773 sllx %g5, TSBMISS_SHIFT, %g5 2774 or %g6, %lo(tsbmiss_area), %g6 2775 add %g6, %g5, %g6 /* g6 = tsbmiss area */ 2776 ld [%g6 + %g1], %g5 2777 add %g5, 1, %g5 2778 jmp %g7 + 4 2779 st %g5, [%g6 + %g1] 2780 2781 2782/* 2783 * fast_trap_done, fast_trap_done_chk_intr: 2784 * 2785 * Due to the design of UltraSPARC pipeline, pending interrupts are not 2786 * taken immediately after a RETRY or DONE instruction which causes IE to 2787 * go from 0 to 1. Instead, the instruction at %tpc or %tnpc is allowed 2788 * to execute first before taking any interrupts. If that instruction 2789 * results in other traps, and if the corresponding trap handler runs 2790 * entirely at TL=1 with interrupts disabled, then pending interrupts 2791 * won't be taken until after yet another instruction following the %tpc 2792 * or %tnpc. 2793 * 2794 * A malicious user program can use this feature to block out interrupts 2795 * for extended durations, which can result in send_mondo_timeout kernel 2796 * panic. 2797 * 2798 * This problem is addressed by servicing any pending interrupts via 2799 * sys_trap before returning back to the user mode from a fast trap 2800 * handler. The "done" instruction within a fast trap handler, which 2801 * runs entirely at TL=1 with interrupts disabled, is replaced with the 2802 * FAST_TRAP_DONE macro, which branches control to this fast_trap_done 2803 * entry point. 2804 * 2805 * We check for any pending interrupts here and force a sys_trap to 2806 * service those interrupts, if any. To minimize overhead, pending 2807 * interrupts are checked if the %tpc happens to be at 16K boundary, 2808 * which allows a malicious program to execute at most 4K consecutive 2809 * instructions before we service any pending interrupts. If a worst 2810 * case fast trap handler takes about 2 usec, then interrupts will be 2811 * blocked for at most 8 msec, less than a clock tick. 2812 * 2813 * For the cases where we don't know if the %tpc will cross a 16K 2814 * boundary, we can't use the above optimization and always process 2815 * any pending interrupts via fast_frap_done_chk_intr entry point. 2816 * 2817 * Entry Conditions: 2818 * %pstate am:0 priv:1 ie:0 2819 * globals are AG (not normal globals) 2820 */ 2821 2822 .global fast_trap_done, fast_trap_done_chk_intr 2823fast_trap_done: 2824 rdpr %tpc, %g5 2825 sethi %hi(0xffffc000), %g6 ! 1's complement of 0x3fff 2826 andncc %g5, %g6, %g0 ! check lower 14 bits of %tpc 2827 bz,pn %icc, 1f ! branch if zero (lower 32 bits only) 2828 nop 2829 done 2830 2831fast_trap_done_chk_intr: 28321: rd SOFTINT, %g6 2833 brnz,pn %g6, 2f ! branch if any pending intr 2834 nop 2835 done 2836 28372: 2838 /* 2839 * We get here if there are any pending interrupts. 2840 * Adjust %tpc/%tnpc as we'll be resuming via "retry" 2841 * instruction. 2842 */ 2843 rdpr %tnpc, %g5 2844 wrpr %g0, %g5, %tpc 2845 add %g5, 4, %g5 2846 wrpr %g0, %g5, %tnpc 2847 2848 /* 2849 * Force a dummy sys_trap call so that interrupts can be serviced. 2850 */ 2851 set fast_trap_dummy_call, %g1 2852 ba,pt %xcc, sys_trap 2853 mov -1, %g4 2854 2855fast_trap_dummy_call: 2856 retl 2857 nop 2858 2859#endif /* lint */ 2860