1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * Hypervisor calls 31 */ 32 33#include <sys/asm_linkage.h> 34#include <sys/machasi.h> 35#include <sys/machparam.h> 36#include <sys/hypervisor_api.h> 37 38#if defined(lint) || defined(__lint) 39 40/*ARGSUSED*/ 41uint64_t 42hv_mach_exit(uint64_t exit_code) 43{ return (0); } 44 45uint64_t 46hv_mach_sir(void) 47{ return (0); } 48 49/*ARGSUSED*/ 50uint64_t 51hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg) 52{ return (0); } 53 54/*ARGSUSED*/ 55uint64_t 56hv_cpu_stop(uint64_t cpuid) 57{ return (0); } 58 59/*ARGSUSED*/ 60uint64_t 61hv_cpu_set_rtba(uint64_t *rtba) 62{ return (0); } 63 64/*ARGSUSED*/ 65int64_t 66hv_cnputchar(uint8_t ch) 67{ return (0); } 68 69/*ARGSUSED*/ 70int64_t 71hv_cngetchar(uint8_t *ch) 72{ return (0); } 73 74/*ARGSUSED*/ 75uint64_t 76hv_tod_get(uint64_t *seconds) 77{ return (0); } 78 79/*ARGSUSED*/ 80uint64_t 81hv_tod_set(uint64_t seconds) 82{ return (0);} 83 84/*ARGSUSED*/ 85uint64_t 86hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 87{ return (0); } 88 89/*ARGSUSED */ 90uint64_t 91hv_mmu_fault_area_conf(void *raddr) 92{ return (0); } 93 94/*ARGSUSED*/ 95uint64_t 96hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 97{ return (0); } 98 99/*ARGSUSED*/ 100uint64_t 101hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 102{ return (0); } 103 104/*ARGSUSED*/ 105uint64_t 106hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 107{ return (0); } 108 109#ifdef SET_MMU_STATS 110/*ARGSUSED*/ 111uint64_t 112hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 113{ return (0); } 114#endif /* SET_MMU_STATS */ 115 116/*ARGSUSED*/ 117uint64_t 118hv_cpu_qconf(int queue, uint64_t paddr, int size) 119{ return (0); } 120 121/*ARGSUSED*/ 122uint64_t 123hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 124{ return (0); } 125 126/*ARGSUSED*/ 127uint64_t 128hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 129{ return (0); } 130 131/*ARGSUSED*/ 132uint64_t 133hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 134{ return (0); } 135 136/*ARGSUSED*/ 137uint64_t 138hvio_intr_getstate(uint64_t sysino, int *intr_state) 139{ return (0); } 140 141/*ARGSUSED*/ 142uint64_t 143hvio_intr_setstate(uint64_t sysino, int intr_state) 144{ return (0); } 145 146/*ARGSUSED*/ 147uint64_t 148hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 149{ return (0); } 150 151/*ARGSUSED*/ 152uint64_t 153hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 154{ return (0); } 155 156uint64_t 157hv_cpu_yield(void) 158{ return (0); } 159 160/*ARGSUSED*/ 161uint64_t 162hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 163{ return (0); } 164 165/*ARGSUSED*/ 166uint64_t 167hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 168{ return (0); } 169 170/*ARGSUSED*/ 171uint64_t 172hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 173{ return (0); } 174 175/*ARGSUSED*/ 176uint64_t 177hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 178{ return (0); } 179 180/*ARGSUSED*/ 181uint64_t 182hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 183{ return (0); } 184 185/*ARGSUSED*/ 186uint64_t 187hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 188{ return (0); } 189 190/*ARGSUSED*/ 191uint64_t 192hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 193{ return (0); } 194 195/*ARGSUSED*/ 196uint64_t 197hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 198{ return (0); } 199 200/*ARGSUSED*/ 201uint64_t 202hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 203{ return (0); } 204 205/*ARGSUSED*/ 206uint64_t 207hv_ra2pa(uint64_t ra) 208{ return (0); } 209 210/*ARGSUSED*/ 211uint64_t 212hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 213{ return (0); } 214 215/*ARGSUSED*/ 216uint64_t 217hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 218{ return (0); } 219 220/*ARGSUSED*/ 221uint64_t 222hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 223{ return (0); } 224 225/*ARGSUSED*/ 226uint64_t 227hv_ldc_tx_get_state(uint64_t channel, 228 uint64_t *headp, uint64_t *tailp, uint64_t *state) 229{ return (0); } 230 231/*ARGSUSED*/ 232uint64_t 233hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 234{ return (0); } 235 236/*ARGSUSED*/ 237uint64_t 238hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 239{ return (0); } 240 241/*ARGSUSED*/ 242uint64_t 243hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 244{ return (0); } 245 246/*ARGSUSED*/ 247uint64_t 248hv_ldc_rx_get_state(uint64_t channel, 249 uint64_t *headp, uint64_t *tailp, uint64_t *state) 250{ return (0); } 251 252/*ARGSUSED*/ 253uint64_t 254hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 255{ return (0); } 256 257/*ARGSUSED*/ 258uint64_t 259hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra) 260{ return (0); } 261 262/*ARGSUSED*/ 263uint64_t 264hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries) 265{ return (0); } 266 267/*ARGSUSED*/ 268uint64_t 269hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 270 uint64_t raddr, uint64_t length, uint64_t *lengthp) 271{ return (0); } 272 273/*ARGSUSED*/ 274uint64_t 275hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie) 276{ return (0); } 277 278/*ARGSUSED*/ 279uint64_t 280hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie) 281{ return (0); } 282 283/*ARGSUSED*/ 284uint64_t 285hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state) 286{ return (0); } 287 288/*ARGSUSED*/ 289uint64_t 290hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state) 291{ return (0); } 292 293/*ARGSUSED*/ 294uint64_t 295hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state) 296{ return (0); } 297 298/*ARGSUSED*/ 299uint64_t 300hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state) 301{ return (0); } 302 303/*ARGSUSED*/ 304uint64_t 305hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid) 306{ return (0); } 307 308/*ARGSUSED*/ 309uint64_t 310hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid) 311{ return (0); } 312 313/*ARGSUSED*/ 314uint64_t 315hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp) 316{ return (0); } 317 318/*ARGSUSED*/ 319uint64_t 320hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor, 321 uint64_t *supported_minor) 322{ return (0); } 323 324/*ARGSUSED*/ 325uint64_t 326hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 327{ return (0); } 328 329/*ARGSUSED*/ 330int64_t 331hv_cnwrite(uint64_t buf_ra, uint64_t count, uint64_t *retcount) 332{ return (0); } 333 334/*ARGSUSED*/ 335int64_t 336hv_cnread(uint64_t buf_ra, uint64_t count, int64_t *retcount) 337{ return (0); } 338 339/*ARGSUSED*/ 340uint64_t 341hv_soft_state_set(uint64_t state, uint64_t string) 342{ return (0); } 343 344/*ARGSUSED*/ 345uint64_t 346hv_soft_state_get(uint64_t string, uint64_t *state) 347{ return (0); } 348 349#else /* lint || __lint */ 350 351 /* 352 * int hv_mach_exit(uint64_t exit_code) 353 */ 354 ENTRY(hv_mach_exit) 355 mov HV_MACH_EXIT, %o5 356 ta FAST_TRAP 357 retl 358 nop 359 SET_SIZE(hv_mach_exit) 360 361 /* 362 * uint64_t hv_mach_sir(void) 363 */ 364 ENTRY(hv_mach_sir) 365 mov HV_MACH_SIR, %o5 366 ta FAST_TRAP 367 retl 368 nop 369 SET_SIZE(hv_mach_sir) 370 371 /* 372 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 373 * uint64_t arg) 374 */ 375 ENTRY(hv_cpu_start) 376 mov HV_CPU_START, %o5 377 ta FAST_TRAP 378 retl 379 nop 380 SET_SIZE(hv_cpu_start) 381 382 /* 383 * hv_cpu_stop(uint64_t cpuid) 384 */ 385 ENTRY(hv_cpu_stop) 386 mov HV_CPU_STOP, %o5 387 ta FAST_TRAP 388 retl 389 nop 390 SET_SIZE(hv_cpu_stop) 391 392 /* 393 * hv_cpu_set_rtba(uint64_t *rtba) 394 */ 395 ENTRY(hv_cpu_set_rtba) 396 mov %o0, %o2 397 ldx [%o2], %o0 398 mov HV_CPU_SET_RTBA, %o5 399 ta FAST_TRAP 400 stx %o1, [%o2] 401 retl 402 nop 403 SET_SIZE(hv_cpu_set_rtba) 404 405 /* 406 * int64_t hv_cnputchar(uint8_t ch) 407 */ 408 ENTRY(hv_cnputchar) 409 mov CONS_PUTCHAR, %o5 410 ta FAST_TRAP 411 retl 412 nop 413 SET_SIZE(hv_cnputchar) 414 415 /* 416 * int64_t hv_cngetchar(uint8_t *ch) 417 */ 418 ENTRY(hv_cngetchar) 419 mov %o0, %o2 420 mov CONS_GETCHAR, %o5 421 ta FAST_TRAP 422 brnz,a %o0, 1f ! failure, just return error 423 nop 424 425 cmp %o1, H_BREAK 426 be 1f 427 mov %o1, %o0 428 429 cmp %o1, H_HUP 430 be 1f 431 mov %o1, %o0 432 433 stb %o1, [%o2] ! success, save character and return 0 434 mov 0, %o0 4351: 436 retl 437 nop 438 SET_SIZE(hv_cngetchar) 439 440 ENTRY(hv_tod_get) 441 mov %o0, %o4 442 mov TOD_GET, %o5 443 ta FAST_TRAP 444 retl 445 stx %o1, [%o4] 446 SET_SIZE(hv_tod_get) 447 448 ENTRY(hv_tod_set) 449 mov TOD_SET, %o5 450 ta FAST_TRAP 451 retl 452 nop 453 SET_SIZE(hv_tod_set) 454 455 /* 456 * Map permanent address 457 * arg0 vaddr (%o0) 458 * arg1 context (%o1) 459 * arg2 tte (%o2) 460 * arg3 flags (%o3) 0x1=d 0x2=i 461 */ 462 ENTRY(hv_mmu_map_perm_addr) 463 mov MAP_PERM_ADDR, %o5 464 ta FAST_TRAP 465 retl 466 nop 467 SET_SIZE(hv_mmu_map_perm_addr) 468 469 /* 470 * hv_mmu_fault_area_conf(void *raddr) 471 */ 472 ENTRY(hv_mmu_fault_area_conf) 473 mov %o0, %o2 474 ldx [%o2], %o0 475 mov MMU_SET_INFOPTR, %o5 476 ta FAST_TRAP 477 stx %o1, [%o2] 478 retl 479 nop 480 SET_SIZE(hv_mmu_fault_area_conf) 481 482 /* 483 * Unmap permanent address 484 * arg0 vaddr (%o0) 485 * arg1 context (%o1) 486 * arg2 flags (%o2) 0x1=d 0x2=i 487 */ 488 ENTRY(hv_mmu_unmap_perm_addr) 489 mov UNMAP_PERM_ADDR, %o5 490 ta FAST_TRAP 491 retl 492 nop 493 SET_SIZE(hv_mmu_unmap_perm_addr) 494 495 /* 496 * Set TSB for context 0 497 * arg0 ntsb_descriptor (%o0) 498 * arg1 desc_ra (%o1) 499 */ 500 ENTRY(hv_set_ctx0) 501 mov MMU_TSB_CTX0, %o5 502 ta FAST_TRAP 503 retl 504 nop 505 SET_SIZE(hv_set_ctx0) 506 507 /* 508 * Set TSB for context non0 509 * arg0 ntsb_descriptor (%o0) 510 * arg1 desc_ra (%o1) 511 */ 512 ENTRY(hv_set_ctxnon0) 513 mov MMU_TSB_CTXNON0, %o5 514 ta FAST_TRAP 515 retl 516 nop 517 SET_SIZE(hv_set_ctxnon0) 518 519#ifdef SET_MMU_STATS 520 /* 521 * Returns old stat area on success 522 */ 523 ENTRY(hv_mmu_set_stat_area) 524 mov MMU_STAT_AREA, %o5 525 ta FAST_TRAP 526 retl 527 nop 528 SET_SIZE(hv_mmu_set_stat_area) 529#endif /* SET_MMU_STATS */ 530 531 /* 532 * CPU Q Configure 533 * arg0 queue (%o0) 534 * arg1 Base address RA (%o1) 535 * arg2 Size (%o2) 536 */ 537 ENTRY(hv_cpu_qconf) 538 mov HV_CPU_QCONF, %o5 539 ta FAST_TRAP 540 retl 541 nop 542 SET_SIZE(hv_cpu_qconf) 543 544 /* 545 * arg0 - devhandle 546 * arg1 - devino 547 * 548 * ret0 - status 549 * ret1 - sysino 550 */ 551 ENTRY(hvio_intr_devino_to_sysino) 552 mov HVIO_INTR_DEVINO2SYSINO, %o5 553 ta FAST_TRAP 554 brz,a %o0, 1f 555 stx %o1, [%o2] 5561: retl 557 nop 558 SET_SIZE(hvio_intr_devino_to_sysino) 559 560 /* 561 * arg0 - sysino 562 * 563 * ret0 - status 564 * ret1 - intr_valid_state 565 */ 566 ENTRY(hvio_intr_getvalid) 567 mov %o1, %o2 568 mov HVIO_INTR_GETVALID, %o5 569 ta FAST_TRAP 570 brz,a %o0, 1f 571 stuw %o1, [%o2] 5721: retl 573 nop 574 SET_SIZE(hvio_intr_getvalid) 575 576 /* 577 * arg0 - sysino 578 * arg1 - intr_valid_state 579 * 580 * ret0 - status 581 */ 582 ENTRY(hvio_intr_setvalid) 583 mov HVIO_INTR_SETVALID, %o5 584 ta FAST_TRAP 585 retl 586 nop 587 SET_SIZE(hvio_intr_setvalid) 588 589 /* 590 * arg0 - sysino 591 * 592 * ret0 - status 593 * ret1 - intr_state 594 */ 595 ENTRY(hvio_intr_getstate) 596 mov %o1, %o2 597 mov HVIO_INTR_GETSTATE, %o5 598 ta FAST_TRAP 599 brz,a %o0, 1f 600 stuw %o1, [%o2] 6011: retl 602 nop 603 SET_SIZE(hvio_intr_getstate) 604 605 /* 606 * arg0 - sysino 607 * arg1 - intr_state 608 * 609 * ret0 - status 610 */ 611 ENTRY(hvio_intr_setstate) 612 mov HVIO_INTR_SETSTATE, %o5 613 ta FAST_TRAP 614 retl 615 nop 616 SET_SIZE(hvio_intr_setstate) 617 618 /* 619 * arg0 - sysino 620 * 621 * ret0 - status 622 * ret1 - cpu_id 623 */ 624 ENTRY(hvio_intr_gettarget) 625 mov %o1, %o2 626 mov HVIO_INTR_GETTARGET, %o5 627 ta FAST_TRAP 628 brz,a %o0, 1f 629 stuw %o1, [%o2] 6301: retl 631 nop 632 SET_SIZE(hvio_intr_gettarget) 633 634 /* 635 * arg0 - sysino 636 * arg1 - cpu_id 637 * 638 * ret0 - status 639 */ 640 ENTRY(hvio_intr_settarget) 641 mov HVIO_INTR_SETTARGET, %o5 642 ta FAST_TRAP 643 retl 644 nop 645 SET_SIZE(hvio_intr_settarget) 646 647 /* 648 * hv_cpu_yield(void) 649 */ 650 ENTRY(hv_cpu_yield) 651 mov HV_CPU_YIELD, %o5 652 ta FAST_TRAP 653 retl 654 nop 655 SET_SIZE(hv_cpu_yield) 656 657 /* 658 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 659 */ 660 ENTRY(hv_cpu_state) 661 mov %o1, %o4 ! save datap 662 mov HV_CPU_STATE, %o5 663 ta FAST_TRAP 664 brz,a %o0, 1f 665 stx %o1, [%o4] 6661: 667 retl 668 nop 669 SET_SIZE(hv_cpu_state) 670 671 /* 672 * HV state dump zone Configure 673 * arg0 real adrs of dump buffer (%o0) 674 * arg1 size of dump buffer (%o1) 675 * ret0 status (%o0) 676 * ret1 size of buffer on success and min size on EINVAL (%o1) 677 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 678 */ 679 ENTRY(hv_dump_buf_update) 680 mov DUMP_BUF_UPDATE, %o5 681 ta FAST_TRAP 682 retl 683 stx %o1, [%o2] 684 SET_SIZE(hv_dump_buf_update) 685 686 /* 687 * arg0 - timeout value (%o0) 688 * 689 * ret0 - status (%o0) 690 * ret1 - time_remaining (%o1) 691 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 692 */ 693 ENTRY(hv_mach_set_watchdog) 694 mov %o1, %o2 695 mov MACH_SET_WATCHDOG, %o5 696 ta FAST_TRAP 697 retl 698 stx %o1, [%o2] 699 SET_SIZE(hv_mach_set_watchdog) 700 701 /* 702 * For memory scrub 703 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 704 * uint64_t *scrubbed_len); 705 * Retun %o0 -- status 706 * %o1 -- bytes scrubbed 707 */ 708 ENTRY(hv_mem_scrub) 709 mov %o2, %o4 710 mov HV_MEM_SCRUB, %o5 711 ta FAST_TRAP 712 retl 713 stx %o1, [%o4] 714 SET_SIZE(hv_mem_scrub) 715 716 /* 717 * Flush ecache 718 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 719 * uint64_t *flushed_len); 720 * Retun %o0 -- status 721 * %o1 -- bytes flushed 722 */ 723 ENTRY(hv_mem_sync) 724 mov %o2, %o4 725 mov HV_MEM_SYNC, %o5 726 ta FAST_TRAP 727 retl 728 stx %o1, [%o4] 729 SET_SIZE(hv_mem_sync) 730 731 /* 732 * TTRACE_BUF_CONF Configure 733 * arg0 RA base of buffer (%o0) 734 * arg1 buf size in no. of entries (%o1) 735 * ret0 status (%o0) 736 * ret1 minimum size in no. of entries on failure, 737 * actual size in no. of entries on success (%o1) 738 */ 739 ENTRY(hv_ttrace_buf_conf) 740 mov TTRACE_BUF_CONF, %o5 741 ta FAST_TRAP 742 retl 743 stx %o1, [%o2] 744 SET_SIZE(hv_ttrace_buf_conf) 745 746 /* 747 * TTRACE_BUF_INFO 748 * ret0 status (%o0) 749 * ret1 RA base of buffer (%o1) 750 * ret2 size in no. of entries (%o2) 751 */ 752 ENTRY(hv_ttrace_buf_info) 753 mov %o0, %o3 754 mov %o1, %o4 755 mov TTRACE_BUF_INFO, %o5 756 ta FAST_TRAP 757 stx %o1, [%o3] 758 retl 759 stx %o2, [%o4] 760 SET_SIZE(hv_ttrace_buf_info) 761 762 /* 763 * TTRACE_ENABLE 764 * arg0 enable/ disable (%o0) 765 * ret0 status (%o0) 766 * ret1 previous enable state (%o1) 767 */ 768 ENTRY(hv_ttrace_enable) 769 mov %o1, %o2 770 mov TTRACE_ENABLE, %o5 771 ta FAST_TRAP 772 retl 773 stx %o1, [%o2] 774 SET_SIZE(hv_ttrace_enable) 775 776 /* 777 * TTRACE_FREEZE 778 * arg0 enable/ freeze (%o0) 779 * ret0 status (%o0) 780 * ret1 previous freeze state (%o1) 781 */ 782 ENTRY(hv_ttrace_freeze) 783 mov %o1, %o2 784 mov TTRACE_FREEZE, %o5 785 ta FAST_TRAP 786 retl 787 stx %o1, [%o2] 788 SET_SIZE(hv_ttrace_freeze) 789 790 /* 791 * MACH_DESC 792 * arg0 buffer real address 793 * arg1 pointer to uint64_t for size of buffer 794 * ret0 status 795 * ret1 return required size of buffer / returned data size 796 */ 797 ENTRY(hv_mach_desc) 798 mov %o1, %o4 ! save datap 799 ldx [%o1], %o1 800 mov HV_MACH_DESC, %o5 801 ta FAST_TRAP 802 retl 803 stx %o1, [%o4] 804 SET_SIZE(hv_mach_desc) 805 806 /* 807 * hv_ra2pa(uint64_t ra) 808 * 809 * MACH_DESC 810 * arg0 Real address to convert 811 * ret0 Returned physical address or -1 on error 812 */ 813 ENTRY(hv_ra2pa) 814 mov HV_RA2PA, %o5 815 ta FAST_TRAP 816 cmp %o0, 0 817 move %xcc, %o1, %o0 818 movne %xcc, -1, %o0 819 retl 820 nop 821 SET_SIZE(hv_ra2pa) 822 823 /* 824 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 825 * 826 * MACH_DESC 827 * arg0 OS function to call 828 * arg1 First arg to OS function 829 * arg2 Second arg to OS function 830 * arg3 Third arg to OS function 831 * ret0 Returned value from function 832 */ 833 834 ENTRY(hv_hpriv) 835 mov HV_HPRIV, %o5 836 ta FAST_TRAP 837 retl 838 nop 839 SET_SIZE(hv_hpriv) 840 841 /* 842 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 843 * uint64_t nentries); 844 */ 845 ENTRY(hv_ldc_tx_qconf) 846 mov LDC_TX_QCONF, %o5 847 ta FAST_TRAP 848 retl 849 nop 850 SET_SIZE(hv_ldc_tx_qconf) 851 852 853 /* 854 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 855 * uint64_t *nentries); 856 */ 857 ENTRY(hv_ldc_tx_qinfo) 858 mov %o1, %g1 859 mov %o2, %g2 860 mov LDC_TX_QINFO, %o5 861 ta FAST_TRAP 862 stx %o1, [%g1] 863 retl 864 stx %o2, [%g2] 865 SET_SIZE(hv_ldc_tx_qinfo) 866 867 868 /* 869 * hv_ldc_tx_get_state(uint64_t channel, 870 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 871 */ 872 ENTRY(hv_ldc_tx_get_state) 873 mov LDC_TX_GET_STATE, %o5 874 mov %o1, %g1 875 mov %o2, %g2 876 mov %o3, %g3 877 ta FAST_TRAP 878 stx %o1, [%g1] 879 stx %o2, [%g2] 880 retl 881 stx %o3, [%g3] 882 SET_SIZE(hv_ldc_tx_get_state) 883 884 885 /* 886 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 887 */ 888 ENTRY(hv_ldc_tx_set_qtail) 889 mov LDC_TX_SET_QTAIL, %o5 890 ta FAST_TRAP 891 retl 892 SET_SIZE(hv_ldc_tx_set_qtail) 893 894 895 /* 896 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 897 * uint64_t nentries); 898 */ 899 ENTRY(hv_ldc_rx_qconf) 900 mov LDC_RX_QCONF, %o5 901 ta FAST_TRAP 902 retl 903 nop 904 SET_SIZE(hv_ldc_rx_qconf) 905 906 907 /* 908 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 909 * uint64_t *nentries); 910 */ 911 ENTRY(hv_ldc_rx_qinfo) 912 mov %o1, %g1 913 mov %o2, %g2 914 mov LDC_RX_QINFO, %o5 915 ta FAST_TRAP 916 stx %o1, [%g1] 917 retl 918 stx %o2, [%g2] 919 SET_SIZE(hv_ldc_rx_qinfo) 920 921 922 /* 923 * hv_ldc_rx_get_state(uint64_t channel, 924 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 925 */ 926 ENTRY(hv_ldc_rx_get_state) 927 mov LDC_RX_GET_STATE, %o5 928 mov %o1, %g1 929 mov %o2, %g2 930 mov %o3, %g3 931 ta FAST_TRAP 932 stx %o1, [%g1] 933 stx %o2, [%g2] 934 retl 935 stx %o3, [%g3] 936 SET_SIZE(hv_ldc_rx_get_state) 937 938 939 /* 940 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 941 */ 942 ENTRY(hv_ldc_rx_set_qhead) 943 mov LDC_RX_SET_QHEAD, %o5 944 ta FAST_TRAP 945 retl 946 SET_SIZE(hv_ldc_rx_set_qhead) 947 948 /* 949 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 950 * uint64_t tbl_entries) 951 */ 952 ENTRY(hv_ldc_set_map_table) 953 mov LDC_SET_MAP_TABLE, %o5 954 ta FAST_TRAP 955 retl 956 nop 957 SET_SIZE(hv_ldc_set_map_table) 958 959 960 /* 961 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 962 * uint64_t *tbl_entries) 963 */ 964 ENTRY(hv_ldc_get_map_table) 965 mov %o1, %g1 966 mov %o2, %g2 967 mov LDC_GET_MAP_TABLE, %o5 968 ta FAST_TRAP 969 stx %o1, [%g1] 970 retl 971 stx %o2, [%g2] 972 SET_SIZE(hv_ldc_get_map_table) 973 974 975 /* 976 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 977 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 978 */ 979 ENTRY(hv_ldc_copy) 980 mov %o5, %g1 981 mov LDC_COPY, %o5 982 ta FAST_TRAP 983 retl 984 stx %o1, [%g1] 985 SET_SIZE(hv_ldc_copy) 986 987 988 /* 989 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 990 * uint64_t *perm) 991 */ 992 ENTRY(hv_ldc_mapin) 993 mov %o2, %g1 994 mov %o3, %g2 995 mov LDC_MAPIN, %o5 996 ta FAST_TRAP 997 stx %o1, [%g1] 998 retl 999 stx %o2, [%g2] 1000 SET_SIZE(hv_ldc_mapin) 1001 1002 1003 /* 1004 * hv_ldc_unmap(uint64_t raddr) 1005 */ 1006 ENTRY(hv_ldc_unmap) 1007 mov LDC_UNMAP, %o5 1008 ta FAST_TRAP 1009 retl 1010 nop 1011 SET_SIZE(hv_ldc_unmap) 1012 1013 1014 /* 1015 * hv_ldc_revoke(uint64_t channel, uint64_t cookie, 1016 * uint64_t revoke_cookie 1017 */ 1018 ENTRY(hv_ldc_revoke) 1019 mov LDC_REVOKE, %o5 1020 ta FAST_TRAP 1021 retl 1022 nop 1023 SET_SIZE(hv_ldc_revoke) 1024 1025 1026 /* 1027 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 1028 * uint64_t *cookie); 1029 */ 1030 ENTRY(hvldc_intr_getcookie) 1031 mov %o2, %g1 1032 mov VINTR_GET_COOKIE, %o5 1033 ta FAST_TRAP 1034 retl 1035 stx %o1, [%g1] 1036 SET_SIZE(hvldc_intr_getcookie) 1037 1038 /* 1039 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 1040 * uint64_t cookie); 1041 */ 1042 ENTRY(hvldc_intr_setcookie) 1043 mov VINTR_SET_COOKIE, %o5 1044 ta FAST_TRAP 1045 retl 1046 nop 1047 SET_SIZE(hvldc_intr_setcookie) 1048 1049 1050 /* 1051 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 1052 * int *intr_valid_state); 1053 */ 1054 ENTRY(hvldc_intr_getvalid) 1055 mov %o2, %g1 1056 mov VINTR_GET_VALID, %o5 1057 ta FAST_TRAP 1058 retl 1059 stuw %o1, [%g1] 1060 SET_SIZE(hvldc_intr_getvalid) 1061 1062 /* 1063 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 1064 * int intr_valid_state); 1065 */ 1066 ENTRY(hvldc_intr_setvalid) 1067 mov VINTR_SET_VALID, %o5 1068 ta FAST_TRAP 1069 retl 1070 nop 1071 SET_SIZE(hvldc_intr_setvalid) 1072 1073 /* 1074 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 1075 * int *intr_state); 1076 */ 1077 ENTRY(hvldc_intr_getstate) 1078 mov %o2, %g1 1079 mov VINTR_GET_STATE, %o5 1080 ta FAST_TRAP 1081 retl 1082 stuw %o1, [%g1] 1083 SET_SIZE(hvldc_intr_getstate) 1084 1085 /* 1086 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 1087 * int intr_state); 1088 */ 1089 ENTRY(hvldc_intr_setstate) 1090 mov VINTR_SET_STATE, %o5 1091 ta FAST_TRAP 1092 retl 1093 nop 1094 SET_SIZE(hvldc_intr_setstate) 1095 1096 /* 1097 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 1098 * uint32_t *cpuid); 1099 */ 1100 ENTRY(hvldc_intr_gettarget) 1101 mov %o2, %g1 1102 mov VINTR_GET_TARGET, %o5 1103 ta FAST_TRAP 1104 retl 1105 stuw %o1, [%g1] 1106 SET_SIZE(hvldc_intr_gettarget) 1107 1108 /* 1109 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 1110 * uint32_t cpuid); 1111 */ 1112 ENTRY(hvldc_intr_settarget) 1113 mov VINTR_SET_TARGET, %o5 1114 ta FAST_TRAP 1115 retl 1116 nop 1117 SET_SIZE(hvldc_intr_settarget) 1118 1119 /* 1120 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 1121 * uint64_t *minorp) 1122 * 1123 * API_GET_VERSION 1124 * arg0 API group 1125 * ret0 status 1126 * ret1 major number 1127 * ret2 minor number 1128 */ 1129 ENTRY(hv_api_get_version) 1130 mov %o1, %o3 1131 mov %o2, %o4 1132 mov API_GET_VERSION, %o5 1133 ta CORE_TRAP 1134 stx %o1, [%o3] 1135 retl 1136 stx %o2, [%o4] 1137 SET_SIZE(hv_api_get_version) 1138 1139 /* 1140 * hv_api_set_version(uint64_t api_group, uint64_t major, 1141 * uint64_t minor, uint64_t *supported_minor) 1142 * 1143 * API_SET_VERSION 1144 * arg0 API group 1145 * arg1 major number 1146 * arg2 requested minor number 1147 * ret0 status 1148 * ret1 actual minor number 1149 */ 1150 ENTRY(hv_api_set_version) 1151 mov %o3, %o4 1152 mov API_SET_VERSION, %o5 1153 ta CORE_TRAP 1154 retl 1155 stx %o1, [%o4] 1156 SET_SIZE(hv_api_set_version) 1157 1158 /* 1159 * %o0 - buffer real address 1160 * %o1 - buffer size 1161 * %o2 - &characters written 1162 * returns 1163 * status 1164 */ 1165 ENTRY(hv_cnwrite) 1166 mov CONS_WRITE, %o5 1167 ta FAST_TRAP 1168 retl 1169 stx %o1, [%o2] 1170 SET_SIZE(hv_cnwrite) 1171 1172 /* 1173 * %o0 character buffer ra 1174 * %o1 buffer size 1175 * %o2 pointer to returned size 1176 * return values: 1177 * 0 success 1178 * hv_errno failure 1179 */ 1180 ENTRY(hv_cnread) 1181 mov CONS_READ, %o5 1182 ta FAST_TRAP 1183 brnz,a %o0, 1f ! failure, just return error 1184 nop 1185 1186 cmp %o1, H_BREAK 1187 be 1f 1188 mov %o1, %o0 1189 1190 cmp %o1, H_HUP 1191 be 1f 1192 mov %o1, %o0 1193 1194 stx %o1, [%o2] ! success, save count and return 0 1195 mov 0, %o0 11961: 1197 retl 1198 nop 1199 SET_SIZE(hv_cnread) 1200 1201 /* 1202 * SOFT_STATE_SET 1203 * arg0 state (%o0) 1204 * arg1 string (%o1) 1205 * ret0 status (%o0) 1206 */ 1207 ENTRY(hv_soft_state_set) 1208 mov SOFT_STATE_SET, %o5 1209 ta FAST_TRAP 1210 retl 1211 nop 1212 SET_SIZE(hv_soft_state_set) 1213 1214 /* 1215 * SOFT_STATE_GET 1216 * arg0 string buffer (%o0) 1217 * ret0 status (%o0) 1218 * ret1 current state (%o1) 1219 */ 1220 ENTRY(hv_soft_state_get) 1221 mov %o1, %o2 1222 mov SOFT_STATE_GET, %o5 1223 ta FAST_TRAP 1224 retl 1225 stx %o1, [%o2] 1226 SET_SIZE(hv_soft_state_get) 1227 1228#endif /* lint || __lint */ 1229