1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Hypervisor calls 29 */ 30 31#include <sys/asm_linkage.h> 32#include <sys/machasi.h> 33#include <sys/machparam.h> 34#include <sys/hypervisor_api.h> 35 36#if defined(lint) || defined(__lint) 37 38/*ARGSUSED*/ 39uint64_t 40hv_mach_exit(uint64_t exit_code) 41{ return (0); } 42 43uint64_t 44hv_mach_sir(void) 45{ return (0); } 46 47/*ARGSUSED*/ 48uint64_t 49hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg) 50{ return (0); } 51 52/*ARGSUSED*/ 53uint64_t 54hv_cpu_stop(uint64_t cpuid) 55{ return (0); } 56 57/*ARGSUSED*/ 58uint64_t 59hv_cpu_set_rtba(uint64_t *rtba) 60{ return (0); } 61 62/*ARGSUSED*/ 63int64_t 64hv_cnputchar(uint8_t ch) 65{ return (0); } 66 67/*ARGSUSED*/ 68int64_t 69hv_cngetchar(uint8_t *ch) 70{ return (0); } 71 72/*ARGSUSED*/ 73uint64_t 74hv_tod_get(uint64_t *seconds) 75{ return (0); } 76 77/*ARGSUSED*/ 78uint64_t 79hv_tod_set(uint64_t seconds) 80{ return (0);} 81 82/*ARGSUSED*/ 83uint64_t 84hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 85{ return (0); } 86 87/*ARGSUSED */ 88uint64_t 89hv_mmu_fault_area_conf(void *raddr) 90{ return (0); } 91 92/*ARGSUSED*/ 93uint64_t 94hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 95{ return (0); } 96 97/*ARGSUSED*/ 98uint64_t 99hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 100{ return (0); } 101 102/*ARGSUSED*/ 103uint64_t 104hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 105{ return (0); } 106 107#ifdef SET_MMU_STATS 108/*ARGSUSED*/ 109uint64_t 110hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 111{ return (0); } 112#endif /* SET_MMU_STATS */ 113 114/*ARGSUSED*/ 115uint64_t 116hv_cpu_qconf(int queue, uint64_t paddr, int size) 117{ return (0); } 118 119/*ARGSUSED*/ 120uint64_t 121hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 122{ return (0); } 123 124/*ARGSUSED*/ 125uint64_t 126hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 127{ return (0); } 128 129/*ARGSUSED*/ 130uint64_t 131hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 132{ return (0); } 133 134/*ARGSUSED*/ 135uint64_t 136hvio_intr_getstate(uint64_t sysino, int *intr_state) 137{ return (0); } 138 139/*ARGSUSED*/ 140uint64_t 141hvio_intr_setstate(uint64_t sysino, int intr_state) 142{ return (0); } 143 144/*ARGSUSED*/ 145uint64_t 146hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 147{ return (0); } 148 149/*ARGSUSED*/ 150uint64_t 151hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 152{ return (0); } 153 154uint64_t 155hv_cpu_yield(void) 156{ return (0); } 157 158/*ARGSUSED*/ 159uint64_t 160hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 161{ return (0); } 162 163/*ARGSUSED*/ 164uint64_t 165hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 166{ return (0); } 167 168/*ARGSUSED*/ 169uint64_t 170hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 171{ return (0); } 172 173/*ARGSUSED*/ 174uint64_t 175hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 176{ return (0); } 177 178/*ARGSUSED*/ 179uint64_t 180hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 181{ return (0); } 182 183/*ARGSUSED*/ 184uint64_t 185hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 186{ return (0); } 187 188/*ARGSUSED*/ 189uint64_t 190hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 191{ return (0); } 192 193/*ARGSUSED*/ 194uint64_t 195hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 196{ return (0); } 197 198/*ARGSUSED*/ 199uint64_t 200hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 201{ return (0); } 202 203/*ARGSUSED*/ 204uint64_t 205hv_ra2pa(uint64_t ra) 206{ return (0); } 207 208/*ARGSUSED*/ 209uint64_t 210hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 211{ return (0); } 212 213/*ARGSUSED*/ 214uint64_t 215hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 216{ return (0); } 217 218/*ARGSUSED*/ 219uint64_t 220hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 221{ return (0); } 222 223/*ARGSUSED*/ 224uint64_t 225hv_ldc_tx_get_state(uint64_t channel, 226 uint64_t *headp, uint64_t *tailp, uint64_t *state) 227{ return (0); } 228 229/*ARGSUSED*/ 230uint64_t 231hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 232{ return (0); } 233 234/*ARGSUSED*/ 235uint64_t 236hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 237{ return (0); } 238 239/*ARGSUSED*/ 240uint64_t 241hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 242{ return (0); } 243 244/*ARGSUSED*/ 245uint64_t 246hv_ldc_rx_get_state(uint64_t channel, 247 uint64_t *headp, uint64_t *tailp, uint64_t *state) 248{ return (0); } 249 250/*ARGSUSED*/ 251uint64_t 252hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 253{ return (0); } 254 255/*ARGSUSED*/ 256uint64_t 257hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra) 258{ return (0); } 259 260/*ARGSUSED*/ 261uint64_t 262hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries) 263{ return (0); } 264 265/*ARGSUSED*/ 266uint64_t 267hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 268 uint64_t raddr, uint64_t length, uint64_t *lengthp) 269{ return (0); } 270 271/*ARGSUSED*/ 272uint64_t 273hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie) 274{ return (0); } 275 276/*ARGSUSED*/ 277uint64_t 278hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie) 279{ return (0); } 280 281/*ARGSUSED*/ 282uint64_t 283hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state) 284{ return (0); } 285 286/*ARGSUSED*/ 287uint64_t 288hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state) 289{ return (0); } 290 291/*ARGSUSED*/ 292uint64_t 293hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state) 294{ return (0); } 295 296/*ARGSUSED*/ 297uint64_t 298hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state) 299{ return (0); } 300 301/*ARGSUSED*/ 302uint64_t 303hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid) 304{ return (0); } 305 306/*ARGSUSED*/ 307uint64_t 308hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid) 309{ return (0); } 310 311/*ARGSUSED*/ 312uint64_t 313hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp) 314{ return (0); } 315 316/*ARGSUSED*/ 317uint64_t 318hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor, 319 uint64_t *supported_minor) 320{ return (0); } 321 322/*ARGSUSED*/ 323uint64_t 324hv_tm_enable(uint64_t enable) 325{ return (0); } 326 327/*ARGSUSED*/ 328uint64_t 329hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 330{ return (0); } 331 332/*ARGSUSED*/ 333int64_t 334hv_cnwrite(uint64_t buf_ra, uint64_t count, uint64_t *retcount) 335{ return (0); } 336 337/*ARGSUSED*/ 338int64_t 339hv_cnread(uint64_t buf_ra, uint64_t count, int64_t *retcount) 340{ return (0); } 341 342/*ARGSUSED*/ 343uint64_t 344hv_soft_state_set(uint64_t state, uint64_t string) 345{ return (0); } 346 347/*ARGSUSED*/ 348uint64_t 349hv_soft_state_get(uint64_t string, uint64_t *state) 350{ return (0); } 351 352#else /* lint || __lint */ 353 354 /* 355 * int hv_mach_exit(uint64_t exit_code) 356 */ 357 ENTRY(hv_mach_exit) 358 mov HV_MACH_EXIT, %o5 359 ta FAST_TRAP 360 retl 361 nop 362 SET_SIZE(hv_mach_exit) 363 364 /* 365 * uint64_t hv_mach_sir(void) 366 */ 367 ENTRY(hv_mach_sir) 368 mov HV_MACH_SIR, %o5 369 ta FAST_TRAP 370 retl 371 nop 372 SET_SIZE(hv_mach_sir) 373 374 /* 375 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 376 * uint64_t arg) 377 */ 378 ENTRY(hv_cpu_start) 379 mov HV_CPU_START, %o5 380 ta FAST_TRAP 381 retl 382 nop 383 SET_SIZE(hv_cpu_start) 384 385 /* 386 * hv_cpu_stop(uint64_t cpuid) 387 */ 388 ENTRY(hv_cpu_stop) 389 mov HV_CPU_STOP, %o5 390 ta FAST_TRAP 391 retl 392 nop 393 SET_SIZE(hv_cpu_stop) 394 395 /* 396 * hv_cpu_set_rtba(uint64_t *rtba) 397 */ 398 ENTRY(hv_cpu_set_rtba) 399 mov %o0, %o2 400 ldx [%o2], %o0 401 mov HV_CPU_SET_RTBA, %o5 402 ta FAST_TRAP 403 stx %o1, [%o2] 404 retl 405 nop 406 SET_SIZE(hv_cpu_set_rtba) 407 408 /* 409 * int64_t hv_cnputchar(uint8_t ch) 410 */ 411 ENTRY(hv_cnputchar) 412 mov CONS_PUTCHAR, %o5 413 ta FAST_TRAP 414 retl 415 nop 416 SET_SIZE(hv_cnputchar) 417 418 /* 419 * int64_t hv_cngetchar(uint8_t *ch) 420 */ 421 ENTRY(hv_cngetchar) 422 mov %o0, %o2 423 mov CONS_GETCHAR, %o5 424 ta FAST_TRAP 425 brnz,a %o0, 1f ! failure, just return error 426 nop 427 428 cmp %o1, H_BREAK 429 be 1f 430 mov %o1, %o0 431 432 cmp %o1, H_HUP 433 be 1f 434 mov %o1, %o0 435 436 stb %o1, [%o2] ! success, save character and return 0 437 mov 0, %o0 4381: 439 retl 440 nop 441 SET_SIZE(hv_cngetchar) 442 443 ENTRY(hv_tod_get) 444 mov %o0, %o4 445 mov TOD_GET, %o5 446 ta FAST_TRAP 447 retl 448 stx %o1, [%o4] 449 SET_SIZE(hv_tod_get) 450 451 ENTRY(hv_tod_set) 452 mov TOD_SET, %o5 453 ta FAST_TRAP 454 retl 455 nop 456 SET_SIZE(hv_tod_set) 457 458 /* 459 * Map permanent address 460 * arg0 vaddr (%o0) 461 * arg1 context (%o1) 462 * arg2 tte (%o2) 463 * arg3 flags (%o3) 0x1=d 0x2=i 464 */ 465 ENTRY(hv_mmu_map_perm_addr) 466 mov MAP_PERM_ADDR, %o5 467 ta FAST_TRAP 468 retl 469 nop 470 SET_SIZE(hv_mmu_map_perm_addr) 471 472 /* 473 * hv_mmu_fault_area_conf(void *raddr) 474 */ 475 ENTRY(hv_mmu_fault_area_conf) 476 mov %o0, %o2 477 ldx [%o2], %o0 478 mov MMU_SET_INFOPTR, %o5 479 ta FAST_TRAP 480 stx %o1, [%o2] 481 retl 482 nop 483 SET_SIZE(hv_mmu_fault_area_conf) 484 485 /* 486 * Unmap permanent address 487 * arg0 vaddr (%o0) 488 * arg1 context (%o1) 489 * arg2 flags (%o2) 0x1=d 0x2=i 490 */ 491 ENTRY(hv_mmu_unmap_perm_addr) 492 mov UNMAP_PERM_ADDR, %o5 493 ta FAST_TRAP 494 retl 495 nop 496 SET_SIZE(hv_mmu_unmap_perm_addr) 497 498 /* 499 * Set TSB for context 0 500 * arg0 ntsb_descriptor (%o0) 501 * arg1 desc_ra (%o1) 502 */ 503 ENTRY(hv_set_ctx0) 504 mov MMU_TSB_CTX0, %o5 505 ta FAST_TRAP 506 retl 507 nop 508 SET_SIZE(hv_set_ctx0) 509 510 /* 511 * Set TSB for context non0 512 * arg0 ntsb_descriptor (%o0) 513 * arg1 desc_ra (%o1) 514 */ 515 ENTRY(hv_set_ctxnon0) 516 mov MMU_TSB_CTXNON0, %o5 517 ta FAST_TRAP 518 retl 519 nop 520 SET_SIZE(hv_set_ctxnon0) 521 522#ifdef SET_MMU_STATS 523 /* 524 * Returns old stat area on success 525 */ 526 ENTRY(hv_mmu_set_stat_area) 527 mov MMU_STAT_AREA, %o5 528 ta FAST_TRAP 529 retl 530 nop 531 SET_SIZE(hv_mmu_set_stat_area) 532#endif /* SET_MMU_STATS */ 533 534 /* 535 * CPU Q Configure 536 * arg0 queue (%o0) 537 * arg1 Base address RA (%o1) 538 * arg2 Size (%o2) 539 */ 540 ENTRY(hv_cpu_qconf) 541 mov HV_CPU_QCONF, %o5 542 ta FAST_TRAP 543 retl 544 nop 545 SET_SIZE(hv_cpu_qconf) 546 547 /* 548 * arg0 - devhandle 549 * arg1 - devino 550 * 551 * ret0 - status 552 * ret1 - sysino 553 */ 554 ENTRY(hvio_intr_devino_to_sysino) 555 mov HVIO_INTR_DEVINO2SYSINO, %o5 556 ta FAST_TRAP 557 brz,a %o0, 1f 558 stx %o1, [%o2] 5591: retl 560 nop 561 SET_SIZE(hvio_intr_devino_to_sysino) 562 563 /* 564 * arg0 - sysino 565 * 566 * ret0 - status 567 * ret1 - intr_valid_state 568 */ 569 ENTRY(hvio_intr_getvalid) 570 mov %o1, %o2 571 mov HVIO_INTR_GETVALID, %o5 572 ta FAST_TRAP 573 brz,a %o0, 1f 574 stuw %o1, [%o2] 5751: retl 576 nop 577 SET_SIZE(hvio_intr_getvalid) 578 579 /* 580 * arg0 - sysino 581 * arg1 - intr_valid_state 582 * 583 * ret0 - status 584 */ 585 ENTRY(hvio_intr_setvalid) 586 mov HVIO_INTR_SETVALID, %o5 587 ta FAST_TRAP 588 retl 589 nop 590 SET_SIZE(hvio_intr_setvalid) 591 592 /* 593 * arg0 - sysino 594 * 595 * ret0 - status 596 * ret1 - intr_state 597 */ 598 ENTRY(hvio_intr_getstate) 599 mov %o1, %o2 600 mov HVIO_INTR_GETSTATE, %o5 601 ta FAST_TRAP 602 brz,a %o0, 1f 603 stuw %o1, [%o2] 6041: retl 605 nop 606 SET_SIZE(hvio_intr_getstate) 607 608 /* 609 * arg0 - sysino 610 * arg1 - intr_state 611 * 612 * ret0 - status 613 */ 614 ENTRY(hvio_intr_setstate) 615 mov HVIO_INTR_SETSTATE, %o5 616 ta FAST_TRAP 617 retl 618 nop 619 SET_SIZE(hvio_intr_setstate) 620 621 /* 622 * arg0 - sysino 623 * 624 * ret0 - status 625 * ret1 - cpu_id 626 */ 627 ENTRY(hvio_intr_gettarget) 628 mov %o1, %o2 629 mov HVIO_INTR_GETTARGET, %o5 630 ta FAST_TRAP 631 brz,a %o0, 1f 632 stuw %o1, [%o2] 6331: retl 634 nop 635 SET_SIZE(hvio_intr_gettarget) 636 637 /* 638 * arg0 - sysino 639 * arg1 - cpu_id 640 * 641 * ret0 - status 642 */ 643 ENTRY(hvio_intr_settarget) 644 mov HVIO_INTR_SETTARGET, %o5 645 ta FAST_TRAP 646 retl 647 nop 648 SET_SIZE(hvio_intr_settarget) 649 650 /* 651 * hv_cpu_yield(void) 652 */ 653 ENTRY(hv_cpu_yield) 654 mov HV_CPU_YIELD, %o5 655 ta FAST_TRAP 656 retl 657 nop 658 SET_SIZE(hv_cpu_yield) 659 660 /* 661 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 662 */ 663 ENTRY(hv_cpu_state) 664 mov %o1, %o4 ! save datap 665 mov HV_CPU_STATE, %o5 666 ta FAST_TRAP 667 brz,a %o0, 1f 668 stx %o1, [%o4] 6691: 670 retl 671 nop 672 SET_SIZE(hv_cpu_state) 673 674 /* 675 * HV state dump zone Configure 676 * arg0 real adrs of dump buffer (%o0) 677 * arg1 size of dump buffer (%o1) 678 * ret0 status (%o0) 679 * ret1 size of buffer on success and min size on EINVAL (%o1) 680 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 681 */ 682 ENTRY(hv_dump_buf_update) 683 mov DUMP_BUF_UPDATE, %o5 684 ta FAST_TRAP 685 retl 686 stx %o1, [%o2] 687 SET_SIZE(hv_dump_buf_update) 688 689 /* 690 * arg0 - timeout value (%o0) 691 * 692 * ret0 - status (%o0) 693 * ret1 - time_remaining (%o1) 694 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 695 */ 696 ENTRY(hv_mach_set_watchdog) 697 mov %o1, %o2 698 mov MACH_SET_WATCHDOG, %o5 699 ta FAST_TRAP 700 retl 701 stx %o1, [%o2] 702 SET_SIZE(hv_mach_set_watchdog) 703 704 /* 705 * For memory scrub 706 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 707 * uint64_t *scrubbed_len); 708 * Retun %o0 -- status 709 * %o1 -- bytes scrubbed 710 */ 711 ENTRY(hv_mem_scrub) 712 mov %o2, %o4 713 mov HV_MEM_SCRUB, %o5 714 ta FAST_TRAP 715 retl 716 stx %o1, [%o4] 717 SET_SIZE(hv_mem_scrub) 718 719 /* 720 * Flush ecache 721 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 722 * uint64_t *flushed_len); 723 * Retun %o0 -- status 724 * %o1 -- bytes flushed 725 */ 726 ENTRY(hv_mem_sync) 727 mov %o2, %o4 728 mov HV_MEM_SYNC, %o5 729 ta FAST_TRAP 730 retl 731 stx %o1, [%o4] 732 SET_SIZE(hv_mem_sync) 733 734 /* 735 * uint64_t hv_tm_enable(uint64_t enable) 736 */ 737 ENTRY(hv_tm_enable) 738 mov HV_TM_ENABLE, %o5 739 ta FAST_TRAP 740 retl 741 nop 742 SET_SIZE(hv_tm_enable) 743 744 /* 745 * TTRACE_BUF_CONF Configure 746 * arg0 RA base of buffer (%o0) 747 * arg1 buf size in no. of entries (%o1) 748 * ret0 status (%o0) 749 * ret1 minimum size in no. of entries on failure, 750 * actual size in no. of entries on success (%o1) 751 */ 752 ENTRY(hv_ttrace_buf_conf) 753 mov TTRACE_BUF_CONF, %o5 754 ta FAST_TRAP 755 retl 756 stx %o1, [%o2] 757 SET_SIZE(hv_ttrace_buf_conf) 758 759 /* 760 * TTRACE_BUF_INFO 761 * ret0 status (%o0) 762 * ret1 RA base of buffer (%o1) 763 * ret2 size in no. of entries (%o2) 764 */ 765 ENTRY(hv_ttrace_buf_info) 766 mov %o0, %o3 767 mov %o1, %o4 768 mov TTRACE_BUF_INFO, %o5 769 ta FAST_TRAP 770 stx %o1, [%o3] 771 retl 772 stx %o2, [%o4] 773 SET_SIZE(hv_ttrace_buf_info) 774 775 /* 776 * TTRACE_ENABLE 777 * arg0 enable/ disable (%o0) 778 * ret0 status (%o0) 779 * ret1 previous enable state (%o1) 780 */ 781 ENTRY(hv_ttrace_enable) 782 mov %o1, %o2 783 mov TTRACE_ENABLE, %o5 784 ta FAST_TRAP 785 retl 786 stx %o1, [%o2] 787 SET_SIZE(hv_ttrace_enable) 788 789 /* 790 * TTRACE_FREEZE 791 * arg0 enable/ freeze (%o0) 792 * ret0 status (%o0) 793 * ret1 previous freeze state (%o1) 794 */ 795 ENTRY(hv_ttrace_freeze) 796 mov %o1, %o2 797 mov TTRACE_FREEZE, %o5 798 ta FAST_TRAP 799 retl 800 stx %o1, [%o2] 801 SET_SIZE(hv_ttrace_freeze) 802 803 /* 804 * MACH_DESC 805 * arg0 buffer real address 806 * arg1 pointer to uint64_t for size of buffer 807 * ret0 status 808 * ret1 return required size of buffer / returned data size 809 */ 810 ENTRY(hv_mach_desc) 811 mov %o1, %o4 ! save datap 812 ldx [%o1], %o1 813 mov HV_MACH_DESC, %o5 814 ta FAST_TRAP 815 retl 816 stx %o1, [%o4] 817 SET_SIZE(hv_mach_desc) 818 819 /* 820 * hv_ra2pa(uint64_t ra) 821 * 822 * MACH_DESC 823 * arg0 Real address to convert 824 * ret0 Returned physical address or -1 on error 825 */ 826 ENTRY(hv_ra2pa) 827 mov HV_RA2PA, %o5 828 ta FAST_TRAP 829 cmp %o0, 0 830 move %xcc, %o1, %o0 831 movne %xcc, -1, %o0 832 retl 833 nop 834 SET_SIZE(hv_ra2pa) 835 836 /* 837 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 838 * 839 * MACH_DESC 840 * arg0 OS function to call 841 * arg1 First arg to OS function 842 * arg2 Second arg to OS function 843 * arg3 Third arg to OS function 844 * ret0 Returned value from function 845 */ 846 847 ENTRY(hv_hpriv) 848 mov HV_HPRIV, %o5 849 ta FAST_TRAP 850 retl 851 nop 852 SET_SIZE(hv_hpriv) 853 854 /* 855 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 856 * uint64_t nentries); 857 */ 858 ENTRY(hv_ldc_tx_qconf) 859 mov LDC_TX_QCONF, %o5 860 ta FAST_TRAP 861 retl 862 nop 863 SET_SIZE(hv_ldc_tx_qconf) 864 865 866 /* 867 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 868 * uint64_t *nentries); 869 */ 870 ENTRY(hv_ldc_tx_qinfo) 871 mov %o1, %g1 872 mov %o2, %g2 873 mov LDC_TX_QINFO, %o5 874 ta FAST_TRAP 875 stx %o1, [%g1] 876 retl 877 stx %o2, [%g2] 878 SET_SIZE(hv_ldc_tx_qinfo) 879 880 881 /* 882 * hv_ldc_tx_get_state(uint64_t channel, 883 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 884 */ 885 ENTRY(hv_ldc_tx_get_state) 886 mov LDC_TX_GET_STATE, %o5 887 mov %o1, %g1 888 mov %o2, %g2 889 mov %o3, %g3 890 ta FAST_TRAP 891 stx %o1, [%g1] 892 stx %o2, [%g2] 893 retl 894 stx %o3, [%g3] 895 SET_SIZE(hv_ldc_tx_get_state) 896 897 898 /* 899 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 900 */ 901 ENTRY(hv_ldc_tx_set_qtail) 902 mov LDC_TX_SET_QTAIL, %o5 903 ta FAST_TRAP 904 retl 905 SET_SIZE(hv_ldc_tx_set_qtail) 906 907 908 /* 909 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 910 * uint64_t nentries); 911 */ 912 ENTRY(hv_ldc_rx_qconf) 913 mov LDC_RX_QCONF, %o5 914 ta FAST_TRAP 915 retl 916 nop 917 SET_SIZE(hv_ldc_rx_qconf) 918 919 920 /* 921 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 922 * uint64_t *nentries); 923 */ 924 ENTRY(hv_ldc_rx_qinfo) 925 mov %o1, %g1 926 mov %o2, %g2 927 mov LDC_RX_QINFO, %o5 928 ta FAST_TRAP 929 stx %o1, [%g1] 930 retl 931 stx %o2, [%g2] 932 SET_SIZE(hv_ldc_rx_qinfo) 933 934 935 /* 936 * hv_ldc_rx_get_state(uint64_t channel, 937 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 938 */ 939 ENTRY(hv_ldc_rx_get_state) 940 mov LDC_RX_GET_STATE, %o5 941 mov %o1, %g1 942 mov %o2, %g2 943 mov %o3, %g3 944 ta FAST_TRAP 945 stx %o1, [%g1] 946 stx %o2, [%g2] 947 retl 948 stx %o3, [%g3] 949 SET_SIZE(hv_ldc_rx_get_state) 950 951 952 /* 953 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 954 */ 955 ENTRY(hv_ldc_rx_set_qhead) 956 mov LDC_RX_SET_QHEAD, %o5 957 ta FAST_TRAP 958 retl 959 SET_SIZE(hv_ldc_rx_set_qhead) 960 961 /* 962 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 963 * uint64_t tbl_entries) 964 */ 965 ENTRY(hv_ldc_set_map_table) 966 mov LDC_SET_MAP_TABLE, %o5 967 ta FAST_TRAP 968 retl 969 nop 970 SET_SIZE(hv_ldc_set_map_table) 971 972 973 /* 974 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 975 * uint64_t *tbl_entries) 976 */ 977 ENTRY(hv_ldc_get_map_table) 978 mov %o1, %g1 979 mov %o2, %g2 980 mov LDC_GET_MAP_TABLE, %o5 981 ta FAST_TRAP 982 stx %o1, [%g1] 983 retl 984 stx %o2, [%g2] 985 SET_SIZE(hv_ldc_get_map_table) 986 987 988 /* 989 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 990 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 991 */ 992 ENTRY(hv_ldc_copy) 993 mov %o5, %g1 994 mov LDC_COPY, %o5 995 ta FAST_TRAP 996 retl 997 stx %o1, [%g1] 998 SET_SIZE(hv_ldc_copy) 999 1000 1001 /* 1002 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 1003 * uint64_t *perm) 1004 */ 1005 ENTRY(hv_ldc_mapin) 1006 mov %o2, %g1 1007 mov %o3, %g2 1008 mov LDC_MAPIN, %o5 1009 ta FAST_TRAP 1010 stx %o1, [%g1] 1011 retl 1012 stx %o2, [%g2] 1013 SET_SIZE(hv_ldc_mapin) 1014 1015 1016 /* 1017 * hv_ldc_unmap(uint64_t raddr) 1018 */ 1019 ENTRY(hv_ldc_unmap) 1020 mov LDC_UNMAP, %o5 1021 ta FAST_TRAP 1022 retl 1023 nop 1024 SET_SIZE(hv_ldc_unmap) 1025 1026 1027 /* 1028 * hv_ldc_revoke(uint64_t channel, uint64_t cookie, 1029 * uint64_t revoke_cookie 1030 */ 1031 ENTRY(hv_ldc_revoke) 1032 mov LDC_REVOKE, %o5 1033 ta FAST_TRAP 1034 retl 1035 nop 1036 SET_SIZE(hv_ldc_revoke) 1037 1038 1039 /* 1040 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 1041 * uint64_t *cookie); 1042 */ 1043 ENTRY(hvldc_intr_getcookie) 1044 mov %o2, %g1 1045 mov VINTR_GET_COOKIE, %o5 1046 ta FAST_TRAP 1047 retl 1048 stx %o1, [%g1] 1049 SET_SIZE(hvldc_intr_getcookie) 1050 1051 /* 1052 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 1053 * uint64_t cookie); 1054 */ 1055 ENTRY(hvldc_intr_setcookie) 1056 mov VINTR_SET_COOKIE, %o5 1057 ta FAST_TRAP 1058 retl 1059 nop 1060 SET_SIZE(hvldc_intr_setcookie) 1061 1062 1063 /* 1064 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 1065 * int *intr_valid_state); 1066 */ 1067 ENTRY(hvldc_intr_getvalid) 1068 mov %o2, %g1 1069 mov VINTR_GET_VALID, %o5 1070 ta FAST_TRAP 1071 retl 1072 stuw %o1, [%g1] 1073 SET_SIZE(hvldc_intr_getvalid) 1074 1075 /* 1076 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 1077 * int intr_valid_state); 1078 */ 1079 ENTRY(hvldc_intr_setvalid) 1080 mov VINTR_SET_VALID, %o5 1081 ta FAST_TRAP 1082 retl 1083 nop 1084 SET_SIZE(hvldc_intr_setvalid) 1085 1086 /* 1087 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 1088 * int *intr_state); 1089 */ 1090 ENTRY(hvldc_intr_getstate) 1091 mov %o2, %g1 1092 mov VINTR_GET_STATE, %o5 1093 ta FAST_TRAP 1094 retl 1095 stuw %o1, [%g1] 1096 SET_SIZE(hvldc_intr_getstate) 1097 1098 /* 1099 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 1100 * int intr_state); 1101 */ 1102 ENTRY(hvldc_intr_setstate) 1103 mov VINTR_SET_STATE, %o5 1104 ta FAST_TRAP 1105 retl 1106 nop 1107 SET_SIZE(hvldc_intr_setstate) 1108 1109 /* 1110 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 1111 * uint32_t *cpuid); 1112 */ 1113 ENTRY(hvldc_intr_gettarget) 1114 mov %o2, %g1 1115 mov VINTR_GET_TARGET, %o5 1116 ta FAST_TRAP 1117 retl 1118 stuw %o1, [%g1] 1119 SET_SIZE(hvldc_intr_gettarget) 1120 1121 /* 1122 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 1123 * uint32_t cpuid); 1124 */ 1125 ENTRY(hvldc_intr_settarget) 1126 mov VINTR_SET_TARGET, %o5 1127 ta FAST_TRAP 1128 retl 1129 nop 1130 SET_SIZE(hvldc_intr_settarget) 1131 1132 /* 1133 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 1134 * uint64_t *minorp) 1135 * 1136 * API_GET_VERSION 1137 * arg0 API group 1138 * ret0 status 1139 * ret1 major number 1140 * ret2 minor number 1141 */ 1142 ENTRY(hv_api_get_version) 1143 mov %o1, %o3 1144 mov %o2, %o4 1145 mov API_GET_VERSION, %o5 1146 ta CORE_TRAP 1147 stx %o1, [%o3] 1148 retl 1149 stx %o2, [%o4] 1150 SET_SIZE(hv_api_get_version) 1151 1152 /* 1153 * hv_api_set_version(uint64_t api_group, uint64_t major, 1154 * uint64_t minor, uint64_t *supported_minor) 1155 * 1156 * API_SET_VERSION 1157 * arg0 API group 1158 * arg1 major number 1159 * arg2 requested minor number 1160 * ret0 status 1161 * ret1 actual minor number 1162 */ 1163 ENTRY(hv_api_set_version) 1164 mov %o3, %o4 1165 mov API_SET_VERSION, %o5 1166 ta CORE_TRAP 1167 retl 1168 stx %o1, [%o4] 1169 SET_SIZE(hv_api_set_version) 1170 1171 /* 1172 * %o0 - buffer real address 1173 * %o1 - buffer size 1174 * %o2 - &characters written 1175 * returns 1176 * status 1177 */ 1178 ENTRY(hv_cnwrite) 1179 mov CONS_WRITE, %o5 1180 ta FAST_TRAP 1181 retl 1182 stx %o1, [%o2] 1183 SET_SIZE(hv_cnwrite) 1184 1185 /* 1186 * %o0 character buffer ra 1187 * %o1 buffer size 1188 * %o2 pointer to returned size 1189 * return values: 1190 * 0 success 1191 * hv_errno failure 1192 */ 1193 ENTRY(hv_cnread) 1194 mov CONS_READ, %o5 1195 ta FAST_TRAP 1196 brnz,a %o0, 1f ! failure, just return error 1197 nop 1198 1199 cmp %o1, H_BREAK 1200 be 1f 1201 mov %o1, %o0 1202 1203 cmp %o1, H_HUP 1204 be 1f 1205 mov %o1, %o0 1206 1207 stx %o1, [%o2] ! success, save count and return 0 1208 mov 0, %o0 12091: 1210 retl 1211 nop 1212 SET_SIZE(hv_cnread) 1213 1214 /* 1215 * SOFT_STATE_SET 1216 * arg0 state (%o0) 1217 * arg1 string (%o1) 1218 * ret0 status (%o0) 1219 */ 1220 ENTRY(hv_soft_state_set) 1221 mov SOFT_STATE_SET, %o5 1222 ta FAST_TRAP 1223 retl 1224 nop 1225 SET_SIZE(hv_soft_state_set) 1226 1227 /* 1228 * SOFT_STATE_GET 1229 * arg0 string buffer (%o0) 1230 * ret0 status (%o0) 1231 * ret1 current state (%o1) 1232 */ 1233 ENTRY(hv_soft_state_get) 1234 mov %o1, %o2 1235 mov SOFT_STATE_GET, %o5 1236 ta FAST_TRAP 1237 retl 1238 stx %o1, [%o2] 1239 SET_SIZE(hv_soft_state_get) 1240 1241#endif /* lint || __lint */ 1242