1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Hypervisor calls 29 */ 30 31#include <sys/asm_linkage.h> 32#include <sys/machasi.h> 33#include <sys/machparam.h> 34#include <sys/hypervisor_api.h> 35 36#if defined(lint) || defined(__lint) 37 38/*ARGSUSED*/ 39uint64_t 40hv_mach_exit(uint64_t exit_code) 41{ return (0); } 42 43uint64_t 44hv_mach_sir(void) 45{ return (0); } 46 47/*ARGSUSED*/ 48uint64_t 49hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg) 50{ return (0); } 51 52/*ARGSUSED*/ 53uint64_t 54hv_cpu_stop(uint64_t cpuid) 55{ return (0); } 56 57/*ARGSUSED*/ 58uint64_t 59hv_cpu_set_rtba(uint64_t *rtba) 60{ return (0); } 61 62/*ARGSUSED*/ 63int64_t 64hv_cnputchar(uint8_t ch) 65{ return (0); } 66 67/*ARGSUSED*/ 68int64_t 69hv_cngetchar(uint8_t *ch) 70{ return (0); } 71 72/*ARGSUSED*/ 73uint64_t 74hv_tod_get(uint64_t *seconds) 75{ return (0); } 76 77/*ARGSUSED*/ 78uint64_t 79hv_tod_set(uint64_t seconds) 80{ return (0);} 81 82/*ARGSUSED*/ 83uint64_t 84hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 85{ return (0); } 86 87/*ARGSUSED */ 88uint64_t 89hv_mmu_fault_area_conf(void *raddr) 90{ return (0); } 91 92/*ARGSUSED*/ 93uint64_t 94hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 95{ return (0); } 96 97/*ARGSUSED*/ 98uint64_t 99hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 100{ return (0); } 101 102/*ARGSUSED*/ 103uint64_t 104hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 105{ return (0); } 106 107#ifdef SET_MMU_STATS 108/*ARGSUSED*/ 109uint64_t 110hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 111{ return (0); } 112#endif /* SET_MMU_STATS */ 113 114/*ARGSUSED*/ 115uint64_t 116hv_cpu_qconf(int queue, uint64_t paddr, int size) 117{ return (0); } 118 119/*ARGSUSED*/ 120uint64_t 121hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 122{ return (0); } 123 124/*ARGSUSED*/ 125uint64_t 126hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 127{ return (0); } 128 129/*ARGSUSED*/ 130uint64_t 131hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 132{ return (0); } 133 134/*ARGSUSED*/ 135uint64_t 136hvio_intr_getstate(uint64_t sysino, int *intr_state) 137{ return (0); } 138 139/*ARGSUSED*/ 140uint64_t 141hvio_intr_setstate(uint64_t sysino, int intr_state) 142{ return (0); } 143 144/*ARGSUSED*/ 145uint64_t 146hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 147{ return (0); } 148 149/*ARGSUSED*/ 150uint64_t 151hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 152{ return (0); } 153 154uint64_t 155hv_cpu_yield(void) 156{ return (0); } 157 158/*ARGSUSED*/ 159uint64_t 160hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 161{ return (0); } 162 163/*ARGSUSED*/ 164uint64_t 165hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 166{ return (0); } 167 168/*ARGSUSED*/ 169uint64_t 170hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 171{ return (0); } 172 173/*ARGSUSED*/ 174uint64_t 175hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 176{ return (0); } 177 178/*ARGSUSED*/ 179uint64_t 180hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 181{ return (0); } 182 183/*ARGSUSED*/ 184uint64_t 185hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 186{ return (0); } 187 188/*ARGSUSED*/ 189uint64_t 190hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 191{ return (0); } 192 193/*ARGSUSED*/ 194uint64_t 195hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 196{ return (0); } 197 198/*ARGSUSED*/ 199uint64_t 200hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 201{ return (0); } 202 203/*ARGSUSED*/ 204uint64_t 205hv_ra2pa(uint64_t ra) 206{ return (0); } 207 208/*ARGSUSED*/ 209uint64_t 210hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 211{ return (0); } 212 213/*ARGSUSED*/ 214uint64_t 215hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 216{ return (0); } 217 218/*ARGSUSED*/ 219uint64_t 220hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 221{ return (0); } 222 223/*ARGSUSED*/ 224uint64_t 225hv_ldc_tx_get_state(uint64_t channel, 226 uint64_t *headp, uint64_t *tailp, uint64_t *state) 227{ return (0); } 228 229/*ARGSUSED*/ 230uint64_t 231hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 232{ return (0); } 233 234/*ARGSUSED*/ 235uint64_t 236hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 237{ return (0); } 238 239/*ARGSUSED*/ 240uint64_t 241hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 242{ return (0); } 243 244/*ARGSUSED*/ 245uint64_t 246hv_ldc_rx_get_state(uint64_t channel, 247 uint64_t *headp, uint64_t *tailp, uint64_t *state) 248{ return (0); } 249 250/*ARGSUSED*/ 251uint64_t 252hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 253{ return (0); } 254 255/*ARGSUSED*/ 256uint64_t 257hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra) 258{ return (0); } 259 260/*ARGSUSED*/ 261uint64_t 262hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries) 263{ return (0); } 264 265/*ARGSUSED*/ 266uint64_t 267hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 268 uint64_t raddr, uint64_t length, uint64_t *lengthp) 269{ return (0); } 270 271/*ARGSUSED*/ 272uint64_t 273hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie) 274{ return (0); } 275 276/*ARGSUSED*/ 277uint64_t 278hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie) 279{ return (0); } 280 281/*ARGSUSED*/ 282uint64_t 283hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state) 284{ return (0); } 285 286/*ARGSUSED*/ 287uint64_t 288hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state) 289{ return (0); } 290 291/*ARGSUSED*/ 292uint64_t 293hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state) 294{ return (0); } 295 296/*ARGSUSED*/ 297uint64_t 298hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state) 299{ return (0); } 300 301/*ARGSUSED*/ 302uint64_t 303hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid) 304{ return (0); } 305 306/*ARGSUSED*/ 307uint64_t 308hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid) 309{ return (0); } 310 311/*ARGSUSED*/ 312uint64_t 313hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp) 314{ return (0); } 315 316/*ARGSUSED*/ 317uint64_t 318hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor, 319 uint64_t *supported_minor) 320{ return (0); } 321 322/*ARGSUSED*/ 323uint64_t 324hv_tm_enable(uint64_t enable) 325{ return (0); } 326 327/*ARGSUSED*/ 328uint64_t 329hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 330{ return (0); } 331 332/*ARGSUSED*/ 333int64_t 334hv_cnwrite(uint64_t buf_ra, uint64_t count, uint64_t *retcount) 335{ return (0); } 336 337/*ARGSUSED*/ 338int64_t 339hv_cnread(uint64_t buf_ra, uint64_t count, int64_t *retcount) 340{ return (0); } 341 342/*ARGSUSED*/ 343uint64_t 344hv_soft_state_set(uint64_t state, uint64_t string) 345{ return (0); } 346 347/*ARGSUSED*/ 348uint64_t 349hv_soft_state_get(uint64_t string, uint64_t *state) 350{ return (0); } 351 352uint64_t 353hv_guest_suspend(void) 354{ return (0); } 355 356/*ARGSUSED*/ 357uint64_t 358hv_set_tick_npt(uint64_t npt) 359{ return (0); } 360 361/*ARGSUSED*/ 362uint64_t 363hv_set_stick_npt(uint64_t npt) 364{ return (0); } 365 366#else /* lint || __lint */ 367 368 /* 369 * int hv_mach_exit(uint64_t exit_code) 370 */ 371 ENTRY(hv_mach_exit) 372 mov HV_MACH_EXIT, %o5 373 ta FAST_TRAP 374 retl 375 nop 376 SET_SIZE(hv_mach_exit) 377 378 /* 379 * uint64_t hv_mach_sir(void) 380 */ 381 ENTRY(hv_mach_sir) 382 mov HV_MACH_SIR, %o5 383 ta FAST_TRAP 384 retl 385 nop 386 SET_SIZE(hv_mach_sir) 387 388 /* 389 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 390 * uint64_t arg) 391 */ 392 ENTRY(hv_cpu_start) 393 mov HV_CPU_START, %o5 394 ta FAST_TRAP 395 retl 396 nop 397 SET_SIZE(hv_cpu_start) 398 399 /* 400 * hv_cpu_stop(uint64_t cpuid) 401 */ 402 ENTRY(hv_cpu_stop) 403 mov HV_CPU_STOP, %o5 404 ta FAST_TRAP 405 retl 406 nop 407 SET_SIZE(hv_cpu_stop) 408 409 /* 410 * hv_cpu_set_rtba(uint64_t *rtba) 411 */ 412 ENTRY(hv_cpu_set_rtba) 413 mov %o0, %o2 414 ldx [%o2], %o0 415 mov HV_CPU_SET_RTBA, %o5 416 ta FAST_TRAP 417 stx %o1, [%o2] 418 retl 419 nop 420 SET_SIZE(hv_cpu_set_rtba) 421 422 /* 423 * int64_t hv_cnputchar(uint8_t ch) 424 */ 425 ENTRY(hv_cnputchar) 426 mov CONS_PUTCHAR, %o5 427 ta FAST_TRAP 428 retl 429 nop 430 SET_SIZE(hv_cnputchar) 431 432 /* 433 * int64_t hv_cngetchar(uint8_t *ch) 434 */ 435 ENTRY(hv_cngetchar) 436 mov %o0, %o2 437 mov CONS_GETCHAR, %o5 438 ta FAST_TRAP 439 brnz,a %o0, 1f ! failure, just return error 440 nop 441 442 cmp %o1, H_BREAK 443 be 1f 444 mov %o1, %o0 445 446 cmp %o1, H_HUP 447 be 1f 448 mov %o1, %o0 449 450 stb %o1, [%o2] ! success, save character and return 0 451 mov 0, %o0 4521: 453 retl 454 nop 455 SET_SIZE(hv_cngetchar) 456 457 ENTRY(hv_tod_get) 458 mov %o0, %o4 459 mov TOD_GET, %o5 460 ta FAST_TRAP 461 retl 462 stx %o1, [%o4] 463 SET_SIZE(hv_tod_get) 464 465 ENTRY(hv_tod_set) 466 mov TOD_SET, %o5 467 ta FAST_TRAP 468 retl 469 nop 470 SET_SIZE(hv_tod_set) 471 472 /* 473 * Map permanent address 474 * arg0 vaddr (%o0) 475 * arg1 context (%o1) 476 * arg2 tte (%o2) 477 * arg3 flags (%o3) 0x1=d 0x2=i 478 */ 479 ENTRY(hv_mmu_map_perm_addr) 480 mov MAP_PERM_ADDR, %o5 481 ta FAST_TRAP 482 retl 483 nop 484 SET_SIZE(hv_mmu_map_perm_addr) 485 486 /* 487 * hv_mmu_fault_area_conf(void *raddr) 488 */ 489 ENTRY(hv_mmu_fault_area_conf) 490 mov %o0, %o2 491 ldx [%o2], %o0 492 mov MMU_SET_INFOPTR, %o5 493 ta FAST_TRAP 494 stx %o1, [%o2] 495 retl 496 nop 497 SET_SIZE(hv_mmu_fault_area_conf) 498 499 /* 500 * Unmap permanent address 501 * arg0 vaddr (%o0) 502 * arg1 context (%o1) 503 * arg2 flags (%o2) 0x1=d 0x2=i 504 */ 505 ENTRY(hv_mmu_unmap_perm_addr) 506 mov UNMAP_PERM_ADDR, %o5 507 ta FAST_TRAP 508 retl 509 nop 510 SET_SIZE(hv_mmu_unmap_perm_addr) 511 512 /* 513 * Set TSB for context 0 514 * arg0 ntsb_descriptor (%o0) 515 * arg1 desc_ra (%o1) 516 */ 517 ENTRY(hv_set_ctx0) 518 mov MMU_TSB_CTX0, %o5 519 ta FAST_TRAP 520 retl 521 nop 522 SET_SIZE(hv_set_ctx0) 523 524 /* 525 * Set TSB for context non0 526 * arg0 ntsb_descriptor (%o0) 527 * arg1 desc_ra (%o1) 528 */ 529 ENTRY(hv_set_ctxnon0) 530 mov MMU_TSB_CTXNON0, %o5 531 ta FAST_TRAP 532 retl 533 nop 534 SET_SIZE(hv_set_ctxnon0) 535 536#ifdef SET_MMU_STATS 537 /* 538 * Returns old stat area on success 539 */ 540 ENTRY(hv_mmu_set_stat_area) 541 mov MMU_STAT_AREA, %o5 542 ta FAST_TRAP 543 retl 544 nop 545 SET_SIZE(hv_mmu_set_stat_area) 546#endif /* SET_MMU_STATS */ 547 548 /* 549 * CPU Q Configure 550 * arg0 queue (%o0) 551 * arg1 Base address RA (%o1) 552 * arg2 Size (%o2) 553 */ 554 ENTRY(hv_cpu_qconf) 555 mov HV_CPU_QCONF, %o5 556 ta FAST_TRAP 557 retl 558 nop 559 SET_SIZE(hv_cpu_qconf) 560 561 /* 562 * arg0 - devhandle 563 * arg1 - devino 564 * 565 * ret0 - status 566 * ret1 - sysino 567 */ 568 ENTRY(hvio_intr_devino_to_sysino) 569 mov HVIO_INTR_DEVINO2SYSINO, %o5 570 ta FAST_TRAP 571 brz,a %o0, 1f 572 stx %o1, [%o2] 5731: retl 574 nop 575 SET_SIZE(hvio_intr_devino_to_sysino) 576 577 /* 578 * arg0 - sysino 579 * 580 * ret0 - status 581 * ret1 - intr_valid_state 582 */ 583 ENTRY(hvio_intr_getvalid) 584 mov %o1, %o2 585 mov HVIO_INTR_GETVALID, %o5 586 ta FAST_TRAP 587 brz,a %o0, 1f 588 stuw %o1, [%o2] 5891: retl 590 nop 591 SET_SIZE(hvio_intr_getvalid) 592 593 /* 594 * arg0 - sysino 595 * arg1 - intr_valid_state 596 * 597 * ret0 - status 598 */ 599 ENTRY(hvio_intr_setvalid) 600 mov HVIO_INTR_SETVALID, %o5 601 ta FAST_TRAP 602 retl 603 nop 604 SET_SIZE(hvio_intr_setvalid) 605 606 /* 607 * arg0 - sysino 608 * 609 * ret0 - status 610 * ret1 - intr_state 611 */ 612 ENTRY(hvio_intr_getstate) 613 mov %o1, %o2 614 mov HVIO_INTR_GETSTATE, %o5 615 ta FAST_TRAP 616 brz,a %o0, 1f 617 stuw %o1, [%o2] 6181: retl 619 nop 620 SET_SIZE(hvio_intr_getstate) 621 622 /* 623 * arg0 - sysino 624 * arg1 - intr_state 625 * 626 * ret0 - status 627 */ 628 ENTRY(hvio_intr_setstate) 629 mov HVIO_INTR_SETSTATE, %o5 630 ta FAST_TRAP 631 retl 632 nop 633 SET_SIZE(hvio_intr_setstate) 634 635 /* 636 * arg0 - sysino 637 * 638 * ret0 - status 639 * ret1 - cpu_id 640 */ 641 ENTRY(hvio_intr_gettarget) 642 mov %o1, %o2 643 mov HVIO_INTR_GETTARGET, %o5 644 ta FAST_TRAP 645 brz,a %o0, 1f 646 stuw %o1, [%o2] 6471: retl 648 nop 649 SET_SIZE(hvio_intr_gettarget) 650 651 /* 652 * arg0 - sysino 653 * arg1 - cpu_id 654 * 655 * ret0 - status 656 */ 657 ENTRY(hvio_intr_settarget) 658 mov HVIO_INTR_SETTARGET, %o5 659 ta FAST_TRAP 660 retl 661 nop 662 SET_SIZE(hvio_intr_settarget) 663 664 /* 665 * hv_cpu_yield(void) 666 */ 667 ENTRY(hv_cpu_yield) 668 mov HV_CPU_YIELD, %o5 669 ta FAST_TRAP 670 retl 671 nop 672 SET_SIZE(hv_cpu_yield) 673 674 /* 675 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 676 */ 677 ENTRY(hv_cpu_state) 678 mov %o1, %o4 ! save datap 679 mov HV_CPU_STATE, %o5 680 ta FAST_TRAP 681 brz,a %o0, 1f 682 stx %o1, [%o4] 6831: 684 retl 685 nop 686 SET_SIZE(hv_cpu_state) 687 688 /* 689 * HV state dump zone Configure 690 * arg0 real adrs of dump buffer (%o0) 691 * arg1 size of dump buffer (%o1) 692 * ret0 status (%o0) 693 * ret1 size of buffer on success and min size on EINVAL (%o1) 694 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 695 */ 696 ENTRY(hv_dump_buf_update) 697 mov DUMP_BUF_UPDATE, %o5 698 ta FAST_TRAP 699 retl 700 stx %o1, [%o2] 701 SET_SIZE(hv_dump_buf_update) 702 703 /* 704 * arg0 - timeout value (%o0) 705 * 706 * ret0 - status (%o0) 707 * ret1 - time_remaining (%o1) 708 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 709 */ 710 ENTRY(hv_mach_set_watchdog) 711 mov %o1, %o2 712 mov MACH_SET_WATCHDOG, %o5 713 ta FAST_TRAP 714 retl 715 stx %o1, [%o2] 716 SET_SIZE(hv_mach_set_watchdog) 717 718 /* 719 * For memory scrub 720 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 721 * uint64_t *scrubbed_len); 722 * Retun %o0 -- status 723 * %o1 -- bytes scrubbed 724 */ 725 ENTRY(hv_mem_scrub) 726 mov %o2, %o4 727 mov HV_MEM_SCRUB, %o5 728 ta FAST_TRAP 729 retl 730 stx %o1, [%o4] 731 SET_SIZE(hv_mem_scrub) 732 733 /* 734 * Flush ecache 735 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 736 * uint64_t *flushed_len); 737 * Retun %o0 -- status 738 * %o1 -- bytes flushed 739 */ 740 ENTRY(hv_mem_sync) 741 mov %o2, %o4 742 mov HV_MEM_SYNC, %o5 743 ta FAST_TRAP 744 retl 745 stx %o1, [%o4] 746 SET_SIZE(hv_mem_sync) 747 748 /* 749 * uint64_t hv_tm_enable(uint64_t enable) 750 */ 751 ENTRY(hv_tm_enable) 752 mov HV_TM_ENABLE, %o5 753 ta FAST_TRAP 754 retl 755 nop 756 SET_SIZE(hv_tm_enable) 757 758 /* 759 * TTRACE_BUF_CONF Configure 760 * arg0 RA base of buffer (%o0) 761 * arg1 buf size in no. of entries (%o1) 762 * ret0 status (%o0) 763 * ret1 minimum size in no. of entries on failure, 764 * actual size in no. of entries on success (%o1) 765 */ 766 ENTRY(hv_ttrace_buf_conf) 767 mov TTRACE_BUF_CONF, %o5 768 ta FAST_TRAP 769 retl 770 stx %o1, [%o2] 771 SET_SIZE(hv_ttrace_buf_conf) 772 773 /* 774 * TTRACE_BUF_INFO 775 * ret0 status (%o0) 776 * ret1 RA base of buffer (%o1) 777 * ret2 size in no. of entries (%o2) 778 */ 779 ENTRY(hv_ttrace_buf_info) 780 mov %o0, %o3 781 mov %o1, %o4 782 mov TTRACE_BUF_INFO, %o5 783 ta FAST_TRAP 784 stx %o1, [%o3] 785 retl 786 stx %o2, [%o4] 787 SET_SIZE(hv_ttrace_buf_info) 788 789 /* 790 * TTRACE_ENABLE 791 * arg0 enable/ disable (%o0) 792 * ret0 status (%o0) 793 * ret1 previous enable state (%o1) 794 */ 795 ENTRY(hv_ttrace_enable) 796 mov %o1, %o2 797 mov TTRACE_ENABLE, %o5 798 ta FAST_TRAP 799 retl 800 stx %o1, [%o2] 801 SET_SIZE(hv_ttrace_enable) 802 803 /* 804 * TTRACE_FREEZE 805 * arg0 enable/ freeze (%o0) 806 * ret0 status (%o0) 807 * ret1 previous freeze state (%o1) 808 */ 809 ENTRY(hv_ttrace_freeze) 810 mov %o1, %o2 811 mov TTRACE_FREEZE, %o5 812 ta FAST_TRAP 813 retl 814 stx %o1, [%o2] 815 SET_SIZE(hv_ttrace_freeze) 816 817 /* 818 * MACH_DESC 819 * arg0 buffer real address 820 * arg1 pointer to uint64_t for size of buffer 821 * ret0 status 822 * ret1 return required size of buffer / returned data size 823 */ 824 ENTRY(hv_mach_desc) 825 mov %o1, %o4 ! save datap 826 ldx [%o1], %o1 827 mov HV_MACH_DESC, %o5 828 ta FAST_TRAP 829 retl 830 stx %o1, [%o4] 831 SET_SIZE(hv_mach_desc) 832 833 /* 834 * hv_ra2pa(uint64_t ra) 835 * 836 * MACH_DESC 837 * arg0 Real address to convert 838 * ret0 Returned physical address or -1 on error 839 */ 840 ENTRY(hv_ra2pa) 841 mov HV_RA2PA, %o5 842 ta FAST_TRAP 843 cmp %o0, 0 844 move %xcc, %o1, %o0 845 movne %xcc, -1, %o0 846 retl 847 nop 848 SET_SIZE(hv_ra2pa) 849 850 /* 851 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 852 * 853 * MACH_DESC 854 * arg0 OS function to call 855 * arg1 First arg to OS function 856 * arg2 Second arg to OS function 857 * arg3 Third arg to OS function 858 * ret0 Returned value from function 859 */ 860 861 ENTRY(hv_hpriv) 862 mov HV_HPRIV, %o5 863 ta FAST_TRAP 864 retl 865 nop 866 SET_SIZE(hv_hpriv) 867 868 /* 869 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 870 * uint64_t nentries); 871 */ 872 ENTRY(hv_ldc_tx_qconf) 873 mov LDC_TX_QCONF, %o5 874 ta FAST_TRAP 875 retl 876 nop 877 SET_SIZE(hv_ldc_tx_qconf) 878 879 880 /* 881 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 882 * uint64_t *nentries); 883 */ 884 ENTRY(hv_ldc_tx_qinfo) 885 mov %o1, %g1 886 mov %o2, %g2 887 mov LDC_TX_QINFO, %o5 888 ta FAST_TRAP 889 stx %o1, [%g1] 890 retl 891 stx %o2, [%g2] 892 SET_SIZE(hv_ldc_tx_qinfo) 893 894 895 /* 896 * hv_ldc_tx_get_state(uint64_t channel, 897 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 898 */ 899 ENTRY(hv_ldc_tx_get_state) 900 mov LDC_TX_GET_STATE, %o5 901 mov %o1, %g1 902 mov %o2, %g2 903 mov %o3, %g3 904 ta FAST_TRAP 905 stx %o1, [%g1] 906 stx %o2, [%g2] 907 retl 908 stx %o3, [%g3] 909 SET_SIZE(hv_ldc_tx_get_state) 910 911 912 /* 913 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 914 */ 915 ENTRY(hv_ldc_tx_set_qtail) 916 mov LDC_TX_SET_QTAIL, %o5 917 ta FAST_TRAP 918 retl 919 SET_SIZE(hv_ldc_tx_set_qtail) 920 921 922 /* 923 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 924 * uint64_t nentries); 925 */ 926 ENTRY(hv_ldc_rx_qconf) 927 mov LDC_RX_QCONF, %o5 928 ta FAST_TRAP 929 retl 930 nop 931 SET_SIZE(hv_ldc_rx_qconf) 932 933 934 /* 935 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 936 * uint64_t *nentries); 937 */ 938 ENTRY(hv_ldc_rx_qinfo) 939 mov %o1, %g1 940 mov %o2, %g2 941 mov LDC_RX_QINFO, %o5 942 ta FAST_TRAP 943 stx %o1, [%g1] 944 retl 945 stx %o2, [%g2] 946 SET_SIZE(hv_ldc_rx_qinfo) 947 948 949 /* 950 * hv_ldc_rx_get_state(uint64_t channel, 951 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 952 */ 953 ENTRY(hv_ldc_rx_get_state) 954 mov LDC_RX_GET_STATE, %o5 955 mov %o1, %g1 956 mov %o2, %g2 957 mov %o3, %g3 958 ta FAST_TRAP 959 stx %o1, [%g1] 960 stx %o2, [%g2] 961 retl 962 stx %o3, [%g3] 963 SET_SIZE(hv_ldc_rx_get_state) 964 965 966 /* 967 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 968 */ 969 ENTRY(hv_ldc_rx_set_qhead) 970 mov LDC_RX_SET_QHEAD, %o5 971 ta FAST_TRAP 972 retl 973 SET_SIZE(hv_ldc_rx_set_qhead) 974 975 /* 976 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 977 * uint64_t tbl_entries) 978 */ 979 ENTRY(hv_ldc_set_map_table) 980 mov LDC_SET_MAP_TABLE, %o5 981 ta FAST_TRAP 982 retl 983 nop 984 SET_SIZE(hv_ldc_set_map_table) 985 986 987 /* 988 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 989 * uint64_t *tbl_entries) 990 */ 991 ENTRY(hv_ldc_get_map_table) 992 mov %o1, %g1 993 mov %o2, %g2 994 mov LDC_GET_MAP_TABLE, %o5 995 ta FAST_TRAP 996 stx %o1, [%g1] 997 retl 998 stx %o2, [%g2] 999 SET_SIZE(hv_ldc_get_map_table) 1000 1001 1002 /* 1003 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 1004 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 1005 */ 1006 ENTRY(hv_ldc_copy) 1007 mov %o5, %g1 1008 mov LDC_COPY, %o5 1009 ta FAST_TRAP 1010 retl 1011 stx %o1, [%g1] 1012 SET_SIZE(hv_ldc_copy) 1013 1014 1015 /* 1016 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 1017 * uint64_t *perm) 1018 */ 1019 ENTRY(hv_ldc_mapin) 1020 mov %o2, %g1 1021 mov %o3, %g2 1022 mov LDC_MAPIN, %o5 1023 ta FAST_TRAP 1024 stx %o1, [%g1] 1025 retl 1026 stx %o2, [%g2] 1027 SET_SIZE(hv_ldc_mapin) 1028 1029 1030 /* 1031 * hv_ldc_unmap(uint64_t raddr) 1032 */ 1033 ENTRY(hv_ldc_unmap) 1034 mov LDC_UNMAP, %o5 1035 ta FAST_TRAP 1036 retl 1037 nop 1038 SET_SIZE(hv_ldc_unmap) 1039 1040 1041 /* 1042 * hv_ldc_revoke(uint64_t channel, uint64_t cookie, 1043 * uint64_t revoke_cookie 1044 */ 1045 ENTRY(hv_ldc_revoke) 1046 mov LDC_REVOKE, %o5 1047 ta FAST_TRAP 1048 retl 1049 nop 1050 SET_SIZE(hv_ldc_revoke) 1051 1052 1053 /* 1054 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 1055 * uint64_t *cookie); 1056 */ 1057 ENTRY(hvldc_intr_getcookie) 1058 mov %o2, %g1 1059 mov VINTR_GET_COOKIE, %o5 1060 ta FAST_TRAP 1061 retl 1062 stx %o1, [%g1] 1063 SET_SIZE(hvldc_intr_getcookie) 1064 1065 /* 1066 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 1067 * uint64_t cookie); 1068 */ 1069 ENTRY(hvldc_intr_setcookie) 1070 mov VINTR_SET_COOKIE, %o5 1071 ta FAST_TRAP 1072 retl 1073 nop 1074 SET_SIZE(hvldc_intr_setcookie) 1075 1076 1077 /* 1078 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 1079 * int *intr_valid_state); 1080 */ 1081 ENTRY(hvldc_intr_getvalid) 1082 mov %o2, %g1 1083 mov VINTR_GET_VALID, %o5 1084 ta FAST_TRAP 1085 retl 1086 stuw %o1, [%g1] 1087 SET_SIZE(hvldc_intr_getvalid) 1088 1089 /* 1090 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 1091 * int intr_valid_state); 1092 */ 1093 ENTRY(hvldc_intr_setvalid) 1094 mov VINTR_SET_VALID, %o5 1095 ta FAST_TRAP 1096 retl 1097 nop 1098 SET_SIZE(hvldc_intr_setvalid) 1099 1100 /* 1101 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 1102 * int *intr_state); 1103 */ 1104 ENTRY(hvldc_intr_getstate) 1105 mov %o2, %g1 1106 mov VINTR_GET_STATE, %o5 1107 ta FAST_TRAP 1108 retl 1109 stuw %o1, [%g1] 1110 SET_SIZE(hvldc_intr_getstate) 1111 1112 /* 1113 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 1114 * int intr_state); 1115 */ 1116 ENTRY(hvldc_intr_setstate) 1117 mov VINTR_SET_STATE, %o5 1118 ta FAST_TRAP 1119 retl 1120 nop 1121 SET_SIZE(hvldc_intr_setstate) 1122 1123 /* 1124 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 1125 * uint32_t *cpuid); 1126 */ 1127 ENTRY(hvldc_intr_gettarget) 1128 mov %o2, %g1 1129 mov VINTR_GET_TARGET, %o5 1130 ta FAST_TRAP 1131 retl 1132 stuw %o1, [%g1] 1133 SET_SIZE(hvldc_intr_gettarget) 1134 1135 /* 1136 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 1137 * uint32_t cpuid); 1138 */ 1139 ENTRY(hvldc_intr_settarget) 1140 mov VINTR_SET_TARGET, %o5 1141 ta FAST_TRAP 1142 retl 1143 nop 1144 SET_SIZE(hvldc_intr_settarget) 1145 1146 /* 1147 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 1148 * uint64_t *minorp) 1149 * 1150 * API_GET_VERSION 1151 * arg0 API group 1152 * ret0 status 1153 * ret1 major number 1154 * ret2 minor number 1155 */ 1156 ENTRY(hv_api_get_version) 1157 mov %o1, %o3 1158 mov %o2, %o4 1159 mov API_GET_VERSION, %o5 1160 ta CORE_TRAP 1161 stx %o1, [%o3] 1162 retl 1163 stx %o2, [%o4] 1164 SET_SIZE(hv_api_get_version) 1165 1166 /* 1167 * hv_api_set_version(uint64_t api_group, uint64_t major, 1168 * uint64_t minor, uint64_t *supported_minor) 1169 * 1170 * API_SET_VERSION 1171 * arg0 API group 1172 * arg1 major number 1173 * arg2 requested minor number 1174 * ret0 status 1175 * ret1 actual minor number 1176 */ 1177 ENTRY(hv_api_set_version) 1178 mov %o3, %o4 1179 mov API_SET_VERSION, %o5 1180 ta CORE_TRAP 1181 retl 1182 stx %o1, [%o4] 1183 SET_SIZE(hv_api_set_version) 1184 1185 /* 1186 * %o0 - buffer real address 1187 * %o1 - buffer size 1188 * %o2 - &characters written 1189 * returns 1190 * status 1191 */ 1192 ENTRY(hv_cnwrite) 1193 mov CONS_WRITE, %o5 1194 ta FAST_TRAP 1195 retl 1196 stx %o1, [%o2] 1197 SET_SIZE(hv_cnwrite) 1198 1199 /* 1200 * %o0 character buffer ra 1201 * %o1 buffer size 1202 * %o2 pointer to returned size 1203 * return values: 1204 * 0 success 1205 * hv_errno failure 1206 */ 1207 ENTRY(hv_cnread) 1208 mov CONS_READ, %o5 1209 ta FAST_TRAP 1210 brnz,a %o0, 1f ! failure, just return error 1211 nop 1212 1213 cmp %o1, H_BREAK 1214 be 1f 1215 mov %o1, %o0 1216 1217 cmp %o1, H_HUP 1218 be 1f 1219 mov %o1, %o0 1220 1221 stx %o1, [%o2] ! success, save count and return 0 1222 mov 0, %o0 12231: 1224 retl 1225 nop 1226 SET_SIZE(hv_cnread) 1227 1228 /* 1229 * SOFT_STATE_SET 1230 * arg0 state (%o0) 1231 * arg1 string (%o1) 1232 * ret0 status (%o0) 1233 */ 1234 ENTRY(hv_soft_state_set) 1235 mov SOFT_STATE_SET, %o5 1236 ta FAST_TRAP 1237 retl 1238 nop 1239 SET_SIZE(hv_soft_state_set) 1240 1241 /* 1242 * SOFT_STATE_GET 1243 * arg0 string buffer (%o0) 1244 * ret0 status (%o0) 1245 * ret1 current state (%o1) 1246 */ 1247 ENTRY(hv_soft_state_get) 1248 mov %o1, %o2 1249 mov SOFT_STATE_GET, %o5 1250 ta FAST_TRAP 1251 retl 1252 stx %o1, [%o2] 1253 SET_SIZE(hv_soft_state_get) 1254 1255 ENTRY(hv_guest_suspend) 1256 mov GUEST_SUSPEND, %o5 1257 ta FAST_TRAP 1258 retl 1259 nop 1260 SET_SIZE(hv_guest_suspend) 1261 1262 ENTRY(hv_tick_set_npt) 1263 mov TICK_SET_NPT, %o5 1264 ta FAST_TRAP 1265 retl 1266 nop 1267 SET_SIZE(hv_tick_set_npt) 1268 1269 ENTRY(hv_stick_set_npt) 1270 mov STICK_SET_NPT, %o5 1271 ta FAST_TRAP 1272 retl 1273 nop 1274 SET_SIZE(hv_stick_set_npt) 1275 1276#endif /* lint || __lint */ 1277