1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Hypervisor calls 29 */ 30 31#include <sys/asm_linkage.h> 32#include <sys/machasi.h> 33#include <sys/machparam.h> 34#include <sys/hypervisor_api.h> 35 36#if defined(lint) || defined(__lint) 37 38/*ARGSUSED*/ 39uint64_t 40hv_mach_exit(uint64_t exit_code) 41{ return (0); } 42 43uint64_t 44hv_mach_sir(void) 45{ return (0); } 46 47/*ARGSUSED*/ 48uint64_t 49hv_cpu_start(uint64_t cpuid, uint64_t pc, uint64_t rtba, uint64_t arg) 50{ return (0); } 51 52/*ARGSUSED*/ 53uint64_t 54hv_cpu_stop(uint64_t cpuid) 55{ return (0); } 56 57/*ARGSUSED*/ 58uint64_t 59hv_cpu_set_rtba(uint64_t *rtba) 60{ return (0); } 61 62/*ARGSUSED*/ 63int64_t 64hv_cnputchar(uint8_t ch) 65{ return (0); } 66 67/*ARGSUSED*/ 68int64_t 69hv_cngetchar(uint8_t *ch) 70{ return (0); } 71 72/*ARGSUSED*/ 73uint64_t 74hv_tod_get(uint64_t *seconds) 75{ return (0); } 76 77/*ARGSUSED*/ 78uint64_t 79hv_tod_set(uint64_t seconds) 80{ return (0);} 81 82/*ARGSUSED*/ 83uint64_t 84hv_mmu_map_perm_addr(void *vaddr, int ctx, uint64_t tte, int flags) 85{ return (0); } 86 87/*ARGSUSED */ 88uint64_t 89hv_mmu_fault_area_conf(void *raddr) 90{ return (0); } 91 92/*ARGSUSED*/ 93uint64_t 94hv_mmu_unmap_perm_addr(void *vaddr, int ctx, int flags) 95{ return (0); } 96 97/*ARGSUSED*/ 98uint64_t 99hv_set_ctx0(uint64_t ntsb_descriptor, uint64_t desc_ra) 100{ return (0); } 101 102/*ARGSUSED*/ 103uint64_t 104hv_set_ctxnon0(uint64_t ntsb_descriptor, uint64_t desc_ra) 105{ return (0); } 106 107#ifdef SET_MMU_STATS 108/*ARGSUSED*/ 109uint64_t 110hv_mmu_set_stat_area(uint64_t rstatarea, uint64_t size) 111{ return (0); } 112#endif /* SET_MMU_STATS */ 113 114/*ARGSUSED*/ 115uint64_t 116hv_cpu_qconf(int queue, uint64_t paddr, int size) 117{ return (0); } 118 119/*ARGSUSED*/ 120uint64_t 121hvio_intr_devino_to_sysino(uint64_t dev_hdl, uint32_t devino, uint64_t *sysino) 122{ return (0); } 123 124/*ARGSUSED*/ 125uint64_t 126hvio_intr_getvalid(uint64_t sysino, int *intr_valid_state) 127{ return (0); } 128 129/*ARGSUSED*/ 130uint64_t 131hvio_intr_setvalid(uint64_t sysino, int intr_valid_state) 132{ return (0); } 133 134/*ARGSUSED*/ 135uint64_t 136hvio_intr_getstate(uint64_t sysino, int *intr_state) 137{ return (0); } 138 139/*ARGSUSED*/ 140uint64_t 141hvio_intr_setstate(uint64_t sysino, int intr_state) 142{ return (0); } 143 144/*ARGSUSED*/ 145uint64_t 146hvio_intr_gettarget(uint64_t sysino, uint32_t *cpuid) 147{ return (0); } 148 149/*ARGSUSED*/ 150uint64_t 151hvio_intr_settarget(uint64_t sysino, uint32_t cpuid) 152{ return (0); } 153 154uint64_t 155hv_cpu_yield(void) 156{ return (0); } 157 158/*ARGSUSED*/ 159uint64_t 160hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state) 161{ return (0); } 162 163/*ARGSUSED*/ 164uint64_t 165hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *minsize) 166{ return (0); } 167 168/*ARGSUSED*/ 169uint64_t 170hv_mem_scrub(uint64_t real_addr, uint64_t length, uint64_t *scrubbed_len) 171{ return (0); } 172 173/*ARGSUSED*/ 174uint64_t 175hv_mem_sync(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 176{ return (0); } 177 178/*ARGSUSED*/ 179uint64_t 180hv_ttrace_buf_conf(uint64_t paddr, uint64_t size, uint64_t *size1) 181{ return (0); } 182 183/*ARGSUSED*/ 184uint64_t 185hv_ttrace_buf_info(uint64_t *paddr, uint64_t *size) 186{ return (0); } 187 188/*ARGSUSED*/ 189uint64_t 190hv_ttrace_enable(uint64_t enable, uint64_t *prev_enable) 191{ return (0); } 192 193/*ARGSUSED*/ 194uint64_t 195hv_ttrace_freeze(uint64_t freeze, uint64_t *prev_freeze) 196{ return (0); } 197 198/*ARGSUSED*/ 199uint64_t 200hv_mach_desc(uint64_t buffer_ra, uint64_t *buffer_sizep) 201{ return (0); } 202 203/*ARGSUSED*/ 204uint64_t 205hv_ra2pa(uint64_t ra) 206{ return (0); } 207 208/*ARGSUSED*/ 209uint64_t 210hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 211{ return (0); } 212 213/*ARGSUSED*/ 214uint64_t 215hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 216{ return (0); } 217 218/*ARGSUSED*/ 219uint64_t 220hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 221{ return (0); } 222 223/*ARGSUSED*/ 224uint64_t 225hv_ldc_tx_get_state(uint64_t channel, 226 uint64_t *headp, uint64_t *tailp, uint64_t *state) 227{ return (0); } 228 229/*ARGSUSED*/ 230uint64_t 231hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 232{ return (0); } 233 234/*ARGSUSED*/ 235uint64_t 236hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, uint64_t nentries) 237{ return (0); } 238 239/*ARGSUSED*/ 240uint64_t 241hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, uint64_t *nentries) 242{ return (0); } 243 244/*ARGSUSED*/ 245uint64_t 246hv_ldc_rx_get_state(uint64_t channel, 247 uint64_t *headp, uint64_t *tailp, uint64_t *state) 248{ return (0); } 249 250/*ARGSUSED*/ 251uint64_t 252hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 253{ return (0); } 254 255/*ARGSUSED*/ 256uint64_t 257hv_ldc_send_msg(uint64_t channel, uint64_t msg_ra) 258{ return (0); } 259 260/*ARGSUSED*/ 261uint64_t 262hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, uint64_t tbl_entries) 263{ return (0); } 264 265/*ARGSUSED*/ 266uint64_t 267hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 268 uint64_t raddr, uint64_t length, uint64_t *lengthp) 269{ return (0); } 270 271/*ARGSUSED*/ 272uint64_t 273hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, uint64_t *cookie) 274{ return (0); } 275 276/*ARGSUSED*/ 277uint64_t 278hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, uint64_t cookie) 279{ return (0); } 280 281/*ARGSUSED*/ 282uint64_t 283hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, int *intr_valid_state) 284{ return (0); } 285 286/*ARGSUSED*/ 287uint64_t 288hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, int intr_valid_state) 289{ return (0); } 290 291/*ARGSUSED*/ 292uint64_t 293hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, int *intr_state) 294{ return (0); } 295 296/*ARGSUSED*/ 297uint64_t 298hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, int intr_state) 299{ return (0); } 300 301/*ARGSUSED*/ 302uint64_t 303hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, uint32_t *cpuid) 304{ return (0); } 305 306/*ARGSUSED*/ 307uint64_t 308hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, uint32_t cpuid) 309{ return (0); } 310 311/*ARGSUSED*/ 312uint64_t 313hv_api_get_version(uint64_t api_group, uint64_t *majorp, uint64_t *minorp) 314{ return (0); } 315 316/*ARGSUSED*/ 317uint64_t 318hv_api_set_version(uint64_t api_group, uint64_t major, uint64_t minor, 319 uint64_t *supported_minor) 320{ return (0); } 321 322/*ARGSUSED*/ 323uint64_t 324hv_mem_iflush(uint64_t real_addr, uint64_t length, uint64_t *flushed_len) 325{ return (0); } 326 327/*ARGSUSED*/ 328uint64_t 329hv_mem_iflush_all() 330{ return (0); } 331 332/*ARGSUSED*/ 333uint64_t 334hv_tm_enable(uint64_t enable) 335{ return (0); } 336 337/*ARGSUSED*/ 338uint64_t 339hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 340{ return (0); } 341 342/*ARGSUSED*/ 343int64_t 344hv_cnwrite(uint64_t buf_ra, uint64_t count, uint64_t *retcount) 345{ return (0); } 346 347/*ARGSUSED*/ 348int64_t 349hv_cnread(uint64_t buf_ra, uint64_t count, int64_t *retcount) 350{ return (0); } 351 352/*ARGSUSED*/ 353uint64_t 354hv_soft_state_set(uint64_t state, uint64_t string) 355{ return (0); } 356 357/*ARGSUSED*/ 358uint64_t 359hv_soft_state_get(uint64_t string, uint64_t *state) 360{ return (0); } 361 362#else /* lint || __lint */ 363 364 /* 365 * int hv_mach_exit(uint64_t exit_code) 366 */ 367 ENTRY(hv_mach_exit) 368 mov HV_MACH_EXIT, %o5 369 ta FAST_TRAP 370 retl 371 nop 372 SET_SIZE(hv_mach_exit) 373 374 /* 375 * uint64_t hv_mach_sir(void) 376 */ 377 ENTRY(hv_mach_sir) 378 mov HV_MACH_SIR, %o5 379 ta FAST_TRAP 380 retl 381 nop 382 SET_SIZE(hv_mach_sir) 383 384 /* 385 * hv_cpu_start(uint64_t cpuid, uint64_t pc, ui64_t rtba, 386 * uint64_t arg) 387 */ 388 ENTRY(hv_cpu_start) 389 mov HV_CPU_START, %o5 390 ta FAST_TRAP 391 retl 392 nop 393 SET_SIZE(hv_cpu_start) 394 395 /* 396 * hv_cpu_stop(uint64_t cpuid) 397 */ 398 ENTRY(hv_cpu_stop) 399 mov HV_CPU_STOP, %o5 400 ta FAST_TRAP 401 retl 402 nop 403 SET_SIZE(hv_cpu_stop) 404 405 /* 406 * hv_cpu_set_rtba(uint64_t *rtba) 407 */ 408 ENTRY(hv_cpu_set_rtba) 409 mov %o0, %o2 410 ldx [%o2], %o0 411 mov HV_CPU_SET_RTBA, %o5 412 ta FAST_TRAP 413 stx %o1, [%o2] 414 retl 415 nop 416 SET_SIZE(hv_cpu_set_rtba) 417 418 /* 419 * int64_t hv_cnputchar(uint8_t ch) 420 */ 421 ENTRY(hv_cnputchar) 422 mov CONS_PUTCHAR, %o5 423 ta FAST_TRAP 424 retl 425 nop 426 SET_SIZE(hv_cnputchar) 427 428 /* 429 * int64_t hv_cngetchar(uint8_t *ch) 430 */ 431 ENTRY(hv_cngetchar) 432 mov %o0, %o2 433 mov CONS_GETCHAR, %o5 434 ta FAST_TRAP 435 brnz,a %o0, 1f ! failure, just return error 436 nop 437 438 cmp %o1, H_BREAK 439 be 1f 440 mov %o1, %o0 441 442 cmp %o1, H_HUP 443 be 1f 444 mov %o1, %o0 445 446 stb %o1, [%o2] ! success, save character and return 0 447 mov 0, %o0 4481: 449 retl 450 nop 451 SET_SIZE(hv_cngetchar) 452 453 ENTRY(hv_tod_get) 454 mov %o0, %o4 455 mov TOD_GET, %o5 456 ta FAST_TRAP 457 retl 458 stx %o1, [%o4] 459 SET_SIZE(hv_tod_get) 460 461 ENTRY(hv_tod_set) 462 mov TOD_SET, %o5 463 ta FAST_TRAP 464 retl 465 nop 466 SET_SIZE(hv_tod_set) 467 468 /* 469 * Map permanent address 470 * arg0 vaddr (%o0) 471 * arg1 context (%o1) 472 * arg2 tte (%o2) 473 * arg3 flags (%o3) 0x1=d 0x2=i 474 */ 475 ENTRY(hv_mmu_map_perm_addr) 476 mov MAP_PERM_ADDR, %o5 477 ta FAST_TRAP 478 retl 479 nop 480 SET_SIZE(hv_mmu_map_perm_addr) 481 482 /* 483 * hv_mmu_fault_area_conf(void *raddr) 484 */ 485 ENTRY(hv_mmu_fault_area_conf) 486 mov %o0, %o2 487 ldx [%o2], %o0 488 mov MMU_SET_INFOPTR, %o5 489 ta FAST_TRAP 490 stx %o1, [%o2] 491 retl 492 nop 493 SET_SIZE(hv_mmu_fault_area_conf) 494 495 /* 496 * Unmap permanent address 497 * arg0 vaddr (%o0) 498 * arg1 context (%o1) 499 * arg2 flags (%o2) 0x1=d 0x2=i 500 */ 501 ENTRY(hv_mmu_unmap_perm_addr) 502 mov UNMAP_PERM_ADDR, %o5 503 ta FAST_TRAP 504 retl 505 nop 506 SET_SIZE(hv_mmu_unmap_perm_addr) 507 508 /* 509 * Set TSB for context 0 510 * arg0 ntsb_descriptor (%o0) 511 * arg1 desc_ra (%o1) 512 */ 513 ENTRY(hv_set_ctx0) 514 mov MMU_TSB_CTX0, %o5 515 ta FAST_TRAP 516 retl 517 nop 518 SET_SIZE(hv_set_ctx0) 519 520 /* 521 * Set TSB for context non0 522 * arg0 ntsb_descriptor (%o0) 523 * arg1 desc_ra (%o1) 524 */ 525 ENTRY(hv_set_ctxnon0) 526 mov MMU_TSB_CTXNON0, %o5 527 ta FAST_TRAP 528 retl 529 nop 530 SET_SIZE(hv_set_ctxnon0) 531 532#ifdef SET_MMU_STATS 533 /* 534 * Returns old stat area on success 535 */ 536 ENTRY(hv_mmu_set_stat_area) 537 mov MMU_STAT_AREA, %o5 538 ta FAST_TRAP 539 retl 540 nop 541 SET_SIZE(hv_mmu_set_stat_area) 542#endif /* SET_MMU_STATS */ 543 544 /* 545 * CPU Q Configure 546 * arg0 queue (%o0) 547 * arg1 Base address RA (%o1) 548 * arg2 Size (%o2) 549 */ 550 ENTRY(hv_cpu_qconf) 551 mov HV_CPU_QCONF, %o5 552 ta FAST_TRAP 553 retl 554 nop 555 SET_SIZE(hv_cpu_qconf) 556 557 /* 558 * arg0 - devhandle 559 * arg1 - devino 560 * 561 * ret0 - status 562 * ret1 - sysino 563 */ 564 ENTRY(hvio_intr_devino_to_sysino) 565 mov HVIO_INTR_DEVINO2SYSINO, %o5 566 ta FAST_TRAP 567 brz,a %o0, 1f 568 stx %o1, [%o2] 5691: retl 570 nop 571 SET_SIZE(hvio_intr_devino_to_sysino) 572 573 /* 574 * arg0 - sysino 575 * 576 * ret0 - status 577 * ret1 - intr_valid_state 578 */ 579 ENTRY(hvio_intr_getvalid) 580 mov %o1, %o2 581 mov HVIO_INTR_GETVALID, %o5 582 ta FAST_TRAP 583 brz,a %o0, 1f 584 stuw %o1, [%o2] 5851: retl 586 nop 587 SET_SIZE(hvio_intr_getvalid) 588 589 /* 590 * arg0 - sysino 591 * arg1 - intr_valid_state 592 * 593 * ret0 - status 594 */ 595 ENTRY(hvio_intr_setvalid) 596 mov HVIO_INTR_SETVALID, %o5 597 ta FAST_TRAP 598 retl 599 nop 600 SET_SIZE(hvio_intr_setvalid) 601 602 /* 603 * arg0 - sysino 604 * 605 * ret0 - status 606 * ret1 - intr_state 607 */ 608 ENTRY(hvio_intr_getstate) 609 mov %o1, %o2 610 mov HVIO_INTR_GETSTATE, %o5 611 ta FAST_TRAP 612 brz,a %o0, 1f 613 stuw %o1, [%o2] 6141: retl 615 nop 616 SET_SIZE(hvio_intr_getstate) 617 618 /* 619 * arg0 - sysino 620 * arg1 - intr_state 621 * 622 * ret0 - status 623 */ 624 ENTRY(hvio_intr_setstate) 625 mov HVIO_INTR_SETSTATE, %o5 626 ta FAST_TRAP 627 retl 628 nop 629 SET_SIZE(hvio_intr_setstate) 630 631 /* 632 * arg0 - sysino 633 * 634 * ret0 - status 635 * ret1 - cpu_id 636 */ 637 ENTRY(hvio_intr_gettarget) 638 mov %o1, %o2 639 mov HVIO_INTR_GETTARGET, %o5 640 ta FAST_TRAP 641 brz,a %o0, 1f 642 stuw %o1, [%o2] 6431: retl 644 nop 645 SET_SIZE(hvio_intr_gettarget) 646 647 /* 648 * arg0 - sysino 649 * arg1 - cpu_id 650 * 651 * ret0 - status 652 */ 653 ENTRY(hvio_intr_settarget) 654 mov HVIO_INTR_SETTARGET, %o5 655 ta FAST_TRAP 656 retl 657 nop 658 SET_SIZE(hvio_intr_settarget) 659 660 /* 661 * hv_cpu_yield(void) 662 */ 663 ENTRY(hv_cpu_yield) 664 mov HV_CPU_YIELD, %o5 665 ta FAST_TRAP 666 retl 667 nop 668 SET_SIZE(hv_cpu_yield) 669 670 /* 671 * int hv_cpu_state(uint64_t cpuid, uint64_t *cpu_state); 672 */ 673 ENTRY(hv_cpu_state) 674 mov %o1, %o4 ! save datap 675 mov HV_CPU_STATE, %o5 676 ta FAST_TRAP 677 brz,a %o0, 1f 678 stx %o1, [%o4] 6791: 680 retl 681 nop 682 SET_SIZE(hv_cpu_state) 683 684 /* 685 * HV state dump zone Configure 686 * arg0 real adrs of dump buffer (%o0) 687 * arg1 size of dump buffer (%o1) 688 * ret0 status (%o0) 689 * ret1 size of buffer on success and min size on EINVAL (%o1) 690 * hv_dump_buf_update(uint64_t paddr, uint64_t size, uint64_t *ret_size) 691 */ 692 ENTRY(hv_dump_buf_update) 693 mov DUMP_BUF_UPDATE, %o5 694 ta FAST_TRAP 695 retl 696 stx %o1, [%o2] 697 SET_SIZE(hv_dump_buf_update) 698 699 /* 700 * arg0 - timeout value (%o0) 701 * 702 * ret0 - status (%o0) 703 * ret1 - time_remaining (%o1) 704 * hv_mach_set_watchdog(uint64_t timeout, uint64_t *time_remaining) 705 */ 706 ENTRY(hv_mach_set_watchdog) 707 mov %o1, %o2 708 mov MACH_SET_WATCHDOG, %o5 709 ta FAST_TRAP 710 retl 711 stx %o1, [%o2] 712 SET_SIZE(hv_mach_set_watchdog) 713 714 /* 715 * For memory scrub 716 * int hv_mem_scrub(uint64_t real_addr, uint64_t length, 717 * uint64_t *scrubbed_len); 718 * Retun %o0 -- status 719 * %o1 -- bytes scrubbed 720 */ 721 ENTRY(hv_mem_scrub) 722 mov %o2, %o4 723 mov HV_MEM_SCRUB, %o5 724 ta FAST_TRAP 725 retl 726 stx %o1, [%o4] 727 SET_SIZE(hv_mem_scrub) 728 729 /* 730 * Flush ecache 731 * int hv_mem_sync(uint64_t real_addr, uint64_t length, 732 * uint64_t *flushed_len); 733 * Retun %o0 -- status 734 * %o1 -- bytes flushed 735 */ 736 ENTRY(hv_mem_sync) 737 mov %o2, %o4 738 mov HV_MEM_SYNC, %o5 739 ta FAST_TRAP 740 retl 741 stx %o1, [%o4] 742 SET_SIZE(hv_mem_sync) 743 744 /* 745 * HV_MEM_IFLUSH 746 * arg0 memory real address 747 * arg1 flush length 748 * ret0 status 749 * ret1 flushed length 750 * 751 */ 752 ENTRY(hv_mem_iflush) 753 mov %o2, %o4 754 mov HV_MEM_IFLUSH, %o5 755 ta FAST_TRAP 756 retl 757 stx %o1, [%o4] 758 SET_SIZE(hv_mem_iflush) 759 760 /* 761 * HV_MEM_IFLUSH_ALL 762 * ret0 status 763 */ 764 ENTRY(hv_mem_iflush_all) 765 mov HV_MEM_IFLUSH_ALL, %o5 766 ta FAST_TRAP 767 retl 768 nop 769 SET_SIZE(hv_mem_iflush_all) 770 771 /* 772 * uint64_t hv_rk_tm_enable(uint64_t enable) 773 */ 774 ENTRY(hv_tm_enable) 775 mov HV_TM_ENABLE, %o5 776 ta FAST_TRAP 777 retl 778 nop 779 SET_SIZE(hv_tm_enable) 780 781 /* 782 * TTRACE_BUF_CONF Configure 783 * arg0 RA base of buffer (%o0) 784 * arg1 buf size in no. of entries (%o1) 785 * ret0 status (%o0) 786 * ret1 minimum size in no. of entries on failure, 787 * actual size in no. of entries on success (%o1) 788 */ 789 ENTRY(hv_ttrace_buf_conf) 790 mov TTRACE_BUF_CONF, %o5 791 ta FAST_TRAP 792 retl 793 stx %o1, [%o2] 794 SET_SIZE(hv_ttrace_buf_conf) 795 796 /* 797 * TTRACE_BUF_INFO 798 * ret0 status (%o0) 799 * ret1 RA base of buffer (%o1) 800 * ret2 size in no. of entries (%o2) 801 */ 802 ENTRY(hv_ttrace_buf_info) 803 mov %o0, %o3 804 mov %o1, %o4 805 mov TTRACE_BUF_INFO, %o5 806 ta FAST_TRAP 807 stx %o1, [%o3] 808 retl 809 stx %o2, [%o4] 810 SET_SIZE(hv_ttrace_buf_info) 811 812 /* 813 * TTRACE_ENABLE 814 * arg0 enable/ disable (%o0) 815 * ret0 status (%o0) 816 * ret1 previous enable state (%o1) 817 */ 818 ENTRY(hv_ttrace_enable) 819 mov %o1, %o2 820 mov TTRACE_ENABLE, %o5 821 ta FAST_TRAP 822 retl 823 stx %o1, [%o2] 824 SET_SIZE(hv_ttrace_enable) 825 826 /* 827 * TTRACE_FREEZE 828 * arg0 enable/ freeze (%o0) 829 * ret0 status (%o0) 830 * ret1 previous freeze state (%o1) 831 */ 832 ENTRY(hv_ttrace_freeze) 833 mov %o1, %o2 834 mov TTRACE_FREEZE, %o5 835 ta FAST_TRAP 836 retl 837 stx %o1, [%o2] 838 SET_SIZE(hv_ttrace_freeze) 839 840 /* 841 * MACH_DESC 842 * arg0 buffer real address 843 * arg1 pointer to uint64_t for size of buffer 844 * ret0 status 845 * ret1 return required size of buffer / returned data size 846 */ 847 ENTRY(hv_mach_desc) 848 mov %o1, %o4 ! save datap 849 ldx [%o1], %o1 850 mov HV_MACH_DESC, %o5 851 ta FAST_TRAP 852 retl 853 stx %o1, [%o4] 854 SET_SIZE(hv_mach_desc) 855 856 /* 857 * hv_ra2pa(uint64_t ra) 858 * 859 * MACH_DESC 860 * arg0 Real address to convert 861 * ret0 Returned physical address or -1 on error 862 */ 863 ENTRY(hv_ra2pa) 864 mov HV_RA2PA, %o5 865 ta FAST_TRAP 866 cmp %o0, 0 867 move %xcc, %o1, %o0 868 movne %xcc, -1, %o0 869 retl 870 nop 871 SET_SIZE(hv_ra2pa) 872 873 /* 874 * hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, uint64_t arg3) 875 * 876 * MACH_DESC 877 * arg0 OS function to call 878 * arg1 First arg to OS function 879 * arg2 Second arg to OS function 880 * arg3 Third arg to OS function 881 * ret0 Returned value from function 882 */ 883 884 ENTRY(hv_hpriv) 885 mov HV_HPRIV, %o5 886 ta FAST_TRAP 887 retl 888 nop 889 SET_SIZE(hv_hpriv) 890 891 /* 892 * hv_ldc_tx_qconf(uint64_t channel, uint64_t ra_base, 893 * uint64_t nentries); 894 */ 895 ENTRY(hv_ldc_tx_qconf) 896 mov LDC_TX_QCONF, %o5 897 ta FAST_TRAP 898 retl 899 nop 900 SET_SIZE(hv_ldc_tx_qconf) 901 902 903 /* 904 * hv_ldc_tx_qinfo(uint64_t channel, uint64_t *ra_base, 905 * uint64_t *nentries); 906 */ 907 ENTRY(hv_ldc_tx_qinfo) 908 mov %o1, %g1 909 mov %o2, %g2 910 mov LDC_TX_QINFO, %o5 911 ta FAST_TRAP 912 stx %o1, [%g1] 913 retl 914 stx %o2, [%g2] 915 SET_SIZE(hv_ldc_tx_qinfo) 916 917 918 /* 919 * hv_ldc_tx_get_state(uint64_t channel, 920 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 921 */ 922 ENTRY(hv_ldc_tx_get_state) 923 mov LDC_TX_GET_STATE, %o5 924 mov %o1, %g1 925 mov %o2, %g2 926 mov %o3, %g3 927 ta FAST_TRAP 928 stx %o1, [%g1] 929 stx %o2, [%g2] 930 retl 931 stx %o3, [%g3] 932 SET_SIZE(hv_ldc_tx_get_state) 933 934 935 /* 936 * hv_ldc_tx_set_qtail(uint64_t channel, uint64_t tail) 937 */ 938 ENTRY(hv_ldc_tx_set_qtail) 939 mov LDC_TX_SET_QTAIL, %o5 940 ta FAST_TRAP 941 retl 942 SET_SIZE(hv_ldc_tx_set_qtail) 943 944 945 /* 946 * hv_ldc_rx_qconf(uint64_t channel, uint64_t ra_base, 947 * uint64_t nentries); 948 */ 949 ENTRY(hv_ldc_rx_qconf) 950 mov LDC_RX_QCONF, %o5 951 ta FAST_TRAP 952 retl 953 nop 954 SET_SIZE(hv_ldc_rx_qconf) 955 956 957 /* 958 * hv_ldc_rx_qinfo(uint64_t channel, uint64_t *ra_base, 959 * uint64_t *nentries); 960 */ 961 ENTRY(hv_ldc_rx_qinfo) 962 mov %o1, %g1 963 mov %o2, %g2 964 mov LDC_RX_QINFO, %o5 965 ta FAST_TRAP 966 stx %o1, [%g1] 967 retl 968 stx %o2, [%g2] 969 SET_SIZE(hv_ldc_rx_qinfo) 970 971 972 /* 973 * hv_ldc_rx_get_state(uint64_t channel, 974 * uint64_t *headp, uint64_t *tailp, uint64_t *state); 975 */ 976 ENTRY(hv_ldc_rx_get_state) 977 mov LDC_RX_GET_STATE, %o5 978 mov %o1, %g1 979 mov %o2, %g2 980 mov %o3, %g3 981 ta FAST_TRAP 982 stx %o1, [%g1] 983 stx %o2, [%g2] 984 retl 985 stx %o3, [%g3] 986 SET_SIZE(hv_ldc_rx_get_state) 987 988 989 /* 990 * hv_ldc_rx_set_qhead(uint64_t channel, uint64_t head) 991 */ 992 ENTRY(hv_ldc_rx_set_qhead) 993 mov LDC_RX_SET_QHEAD, %o5 994 ta FAST_TRAP 995 retl 996 SET_SIZE(hv_ldc_rx_set_qhead) 997 998 /* 999 * hv_ldc_set_map_table(uint64_t channel, uint64_t tbl_ra, 1000 * uint64_t tbl_entries) 1001 */ 1002 ENTRY(hv_ldc_set_map_table) 1003 mov LDC_SET_MAP_TABLE, %o5 1004 ta FAST_TRAP 1005 retl 1006 nop 1007 SET_SIZE(hv_ldc_set_map_table) 1008 1009 1010 /* 1011 * hv_ldc_get_map_table(uint64_t channel, uint64_t *tbl_ra, 1012 * uint64_t *tbl_entries) 1013 */ 1014 ENTRY(hv_ldc_get_map_table) 1015 mov %o1, %g1 1016 mov %o2, %g2 1017 mov LDC_GET_MAP_TABLE, %o5 1018 ta FAST_TRAP 1019 stx %o1, [%g1] 1020 retl 1021 stx %o2, [%g2] 1022 SET_SIZE(hv_ldc_get_map_table) 1023 1024 1025 /* 1026 * hv_ldc_copy(uint64_t channel, uint64_t request, uint64_t cookie, 1027 * uint64_t raddr, uint64_t length, uint64_t *lengthp); 1028 */ 1029 ENTRY(hv_ldc_copy) 1030 mov %o5, %g1 1031 mov LDC_COPY, %o5 1032 ta FAST_TRAP 1033 retl 1034 stx %o1, [%g1] 1035 SET_SIZE(hv_ldc_copy) 1036 1037 1038 /* 1039 * hv_ldc_mapin(uint64_t channel, uint64_t cookie, uint64_t *raddr, 1040 * uint64_t *perm) 1041 */ 1042 ENTRY(hv_ldc_mapin) 1043 mov %o2, %g1 1044 mov %o3, %g2 1045 mov LDC_MAPIN, %o5 1046 ta FAST_TRAP 1047 stx %o1, [%g1] 1048 retl 1049 stx %o2, [%g2] 1050 SET_SIZE(hv_ldc_mapin) 1051 1052 1053 /* 1054 * hv_ldc_unmap(uint64_t raddr) 1055 */ 1056 ENTRY(hv_ldc_unmap) 1057 mov LDC_UNMAP, %o5 1058 ta FAST_TRAP 1059 retl 1060 nop 1061 SET_SIZE(hv_ldc_unmap) 1062 1063 1064 /* 1065 * hv_ldc_revoke(uint64_t channel, uint64_t cookie, 1066 * uint64_t revoke_cookie 1067 */ 1068 ENTRY(hv_ldc_revoke) 1069 mov LDC_REVOKE, %o5 1070 ta FAST_TRAP 1071 retl 1072 nop 1073 SET_SIZE(hv_ldc_revoke) 1074 1075 1076 /* 1077 * hvldc_intr_getcookie(uint64_t dev_hdl, uint32_t devino, 1078 * uint64_t *cookie); 1079 */ 1080 ENTRY(hvldc_intr_getcookie) 1081 mov %o2, %g1 1082 mov VINTR_GET_COOKIE, %o5 1083 ta FAST_TRAP 1084 retl 1085 stx %o1, [%g1] 1086 SET_SIZE(hvldc_intr_getcookie) 1087 1088 /* 1089 * hvldc_intr_setcookie(uint64_t dev_hdl, uint32_t devino, 1090 * uint64_t cookie); 1091 */ 1092 ENTRY(hvldc_intr_setcookie) 1093 mov VINTR_SET_COOKIE, %o5 1094 ta FAST_TRAP 1095 retl 1096 nop 1097 SET_SIZE(hvldc_intr_setcookie) 1098 1099 1100 /* 1101 * hvldc_intr_getvalid(uint64_t dev_hdl, uint32_t devino, 1102 * int *intr_valid_state); 1103 */ 1104 ENTRY(hvldc_intr_getvalid) 1105 mov %o2, %g1 1106 mov VINTR_GET_VALID, %o5 1107 ta FAST_TRAP 1108 retl 1109 stuw %o1, [%g1] 1110 SET_SIZE(hvldc_intr_getvalid) 1111 1112 /* 1113 * hvldc_intr_setvalid(uint64_t dev_hdl, uint32_t devino, 1114 * int intr_valid_state); 1115 */ 1116 ENTRY(hvldc_intr_setvalid) 1117 mov VINTR_SET_VALID, %o5 1118 ta FAST_TRAP 1119 retl 1120 nop 1121 SET_SIZE(hvldc_intr_setvalid) 1122 1123 /* 1124 * hvldc_intr_getstate(uint64_t dev_hdl, uint32_t devino, 1125 * int *intr_state); 1126 */ 1127 ENTRY(hvldc_intr_getstate) 1128 mov %o2, %g1 1129 mov VINTR_GET_STATE, %o5 1130 ta FAST_TRAP 1131 retl 1132 stuw %o1, [%g1] 1133 SET_SIZE(hvldc_intr_getstate) 1134 1135 /* 1136 * hvldc_intr_setstate(uint64_t dev_hdl, uint32_t devino, 1137 * int intr_state); 1138 */ 1139 ENTRY(hvldc_intr_setstate) 1140 mov VINTR_SET_STATE, %o5 1141 ta FAST_TRAP 1142 retl 1143 nop 1144 SET_SIZE(hvldc_intr_setstate) 1145 1146 /* 1147 * hvldc_intr_gettarget(uint64_t dev_hdl, uint32_t devino, 1148 * uint32_t *cpuid); 1149 */ 1150 ENTRY(hvldc_intr_gettarget) 1151 mov %o2, %g1 1152 mov VINTR_GET_TARGET, %o5 1153 ta FAST_TRAP 1154 retl 1155 stuw %o1, [%g1] 1156 SET_SIZE(hvldc_intr_gettarget) 1157 1158 /* 1159 * hvldc_intr_settarget(uint64_t dev_hdl, uint32_t devino, 1160 * uint32_t cpuid); 1161 */ 1162 ENTRY(hvldc_intr_settarget) 1163 mov VINTR_SET_TARGET, %o5 1164 ta FAST_TRAP 1165 retl 1166 nop 1167 SET_SIZE(hvldc_intr_settarget) 1168 1169 /* 1170 * hv_api_get_version(uint64_t api_group, uint64_t *majorp, 1171 * uint64_t *minorp) 1172 * 1173 * API_GET_VERSION 1174 * arg0 API group 1175 * ret0 status 1176 * ret1 major number 1177 * ret2 minor number 1178 */ 1179 ENTRY(hv_api_get_version) 1180 mov %o1, %o3 1181 mov %o2, %o4 1182 mov API_GET_VERSION, %o5 1183 ta CORE_TRAP 1184 stx %o1, [%o3] 1185 retl 1186 stx %o2, [%o4] 1187 SET_SIZE(hv_api_get_version) 1188 1189 /* 1190 * hv_api_set_version(uint64_t api_group, uint64_t major, 1191 * uint64_t minor, uint64_t *supported_minor) 1192 * 1193 * API_SET_VERSION 1194 * arg0 API group 1195 * arg1 major number 1196 * arg2 requested minor number 1197 * ret0 status 1198 * ret1 actual minor number 1199 */ 1200 ENTRY(hv_api_set_version) 1201 mov %o3, %o4 1202 mov API_SET_VERSION, %o5 1203 ta CORE_TRAP 1204 retl 1205 stx %o1, [%o4] 1206 SET_SIZE(hv_api_set_version) 1207 1208 /* 1209 * %o0 - buffer real address 1210 * %o1 - buffer size 1211 * %o2 - &characters written 1212 * returns 1213 * status 1214 */ 1215 ENTRY(hv_cnwrite) 1216 mov CONS_WRITE, %o5 1217 ta FAST_TRAP 1218 retl 1219 stx %o1, [%o2] 1220 SET_SIZE(hv_cnwrite) 1221 1222 /* 1223 * %o0 character buffer ra 1224 * %o1 buffer size 1225 * %o2 pointer to returned size 1226 * return values: 1227 * 0 success 1228 * hv_errno failure 1229 */ 1230 ENTRY(hv_cnread) 1231 mov CONS_READ, %o5 1232 ta FAST_TRAP 1233 brnz,a %o0, 1f ! failure, just return error 1234 nop 1235 1236 cmp %o1, H_BREAK 1237 be 1f 1238 mov %o1, %o0 1239 1240 cmp %o1, H_HUP 1241 be 1f 1242 mov %o1, %o0 1243 1244 stx %o1, [%o2] ! success, save count and return 0 1245 mov 0, %o0 12461: 1247 retl 1248 nop 1249 SET_SIZE(hv_cnread) 1250 1251 /* 1252 * SOFT_STATE_SET 1253 * arg0 state (%o0) 1254 * arg1 string (%o1) 1255 * ret0 status (%o0) 1256 */ 1257 ENTRY(hv_soft_state_set) 1258 mov SOFT_STATE_SET, %o5 1259 ta FAST_TRAP 1260 retl 1261 nop 1262 SET_SIZE(hv_soft_state_set) 1263 1264 /* 1265 * SOFT_STATE_GET 1266 * arg0 string buffer (%o0) 1267 * ret0 status (%o0) 1268 * ret1 current state (%o1) 1269 */ 1270 ENTRY(hv_soft_state_get) 1271 mov %o1, %o2 1272 mov SOFT_STATE_GET, %o5 1273 ta FAST_TRAP 1274 retl 1275 stx %o1, [%o2] 1276 SET_SIZE(hv_soft_state_get) 1277 1278#endif /* lint || __lint */ 1279