1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB4V_H 27 #define _SYS_PX_LIB4V_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * Fasttrap numbers for VPCI hypervisor functions. 35 */ 36 37 #define HVIO_IOMMU_MAP 0xb0 38 #define HVIO_IOMMU_DEMAP 0xb1 39 #define HVIO_IOMMU_GETMAP 0xb2 40 #define HVIO_IOMMU_GETBYPASS 0xb3 41 42 #define HVIO_CONFIG_GET 0xb4 43 #define HVIO_CONFIG_PUT 0xb5 44 45 #define HVIO_PEEK 0xb6 46 #define HVIO_POKE 0xb7 47 48 #define HVIO_DMA_SYNC 0xb8 49 50 #define HVIO_MSIQ_CONF 0xc0 51 #define HVIO_MSIQ_INFO 0xc1 52 #define HVIO_MSIQ_GETVALID 0xc2 53 #define HVIO_MSIQ_SETVALID 0xc3 54 #define HVIO_MSIQ_GETSTATE 0xc4 55 #define HVIO_MSIQ_SETSTATE 0xc5 56 #define HVIO_MSIQ_GETHEAD 0xc6 57 #define HVIO_MSIQ_SETHEAD 0xc7 58 #define HVIO_MSIQ_GETTAIL 0xc8 59 60 #define HVIO_MSI_GETVALID 0xc9 61 #define HVIO_MSI_SETVALID 0xca 62 #define HVIO_MSI_GETMSIQ 0xcb 63 #define HVIO_MSI_SETMSIQ 0xcc 64 #define HVIO_MSI_GETSTATE 0xcd 65 #define HVIO_MSI_SETSTATE 0xce 66 67 #define HVIO_MSG_GETMSIQ 0xd0 68 #define HVIO_MSG_SETMSIQ 0xd1 69 #define HVIO_MSG_GETVALID 0xd2 70 #define HVIO_MSG_SETVALID 0xd3 71 72 /* 73 * Fasttrap numbers for SDIO hypervisor functions. 74 */ 75 #define PCI_IOV_ROOT_CONFIGURED 0xf8 76 77 /* 78 * Fasttrap numbers for SDIO ERR hypervisor functions. 79 */ 80 #define PCI_ERROR_SEND 0xff 81 82 #ifndef _ASM 83 84 /* 85 * The device handle uniquely identifies a SUN4V device. 86 * It consists of the lower 28-bits of the hi-cell of the 87 * first entry of the SUN4V device's "reg" property as 88 * defined by the SUN4V Bus Binding to Open Firmware. 89 */ 90 #define DEVHDLE_MASK 0xFFFFFFF 91 92 #define PX_ADDR2PFN(addr, index, flags, i) \ 93 ((flags & MMU_MAP_PFN) ? \ 94 PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \ 95 hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i)))) 96 97 /* 98 * Hypercall service versioning 99 */ 100 #define PX_HSVC_MAJOR_VER_1 0x1ull 101 #define PX_HSVC_MINOR_VER_0 0x0ull 102 #define PX_HSVC_MINOR_VER_1 0x1ull 103 #define PX_HSVC_MINOR_VER_2 0x2ull 104 105 /* 106 * VPCI API versioning. 107 * Currently PX nexus driver supports VPCI API version 1.2 108 */ 109 #define PX_VPCI_MAJOR_VER PX_HSVC_MAJOR_VER_1 110 #define PX_VPCI_MINOR_VER PX_HSVC_MINOR_VER_2 111 112 /* 113 * SDIO API versioning. 114 * Currently PX nexus driver supports SDIO API version 1.0 115 */ 116 #define PX_SDIO_MAJOR_VER PX_HSVC_MAJOR_VER_1 117 #define PX_SDIO_MINOR_VER PX_HSVC_MINOR_VER_0 118 119 /* 120 * SDIO ERR API versioning. 121 * Currently PX nexus driver supports SDIO ERR API version 1.0 122 */ 123 #define PX_SDIO_ERR_MAJOR_VER PX_HSVC_MAJOR_VER_1 124 #define PX_SDIO_ERR_MINOR_VER PX_HSVC_MINOR_VER_0 125 126 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, 127 pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p, 128 pages_t *pages_mapped); 129 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, 130 pages_t pages, pages_t *pages_demapped); 131 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, 132 io_attributes_t *attr_p, r_addr_t *r_addr_p); 133 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 134 io_attributes_t attr, io_addr_t *io_addr_p); 135 extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, 136 size_t num_bytes, io_sync_direction_t io_sync_direction, 137 size_t *bytes_synched); 138 139 /* 140 * MSIQ Functions: 141 */ 142 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, 143 r_addr_t ra, uint_t msiq_rec_cnt); 144 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, 145 r_addr_t *ra_p, uint_t *msiq_rec_cnt_p); 146 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 147 pci_msiq_valid_state_t *msiq_valid_state); 148 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 149 pci_msiq_valid_state_t msiq_valid_state); 150 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 151 pci_msiq_state_t *msiq_state); 152 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 153 pci_msiq_state_t msiq_state); 154 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 155 msiqhead_t *msiq_head); 156 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 157 msiqhead_t msiq_head); 158 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 159 msiqtail_t *msiq_tail); 160 161 /* 162 * MSI Functions: 163 */ 164 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 165 msiqid_t *msiq_id); 166 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 167 msiqid_t msiq_id, msi_type_t msitype); 168 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 169 pci_msi_valid_state_t *msi_valid_state); 170 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 171 pci_msi_valid_state_t msi_valid_state); 172 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 173 pci_msi_state_t *msi_state); 174 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 175 pci_msi_state_t msi_state); 176 177 178 extern uint64_t pci_error_send(devhandle_t dev_hdl, devino_t devino, 179 pci_device_t bdf); 180 181 /* 182 * MSG Functions: 183 */ 184 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 185 msiqid_t *msiq_id); 186 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 187 msiqid_t msiq_id); 188 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 189 pcie_msg_valid_state_t *msg_valid_state); 190 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 191 pcie_msg_valid_state_t msg_valid_state); 192 193 typedef struct px_config_acc_pvt { 194 dev_info_t *dip; 195 uint32_t raddr; 196 uint32_t vaddr; 197 } px_config_acc_pvt_t; 198 199 /* 200 * Peek/poke functionality: 201 */ 202 203 extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, 204 uint32_t *status, uint64_t *data_p); 205 extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size, 206 uint64_t data, pci_device_t bdf, uint32_t *wrt_stat); 207 extern uint64_t hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf, 208 int32_t *mps_cap); 209 extern uint64_t hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf, 210 int32_t mps); 211 212 /* 213 * Priviledged physical access: 214 */ 215 extern uint64_t hv_ra2pa(uint64_t ra); 216 extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2, 217 uint64_t arg3); 218 extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr); 219 220 /* 221 * PCI IOV SDIO Funcitons: 222 */ 223 extern uint64_t pci_iov_root_configured(devhandle_t dev_hdl); 224 225 #endif /* _ASM */ 226 227 #ifdef __cplusplus 228 } 229 #endif 230 231 #endif /* _SYS_PX_LIB4V_H */ 232