xref: /titanic_41/usr/src/uts/sun4v/io/px/px_lib4v.h (revision 7801e5e8b5bc4af34929c54a02cfb78398da08dd)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_PX_LIB4V_H
27 #define	_SYS_PX_LIB4V_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 /*
34  * Fasttrap numbers for VPCI hypervisor functions.
35  */
36 
37 #define	HVIO_IOMMU_MAP		0xb0
38 #define	HVIO_IOMMU_DEMAP	0xb1
39 #define	HVIO_IOMMU_GETMAP	0xb2
40 #define	HVIO_IOMMU_GETBYPASS	0xb3
41 
42 #define	HVIO_CONFIG_GET		0xb4
43 #define	HVIO_CONFIG_PUT		0xb5
44 
45 #define	HVIO_PEEK		0xb6
46 #define	HVIO_POKE		0xb7
47 
48 #define	HVIO_DMA_SYNC		0xb8
49 
50 #define	HVIO_MSIQ_CONF		0xc0
51 #define	HVIO_MSIQ_INFO		0xc1
52 #define	HVIO_MSIQ_GETVALID	0xc2
53 #define	HVIO_MSIQ_SETVALID	0xc3
54 #define	HVIO_MSIQ_GETSTATE	0xc4
55 #define	HVIO_MSIQ_SETSTATE	0xc5
56 #define	HVIO_MSIQ_GETHEAD	0xc6
57 #define	HVIO_MSIQ_SETHEAD	0xc7
58 #define	HVIO_MSIQ_GETTAIL	0xc8
59 
60 #define	HVIO_MSI_GETVALID	0xc9
61 #define	HVIO_MSI_SETVALID	0xca
62 #define	HVIO_MSI_GETMSIQ	0xcb
63 #define	HVIO_MSI_SETMSIQ	0xcc
64 #define	HVIO_MSI_GETSTATE	0xcd
65 #define	HVIO_MSI_SETSTATE	0xce
66 
67 #define	HVIO_MSG_GETMSIQ	0xd0
68 #define	HVIO_MSG_SETMSIQ	0xd1
69 #define	HVIO_MSG_GETVALID	0xd2
70 #define	HVIO_MSG_SETVALID	0xd3
71 
72 #ifndef _ASM
73 
74 /*
75  * The device handle uniquely identifies a SUN4V device.
76  * It consists of the lower 28-bits of the hi-cell of the
77  * first entry of the SUN4V device's "reg" property as
78  * defined by the SUN4V Bus Binding to Open Firmware.
79  */
80 #define	DEVHDLE_MASK	0xFFFFFFF
81 
82 #define	PX_ADDR2PFN(addr, index, flags, i) \
83 	((flags & MMU_MAP_PFN) ? \
84 	PX_GET_MP_PFN((ddi_dma_impl_t *)(addr), (index + i)) : \
85 	hat_getpfnum(kas.a_hat, ((caddr_t)addr + (MMU_PAGE_SIZE * i))))
86 
87 /*
88  * VPCI API versioning.
89  *
90  * Currently PX nexus driver supports VPCI API version 1.1
91  */
92 #define	PX_VPCI_MAJOR_VER_1	0x1ull
93 #define	PX_VPCI_MAJOR_VER	PX_VPCI_MAJOR_VER_1
94 
95 #define	PX_VPCI_MINOR_VER_0	0x0ull
96 #define	PX_VPCI_MINOR_VER_1	0x1ull
97 #define	PX_VPCI_MINOR_VER	PX_VPCI_MINOR_VER_1
98 
99 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid,
100     pages_t pages, io_attributes_t attr, io_page_list_t *io_page_list_p,
101     pages_t *pages_mapped);
102 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid,
103     pages_t pages, pages_t *pages_demapped);
104 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid,
105     io_attributes_t *attr_p, r_addr_t *r_addr_p);
106 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra,
107     io_attributes_t attr, io_addr_t *io_addr_p);
108 extern uint64_t hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra,
109     size_t num_bytes, io_sync_direction_t io_sync_direction,
110     size_t *bytes_synched);
111 
112 /*
113  * MSIQ Functions:
114  */
115 extern uint64_t hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id,
116     r_addr_t ra, uint_t msiq_rec_cnt);
117 extern uint64_t hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id,
118     r_addr_t *ra_p, uint_t *msiq_rec_cnt_p);
119 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
120     pci_msiq_valid_state_t *msiq_valid_state);
121 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id,
122     pci_msiq_valid_state_t msiq_valid_state);
123 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id,
124     pci_msiq_state_t *msiq_state);
125 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id,
126     pci_msiq_state_t msiq_state);
127 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id,
128     msiqhead_t *msiq_head);
129 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id,
130     msiqhead_t msiq_head);
131 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id,
132     msiqtail_t *msiq_tail);
133 
134 /*
135  * MSI Functions:
136  */
137 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num,
138     msiqid_t *msiq_id);
139 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num,
140     msiqid_t msiq_id, msi_type_t msitype);
141 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num,
142     pci_msi_valid_state_t *msi_valid_state);
143 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num,
144     pci_msi_valid_state_t msi_valid_state);
145 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num,
146     pci_msi_state_t *msi_state);
147 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num,
148     pci_msi_state_t msi_state);
149 
150 /*
151  * MSG Functions:
152  */
153 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
154     msiqid_t *msiq_id);
155 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
156     msiqid_t msiq_id);
157 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
158     pcie_msg_valid_state_t *msg_valid_state);
159 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type,
160     pcie_msg_valid_state_t msg_valid_state);
161 
162 typedef struct px_config_acc_pvt {
163 	dev_info_t *dip;
164 	uint32_t raddr;
165 	uint32_t vaddr;
166 } px_config_acc_pvt_t;
167 
168 /*
169  * Peek/poke functionality:
170  */
171 
172 extern uint64_t hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size,
173     uint32_t *status, uint64_t *data_p);
174 extern uint64_t hvio_poke(devhandle_t dev_hdl, r_addr_t ra, size_t size,
175     uint64_t data, pci_device_t bdf, uint32_t *wrt_stat);
176 extern uint64_t hvio_get_rp_mps_cap(devhandle_t dev_hdl, pci_device_t bdf,
177     int32_t *mps_cap);
178 extern uint64_t hvio_set_rp_mps(devhandle_t dev_hdl, pci_device_t bdf,
179     int32_t mps);
180 
181 /*
182  * Priviledged physical access:
183  */
184 extern uint64_t hv_ra2pa(uint64_t ra);
185 extern uint64_t hv_hpriv(void *func, uint64_t arg1, uint64_t arg2,
186     uint64_t arg3);
187 extern int px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr);
188 
189 #endif /* _ASM */
190 
191 #ifdef	__cplusplus
192 }
193 #endif
194 
195 #endif	/* _SYS_PX_LIB4V_H */
196