1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69 70 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "reg", (uchar_t **)&rp, ®len); 72 if (ret != DDI_PROP_SUCCESS) { 73 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 74 return (DDI_FAILURE); 75 } 76 77 /* 78 * Initilize device handle. The device handle uniquely identifies 79 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 80 * of the first entry of the SUN4V device's "reg" property as 81 * defined by the SUN4V Bus Binding to Open Firmware. 82 */ 83 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 84 ddi_prop_free(rp); 85 86 /* 87 * hotplug implementation requires this property to be associated with 88 * any indirect PCI config access services 89 */ 90 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 91 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 92 PCI_BUS_CONF_MAP_PROP, 1); 93 94 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 95 96 /* 97 * Negotiate the API version for VPCI hypervisor services. 98 */ 99 if (px_vpci_users++) 100 return (DDI_SUCCESS); 101 102 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 103 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 104 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 105 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 106 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 107 108 return (DDI_FAILURE); 109 } 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 112 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 113 114 return (DDI_SUCCESS); 115 } 116 117 /*ARGSUSED*/ 118 int 119 px_lib_dev_fini(dev_info_t *dip) 120 { 121 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 122 123 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 124 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 125 PCI_BUS_CONF_MAP_PROP); 126 127 if (--px_vpci_users == 0) 128 (void) hsvc_unregister(&px_hsvc); 129 130 return (DDI_SUCCESS); 131 } 132 133 /*ARGSUSED*/ 134 int 135 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 136 sysino_t *sysino) 137 { 138 uint64_t ret; 139 140 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 141 "devino 0x%x\n", dip, devino); 142 143 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 144 devino, sysino)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, 146 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 147 return (DDI_FAILURE); 148 } 149 150 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 151 *sysino); 152 153 return (DDI_SUCCESS); 154 } 155 156 /*ARGSUSED*/ 157 int 158 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 159 intr_valid_state_t *intr_valid_state) 160 { 161 uint64_t ret; 162 163 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 164 dip, sysino); 165 166 if ((ret = hvio_intr_getvalid(sysino, 167 (int *)intr_valid_state)) != H_EOK) { 168 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 169 ret); 170 return (DDI_FAILURE); 171 } 172 173 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 174 *intr_valid_state); 175 176 return (DDI_SUCCESS); 177 } 178 179 /*ARGSUSED*/ 180 int 181 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 182 intr_valid_state_t intr_valid_state) 183 { 184 uint64_t ret; 185 186 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 187 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 188 189 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 190 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 191 ret); 192 return (DDI_FAILURE); 193 } 194 195 return (DDI_SUCCESS); 196 } 197 198 /*ARGSUSED*/ 199 int 200 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 201 intr_state_t *intr_state) 202 { 203 uint64_t ret; 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 206 dip, sysino); 207 208 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 209 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 210 ret); 211 return (DDI_FAILURE); 212 } 213 214 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 215 *intr_state); 216 217 return (DDI_SUCCESS); 218 } 219 220 /*ARGSUSED*/ 221 int 222 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 223 intr_state_t intr_state) 224 { 225 uint64_t ret; 226 227 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 228 "intr_state 0x%x\n", dip, sysino, intr_state); 229 230 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 231 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 232 ret); 233 return (DDI_FAILURE); 234 } 235 236 return (DDI_SUCCESS); 237 } 238 239 /*ARGSUSED*/ 240 int 241 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 242 { 243 uint64_t ret; 244 245 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 246 dip, sysino); 247 248 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 249 DBG(DBG_LIB_INT, dip, 250 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 251 return (DDI_FAILURE); 252 } 253 254 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 255 256 return (DDI_SUCCESS); 257 } 258 259 /*ARGSUSED*/ 260 int 261 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 262 { 263 uint64_t ret; 264 265 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 266 "cpuid 0x%x\n", dip, sysino, cpuid); 267 268 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 269 DBG(DBG_LIB_INT, dip, 270 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 271 return (DDI_FAILURE); 272 } 273 274 return (DDI_SUCCESS); 275 } 276 277 /*ARGSUSED*/ 278 int 279 px_lib_intr_reset(dev_info_t *dip) 280 { 281 px_t *px_p = DIP_TO_STATE(dip); 282 px_ib_t *ib_p = px_p->px_ib_p; 283 px_ib_ino_info_t *ino_p; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 286 287 mutex_enter(&ib_p->ib_ino_lst_mutex); 288 289 /* Reset all Interrupts */ 290 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) { 291 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 292 INTR_IDLE_STATE) != DDI_SUCCESS) 293 return (BF_FATAL); 294 } 295 296 mutex_exit(&ib_p->ib_ino_lst_mutex); 297 298 return (BF_NONE); 299 } 300 301 /*ARGSUSED*/ 302 int 303 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 304 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 305 { 306 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 307 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 308 io_page_list_t *pfns, *pfn_p; 309 pages_t ttes_mapped = 0; 310 int i, err = DDI_SUCCESS; 311 312 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 313 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 314 dip, tsbid, pages, attr, addr, pfn_index, flags); 315 316 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 317 KM_NOSLEEP)) == NULL) { 318 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 319 return (DDI_FAILURE); 320 } 321 322 for (i = 0; i < pages; i++) 323 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 324 325 while ((ttes_mapped = pfn_p - pfns) < pages) { 326 uintptr_t ra = va_to_pa(pfn_p); 327 pages_t ttes2map; 328 uint64_t ret; 329 330 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 331 ra = MMU_PTOB(MMU_BTOP(ra)); 332 333 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 334 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 335 336 ttes_mapped = 0; 337 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 338 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 339 ttes2map, attr, (io_page_list_t *)(ra | 340 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 341 &ttes_mapped)) != H_EOK) { 342 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 343 "ret 0x%lx\n", ret); 344 345 ttes_mapped = pfn_p - pfns; 346 err = DDI_FAILURE; 347 goto cleanup; 348 } 349 350 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 351 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 352 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 353 tsb_index + (pfn_p - pfns), ttes2map, attr, 354 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 355 ttes_mapped); 356 } 357 } 358 359 cleanup: 360 if ((err == DDI_FAILURE) && ttes_mapped) 361 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 362 363 kmem_free(pfns, pages * sizeof (io_page_list_t)); 364 return (err); 365 } 366 367 /*ARGSUSED*/ 368 int 369 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 370 { 371 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 372 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 373 pages_t ttes2demap, ttes_demapped = 0; 374 uint64_t ret; 375 376 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 377 "pages 0x%x\n", dip, tsbid, pages); 378 379 for (ttes2demap = pages; ttes2demap; 380 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 381 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 382 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 383 &ttes_demapped)) != H_EOK) { 384 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 385 "ret 0x%lx\n", ret); 386 387 return (DDI_FAILURE); 388 } 389 390 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 391 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 392 tsb_num, tsb_index, ttes2demap, ttes_demapped); 393 } 394 395 return (DDI_SUCCESS); 396 } 397 398 /*ARGSUSED*/ 399 int 400 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 401 r_addr_t *r_addr_p) 402 { 403 uint64_t ret; 404 405 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 406 dip, tsbid); 407 408 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 409 attr_p, r_addr_p)) != H_EOK) { 410 DBG(DBG_LIB_DMA, dip, 411 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 412 413 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 414 } 415 416 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 417 *attr_p, *r_addr_p); 418 419 return (DDI_SUCCESS); 420 } 421 422 423 /* 424 * Checks dma attributes against system bypass ranges 425 * A sun4v device must be capable of generating the entire 64-bit 426 * address in order to perform bypass DMA. 427 */ 428 /*ARGSUSED*/ 429 int 430 px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attr_p, uint64_t *lo_p, uint64_t *hi_p) 431 { 432 if ((attr_p->dma_attr_addr_lo != 0ull) || 433 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 434 435 return (DDI_DMA_BADATTR); 436 } 437 438 *lo_p = 0ull; 439 *hi_p = UINT64_MAX; 440 441 return (DDI_SUCCESS); 442 } 443 444 445 /*ARGSUSED*/ 446 int 447 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 448 io_addr_t *io_addr_p) 449 { 450 uint64_t ret; 451 452 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 453 "attr 0x%x\n", dip, ra, attr); 454 455 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 456 attr, io_addr_p)) != H_EOK) { 457 DBG(DBG_LIB_DMA, dip, 458 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 459 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 460 } 461 462 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 463 *io_addr_p); 464 465 return (DDI_SUCCESS); 466 } 467 468 /*ARGSUSED*/ 469 int 470 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 471 off_t off, size_t len, uint_t cache_flags) 472 { 473 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 474 uint64_t sync_dir; 475 px_dvma_addr_t dvma_addr, pg_off; 476 size_t num_sync; 477 uint64_t status = H_EOK; 478 479 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 480 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 481 dip, rdip, handle, off, len, cache_flags); 482 483 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 484 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 485 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 486 return (DDI_FAILURE); 487 } 488 489 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 490 return (DDI_SUCCESS); 491 492 if (!len) 493 len = mp->dmai_size; 494 495 pg_off = mp->dmai_offset; /* start min */ 496 dvma_addr = MAX(off, pg_off); /* lo */ 497 pg_off += mp->dmai_size; /* end max */ 498 pg_off = MIN(off + len, pg_off); /* hi */ 499 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 500 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 501 ddi_driver_name(rdip), ddi_get_instance(rdip), 502 off, len, mp->dmai_offset, 503 mp->dmai_offset + mp->dmai_size); 504 return (DDI_FAILURE); 505 } 506 507 len = pg_off - dvma_addr; /* sz = hi - lo */ 508 dvma_addr += mp->dmai_mapping; /* start addr */ 509 510 if (mp->dmai_rflags & DDI_DMA_READ) 511 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 512 else 513 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 514 515 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 516 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 517 sync_dir, &num_sync); 518 dvma_addr += num_sync; 519 } 520 521 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 522 } 523 524 525 /* 526 * MSIQ Functions: 527 */ 528 529 /*ARGSUSED*/ 530 int 531 px_lib_msiq_init(dev_info_t *dip) 532 { 533 px_t *px_p = DIP_TO_STATE(dip); 534 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 535 uint64_t *msiq_addr, ra; 536 size_t msiq_size; 537 uint_t rec_cnt; 538 int i, err = DDI_SUCCESS; 539 uint64_t ret; 540 541 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 542 543 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 544 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 545 546 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 547 548 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 549 ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size)); 550 551 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 552 (i + msiq_state_p->msiq_1st_msiq_id), 553 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 554 DBG(DBG_LIB_MSIQ, dip, 555 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 556 err = DDI_FAILURE; 557 break; 558 } 559 560 if ((err = px_lib_msiq_info(dip, 561 (i + msiq_state_p->msiq_1st_msiq_id), 562 &ra, &rec_cnt)) != DDI_SUCCESS) { 563 DBG(DBG_LIB_MSIQ, dip, 564 "px_lib_msiq_info failed, ret 0x%x\n", err); 565 err = DDI_FAILURE; 566 break; 567 } 568 569 DBG(DBG_LIB_MSIQ, dip, 570 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 571 } 572 573 return (err); 574 } 575 576 /*ARGSUSED*/ 577 int 578 px_lib_msiq_fini(dev_info_t *dip) 579 { 580 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 581 582 return (DDI_SUCCESS); 583 } 584 585 /*ARGSUSED*/ 586 int 587 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 588 uint_t *msiq_rec_cnt_p) 589 { 590 uint64_t ret; 591 592 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 593 dip, msiq_id); 594 595 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 596 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 597 DBG(DBG_LIB_MSIQ, dip, 598 "hvio_msiq_info failed, ret 0x%lx\n", ret); 599 return (DDI_FAILURE); 600 } 601 602 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 603 ra_p, *msiq_rec_cnt_p); 604 605 return (DDI_SUCCESS); 606 } 607 608 /*ARGSUSED*/ 609 int 610 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 611 pci_msiq_valid_state_t *msiq_valid_state) 612 { 613 uint64_t ret; 614 615 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 616 dip, msiq_id); 617 618 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 619 msiq_id, msiq_valid_state)) != H_EOK) { 620 DBG(DBG_LIB_MSIQ, dip, 621 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 622 return (DDI_FAILURE); 623 } 624 625 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 626 *msiq_valid_state); 627 628 return (DDI_SUCCESS); 629 } 630 631 /*ARGSUSED*/ 632 int 633 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 634 pci_msiq_valid_state_t msiq_valid_state) 635 { 636 uint64_t ret; 637 638 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 639 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 640 641 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 642 msiq_id, msiq_valid_state)) != H_EOK) { 643 DBG(DBG_LIB_MSIQ, dip, 644 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 645 return (DDI_FAILURE); 646 } 647 648 return (DDI_SUCCESS); 649 } 650 651 /*ARGSUSED*/ 652 int 653 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 654 pci_msiq_state_t *msiq_state) 655 { 656 uint64_t ret; 657 658 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 659 dip, msiq_id); 660 661 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 662 msiq_id, msiq_state)) != H_EOK) { 663 DBG(DBG_LIB_MSIQ, dip, 664 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 665 return (DDI_FAILURE); 666 } 667 668 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 669 *msiq_state); 670 671 return (DDI_SUCCESS); 672 } 673 674 /*ARGSUSED*/ 675 int 676 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 677 pci_msiq_state_t msiq_state) 678 { 679 uint64_t ret; 680 681 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 682 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 683 684 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 685 msiq_id, msiq_state)) != H_EOK) { 686 DBG(DBG_LIB_MSIQ, dip, 687 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 688 return (DDI_FAILURE); 689 } 690 691 return (DDI_SUCCESS); 692 } 693 694 /*ARGSUSED*/ 695 int 696 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 697 msiqhead_t *msiq_head_p) 698 { 699 uint64_t ret; 700 701 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 702 dip, msiq_id); 703 704 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 705 msiq_id, msiq_head_p)) != H_EOK) { 706 DBG(DBG_LIB_MSIQ, dip, 707 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 708 return (DDI_FAILURE); 709 } 710 711 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 712 713 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 714 *msiq_head_p); 715 716 return (DDI_SUCCESS); 717 } 718 719 /*ARGSUSED*/ 720 int 721 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 722 msiqhead_t msiq_head) 723 { 724 uint64_t ret; 725 726 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 727 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 728 729 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 730 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 731 DBG(DBG_LIB_MSIQ, dip, 732 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 733 return (DDI_FAILURE); 734 } 735 736 return (DDI_SUCCESS); 737 } 738 739 /*ARGSUSED*/ 740 int 741 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 742 msiqtail_t *msiq_tail_p) 743 { 744 uint64_t ret; 745 746 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 747 dip, msiq_id); 748 749 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 750 msiq_id, msiq_tail_p)) != H_EOK) { 751 DBG(DBG_LIB_MSIQ, dip, 752 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 753 return (DDI_FAILURE); 754 } 755 756 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 757 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 758 *msiq_tail_p); 759 760 return (DDI_SUCCESS); 761 } 762 763 /*ARGSUSED*/ 764 void 765 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 766 { 767 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_p->msiq_curr; 768 769 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 770 771 if (!curr_msiq_rec_p->msiq_rec_type) 772 return; 773 774 *msiq_rec_p = *curr_msiq_rec_p; 775 776 /* Zero out msiq_rec_type field */ 777 curr_msiq_rec_p->msiq_rec_type = 0; 778 } 779 780 /* 781 * MSI Functions: 782 */ 783 784 /*ARGSUSED*/ 785 int 786 px_lib_msi_init(dev_info_t *dip) 787 { 788 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 789 790 /* Noop */ 791 return (DDI_SUCCESS); 792 } 793 794 /*ARGSUSED*/ 795 int 796 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 797 msiqid_t *msiq_id) 798 { 799 uint64_t ret; 800 801 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 802 dip, msi_num); 803 804 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 805 msi_num, msiq_id)) != H_EOK) { 806 DBG(DBG_LIB_MSI, dip, 807 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 808 return (DDI_FAILURE); 809 } 810 811 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 812 *msiq_id); 813 814 return (DDI_SUCCESS); 815 } 816 817 /*ARGSUSED*/ 818 int 819 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 820 msiqid_t msiq_id, msi_type_t msitype) 821 { 822 uint64_t ret; 823 824 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 825 "msq_id 0x%x\n", dip, msi_num, msiq_id); 826 827 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 828 msi_num, msiq_id, msitype)) != H_EOK) { 829 DBG(DBG_LIB_MSI, dip, 830 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 831 return (DDI_FAILURE); 832 } 833 834 return (DDI_SUCCESS); 835 } 836 837 /*ARGSUSED*/ 838 int 839 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 840 pci_msi_valid_state_t *msi_valid_state) 841 { 842 uint64_t ret; 843 844 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 845 dip, msi_num); 846 847 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 848 msi_num, msi_valid_state)) != H_EOK) { 849 DBG(DBG_LIB_MSI, dip, 850 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 851 return (DDI_FAILURE); 852 } 853 854 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 855 *msi_valid_state); 856 857 return (DDI_SUCCESS); 858 } 859 860 /*ARGSUSED*/ 861 int 862 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 863 pci_msi_valid_state_t msi_valid_state) 864 { 865 uint64_t ret; 866 867 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 868 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 869 870 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 871 msi_num, msi_valid_state)) != H_EOK) { 872 DBG(DBG_LIB_MSI, dip, 873 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 874 return (DDI_FAILURE); 875 } 876 877 return (DDI_SUCCESS); 878 } 879 880 /*ARGSUSED*/ 881 int 882 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 883 pci_msi_state_t *msi_state) 884 { 885 uint64_t ret; 886 887 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 888 dip, msi_num); 889 890 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 891 msi_num, msi_state)) != H_EOK) { 892 DBG(DBG_LIB_MSI, dip, 893 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 894 return (DDI_FAILURE); 895 } 896 897 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 898 *msi_state); 899 900 return (DDI_SUCCESS); 901 } 902 903 /*ARGSUSED*/ 904 int 905 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 906 pci_msi_state_t msi_state) 907 { 908 uint64_t ret; 909 910 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 911 "msi_state 0x%x\n", dip, msi_num, msi_state); 912 913 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 914 msi_num, msi_state)) != H_EOK) { 915 DBG(DBG_LIB_MSI, dip, 916 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 917 return (DDI_FAILURE); 918 } 919 920 return (DDI_SUCCESS); 921 } 922 923 /* 924 * MSG Functions: 925 */ 926 927 /*ARGSUSED*/ 928 int 929 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 930 msiqid_t *msiq_id) 931 { 932 uint64_t ret; 933 934 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 935 dip, msg_type); 936 937 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 938 msg_type, msiq_id)) != H_EOK) { 939 DBG(DBG_LIB_MSG, dip, 940 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 941 return (DDI_FAILURE); 942 } 943 944 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 945 *msiq_id); 946 947 return (DDI_SUCCESS); 948 } 949 950 /*ARGSUSED*/ 951 int 952 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 953 msiqid_t msiq_id) 954 { 955 uint64_t ret; 956 957 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 958 "msq_id 0x%x\n", dip, msg_type, msiq_id); 959 960 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 961 msg_type, msiq_id)) != H_EOK) { 962 DBG(DBG_LIB_MSG, dip, 963 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 964 return (DDI_FAILURE); 965 } 966 967 return (DDI_SUCCESS); 968 } 969 970 /*ARGSUSED*/ 971 int 972 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 973 pcie_msg_valid_state_t *msg_valid_state) 974 { 975 uint64_t ret; 976 977 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 978 dip, msg_type); 979 980 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 981 msg_valid_state)) != H_EOK) { 982 DBG(DBG_LIB_MSG, dip, 983 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 984 return (DDI_FAILURE); 985 } 986 987 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 988 *msg_valid_state); 989 990 return (DDI_SUCCESS); 991 } 992 993 /*ARGSUSED*/ 994 int 995 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 996 pcie_msg_valid_state_t msg_valid_state) 997 { 998 uint64_t ret; 999 1000 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1001 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1002 1003 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1004 msg_valid_state)) != H_EOK) { 1005 DBG(DBG_LIB_MSG, dip, 1006 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1007 return (DDI_FAILURE); 1008 } 1009 1010 return (DDI_SUCCESS); 1011 } 1012 1013 /* 1014 * Suspend/Resume Functions: 1015 * Currently unsupported by hypervisor and all functions are noops. 1016 */ 1017 /*ARGSUSED*/ 1018 int 1019 px_lib_suspend(dev_info_t *dip) 1020 { 1021 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1022 1023 /* Not supported */ 1024 return (DDI_FAILURE); 1025 } 1026 1027 /*ARGSUSED*/ 1028 void 1029 px_lib_resume(dev_info_t *dip) 1030 { 1031 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1032 1033 /* Noop */ 1034 } 1035 1036 /* 1037 * Misc Functions: 1038 * Currently unsupported by hypervisor and all functions are noops. 1039 */ 1040 /*ARGSUSED*/ 1041 static int 1042 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1043 uint8_t size, pci_cfg_data_t *data_p) 1044 { 1045 uint64_t ret; 1046 1047 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1048 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1049 1050 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1051 size, data_p)) != H_EOK) { 1052 DBG(DBG_LIB_CFG, dip, 1053 "hvio_config_get failed, ret 0x%lx\n", ret); 1054 return (DDI_FAILURE); 1055 } 1056 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1057 1058 return (DDI_SUCCESS); 1059 } 1060 1061 /*ARGSUSED*/ 1062 static int 1063 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1064 uint8_t size, pci_cfg_data_t data) 1065 { 1066 uint64_t ret; 1067 1068 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1069 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1070 1071 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1072 size, data)) != H_EOK) { 1073 DBG(DBG_LIB_CFG, dip, 1074 "hvio_config_put failed, ret 0x%lx\n", ret); 1075 return (DDI_FAILURE); 1076 } 1077 1078 return (DDI_SUCCESS); 1079 } 1080 1081 static uint32_t 1082 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1083 { 1084 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1085 handle->ahi_common.ah_bus_private; 1086 uint32_t pci_dev_addr = px_pvt->raddr; 1087 uint32_t vaddr = px_pvt->vaddr; 1088 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1089 uint32_t rdata = 0; 1090 1091 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1092 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1093 /* XXX update error kstats */ 1094 return (0xffffffff); 1095 return (rdata); 1096 } 1097 1098 static void 1099 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1100 int size, pci_cfg_data_t wdata) 1101 { 1102 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1103 handle->ahi_common.ah_bus_private; 1104 uint32_t pci_dev_addr = px_pvt->raddr; 1105 uint32_t vaddr = px_pvt->vaddr; 1106 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1107 1108 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1109 size, wdata) != DDI_SUCCESS) { 1110 /*EMPTY*/ 1111 /* XXX update error kstats */ 1112 } 1113 } 1114 1115 static uint8_t 1116 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1117 { 1118 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1119 } 1120 1121 static uint16_t 1122 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1123 { 1124 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1125 } 1126 1127 static uint32_t 1128 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1129 { 1130 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1131 } 1132 1133 static uint64_t 1134 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1135 { 1136 uint32_t rdatah, rdatal; 1137 1138 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1139 rdatah = (uint32_t)px_pci_config_get(handle, 1140 (uint32_t *)((char *)addr+4), 4); 1141 return (((uint64_t)rdatah << 32) | rdatal); 1142 } 1143 1144 static void 1145 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1146 { 1147 pci_cfg_data_t wdata = { 0 }; 1148 1149 wdata.qw = (uint8_t)data; 1150 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1151 } 1152 1153 static void 1154 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1155 { 1156 pci_cfg_data_t wdata = { 0 }; 1157 1158 wdata.qw = (uint16_t)data; 1159 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1160 } 1161 1162 static void 1163 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1164 { 1165 pci_cfg_data_t wdata = { 0 }; 1166 1167 wdata.qw = (uint32_t)data; 1168 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1169 } 1170 1171 static void 1172 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1173 { 1174 pci_cfg_data_t wdata = { 0 }; 1175 1176 wdata.qw = (uint32_t)(data & 0xffffffff); 1177 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1178 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1179 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1180 } 1181 1182 static void 1183 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1184 uint8_t *dev_addr, size_t repcount, uint_t flags) 1185 { 1186 if (flags == DDI_DEV_AUTOINCR) 1187 for (; repcount; repcount--) 1188 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1189 else 1190 for (; repcount; repcount--) 1191 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1192 } 1193 1194 /* 1195 * Function to rep read 16 bit data off the PCI configuration space behind 1196 * the 21554's host interface. 1197 */ 1198 static void 1199 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1200 uint16_t *dev_addr, size_t repcount, uint_t flags) 1201 { 1202 if (flags == DDI_DEV_AUTOINCR) 1203 for (; repcount; repcount--) 1204 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1205 else 1206 for (; repcount; repcount--) 1207 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1208 } 1209 1210 /* 1211 * Function to rep read 32 bit data off the PCI configuration space behind 1212 * the 21554's host interface. 1213 */ 1214 static void 1215 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1216 uint32_t *dev_addr, size_t repcount, uint_t flags) 1217 { 1218 if (flags == DDI_DEV_AUTOINCR) 1219 for (; repcount; repcount--) 1220 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1221 else 1222 for (; repcount; repcount--) 1223 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1224 } 1225 1226 /* 1227 * Function to rep read 64 bit data off the PCI configuration space behind 1228 * the 21554's host interface. 1229 */ 1230 static void 1231 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1232 uint64_t *dev_addr, size_t repcount, uint_t flags) 1233 { 1234 if (flags == DDI_DEV_AUTOINCR) 1235 for (; repcount; repcount--) 1236 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1237 else 1238 for (; repcount; repcount--) 1239 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1240 } 1241 1242 /* 1243 * Function to rep write 8 bit data into the PCI configuration space behind 1244 * the 21554's host interface. 1245 */ 1246 static void 1247 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1248 uint8_t *dev_addr, size_t repcount, uint_t flags) 1249 { 1250 if (flags == DDI_DEV_AUTOINCR) 1251 for (; repcount; repcount--) 1252 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1253 else 1254 for (; repcount; repcount--) 1255 px_pci_config_put8(handle, dev_addr, *host_addr++); 1256 } 1257 1258 /* 1259 * Function to rep write 16 bit data into the PCI configuration space behind 1260 * the 21554's host interface. 1261 */ 1262 static void 1263 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1264 uint16_t *dev_addr, size_t repcount, uint_t flags) 1265 { 1266 if (flags == DDI_DEV_AUTOINCR) 1267 for (; repcount; repcount--) 1268 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1269 else 1270 for (; repcount; repcount--) 1271 px_pci_config_put16(handle, dev_addr, *host_addr++); 1272 } 1273 1274 /* 1275 * Function to rep write 32 bit data into the PCI configuration space behind 1276 * the 21554's host interface. 1277 */ 1278 static void 1279 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1280 uint32_t *dev_addr, size_t repcount, uint_t flags) 1281 { 1282 if (flags == DDI_DEV_AUTOINCR) 1283 for (; repcount; repcount--) 1284 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1285 else 1286 for (; repcount; repcount--) 1287 px_pci_config_put32(handle, dev_addr, *host_addr++); 1288 } 1289 1290 /* 1291 * Function to rep write 64 bit data into the PCI configuration space behind 1292 * the 21554's host interface. 1293 */ 1294 static void 1295 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1296 uint64_t *dev_addr, size_t repcount, uint_t flags) 1297 { 1298 if (flags == DDI_DEV_AUTOINCR) 1299 for (; repcount; repcount--) 1300 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1301 else 1302 for (; repcount; repcount--) 1303 px_pci_config_put64(handle, dev_addr, *host_addr++); 1304 } 1305 1306 /* 1307 * Provide a private access handle to route config access calls to Hypervisor. 1308 * Beware: Do all error checking for config space accesses before calling 1309 * this function. ie. do error checking from the calling function. 1310 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1311 * DDI_SUCCESS from here makes the code organization readable/easier from 1312 * the generic code. 1313 */ 1314 /*ARGSUSED*/ 1315 int 1316 px_lib_map_vconfig(dev_info_t *dip, 1317 ddi_map_req_t *mp, pci_config_offset_t off, 1318 pci_regspec_t *rp, caddr_t *addrp) 1319 { 1320 ddi_acc_hdl_t *hp; 1321 ddi_acc_impl_t *ap; 1322 uchar_t busnum; /* bus number */ 1323 uchar_t devnum; /* device number */ 1324 uchar_t funcnum; /* function number */ 1325 px_config_acc_pvt_t *px_pvt; 1326 1327 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1328 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1329 1330 /* Check for mapping teardown operation */ 1331 if ((mp->map_op == DDI_MO_UNMAP) || 1332 (mp->map_op == DDI_MO_UNLOCK)) { 1333 /* free up memory allocated for the private access handle. */ 1334 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1335 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1336 1337 /* unmap operation of PCI IO/config space. */ 1338 return (DDI_SUCCESS); 1339 } 1340 1341 ap->ahi_get8 = px_pci_config_get8; 1342 ap->ahi_get16 = px_pci_config_get16; 1343 ap->ahi_get32 = px_pci_config_get32; 1344 ap->ahi_get64 = px_pci_config_get64; 1345 ap->ahi_put8 = px_pci_config_put8; 1346 ap->ahi_put16 = px_pci_config_put16; 1347 ap->ahi_put32 = px_pci_config_put32; 1348 ap->ahi_put64 = px_pci_config_put64; 1349 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1350 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1351 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1352 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1353 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1354 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1355 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1356 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1357 1358 /* Initialize to default check/notify functions */ 1359 ap->ahi_fault = 0; 1360 ap->ahi_fault_check = i_ddi_acc_fault_check; 1361 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1362 1363 /* allocate memory for our private handle */ 1364 px_pvt = (px_config_acc_pvt_t *) 1365 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1366 hp->ah_bus_private = (void *)px_pvt; 1367 1368 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1369 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1370 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1371 1372 /* set up private data for use during IO routines */ 1373 1374 /* addr needed by the HV APIs */ 1375 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1376 /* 1377 * Address that specifies the actual offset into the 256MB 1378 * memory mapped configuration space, 4K per device. 1379 * First 12bits form the offset into 4K config space. 1380 * This address is only used during the IO routines to calculate 1381 * the offset at which the transaction must be performed. 1382 * Drivers bypassing DDI functions to access PCI config space will 1383 * panic the system since the following is a bogus virtual address. 1384 */ 1385 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1386 px_pvt->dip = dip; 1387 1388 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1389 px_pvt->raddr, px_pvt->vaddr); 1390 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1391 return (DDI_SUCCESS); 1392 } 1393 1394 /*ARGSUSED*/ 1395 void 1396 px_lib_map_attr_check(ddi_map_req_t *mp) 1397 { 1398 } 1399 1400 /* 1401 * px_lib_log_safeacc_err: 1402 * Imitate a cpu/mem trap call when a peek/poke fails. 1403 * This will initiate something similar to px_fm_callback. 1404 */ 1405 static void 1406 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1407 { 1408 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1409 ddi_fm_error_t derr; 1410 1411 derr.fme_status = DDI_FM_NONFATAL; 1412 derr.fme_version = DDI_FME_VERSION; 1413 derr.fme_flag = fme_flag; 1414 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1415 derr.fme_acc_handle = handle; 1416 if (hp) 1417 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1418 1419 mutex_enter(&px_p->px_fm_mutex); 1420 1421 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1422 1423 mutex_exit(&px_p->px_fm_mutex); 1424 } 1425 1426 1427 #ifdef DEBUG 1428 int px_peekfault_cnt = 0; 1429 int px_pokefault_cnt = 0; 1430 #endif /* DEBUG */ 1431 1432 static int 1433 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1434 { 1435 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1436 pci_regspec_t regspec_array[8]; 1437 pci_regspec_t *regspec = regspec_array; 1438 int buflen = sizeof (regspec_array); 1439 boolean_t kmalloced = B_FALSE; 1440 int status; 1441 1442 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1443 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1444 1445 /* If need more space, fallback to kmem_alloc. */ 1446 if (status == DDI_PROP_BUF_TOO_SMALL) { 1447 regspec = kmem_alloc(buflen, KM_SLEEP); 1448 1449 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1450 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1451 1452 kmalloced = B_TRUE; 1453 } 1454 1455 /* Get phys_hi from first element. All have same bdf. */ 1456 if (status == DDI_PROP_SUCCESS) 1457 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1458 1459 if (kmalloced) 1460 kmem_free(regspec, buflen); 1461 1462 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1463 } 1464 1465 /* 1466 * Do a safe write to a device. 1467 * 1468 * When this function is given a handle (cautious access), all errors are 1469 * suppressed. 1470 * 1471 * When this function is not given a handle (poke), only Unsupported Request 1472 * and Completer Abort errors are suppressed. 1473 * 1474 * In all cases, all errors are returned in the function return status. 1475 */ 1476 1477 int 1478 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1479 peekpoke_ctlops_t *in_args) 1480 { 1481 px_t *px_p = DIP_TO_STATE(dip); 1482 px_pec_t *pec_p = px_p->px_pec_p; 1483 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1484 1485 size_t repcount = in_args->repcount; 1486 size_t size = in_args->size; 1487 uintptr_t dev_addr = in_args->dev_addr; 1488 uintptr_t host_addr = in_args->host_addr; 1489 1490 int err = DDI_SUCCESS; 1491 uint64_t hvio_poke_status; 1492 uint32_t bdf; 1493 uint32_t wrt_stat; 1494 1495 r_addr_t ra; 1496 uint64_t pokeval; 1497 1498 /* 1499 * Used only to notify error handling peek/poke is occuring 1500 * One scenario is when a fabric err as a result of peek/poke. 1501 * However there is no way to guarantee that the fabric error 1502 * handler will occur in the window where otd is set. 1503 */ 1504 on_trap_data_t otd; 1505 1506 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1507 DBG(DBG_LIB_DMA, px_p->px_dip, 1508 "poke: px_lib_bdf_from_dip failed\n"); 1509 err = DDI_FAILURE; 1510 goto done; 1511 } 1512 1513 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1514 for (; repcount; repcount--) { 1515 1516 switch (size) { 1517 case sizeof (uint8_t): 1518 pokeval = *(uint8_t *)host_addr; 1519 break; 1520 case sizeof (uint16_t): 1521 pokeval = *(uint16_t *)host_addr; 1522 break; 1523 case sizeof (uint32_t): 1524 pokeval = *(uint32_t *)host_addr; 1525 break; 1526 case sizeof (uint64_t): 1527 pokeval = *(uint64_t *)host_addr; 1528 break; 1529 default: 1530 DBG(DBG_MAP, px_p->px_dip, 1531 "poke: invalid size %d passed\n", size); 1532 err = DDI_FAILURE; 1533 goto done; 1534 } 1535 1536 /* 1537 * Grab pokefault mutex since hypervisor does not guarantee 1538 * poke serialization. 1539 */ 1540 if (hp) { 1541 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1542 (ddi_acc_handle_t)hp); 1543 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1544 } else { 1545 mutex_enter(&pec_p->pec_pokefault_mutex); 1546 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1547 } 1548 pec_p->pec_ontrap_data = &otd; 1549 1550 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1551 pokeval, bdf, &wrt_stat); 1552 1553 if (otd.ot_trap & OT_DATA_ACCESS) 1554 err = DDI_FAILURE; 1555 1556 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1557 err = DDI_FAILURE; 1558 #ifdef DEBUG 1559 px_pokefault_cnt++; 1560 #endif 1561 /* 1562 * For CAUTIOUS and POKE access, notify FMA to 1563 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1564 */ 1565 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1566 (hp ? DDI_FM_ERR_EXPECTED : 1567 DDI_FM_ERR_POKE)); 1568 1569 pec_p->pec_ontrap_data = NULL; 1570 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1571 if (hp) { 1572 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1573 (ddi_acc_handle_t)hp); 1574 } else { 1575 mutex_exit(&pec_p->pec_pokefault_mutex); 1576 } 1577 goto done; 1578 } 1579 1580 pec_p->pec_ontrap_data = NULL; 1581 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1582 if (hp) { 1583 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1584 (ddi_acc_handle_t)hp); 1585 } else { 1586 mutex_exit(&pec_p->pec_pokefault_mutex); 1587 } 1588 1589 host_addr += size; 1590 1591 if (in_args->flags == DDI_DEV_AUTOINCR) { 1592 dev_addr += size; 1593 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1594 } 1595 } 1596 1597 done: 1598 return (err); 1599 } 1600 1601 1602 /*ARGSUSED*/ 1603 int 1604 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1605 peekpoke_ctlops_t *in_args, void *result) 1606 { 1607 px_t *px_p = DIP_TO_STATE(dip); 1608 px_pec_t *pec_p = px_p->px_pec_p; 1609 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1610 1611 size_t repcount = in_args->repcount; 1612 uintptr_t dev_addr = in_args->dev_addr; 1613 uintptr_t host_addr = in_args->host_addr; 1614 1615 r_addr_t ra; 1616 uint32_t read_status; 1617 uint64_t hvio_peek_status; 1618 uint64_t peekval; 1619 int err = DDI_SUCCESS; 1620 1621 /* 1622 * Used only to notify error handling peek/poke is occuring 1623 * One scenario is when a fabric err as a result of peek/poke. 1624 * However there is no way to guarantee that the fabric error 1625 * handler will occur in the window where otd is set. 1626 */ 1627 on_trap_data_t otd; 1628 1629 result = (void *)in_args->host_addr; 1630 1631 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1632 for (; repcount; repcount--) { 1633 1634 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1635 if (hp) { 1636 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1637 (ddi_acc_handle_t)hp); 1638 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1639 } else { 1640 mutex_enter(&pec_p->pec_pokefault_mutex); 1641 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1642 } 1643 pec_p->pec_ontrap_data = &otd; 1644 1645 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1646 in_args->size, &read_status, &peekval); 1647 1648 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1649 err = DDI_FAILURE; 1650 1651 /* 1652 * For CAUTIOUS and PEEK access, notify FMA to 1653 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1654 */ 1655 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1656 (hp ? DDI_FM_ERR_EXPECTED : 1657 DDI_FM_ERR_PEEK)); 1658 1659 /* Stuff FFs in host addr if peek. */ 1660 if (hp == NULL) { 1661 int i; 1662 uint8_t *ff_addr = (uint8_t *)host_addr; 1663 for (i = 0; i < in_args->size; i++) 1664 *ff_addr++ = 0xff; 1665 } 1666 #ifdef DEBUG 1667 px_peekfault_cnt++; 1668 #endif 1669 pec_p->pec_ontrap_data = NULL; 1670 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1671 if (hp) { 1672 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1673 (ddi_acc_handle_t)hp); 1674 } else { 1675 mutex_exit(&pec_p->pec_pokefault_mutex); 1676 } 1677 goto done; 1678 1679 } 1680 pec_p->pec_ontrap_data = NULL; 1681 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1682 if (hp) { 1683 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1684 (ddi_acc_handle_t)hp); 1685 } else { 1686 mutex_exit(&pec_p->pec_pokefault_mutex); 1687 } 1688 1689 switch (in_args->size) { 1690 case sizeof (uint8_t): 1691 *(uint8_t *)host_addr = (uint8_t)peekval; 1692 break; 1693 case sizeof (uint16_t): 1694 *(uint16_t *)host_addr = (uint16_t)peekval; 1695 break; 1696 case sizeof (uint32_t): 1697 *(uint32_t *)host_addr = (uint32_t)peekval; 1698 break; 1699 case sizeof (uint64_t): 1700 *(uint64_t *)host_addr = (uint64_t)peekval; 1701 break; 1702 default: 1703 DBG(DBG_MAP, px_p->px_dip, 1704 "peek: invalid size %d passed\n", 1705 in_args->size); 1706 err = DDI_FAILURE; 1707 goto done; 1708 } 1709 1710 host_addr += in_args->size; 1711 1712 if (in_args->flags == DDI_DEV_AUTOINCR) { 1713 dev_addr += in_args->size; 1714 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1715 } 1716 } 1717 done: 1718 return (err); 1719 } 1720 1721 1722 /* add interrupt vector */ 1723 int 1724 px_err_add_intr(px_fault_t *px_fault_p) 1725 { 1726 int ret; 1727 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1728 1729 DBG(DBG_LIB_INT, px_p->px_dip, 1730 "px_err_add_intr: calling add_ivintr"); 1731 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1732 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1733 (caddr_t)&px_fault_p->px_intr_payload[0]); 1734 1735 if (ret != DDI_SUCCESS) { 1736 DBG(DBG_LIB_INT, px_p->px_dip, 1737 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1738 1739 return (ret); 1740 } 1741 DBG(DBG_LIB_INT, px_p->px_dip, 1742 "px_err_add_intr: ib_intr_enable "); 1743 1744 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1745 1746 return (ret); 1747 } 1748 1749 /* remove interrupt vector */ 1750 void 1751 px_err_rem_intr(px_fault_t *px_fault_p) 1752 { 1753 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1754 1755 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1756 IB_INTR_WAIT); 1757 1758 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1759 } 1760 1761 int 1762 px_cb_add_intr(px_fault_t *f_p) 1763 { 1764 return (px_err_add_intr(f_p)); 1765 } 1766 1767 void 1768 px_cb_rem_intr(px_fault_t *f_p) 1769 { 1770 px_err_rem_intr(f_p); 1771 } 1772 1773 void 1774 px_cb_intr_redist(px_t *px_p) 1775 { 1776 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1777 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1778 } 1779 1780 #ifdef FMA 1781 void 1782 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1783 { 1784 px_pec_err_t *err_pkt; 1785 1786 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1787 1788 /* initialise all the structure members */ 1789 rc_status->status_valid = 0; 1790 1791 if (err_pkt->pec_descr.P) { 1792 /* PCI Status Register */ 1793 rc_status->pci_err_status = err_pkt->pci_err_status; 1794 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1795 } 1796 1797 if (err_pkt->pec_descr.E) { 1798 /* PCIe Status Register */ 1799 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1800 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1801 } 1802 1803 if (err_pkt->pec_descr.U) { 1804 rc_status->ue_status = err_pkt->ue_reg_status; 1805 rc_status->status_valid |= UE_STATUS_VALID; 1806 } 1807 1808 if (err_pkt->pec_descr.H) { 1809 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1810 rc_status->status_valid |= UE_HDR1_VALID; 1811 } 1812 1813 if (err_pkt->pec_descr.I) { 1814 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1815 rc_status->status_valid |= UE_HDR2_VALID; 1816 } 1817 1818 /* ue_fst_err_ptr - not available for sun4v?? */ 1819 1820 1821 if (err_pkt->pec_descr.S) { 1822 rc_status->source_id = err_pkt->err_src_reg; 1823 rc_status->status_valid |= SOURCE_ID_VALID; 1824 } 1825 1826 if (err_pkt->pec_descr.R) { 1827 rc_status->root_err_status = err_pkt->root_err_status; 1828 rc_status->status_valid |= CE_STATUS_VALID; 1829 } 1830 } 1831 #endif 1832 1833 /*ARGSUSED*/ 1834 int 1835 px_lib_pmctl(int cmd, px_t *px_p) 1836 { 1837 return (DDI_FAILURE); 1838 } 1839 1840 /*ARGSUSED*/ 1841 uint_t 1842 px_pmeq_intr(caddr_t arg) 1843 { 1844 return (DDI_INTR_CLAIMED); 1845 } 1846 1847 /* 1848 * Unprotected raw reads/writes of fabric device's config space. 1849 * Only used for temporary PCI-E Fabric Error Handling. 1850 */ 1851 uint32_t 1852 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1853 uint32_t data = 0; 1854 1855 (void) hvio_config_get(px_p->px_dev_hdl, 1856 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1857 (pci_cfg_data_t *)&data); 1858 1859 return (data); 1860 } 1861 1862 void 1863 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1864 uint32_t val) { 1865 pci_cfg_data_t wdata = { 0 }; 1866 1867 wdata.qw = (uint32_t)val; 1868 (void) hvio_config_put(px_p->px_dev_hdl, 1869 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1870 } 1871 1872 /*ARGSUSED*/ 1873 int 1874 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1875 { 1876 return (DDI_ENOTSUP); 1877 } 1878 1879 /*ARGSUSED*/ 1880 void 1881 px_lib_hotplug_uninit(dev_info_t *dip) 1882 { 1883 } 1884 1885 /* Dummy cpr add callback */ 1886 /*ARGSUSED*/ 1887 void 1888 px_cpr_add_callb(px_t *px_p) 1889 { 1890 } 1891 1892 /* Dummy cpr rem callback */ 1893 /*ARGSUSED*/ 1894 void 1895 px_cpr_rem_callb(px_t *px_p) 1896 { 1897 } 1898