1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69 70 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "reg", (uchar_t **)&rp, ®len); 72 if (ret != DDI_PROP_SUCCESS) { 73 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 74 return (DDI_FAILURE); 75 } 76 77 /* 78 * Initilize device handle. The device handle uniquely identifies 79 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 80 * of the first entry of the SUN4V device's "reg" property as 81 * defined by the SUN4V Bus Binding to Open Firmware. 82 */ 83 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 84 ddi_prop_free(rp); 85 86 /* 87 * hotplug implementation requires this property to be associated with 88 * any indirect PCI config access services 89 */ 90 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 91 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 92 PCI_BUS_CONF_MAP_PROP, 1); 93 94 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 95 96 /* 97 * Negotiate the API version for VPCI hypervisor services. 98 */ 99 if (px_vpci_users++) 100 return (DDI_SUCCESS); 101 102 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 103 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 104 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 105 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 106 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 107 108 return (DDI_FAILURE); 109 } 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 112 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 113 114 return (DDI_SUCCESS); 115 } 116 117 /*ARGSUSED*/ 118 int 119 px_lib_dev_fini(dev_info_t *dip) 120 { 121 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 122 123 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 124 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 125 PCI_BUS_CONF_MAP_PROP); 126 127 if (--px_vpci_users == 0) 128 (void) hsvc_unregister(&px_hsvc); 129 130 return (DDI_SUCCESS); 131 } 132 133 /*ARGSUSED*/ 134 int 135 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 136 sysino_t *sysino) 137 { 138 uint64_t ret; 139 140 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 141 "devino 0x%x\n", dip, devino); 142 143 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 144 devino, sysino)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, 146 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 147 return (DDI_FAILURE); 148 } 149 150 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 151 *sysino); 152 153 return (DDI_SUCCESS); 154 } 155 156 /*ARGSUSED*/ 157 int 158 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 159 intr_valid_state_t *intr_valid_state) 160 { 161 uint64_t ret; 162 163 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 164 dip, sysino); 165 166 if ((ret = hvio_intr_getvalid(sysino, 167 (int *)intr_valid_state)) != H_EOK) { 168 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 169 ret); 170 return (DDI_FAILURE); 171 } 172 173 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 174 *intr_valid_state); 175 176 return (DDI_SUCCESS); 177 } 178 179 /*ARGSUSED*/ 180 int 181 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 182 intr_valid_state_t intr_valid_state) 183 { 184 uint64_t ret; 185 186 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 187 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 188 189 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 190 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 191 ret); 192 return (DDI_FAILURE); 193 } 194 195 return (DDI_SUCCESS); 196 } 197 198 /*ARGSUSED*/ 199 int 200 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 201 intr_state_t *intr_state) 202 { 203 uint64_t ret; 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 206 dip, sysino); 207 208 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 209 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 210 ret); 211 return (DDI_FAILURE); 212 } 213 214 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 215 *intr_state); 216 217 return (DDI_SUCCESS); 218 } 219 220 /*ARGSUSED*/ 221 int 222 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 223 intr_state_t intr_state) 224 { 225 uint64_t ret; 226 227 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 228 "intr_state 0x%x\n", dip, sysino, intr_state); 229 230 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 231 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 232 ret); 233 return (DDI_FAILURE); 234 } 235 236 return (DDI_SUCCESS); 237 } 238 239 /*ARGSUSED*/ 240 int 241 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 242 { 243 uint64_t ret; 244 245 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 246 dip, sysino); 247 248 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 249 DBG(DBG_LIB_INT, dip, 250 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 251 return (DDI_FAILURE); 252 } 253 254 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 255 256 return (DDI_SUCCESS); 257 } 258 259 /*ARGSUSED*/ 260 int 261 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 262 { 263 uint64_t ret; 264 265 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 266 "cpuid 0x%x\n", dip, sysino, cpuid); 267 268 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 269 DBG(DBG_LIB_INT, dip, 270 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 271 return (DDI_FAILURE); 272 } 273 274 return (DDI_SUCCESS); 275 } 276 277 /*ARGSUSED*/ 278 int 279 px_lib_intr_reset(dev_info_t *dip) 280 { 281 px_t *px_p = DIP_TO_STATE(dip); 282 px_ib_t *ib_p = px_p->px_ib_p; 283 px_ib_ino_info_t *ino_p; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 286 287 mutex_enter(&ib_p->ib_ino_lst_mutex); 288 289 /* Reset all Interrupts */ 290 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) { 291 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 292 INTR_IDLE_STATE) != DDI_SUCCESS) 293 return (BF_FATAL); 294 } 295 296 mutex_exit(&ib_p->ib_ino_lst_mutex); 297 298 return (BF_NONE); 299 } 300 301 /*ARGSUSED*/ 302 int 303 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 304 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 305 { 306 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 307 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 308 io_page_list_t *pfns, *pfn_p; 309 pages_t ttes_mapped = 0; 310 int i, err = DDI_SUCCESS; 311 312 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 313 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 314 dip, tsbid, pages, attr, addr, pfn_index, flags); 315 316 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 317 KM_NOSLEEP)) == NULL) { 318 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 319 return (DDI_FAILURE); 320 } 321 322 for (i = 0; i < pages; i++) 323 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 324 325 while ((ttes_mapped = pfn_p - pfns) < pages) { 326 uintptr_t ra = va_to_pa(pfn_p); 327 pages_t ttes2map; 328 uint64_t ret; 329 330 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 331 ra = MMU_PTOB(MMU_BTOP(ra)); 332 333 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 334 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 335 336 ttes_mapped = 0; 337 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 338 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 339 ttes2map, attr, (io_page_list_t *)(ra | 340 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 341 &ttes_mapped)) != H_EOK) { 342 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 343 "ret 0x%lx\n", ret); 344 345 ttes_mapped = pfn_p - pfns; 346 err = DDI_FAILURE; 347 goto cleanup; 348 } 349 350 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 351 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 352 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 353 tsb_index + (pfn_p - pfns), ttes2map, attr, 354 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 355 ttes_mapped); 356 } 357 } 358 359 cleanup: 360 if ((err == DDI_FAILURE) && ttes_mapped) 361 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 362 363 kmem_free(pfns, pages * sizeof (io_page_list_t)); 364 return (err); 365 } 366 367 /*ARGSUSED*/ 368 int 369 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 370 { 371 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 372 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 373 pages_t ttes2demap, ttes_demapped = 0; 374 uint64_t ret; 375 376 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 377 "pages 0x%x\n", dip, tsbid, pages); 378 379 for (ttes2demap = pages; ttes2demap; 380 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 381 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 382 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 383 &ttes_demapped)) != H_EOK) { 384 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 385 "ret 0x%lx\n", ret); 386 387 return (DDI_FAILURE); 388 } 389 390 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 391 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 392 tsb_num, tsb_index, ttes2demap, ttes_demapped); 393 } 394 395 return (DDI_SUCCESS); 396 } 397 398 /*ARGSUSED*/ 399 int 400 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 401 r_addr_t *r_addr_p) 402 { 403 uint64_t ret; 404 405 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 406 dip, tsbid); 407 408 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 409 attr_p, r_addr_p)) != H_EOK) { 410 DBG(DBG_LIB_DMA, dip, 411 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 412 413 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 414 } 415 416 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 417 *attr_p, *r_addr_p); 418 419 return (DDI_SUCCESS); 420 } 421 422 /* 423 * fetch chip's range propery's value. For sun4v, config space base 424 * is not used (pxtool_get_phys_addr) will return zero, so just return 425 * zero for px_get_range_prop(). 426 */ 427 /*ARGSUSED*/ 428 uint64_t 429 px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank) 430 { 431 return (0); 432 } 433 434 /* 435 * Checks dma attributes against system bypass ranges 436 * A sun4v device must be capable of generating the entire 64-bit 437 * address in order to perform bypass DMA. 438 */ 439 /*ARGSUSED*/ 440 int 441 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 442 uint64_t *lo_p, uint64_t *hi_p) 443 { 444 if ((attr_p->dma_attr_addr_lo != 0ull) || 445 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 446 447 return (DDI_DMA_BADATTR); 448 } 449 450 *lo_p = 0ull; 451 *hi_p = UINT64_MAX; 452 453 return (DDI_SUCCESS); 454 } 455 456 457 /*ARGSUSED*/ 458 int 459 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 460 io_addr_t *io_addr_p) 461 { 462 uint64_t ret; 463 464 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 465 "attr 0x%x\n", dip, ra, attr); 466 467 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 468 attr, io_addr_p)) != H_EOK) { 469 DBG(DBG_LIB_DMA, dip, 470 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 471 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 472 } 473 474 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 475 *io_addr_p); 476 477 return (DDI_SUCCESS); 478 } 479 480 /*ARGSUSED*/ 481 int 482 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 483 off_t off, size_t len, uint_t cache_flags) 484 { 485 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 486 uint64_t sync_dir; 487 px_dvma_addr_t dvma_addr, pg_off; 488 size_t num_sync; 489 uint64_t status = H_EOK; 490 491 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 492 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 493 dip, rdip, handle, off, len, cache_flags); 494 495 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 496 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 497 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 498 return (DDI_FAILURE); 499 } 500 501 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 502 return (DDI_SUCCESS); 503 504 if (!len) 505 len = mp->dmai_size; 506 507 pg_off = mp->dmai_offset; /* start min */ 508 dvma_addr = MAX(off, pg_off); /* lo */ 509 pg_off += mp->dmai_size; /* end max */ 510 pg_off = MIN(off + len, pg_off); /* hi */ 511 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 512 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 513 ddi_driver_name(rdip), ddi_get_instance(rdip), 514 off, len, mp->dmai_offset, 515 mp->dmai_offset + mp->dmai_size); 516 return (DDI_FAILURE); 517 } 518 519 len = pg_off - dvma_addr; /* sz = hi - lo */ 520 dvma_addr += mp->dmai_mapping; /* start addr */ 521 522 if (mp->dmai_rflags & DDI_DMA_READ) 523 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 524 else 525 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 526 527 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 528 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 529 sync_dir, &num_sync); 530 dvma_addr += num_sync; 531 } 532 533 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 534 } 535 536 537 /* 538 * MSIQ Functions: 539 */ 540 541 /*ARGSUSED*/ 542 int 543 px_lib_msiq_init(dev_info_t *dip) 544 { 545 px_t *px_p = DIP_TO_STATE(dip); 546 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 547 uint64_t *msiq_addr, ra; 548 size_t msiq_size; 549 uint_t rec_cnt; 550 int i, err = DDI_SUCCESS; 551 uint64_t ret; 552 553 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 554 555 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 556 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 557 558 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 559 560 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 561 ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size)); 562 563 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 564 (i + msiq_state_p->msiq_1st_msiq_id), 565 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 566 DBG(DBG_LIB_MSIQ, dip, 567 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 568 err = DDI_FAILURE; 569 break; 570 } 571 572 if ((err = px_lib_msiq_info(dip, 573 (i + msiq_state_p->msiq_1st_msiq_id), 574 &ra, &rec_cnt)) != DDI_SUCCESS) { 575 DBG(DBG_LIB_MSIQ, dip, 576 "px_lib_msiq_info failed, ret 0x%x\n", err); 577 err = DDI_FAILURE; 578 break; 579 } 580 581 DBG(DBG_LIB_MSIQ, dip, 582 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 583 } 584 585 return (err); 586 } 587 588 /*ARGSUSED*/ 589 int 590 px_lib_msiq_fini(dev_info_t *dip) 591 { 592 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 593 594 return (DDI_SUCCESS); 595 } 596 597 /*ARGSUSED*/ 598 int 599 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 600 uint_t *msiq_rec_cnt_p) 601 { 602 uint64_t ret; 603 604 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 605 dip, msiq_id); 606 607 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 608 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 609 DBG(DBG_LIB_MSIQ, dip, 610 "hvio_msiq_info failed, ret 0x%lx\n", ret); 611 return (DDI_FAILURE); 612 } 613 614 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 615 ra_p, *msiq_rec_cnt_p); 616 617 return (DDI_SUCCESS); 618 } 619 620 /*ARGSUSED*/ 621 int 622 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 623 pci_msiq_valid_state_t *msiq_valid_state) 624 { 625 uint64_t ret; 626 627 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 628 dip, msiq_id); 629 630 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 631 msiq_id, msiq_valid_state)) != H_EOK) { 632 DBG(DBG_LIB_MSIQ, dip, 633 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 634 return (DDI_FAILURE); 635 } 636 637 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 638 *msiq_valid_state); 639 640 return (DDI_SUCCESS); 641 } 642 643 /*ARGSUSED*/ 644 int 645 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 646 pci_msiq_valid_state_t msiq_valid_state) 647 { 648 uint64_t ret; 649 650 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 651 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 652 653 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 654 msiq_id, msiq_valid_state)) != H_EOK) { 655 DBG(DBG_LIB_MSIQ, dip, 656 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 657 return (DDI_FAILURE); 658 } 659 660 return (DDI_SUCCESS); 661 } 662 663 /*ARGSUSED*/ 664 int 665 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 666 pci_msiq_state_t *msiq_state) 667 { 668 uint64_t ret; 669 670 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 671 dip, msiq_id); 672 673 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 674 msiq_id, msiq_state)) != H_EOK) { 675 DBG(DBG_LIB_MSIQ, dip, 676 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 677 return (DDI_FAILURE); 678 } 679 680 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 681 *msiq_state); 682 683 return (DDI_SUCCESS); 684 } 685 686 /*ARGSUSED*/ 687 int 688 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 689 pci_msiq_state_t msiq_state) 690 { 691 uint64_t ret; 692 693 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 694 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 695 696 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 697 msiq_id, msiq_state)) != H_EOK) { 698 DBG(DBG_LIB_MSIQ, dip, 699 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 700 return (DDI_FAILURE); 701 } 702 703 return (DDI_SUCCESS); 704 } 705 706 /*ARGSUSED*/ 707 int 708 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 709 msiqhead_t *msiq_head_p) 710 { 711 uint64_t ret; 712 713 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 714 dip, msiq_id); 715 716 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 717 msiq_id, msiq_head_p)) != H_EOK) { 718 DBG(DBG_LIB_MSIQ, dip, 719 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 720 return (DDI_FAILURE); 721 } 722 723 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 724 725 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 726 *msiq_head_p); 727 728 return (DDI_SUCCESS); 729 } 730 731 /*ARGSUSED*/ 732 int 733 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 734 msiqhead_t msiq_head) 735 { 736 uint64_t ret; 737 738 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 739 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 740 741 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 742 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 743 DBG(DBG_LIB_MSIQ, dip, 744 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 745 return (DDI_FAILURE); 746 } 747 748 return (DDI_SUCCESS); 749 } 750 751 /*ARGSUSED*/ 752 int 753 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 754 msiqtail_t *msiq_tail_p) 755 { 756 uint64_t ret; 757 758 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 759 dip, msiq_id); 760 761 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 762 msiq_id, msiq_tail_p)) != H_EOK) { 763 DBG(DBG_LIB_MSIQ, dip, 764 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 765 return (DDI_FAILURE); 766 } 767 768 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 769 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 770 *msiq_tail_p); 771 772 return (DDI_SUCCESS); 773 } 774 775 /*ARGSUSED*/ 776 void 777 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 778 { 779 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_p->msiq_curr; 780 781 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 782 783 if (!curr_msiq_rec_p->msiq_rec_type) 784 return; 785 786 *msiq_rec_p = *curr_msiq_rec_p; 787 788 /* Zero out msiq_rec_type field */ 789 curr_msiq_rec_p->msiq_rec_type = 0; 790 } 791 792 /* 793 * MSI Functions: 794 */ 795 796 /*ARGSUSED*/ 797 int 798 px_lib_msi_init(dev_info_t *dip) 799 { 800 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 801 802 /* Noop */ 803 return (DDI_SUCCESS); 804 } 805 806 /*ARGSUSED*/ 807 int 808 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 809 msiqid_t *msiq_id) 810 { 811 uint64_t ret; 812 813 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 814 dip, msi_num); 815 816 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 817 msi_num, msiq_id)) != H_EOK) { 818 DBG(DBG_LIB_MSI, dip, 819 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 820 return (DDI_FAILURE); 821 } 822 823 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 824 *msiq_id); 825 826 return (DDI_SUCCESS); 827 } 828 829 /*ARGSUSED*/ 830 int 831 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 832 msiqid_t msiq_id, msi_type_t msitype) 833 { 834 uint64_t ret; 835 836 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 837 "msq_id 0x%x\n", dip, msi_num, msiq_id); 838 839 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 840 msi_num, msiq_id, msitype)) != H_EOK) { 841 DBG(DBG_LIB_MSI, dip, 842 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 843 return (DDI_FAILURE); 844 } 845 846 return (DDI_SUCCESS); 847 } 848 849 /*ARGSUSED*/ 850 int 851 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 852 pci_msi_valid_state_t *msi_valid_state) 853 { 854 uint64_t ret; 855 856 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 857 dip, msi_num); 858 859 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 860 msi_num, msi_valid_state)) != H_EOK) { 861 DBG(DBG_LIB_MSI, dip, 862 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 863 return (DDI_FAILURE); 864 } 865 866 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 867 *msi_valid_state); 868 869 return (DDI_SUCCESS); 870 } 871 872 /*ARGSUSED*/ 873 int 874 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 875 pci_msi_valid_state_t msi_valid_state) 876 { 877 uint64_t ret; 878 879 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 880 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 881 882 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 883 msi_num, msi_valid_state)) != H_EOK) { 884 DBG(DBG_LIB_MSI, dip, 885 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 886 return (DDI_FAILURE); 887 } 888 889 return (DDI_SUCCESS); 890 } 891 892 /*ARGSUSED*/ 893 int 894 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 895 pci_msi_state_t *msi_state) 896 { 897 uint64_t ret; 898 899 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 900 dip, msi_num); 901 902 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 903 msi_num, msi_state)) != H_EOK) { 904 DBG(DBG_LIB_MSI, dip, 905 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 906 return (DDI_FAILURE); 907 } 908 909 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 910 *msi_state); 911 912 return (DDI_SUCCESS); 913 } 914 915 /*ARGSUSED*/ 916 int 917 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 918 pci_msi_state_t msi_state) 919 { 920 uint64_t ret; 921 922 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 923 "msi_state 0x%x\n", dip, msi_num, msi_state); 924 925 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 926 msi_num, msi_state)) != H_EOK) { 927 DBG(DBG_LIB_MSI, dip, 928 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 929 return (DDI_FAILURE); 930 } 931 932 return (DDI_SUCCESS); 933 } 934 935 /* 936 * MSG Functions: 937 */ 938 939 /*ARGSUSED*/ 940 int 941 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 942 msiqid_t *msiq_id) 943 { 944 uint64_t ret; 945 946 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 947 dip, msg_type); 948 949 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 950 msg_type, msiq_id)) != H_EOK) { 951 DBG(DBG_LIB_MSG, dip, 952 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 953 return (DDI_FAILURE); 954 } 955 956 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 957 *msiq_id); 958 959 return (DDI_SUCCESS); 960 } 961 962 /*ARGSUSED*/ 963 int 964 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 965 msiqid_t msiq_id) 966 { 967 uint64_t ret; 968 969 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 970 "msq_id 0x%x\n", dip, msg_type, msiq_id); 971 972 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 973 msg_type, msiq_id)) != H_EOK) { 974 DBG(DBG_LIB_MSG, dip, 975 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 976 return (DDI_FAILURE); 977 } 978 979 return (DDI_SUCCESS); 980 } 981 982 /*ARGSUSED*/ 983 int 984 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 985 pcie_msg_valid_state_t *msg_valid_state) 986 { 987 uint64_t ret; 988 989 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 990 dip, msg_type); 991 992 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 993 msg_valid_state)) != H_EOK) { 994 DBG(DBG_LIB_MSG, dip, 995 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 996 return (DDI_FAILURE); 997 } 998 999 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1000 *msg_valid_state); 1001 1002 return (DDI_SUCCESS); 1003 } 1004 1005 /*ARGSUSED*/ 1006 int 1007 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1008 pcie_msg_valid_state_t msg_valid_state) 1009 { 1010 uint64_t ret; 1011 1012 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1013 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1014 1015 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1016 msg_valid_state)) != H_EOK) { 1017 DBG(DBG_LIB_MSG, dip, 1018 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1019 return (DDI_FAILURE); 1020 } 1021 1022 return (DDI_SUCCESS); 1023 } 1024 1025 /* 1026 * Suspend/Resume Functions: 1027 * Currently unsupported by hypervisor and all functions are noops. 1028 */ 1029 /*ARGSUSED*/ 1030 int 1031 px_lib_suspend(dev_info_t *dip) 1032 { 1033 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1034 1035 /* Not supported */ 1036 return (DDI_FAILURE); 1037 } 1038 1039 /*ARGSUSED*/ 1040 void 1041 px_lib_resume(dev_info_t *dip) 1042 { 1043 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1044 1045 /* Noop */ 1046 } 1047 1048 /* 1049 * Misc Functions: 1050 * Currently unsupported by hypervisor and all functions are noops. 1051 */ 1052 /*ARGSUSED*/ 1053 static int 1054 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1055 uint8_t size, pci_cfg_data_t *data_p) 1056 { 1057 uint64_t ret; 1058 1059 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1060 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1061 1062 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1063 size, data_p)) != H_EOK) { 1064 DBG(DBG_LIB_CFG, dip, 1065 "hvio_config_get failed, ret 0x%lx\n", ret); 1066 return (DDI_FAILURE); 1067 } 1068 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1069 1070 return (DDI_SUCCESS); 1071 } 1072 1073 /*ARGSUSED*/ 1074 static int 1075 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1076 uint8_t size, pci_cfg_data_t data) 1077 { 1078 uint64_t ret; 1079 1080 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1081 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1082 1083 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1084 size, data)) != H_EOK) { 1085 DBG(DBG_LIB_CFG, dip, 1086 "hvio_config_put failed, ret 0x%lx\n", ret); 1087 return (DDI_FAILURE); 1088 } 1089 1090 return (DDI_SUCCESS); 1091 } 1092 1093 static uint32_t 1094 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1095 { 1096 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1097 handle->ahi_common.ah_bus_private; 1098 uint32_t pci_dev_addr = px_pvt->raddr; 1099 uint32_t vaddr = px_pvt->vaddr; 1100 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1101 uint32_t rdata = 0; 1102 1103 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1104 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1105 /* XXX update error kstats */ 1106 return (0xffffffff); 1107 return (rdata); 1108 } 1109 1110 static void 1111 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1112 int size, pci_cfg_data_t wdata) 1113 { 1114 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1115 handle->ahi_common.ah_bus_private; 1116 uint32_t pci_dev_addr = px_pvt->raddr; 1117 uint32_t vaddr = px_pvt->vaddr; 1118 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1119 1120 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1121 size, wdata) != DDI_SUCCESS) { 1122 /*EMPTY*/ 1123 /* XXX update error kstats */ 1124 } 1125 } 1126 1127 static uint8_t 1128 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1129 { 1130 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1131 } 1132 1133 static uint16_t 1134 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1135 { 1136 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1137 } 1138 1139 static uint32_t 1140 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1141 { 1142 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1143 } 1144 1145 static uint64_t 1146 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1147 { 1148 uint32_t rdatah, rdatal; 1149 1150 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1151 rdatah = (uint32_t)px_pci_config_get(handle, 1152 (uint32_t *)((char *)addr+4), 4); 1153 return (((uint64_t)rdatah << 32) | rdatal); 1154 } 1155 1156 static void 1157 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1158 { 1159 pci_cfg_data_t wdata = { 0 }; 1160 1161 wdata.qw = (uint8_t)data; 1162 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1163 } 1164 1165 static void 1166 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1167 { 1168 pci_cfg_data_t wdata = { 0 }; 1169 1170 wdata.qw = (uint16_t)data; 1171 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1172 } 1173 1174 static void 1175 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1176 { 1177 pci_cfg_data_t wdata = { 0 }; 1178 1179 wdata.qw = (uint32_t)data; 1180 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1181 } 1182 1183 static void 1184 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1185 { 1186 pci_cfg_data_t wdata = { 0 }; 1187 1188 wdata.qw = (uint32_t)(data & 0xffffffff); 1189 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1190 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1191 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1192 } 1193 1194 static void 1195 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1196 uint8_t *dev_addr, size_t repcount, uint_t flags) 1197 { 1198 if (flags == DDI_DEV_AUTOINCR) 1199 for (; repcount; repcount--) 1200 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1201 else 1202 for (; repcount; repcount--) 1203 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1204 } 1205 1206 /* 1207 * Function to rep read 16 bit data off the PCI configuration space behind 1208 * the 21554's host interface. 1209 */ 1210 static void 1211 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1212 uint16_t *dev_addr, size_t repcount, uint_t flags) 1213 { 1214 if (flags == DDI_DEV_AUTOINCR) 1215 for (; repcount; repcount--) 1216 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1217 else 1218 for (; repcount; repcount--) 1219 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1220 } 1221 1222 /* 1223 * Function to rep read 32 bit data off the PCI configuration space behind 1224 * the 21554's host interface. 1225 */ 1226 static void 1227 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1228 uint32_t *dev_addr, size_t repcount, uint_t flags) 1229 { 1230 if (flags == DDI_DEV_AUTOINCR) 1231 for (; repcount; repcount--) 1232 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1233 else 1234 for (; repcount; repcount--) 1235 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1236 } 1237 1238 /* 1239 * Function to rep read 64 bit data off the PCI configuration space behind 1240 * the 21554's host interface. 1241 */ 1242 static void 1243 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1244 uint64_t *dev_addr, size_t repcount, uint_t flags) 1245 { 1246 if (flags == DDI_DEV_AUTOINCR) 1247 for (; repcount; repcount--) 1248 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1249 else 1250 for (; repcount; repcount--) 1251 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1252 } 1253 1254 /* 1255 * Function to rep write 8 bit data into the PCI configuration space behind 1256 * the 21554's host interface. 1257 */ 1258 static void 1259 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1260 uint8_t *dev_addr, size_t repcount, uint_t flags) 1261 { 1262 if (flags == DDI_DEV_AUTOINCR) 1263 for (; repcount; repcount--) 1264 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1265 else 1266 for (; repcount; repcount--) 1267 px_pci_config_put8(handle, dev_addr, *host_addr++); 1268 } 1269 1270 /* 1271 * Function to rep write 16 bit data into the PCI configuration space behind 1272 * the 21554's host interface. 1273 */ 1274 static void 1275 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1276 uint16_t *dev_addr, size_t repcount, uint_t flags) 1277 { 1278 if (flags == DDI_DEV_AUTOINCR) 1279 for (; repcount; repcount--) 1280 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1281 else 1282 for (; repcount; repcount--) 1283 px_pci_config_put16(handle, dev_addr, *host_addr++); 1284 } 1285 1286 /* 1287 * Function to rep write 32 bit data into the PCI configuration space behind 1288 * the 21554's host interface. 1289 */ 1290 static void 1291 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1292 uint32_t *dev_addr, size_t repcount, uint_t flags) 1293 { 1294 if (flags == DDI_DEV_AUTOINCR) 1295 for (; repcount; repcount--) 1296 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1297 else 1298 for (; repcount; repcount--) 1299 px_pci_config_put32(handle, dev_addr, *host_addr++); 1300 } 1301 1302 /* 1303 * Function to rep write 64 bit data into the PCI configuration space behind 1304 * the 21554's host interface. 1305 */ 1306 static void 1307 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1308 uint64_t *dev_addr, size_t repcount, uint_t flags) 1309 { 1310 if (flags == DDI_DEV_AUTOINCR) 1311 for (; repcount; repcount--) 1312 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1313 else 1314 for (; repcount; repcount--) 1315 px_pci_config_put64(handle, dev_addr, *host_addr++); 1316 } 1317 1318 /* 1319 * Provide a private access handle to route config access calls to Hypervisor. 1320 * Beware: Do all error checking for config space accesses before calling 1321 * this function. ie. do error checking from the calling function. 1322 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1323 * DDI_SUCCESS from here makes the code organization readable/easier from 1324 * the generic code. 1325 */ 1326 /*ARGSUSED*/ 1327 int 1328 px_lib_map_vconfig(dev_info_t *dip, 1329 ddi_map_req_t *mp, pci_config_offset_t off, 1330 pci_regspec_t *rp, caddr_t *addrp) 1331 { 1332 ddi_acc_hdl_t *hp; 1333 ddi_acc_impl_t *ap; 1334 uchar_t busnum; /* bus number */ 1335 uchar_t devnum; /* device number */ 1336 uchar_t funcnum; /* function number */ 1337 px_config_acc_pvt_t *px_pvt; 1338 1339 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1340 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1341 1342 /* Check for mapping teardown operation */ 1343 if ((mp->map_op == DDI_MO_UNMAP) || 1344 (mp->map_op == DDI_MO_UNLOCK)) { 1345 /* free up memory allocated for the private access handle. */ 1346 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1347 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1348 1349 /* unmap operation of PCI IO/config space. */ 1350 return (DDI_SUCCESS); 1351 } 1352 1353 ap->ahi_get8 = px_pci_config_get8; 1354 ap->ahi_get16 = px_pci_config_get16; 1355 ap->ahi_get32 = px_pci_config_get32; 1356 ap->ahi_get64 = px_pci_config_get64; 1357 ap->ahi_put8 = px_pci_config_put8; 1358 ap->ahi_put16 = px_pci_config_put16; 1359 ap->ahi_put32 = px_pci_config_put32; 1360 ap->ahi_put64 = px_pci_config_put64; 1361 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1362 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1363 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1364 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1365 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1366 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1367 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1368 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1369 1370 /* Initialize to default check/notify functions */ 1371 ap->ahi_fault = 0; 1372 ap->ahi_fault_check = i_ddi_acc_fault_check; 1373 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1374 1375 /* allocate memory for our private handle */ 1376 px_pvt = (px_config_acc_pvt_t *) 1377 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1378 hp->ah_bus_private = (void *)px_pvt; 1379 1380 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1381 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1382 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1383 1384 /* set up private data for use during IO routines */ 1385 1386 /* addr needed by the HV APIs */ 1387 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1388 /* 1389 * Address that specifies the actual offset into the 256MB 1390 * memory mapped configuration space, 4K per device. 1391 * First 12bits form the offset into 4K config space. 1392 * This address is only used during the IO routines to calculate 1393 * the offset at which the transaction must be performed. 1394 * Drivers bypassing DDI functions to access PCI config space will 1395 * panic the system since the following is a bogus virtual address. 1396 */ 1397 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1398 px_pvt->dip = dip; 1399 1400 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1401 px_pvt->raddr, px_pvt->vaddr); 1402 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1403 return (DDI_SUCCESS); 1404 } 1405 1406 /*ARGSUSED*/ 1407 void 1408 px_lib_map_attr_check(ddi_map_req_t *mp) 1409 { 1410 } 1411 1412 /* 1413 * px_lib_log_safeacc_err: 1414 * Imitate a cpu/mem trap call when a peek/poke fails. 1415 * This will initiate something similar to px_fm_callback. 1416 */ 1417 static void 1418 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1419 { 1420 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1421 ddi_fm_error_t derr; 1422 1423 derr.fme_status = DDI_FM_NONFATAL; 1424 derr.fme_version = DDI_FME_VERSION; 1425 derr.fme_flag = fme_flag; 1426 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1427 derr.fme_acc_handle = handle; 1428 if (hp) 1429 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1430 1431 mutex_enter(&px_p->px_fm_mutex); 1432 1433 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1434 1435 mutex_exit(&px_p->px_fm_mutex); 1436 } 1437 1438 1439 #ifdef DEBUG 1440 int px_peekfault_cnt = 0; 1441 int px_pokefault_cnt = 0; 1442 #endif /* DEBUG */ 1443 1444 static int 1445 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1446 { 1447 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1448 pci_regspec_t regspec_array[8]; 1449 pci_regspec_t *regspec = regspec_array; 1450 int buflen = sizeof (regspec_array); 1451 boolean_t kmalloced = B_FALSE; 1452 int status; 1453 1454 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1455 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1456 1457 /* If need more space, fallback to kmem_alloc. */ 1458 if (status == DDI_PROP_BUF_TOO_SMALL) { 1459 regspec = kmem_alloc(buflen, KM_SLEEP); 1460 1461 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1462 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1463 1464 kmalloced = B_TRUE; 1465 } 1466 1467 /* Get phys_hi from first element. All have same bdf. */ 1468 if (status == DDI_PROP_SUCCESS) 1469 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1470 1471 if (kmalloced) 1472 kmem_free(regspec, buflen); 1473 1474 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1475 } 1476 1477 /* 1478 * Do a safe write to a device. 1479 * 1480 * When this function is given a handle (cautious access), all errors are 1481 * suppressed. 1482 * 1483 * When this function is not given a handle (poke), only Unsupported Request 1484 * and Completer Abort errors are suppressed. 1485 * 1486 * In all cases, all errors are returned in the function return status. 1487 */ 1488 1489 int 1490 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1491 peekpoke_ctlops_t *in_args) 1492 { 1493 px_t *px_p = DIP_TO_STATE(dip); 1494 px_pec_t *pec_p = px_p->px_pec_p; 1495 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1496 1497 size_t repcount = in_args->repcount; 1498 size_t size = in_args->size; 1499 uintptr_t dev_addr = in_args->dev_addr; 1500 uintptr_t host_addr = in_args->host_addr; 1501 1502 int err = DDI_SUCCESS; 1503 uint64_t hvio_poke_status; 1504 uint32_t bdf; 1505 uint32_t wrt_stat; 1506 1507 r_addr_t ra; 1508 uint64_t pokeval; 1509 1510 /* 1511 * Used only to notify error handling peek/poke is occuring 1512 * One scenario is when a fabric err as a result of peek/poke. 1513 * However there is no way to guarantee that the fabric error 1514 * handler will occur in the window where otd is set. 1515 */ 1516 on_trap_data_t otd; 1517 1518 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1519 DBG(DBG_LIB_DMA, px_p->px_dip, 1520 "poke: px_lib_bdf_from_dip failed\n"); 1521 err = DDI_FAILURE; 1522 goto done; 1523 } 1524 1525 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1526 for (; repcount; repcount--) { 1527 1528 switch (size) { 1529 case sizeof (uint8_t): 1530 pokeval = *(uint8_t *)host_addr; 1531 break; 1532 case sizeof (uint16_t): 1533 pokeval = *(uint16_t *)host_addr; 1534 break; 1535 case sizeof (uint32_t): 1536 pokeval = *(uint32_t *)host_addr; 1537 break; 1538 case sizeof (uint64_t): 1539 pokeval = *(uint64_t *)host_addr; 1540 break; 1541 default: 1542 DBG(DBG_MAP, px_p->px_dip, 1543 "poke: invalid size %d passed\n", size); 1544 err = DDI_FAILURE; 1545 goto done; 1546 } 1547 1548 /* 1549 * Grab pokefault mutex since hypervisor does not guarantee 1550 * poke serialization. 1551 */ 1552 if (hp) { 1553 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1554 (ddi_acc_handle_t)hp); 1555 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1556 } else { 1557 mutex_enter(&pec_p->pec_pokefault_mutex); 1558 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1559 } 1560 pec_p->pec_ontrap_data = &otd; 1561 1562 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1563 pokeval, bdf, &wrt_stat); 1564 1565 if (otd.ot_trap & OT_DATA_ACCESS) 1566 err = DDI_FAILURE; 1567 1568 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1569 err = DDI_FAILURE; 1570 #ifdef DEBUG 1571 px_pokefault_cnt++; 1572 #endif 1573 /* 1574 * For CAUTIOUS and POKE access, notify FMA to 1575 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1576 */ 1577 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1578 (hp ? DDI_FM_ERR_EXPECTED : 1579 DDI_FM_ERR_POKE)); 1580 1581 pec_p->pec_ontrap_data = NULL; 1582 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1583 if (hp) { 1584 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1585 (ddi_acc_handle_t)hp); 1586 } else { 1587 mutex_exit(&pec_p->pec_pokefault_mutex); 1588 } 1589 goto done; 1590 } 1591 1592 pec_p->pec_ontrap_data = NULL; 1593 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1594 if (hp) { 1595 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1596 (ddi_acc_handle_t)hp); 1597 } else { 1598 mutex_exit(&pec_p->pec_pokefault_mutex); 1599 } 1600 1601 host_addr += size; 1602 1603 if (in_args->flags == DDI_DEV_AUTOINCR) { 1604 dev_addr += size; 1605 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1606 } 1607 } 1608 1609 done: 1610 return (err); 1611 } 1612 1613 1614 /*ARGSUSED*/ 1615 int 1616 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1617 peekpoke_ctlops_t *in_args, void *result) 1618 { 1619 px_t *px_p = DIP_TO_STATE(dip); 1620 px_pec_t *pec_p = px_p->px_pec_p; 1621 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1622 1623 size_t repcount = in_args->repcount; 1624 uintptr_t dev_addr = in_args->dev_addr; 1625 uintptr_t host_addr = in_args->host_addr; 1626 1627 r_addr_t ra; 1628 uint32_t read_status; 1629 uint64_t hvio_peek_status; 1630 uint64_t peekval; 1631 int err = DDI_SUCCESS; 1632 1633 /* 1634 * Used only to notify error handling peek/poke is occuring 1635 * One scenario is when a fabric err as a result of peek/poke. 1636 * However there is no way to guarantee that the fabric error 1637 * handler will occur in the window where otd is set. 1638 */ 1639 on_trap_data_t otd; 1640 1641 result = (void *)in_args->host_addr; 1642 1643 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1644 for (; repcount; repcount--) { 1645 1646 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1647 if (hp) { 1648 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1649 (ddi_acc_handle_t)hp); 1650 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1651 } else { 1652 mutex_enter(&pec_p->pec_pokefault_mutex); 1653 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1654 } 1655 pec_p->pec_ontrap_data = &otd; 1656 1657 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1658 in_args->size, &read_status, &peekval); 1659 1660 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1661 err = DDI_FAILURE; 1662 1663 /* 1664 * For CAUTIOUS and PEEK access, notify FMA to 1665 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1666 */ 1667 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1668 (hp ? DDI_FM_ERR_EXPECTED : 1669 DDI_FM_ERR_PEEK)); 1670 1671 /* Stuff FFs in host addr if peek. */ 1672 if (hp == NULL) { 1673 int i; 1674 uint8_t *ff_addr = (uint8_t *)host_addr; 1675 for (i = 0; i < in_args->size; i++) 1676 *ff_addr++ = 0xff; 1677 } 1678 #ifdef DEBUG 1679 px_peekfault_cnt++; 1680 #endif 1681 pec_p->pec_ontrap_data = NULL; 1682 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1683 if (hp) { 1684 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1685 (ddi_acc_handle_t)hp); 1686 } else { 1687 mutex_exit(&pec_p->pec_pokefault_mutex); 1688 } 1689 goto done; 1690 1691 } 1692 pec_p->pec_ontrap_data = NULL; 1693 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1694 if (hp) { 1695 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1696 (ddi_acc_handle_t)hp); 1697 } else { 1698 mutex_exit(&pec_p->pec_pokefault_mutex); 1699 } 1700 1701 switch (in_args->size) { 1702 case sizeof (uint8_t): 1703 *(uint8_t *)host_addr = (uint8_t)peekval; 1704 break; 1705 case sizeof (uint16_t): 1706 *(uint16_t *)host_addr = (uint16_t)peekval; 1707 break; 1708 case sizeof (uint32_t): 1709 *(uint32_t *)host_addr = (uint32_t)peekval; 1710 break; 1711 case sizeof (uint64_t): 1712 *(uint64_t *)host_addr = (uint64_t)peekval; 1713 break; 1714 default: 1715 DBG(DBG_MAP, px_p->px_dip, 1716 "peek: invalid size %d passed\n", 1717 in_args->size); 1718 err = DDI_FAILURE; 1719 goto done; 1720 } 1721 1722 host_addr += in_args->size; 1723 1724 if (in_args->flags == DDI_DEV_AUTOINCR) { 1725 dev_addr += in_args->size; 1726 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1727 } 1728 } 1729 done: 1730 return (err); 1731 } 1732 1733 1734 /* add interrupt vector */ 1735 int 1736 px_err_add_intr(px_fault_t *px_fault_p) 1737 { 1738 int ret; 1739 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1740 1741 DBG(DBG_LIB_INT, px_p->px_dip, 1742 "px_err_add_intr: calling add_ivintr"); 1743 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1744 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1745 (caddr_t)&px_fault_p->px_intr_payload[0]); 1746 1747 if (ret != DDI_SUCCESS) { 1748 DBG(DBG_LIB_INT, px_p->px_dip, 1749 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1750 1751 return (ret); 1752 } 1753 DBG(DBG_LIB_INT, px_p->px_dip, 1754 "px_err_add_intr: ib_intr_enable "); 1755 1756 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1757 1758 return (ret); 1759 } 1760 1761 /* remove interrupt vector */ 1762 void 1763 px_err_rem_intr(px_fault_t *px_fault_p) 1764 { 1765 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1766 1767 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1768 IB_INTR_WAIT); 1769 1770 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1771 } 1772 1773 int 1774 px_cb_add_intr(px_fault_t *f_p) 1775 { 1776 return (px_err_add_intr(f_p)); 1777 } 1778 1779 void 1780 px_cb_rem_intr(px_fault_t *f_p) 1781 { 1782 px_err_rem_intr(f_p); 1783 } 1784 1785 void 1786 px_cb_intr_redist(px_t *px_p) 1787 { 1788 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1789 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1790 } 1791 1792 #ifdef FMA 1793 void 1794 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1795 { 1796 px_pec_err_t *err_pkt; 1797 1798 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1799 1800 /* initialise all the structure members */ 1801 rc_status->status_valid = 0; 1802 1803 if (err_pkt->pec_descr.P) { 1804 /* PCI Status Register */ 1805 rc_status->pci_err_status = err_pkt->pci_err_status; 1806 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1807 } 1808 1809 if (err_pkt->pec_descr.E) { 1810 /* PCIe Status Register */ 1811 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1812 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1813 } 1814 1815 if (err_pkt->pec_descr.U) { 1816 rc_status->ue_status = err_pkt->ue_reg_status; 1817 rc_status->status_valid |= UE_STATUS_VALID; 1818 } 1819 1820 if (err_pkt->pec_descr.H) { 1821 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1822 rc_status->status_valid |= UE_HDR1_VALID; 1823 } 1824 1825 if (err_pkt->pec_descr.I) { 1826 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1827 rc_status->status_valid |= UE_HDR2_VALID; 1828 } 1829 1830 /* ue_fst_err_ptr - not available for sun4v?? */ 1831 1832 1833 if (err_pkt->pec_descr.S) { 1834 rc_status->source_id = err_pkt->err_src_reg; 1835 rc_status->status_valid |= SOURCE_ID_VALID; 1836 } 1837 1838 if (err_pkt->pec_descr.R) { 1839 rc_status->root_err_status = err_pkt->root_err_status; 1840 rc_status->status_valid |= CE_STATUS_VALID; 1841 } 1842 } 1843 #endif 1844 1845 /*ARGSUSED*/ 1846 int 1847 px_lib_pmctl(int cmd, px_t *px_p) 1848 { 1849 return (DDI_FAILURE); 1850 } 1851 1852 /*ARGSUSED*/ 1853 uint_t 1854 px_pmeq_intr(caddr_t arg) 1855 { 1856 return (DDI_INTR_CLAIMED); 1857 } 1858 1859 /* 1860 * Unprotected raw reads/writes of fabric device's config space. 1861 * Only used for temporary PCI-E Fabric Error Handling. 1862 */ 1863 uint32_t 1864 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1865 uint32_t data = 0; 1866 1867 (void) hvio_config_get(px_p->px_dev_hdl, 1868 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1869 (pci_cfg_data_t *)&data); 1870 1871 return (data); 1872 } 1873 1874 void 1875 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1876 uint32_t val) { 1877 pci_cfg_data_t wdata = { 0 }; 1878 1879 wdata.qw = (uint32_t)val; 1880 (void) hvio_config_put(px_p->px_dev_hdl, 1881 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1882 } 1883 1884 /*ARGSUSED*/ 1885 int 1886 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1887 { 1888 return (DDI_ENOTSUP); 1889 } 1890 1891 /*ARGSUSED*/ 1892 void 1893 px_lib_hotplug_uninit(dev_info_t *dip) 1894 { 1895 } 1896 1897 /* Dummy cpr add callback */ 1898 /*ARGSUSED*/ 1899 void 1900 px_cpr_add_callb(px_t *px_p) 1901 { 1902 } 1903 1904 /* Dummy cpr rem callback */ 1905 /*ARGSUSED*/ 1906 void 1907 px_cpr_rem_callb(px_t *px_p) 1908 { 1909 } 1910