1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/ddi.h> 31 #include <sys/async.h> 32 #include <sys/sunddi.h> 33 #include <sys/ddifm.h> 34 #include <sys/fm/protocol.h> 35 #include <sys/vmem.h> 36 #include <sys/intr.h> 37 #include <sys/ivintr.h> 38 #include <sys/errno.h> 39 #include <sys/hypervisor_api.h> 40 #include <sys/hsvc.h> 41 #include <px_obj.h> 42 #include <sys/machsystm.h> 43 #include <sys/hotplug/pci/pcihp.h> 44 #include "px_lib4v.h" 45 #include "px_err.h" 46 47 /* mask for the ranges property in calculating the real PFN range */ 48 uint_t px_ranges_phi_mask = ((1 << 28) -1); 49 50 /* 51 * Hypervisor VPCI services information for the px nexus driver. 52 */ 53 static uint64_t px_vpci_min_ver; /* Negotiated VPCI API minor version */ 54 static uint_t px_vpci_users = 0; /* VPCI API users */ 55 56 static hsvc_info_t px_hsvc = { 57 HSVC_REV_1, NULL, HSVC_GROUP_VPCI, PX_VPCI_MAJOR_VER, 58 PX_VPCI_MINOR_VER, "PX" 59 }; 60 61 int 62 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 63 { 64 px_nexus_regspec_t *rp; 65 uint_t reglen; 66 int ret; 67 68 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69 70 ret = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 71 "reg", (uchar_t **)&rp, ®len); 72 if (ret != DDI_PROP_SUCCESS) { 73 DBG(DBG_ATTACH, dip, "px_lib_dev_init failed ret=%d\n", ret); 74 return (DDI_FAILURE); 75 } 76 77 /* 78 * Initilize device handle. The device handle uniquely identifies 79 * a SUN4V device. It consists of the lower 28-bits of the hi-cell 80 * of the first entry of the SUN4V device's "reg" property as 81 * defined by the SUN4V Bus Binding to Open Firmware. 82 */ 83 *dev_hdl = (devhandle_t)((rp->phys_addr >> 32) & DEVHDLE_MASK); 84 ddi_prop_free(rp); 85 86 /* 87 * hotplug implementation requires this property to be associated with 88 * any indirect PCI config access services 89 */ 90 (void) ddi_prop_update_int(makedevice(ddi_driver_major(dip), 91 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 92 PCI_BUS_CONF_MAP_PROP, 1); 93 94 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 95 96 /* 97 * Negotiate the API version for VPCI hypervisor services. 98 */ 99 if (px_vpci_users++) 100 return (DDI_SUCCESS); 101 102 if ((ret = hsvc_register(&px_hsvc, &px_vpci_min_ver)) != 0) { 103 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 104 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d\n", 105 px_hsvc.hsvc_modname, px_hsvc.hsvc_group, 106 px_hsvc.hsvc_major, px_hsvc.hsvc_minor, ret); 107 108 return (DDI_FAILURE); 109 } 110 111 DBG(DBG_ATTACH, dip, "px_lib_dev_init: negotiated VPCI API version, " 112 "major 0x%lx minor 0x%lx\n", px_hsvc.hsvc_major, px_vpci_min_ver); 113 114 return (DDI_SUCCESS); 115 } 116 117 /*ARGSUSED*/ 118 int 119 px_lib_dev_fini(dev_info_t *dip) 120 { 121 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 122 123 (void) ddi_prop_remove(makedevice(ddi_driver_major(dip), 124 PCIHP_AP_MINOR_NUM(ddi_get_instance(dip), PCIHP_DEVCTL_MINOR)), dip, 125 PCI_BUS_CONF_MAP_PROP); 126 127 if (--px_vpci_users == 0) 128 (void) hsvc_unregister(&px_hsvc); 129 130 return (DDI_SUCCESS); 131 } 132 133 /*ARGSUSED*/ 134 int 135 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 136 sysino_t *sysino) 137 { 138 uint64_t ret; 139 140 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 141 "devino 0x%x\n", dip, devino); 142 143 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 144 devino, sysino)) != H_EOK) { 145 DBG(DBG_LIB_INT, dip, 146 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 147 return (DDI_FAILURE); 148 } 149 150 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 151 *sysino); 152 153 return (DDI_SUCCESS); 154 } 155 156 /*ARGSUSED*/ 157 int 158 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 159 intr_valid_state_t *intr_valid_state) 160 { 161 uint64_t ret; 162 163 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 164 dip, sysino); 165 166 if ((ret = hvio_intr_getvalid(sysino, 167 (int *)intr_valid_state)) != H_EOK) { 168 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 169 ret); 170 return (DDI_FAILURE); 171 } 172 173 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 174 *intr_valid_state); 175 176 return (DDI_SUCCESS); 177 } 178 179 /*ARGSUSED*/ 180 int 181 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 182 intr_valid_state_t intr_valid_state) 183 { 184 uint64_t ret; 185 186 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 187 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 188 189 if ((ret = hvio_intr_setvalid(sysino, intr_valid_state)) != H_EOK) { 190 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 191 ret); 192 return (DDI_FAILURE); 193 } 194 195 return (DDI_SUCCESS); 196 } 197 198 /*ARGSUSED*/ 199 int 200 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 201 intr_state_t *intr_state) 202 { 203 uint64_t ret; 204 205 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 206 dip, sysino); 207 208 if ((ret = hvio_intr_getstate(sysino, (int *)intr_state)) != H_EOK) { 209 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 210 ret); 211 return (DDI_FAILURE); 212 } 213 214 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 215 *intr_state); 216 217 return (DDI_SUCCESS); 218 } 219 220 /*ARGSUSED*/ 221 int 222 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 223 intr_state_t intr_state) 224 { 225 uint64_t ret; 226 227 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 228 "intr_state 0x%x\n", dip, sysino, intr_state); 229 230 if ((ret = hvio_intr_setstate(sysino, intr_state)) != H_EOK) { 231 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 232 ret); 233 return (DDI_FAILURE); 234 } 235 236 return (DDI_SUCCESS); 237 } 238 239 /*ARGSUSED*/ 240 int 241 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 242 { 243 uint64_t ret; 244 245 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 246 dip, sysino); 247 248 if ((ret = hvio_intr_gettarget(sysino, cpuid)) != H_EOK) { 249 DBG(DBG_LIB_INT, dip, 250 "hvio_intr_gettarget failed, ret 0x%lx\n", ret); 251 return (DDI_FAILURE); 252 } 253 254 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 255 256 return (DDI_SUCCESS); 257 } 258 259 /*ARGSUSED*/ 260 int 261 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 262 { 263 uint64_t ret; 264 265 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 266 "cpuid 0x%x\n", dip, sysino, cpuid); 267 268 if ((ret = hvio_intr_settarget(sysino, cpuid)) != H_EOK) { 269 DBG(DBG_LIB_INT, dip, 270 "hvio_intr_settarget failed, ret 0x%lx\n", ret); 271 return (DDI_FAILURE); 272 } 273 274 return (DDI_SUCCESS); 275 } 276 277 /*ARGSUSED*/ 278 int 279 px_lib_intr_reset(dev_info_t *dip) 280 { 281 px_t *px_p = DIP_TO_STATE(dip); 282 px_ib_t *ib_p = px_p->px_ib_p; 283 px_ib_ino_info_t *ino_p; 284 285 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 286 287 mutex_enter(&ib_p->ib_ino_lst_mutex); 288 289 /* Reset all Interrupts */ 290 for (ino_p = ib_p->ib_ino_lst; ino_p; ino_p = ino_p->ino_next) { 291 if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 292 INTR_IDLE_STATE) != DDI_SUCCESS) 293 return (BF_FATAL); 294 } 295 296 mutex_exit(&ib_p->ib_ino_lst_mutex); 297 298 return (BF_NONE); 299 } 300 301 /*ARGSUSED*/ 302 int 303 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 304 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 305 { 306 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 307 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 308 io_page_list_t *pfns, *pfn_p; 309 pages_t ttes_mapped = 0; 310 int i, err = DDI_SUCCESS; 311 312 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 313 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 314 dip, tsbid, pages, attr, addr, pfn_index, flags); 315 316 if ((pfns = pfn_p = kmem_zalloc((pages * sizeof (io_page_list_t)), 317 KM_NOSLEEP)) == NULL) { 318 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: kmem_zalloc failed\n"); 319 return (DDI_FAILURE); 320 } 321 322 for (i = 0; i < pages; i++) 323 pfns[i] = MMU_PTOB(PX_ADDR2PFN(addr, pfn_index, flags, i)); 324 325 /* 326 * If HV VPCI version is 1.1 and higher, pass the BDF, phantom 327 * function, and relax ordering information. Otherwise, justp pass 328 * read or write attribute information. 329 */ 330 if (px_vpci_min_ver == PX_VPCI_MINOR_VER_0) 331 attr = attr & (PCI_MAP_ATTR_READ | PCI_MAP_ATTR_WRITE); 332 333 while ((ttes_mapped = pfn_p - pfns) < pages) { 334 uintptr_t ra = va_to_pa(pfn_p); 335 pages_t ttes2map; 336 uint64_t ret; 337 338 ttes2map = (MMU_PAGE_SIZE - P2PHASE(ra, MMU_PAGE_SIZE)) >> 3; 339 ra = MMU_PTOB(MMU_BTOP(ra)); 340 341 for (ttes2map = MIN(ttes2map, pages - ttes_mapped); ttes2map; 342 ttes2map -= ttes_mapped, pfn_p += ttes_mapped) { 343 344 ttes_mapped = 0; 345 if ((ret = hvio_iommu_map(DIP_TO_HANDLE(dip), 346 PCI_TSBID(tsb_num, tsb_index + (pfn_p - pfns)), 347 ttes2map, attr, (io_page_list_t *)(ra | 348 ((uintptr_t)pfn_p & MMU_PAGE_OFFSET)), 349 &ttes_mapped)) != H_EOK) { 350 DBG(DBG_LIB_DMA, dip, "hvio_iommu_map failed " 351 "ret 0x%lx\n", ret); 352 353 ttes_mapped = pfn_p - pfns; 354 err = DDI_FAILURE; 355 goto cleanup; 356 } 357 358 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: tsb_num 0x%x " 359 "tsb_index 0x%lx ttes_to_map 0x%lx attr 0x%x " 360 "ra 0x%p ttes_mapped 0x%x\n", tsb_num, 361 tsb_index + (pfn_p - pfns), ttes2map, attr, 362 ra | ((uintptr_t)pfn_p & MMU_PAGE_OFFSET), 363 ttes_mapped); 364 } 365 } 366 367 cleanup: 368 if ((err == DDI_FAILURE) && ttes_mapped) 369 (void) px_lib_iommu_demap(dip, tsbid, ttes_mapped); 370 371 kmem_free(pfns, pages * sizeof (io_page_list_t)); 372 return (err); 373 } 374 375 /*ARGSUSED*/ 376 int 377 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 378 { 379 tsbnum_t tsb_num = PCI_TSBID_TO_TSBNUM(tsbid); 380 tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 381 pages_t ttes2demap, ttes_demapped = 0; 382 uint64_t ret; 383 384 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 385 "pages 0x%x\n", dip, tsbid, pages); 386 387 for (ttes2demap = pages; ttes2demap; 388 ttes2demap -= ttes_demapped, tsb_index += ttes_demapped) { 389 if ((ret = hvio_iommu_demap(DIP_TO_HANDLE(dip), 390 PCI_TSBID(tsb_num, tsb_index), ttes2demap, 391 &ttes_demapped)) != H_EOK) { 392 DBG(DBG_LIB_DMA, dip, "hvio_iommu_demap failed, " 393 "ret 0x%lx\n", ret); 394 395 return (DDI_FAILURE); 396 } 397 398 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: tsb_num 0x%x " 399 "tsb_index 0x%lx ttes_to_demap 0x%lx ttes_demapped 0x%x\n", 400 tsb_num, tsb_index, ttes2demap, ttes_demapped); 401 } 402 403 return (DDI_SUCCESS); 404 } 405 406 /*ARGSUSED*/ 407 int 408 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 409 r_addr_t *r_addr_p) 410 { 411 uint64_t ret; 412 413 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 414 dip, tsbid); 415 416 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), tsbid, 417 attr_p, r_addr_p)) != H_EOK) { 418 DBG(DBG_LIB_DMA, dip, 419 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 420 421 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 422 } 423 424 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 425 *attr_p, *r_addr_p); 426 427 return (DDI_SUCCESS); 428 } 429 430 /*ARGSUSED*/ 431 uint64_t 432 px_get_rng_parent_hi_mask(px_t *px_p) 433 { 434 return (PX_RANGE_PROP_MASK); 435 } 436 437 /* 438 * Checks dma attributes against system bypass ranges 439 * A sun4v device must be capable of generating the entire 64-bit 440 * address in order to perform bypass DMA. 441 */ 442 /*ARGSUSED*/ 443 int 444 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 445 uint64_t *lo_p, uint64_t *hi_p) 446 { 447 if ((attr_p->dma_attr_addr_lo != 0ull) || 448 (attr_p->dma_attr_addr_hi != UINT64_MAX)) { 449 450 return (DDI_DMA_BADATTR); 451 } 452 453 *lo_p = 0ull; 454 *hi_p = UINT64_MAX; 455 456 return (DDI_SUCCESS); 457 } 458 459 460 /*ARGSUSED*/ 461 int 462 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 463 io_addr_t *io_addr_p) 464 { 465 uint64_t ret; 466 467 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 468 "attr 0x%x\n", dip, ra, attr); 469 470 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 471 attr, io_addr_p)) != H_EOK) { 472 DBG(DBG_LIB_DMA, dip, 473 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 474 return (ret == H_ENOTSUPPORTED ? DDI_ENOTSUP : DDI_FAILURE); 475 } 476 477 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 478 *io_addr_p); 479 480 return (DDI_SUCCESS); 481 } 482 483 /*ARGSUSED*/ 484 int 485 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 486 off_t off, size_t len, uint_t cache_flags) 487 { 488 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 489 uint64_t sync_dir; 490 px_dvma_addr_t dvma_addr, pg_off; 491 size_t num_sync; 492 uint64_t status = H_EOK; 493 494 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 495 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 496 dip, rdip, handle, off, len, cache_flags); 497 498 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 499 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 500 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 501 return (DDI_FAILURE); 502 } 503 504 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 505 return (DDI_SUCCESS); 506 507 if (!len) 508 len = mp->dmai_size; 509 510 pg_off = mp->dmai_offset; /* start min */ 511 dvma_addr = MAX(off, pg_off); /* lo */ 512 pg_off += mp->dmai_size; /* end max */ 513 pg_off = MIN(off + len, pg_off); /* hi */ 514 if (dvma_addr >= pg_off) { /* lo >= hi ? */ 515 cmn_err(CE_WARN, "%s%d: %lx + %lx out of window [%lx,%lx]", 516 ddi_driver_name(rdip), ddi_get_instance(rdip), 517 off, len, mp->dmai_offset, 518 mp->dmai_offset + mp->dmai_size); 519 return (DDI_FAILURE); 520 } 521 522 len = pg_off - dvma_addr; /* sz = hi - lo */ 523 dvma_addr += mp->dmai_mapping; /* start addr */ 524 525 if (mp->dmai_rflags & DDI_DMA_READ) 526 sync_dir = HVIO_DMA_SYNC_DIR_FROM_DEV; 527 else 528 sync_dir = HVIO_DMA_SYNC_DIR_TO_DEV; 529 530 for (; ((len > 0) && (status == H_EOK)); len -= num_sync) { 531 status = hvio_dma_sync(DIP_TO_HANDLE(dip), dvma_addr, len, 532 sync_dir, &num_sync); 533 dvma_addr += num_sync; 534 } 535 536 return ((status == H_EOK) ? DDI_SUCCESS : DDI_FAILURE); 537 } 538 539 540 /* 541 * MSIQ Functions: 542 */ 543 544 /*ARGSUSED*/ 545 int 546 px_lib_msiq_init(dev_info_t *dip) 547 { 548 px_t *px_p = DIP_TO_STATE(dip); 549 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 550 uint64_t *msiq_addr, ra; 551 size_t msiq_size; 552 uint_t rec_cnt; 553 int i, err = DDI_SUCCESS; 554 uint64_t ret; 555 556 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 557 558 msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 559 (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 560 561 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 562 563 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 564 ra = (r_addr_t)va_to_pa((caddr_t)msiq_addr + (i * msiq_size)); 565 566 if ((ret = hvio_msiq_conf(DIP_TO_HANDLE(dip), 567 (i + msiq_state_p->msiq_1st_msiq_id), 568 ra, msiq_state_p->msiq_rec_cnt)) != H_EOK) { 569 DBG(DBG_LIB_MSIQ, dip, 570 "hvio_msiq_conf failed, ret 0x%lx\n", ret); 571 err = DDI_FAILURE; 572 break; 573 } 574 575 if ((err = px_lib_msiq_info(dip, 576 (i + msiq_state_p->msiq_1st_msiq_id), 577 &ra, &rec_cnt)) != DDI_SUCCESS) { 578 DBG(DBG_LIB_MSIQ, dip, 579 "px_lib_msiq_info failed, ret 0x%x\n", err); 580 err = DDI_FAILURE; 581 break; 582 } 583 584 DBG(DBG_LIB_MSIQ, dip, 585 "px_lib_msiq_init: ra 0x%p rec_cnt 0x%x\n", ra, rec_cnt); 586 } 587 588 return (err); 589 } 590 591 /*ARGSUSED*/ 592 int 593 px_lib_msiq_fini(dev_info_t *dip) 594 { 595 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 596 597 return (DDI_SUCCESS); 598 } 599 600 /*ARGSUSED*/ 601 int 602 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 603 uint_t *msiq_rec_cnt_p) 604 { 605 uint64_t ret; 606 607 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 608 dip, msiq_id); 609 610 if ((ret = hvio_msiq_info(DIP_TO_HANDLE(dip), 611 msiq_id, ra_p, msiq_rec_cnt_p)) != H_EOK) { 612 DBG(DBG_LIB_MSIQ, dip, 613 "hvio_msiq_info failed, ret 0x%lx\n", ret); 614 return (DDI_FAILURE); 615 } 616 617 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 618 ra_p, *msiq_rec_cnt_p); 619 620 return (DDI_SUCCESS); 621 } 622 623 /*ARGSUSED*/ 624 int 625 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 626 pci_msiq_valid_state_t *msiq_valid_state) 627 { 628 uint64_t ret; 629 630 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 631 dip, msiq_id); 632 633 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 634 msiq_id, msiq_valid_state)) != H_EOK) { 635 DBG(DBG_LIB_MSIQ, dip, 636 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 637 return (DDI_FAILURE); 638 } 639 640 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 641 *msiq_valid_state); 642 643 return (DDI_SUCCESS); 644 } 645 646 /*ARGSUSED*/ 647 int 648 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 649 pci_msiq_valid_state_t msiq_valid_state) 650 { 651 uint64_t ret; 652 653 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 654 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 655 656 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 657 msiq_id, msiq_valid_state)) != H_EOK) { 658 DBG(DBG_LIB_MSIQ, dip, 659 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 660 return (DDI_FAILURE); 661 } 662 663 return (DDI_SUCCESS); 664 } 665 666 /*ARGSUSED*/ 667 int 668 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 669 pci_msiq_state_t *msiq_state) 670 { 671 uint64_t ret; 672 673 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 674 dip, msiq_id); 675 676 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 677 msiq_id, msiq_state)) != H_EOK) { 678 DBG(DBG_LIB_MSIQ, dip, 679 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 680 return (DDI_FAILURE); 681 } 682 683 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 684 *msiq_state); 685 686 return (DDI_SUCCESS); 687 } 688 689 /*ARGSUSED*/ 690 int 691 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 692 pci_msiq_state_t msiq_state) 693 { 694 uint64_t ret; 695 696 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 697 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 698 699 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 700 msiq_id, msiq_state)) != H_EOK) { 701 DBG(DBG_LIB_MSIQ, dip, 702 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 703 return (DDI_FAILURE); 704 } 705 706 return (DDI_SUCCESS); 707 } 708 709 /*ARGSUSED*/ 710 int 711 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 712 msiqhead_t *msiq_head_p) 713 { 714 uint64_t ret; 715 716 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 717 dip, msiq_id); 718 719 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 720 msiq_id, msiq_head_p)) != H_EOK) { 721 DBG(DBG_LIB_MSIQ, dip, 722 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 723 return (DDI_FAILURE); 724 } 725 726 *msiq_head_p = (*msiq_head_p / sizeof (msiq_rec_t)); 727 728 DBG(DBG_LIB_MSIQ, dip, "px_msiq_gethead: msiq_head 0x%x\n", 729 *msiq_head_p); 730 731 return (DDI_SUCCESS); 732 } 733 734 /*ARGSUSED*/ 735 int 736 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 737 msiqhead_t msiq_head) 738 { 739 uint64_t ret; 740 741 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 742 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 743 744 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 745 msiq_id, msiq_head * sizeof (msiq_rec_t))) != H_EOK) { 746 DBG(DBG_LIB_MSIQ, dip, 747 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 748 return (DDI_FAILURE); 749 } 750 751 return (DDI_SUCCESS); 752 } 753 754 /*ARGSUSED*/ 755 int 756 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 757 msiqtail_t *msiq_tail_p) 758 { 759 uint64_t ret; 760 761 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 762 dip, msiq_id); 763 764 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 765 msiq_id, msiq_tail_p)) != H_EOK) { 766 DBG(DBG_LIB_MSIQ, dip, 767 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 768 return (DDI_FAILURE); 769 } 770 771 *msiq_tail_p = (*msiq_tail_p / sizeof (msiq_rec_t)); 772 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 773 *msiq_tail_p); 774 775 return (DDI_SUCCESS); 776 } 777 778 /*ARGSUSED*/ 779 void 780 px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 781 { 782 msiq_rec_t *curr_msiq_rec_p = (msiq_rec_t *)msiq_p->msiq_curr; 783 784 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p\n", dip); 785 786 if (!curr_msiq_rec_p->msiq_rec_type) 787 return; 788 789 *msiq_rec_p = *curr_msiq_rec_p; 790 791 /* Zero out msiq_rec_type field */ 792 curr_msiq_rec_p->msiq_rec_type = 0; 793 } 794 795 /* 796 * MSI Functions: 797 */ 798 799 /*ARGSUSED*/ 800 int 801 px_lib_msi_init(dev_info_t *dip) 802 { 803 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 804 805 /* Noop */ 806 return (DDI_SUCCESS); 807 } 808 809 /*ARGSUSED*/ 810 int 811 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 812 msiqid_t *msiq_id) 813 { 814 uint64_t ret; 815 816 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 817 dip, msi_num); 818 819 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 820 msi_num, msiq_id)) != H_EOK) { 821 DBG(DBG_LIB_MSI, dip, 822 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 823 return (DDI_FAILURE); 824 } 825 826 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 827 *msiq_id); 828 829 return (DDI_SUCCESS); 830 } 831 832 /*ARGSUSED*/ 833 int 834 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 835 msiqid_t msiq_id, msi_type_t msitype) 836 { 837 uint64_t ret; 838 839 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 840 "msq_id 0x%x\n", dip, msi_num, msiq_id); 841 842 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 843 msi_num, msiq_id, msitype)) != H_EOK) { 844 DBG(DBG_LIB_MSI, dip, 845 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 846 return (DDI_FAILURE); 847 } 848 849 return (DDI_SUCCESS); 850 } 851 852 /*ARGSUSED*/ 853 int 854 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 855 pci_msi_valid_state_t *msi_valid_state) 856 { 857 uint64_t ret; 858 859 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 860 dip, msi_num); 861 862 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 863 msi_num, msi_valid_state)) != H_EOK) { 864 DBG(DBG_LIB_MSI, dip, 865 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 866 return (DDI_FAILURE); 867 } 868 869 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 870 *msi_valid_state); 871 872 return (DDI_SUCCESS); 873 } 874 875 /*ARGSUSED*/ 876 int 877 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 878 pci_msi_valid_state_t msi_valid_state) 879 { 880 uint64_t ret; 881 882 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 883 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 884 885 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 886 msi_num, msi_valid_state)) != H_EOK) { 887 DBG(DBG_LIB_MSI, dip, 888 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 889 return (DDI_FAILURE); 890 } 891 892 return (DDI_SUCCESS); 893 } 894 895 /*ARGSUSED*/ 896 int 897 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 898 pci_msi_state_t *msi_state) 899 { 900 uint64_t ret; 901 902 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 903 dip, msi_num); 904 905 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 906 msi_num, msi_state)) != H_EOK) { 907 DBG(DBG_LIB_MSI, dip, 908 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 909 return (DDI_FAILURE); 910 } 911 912 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 913 *msi_state); 914 915 return (DDI_SUCCESS); 916 } 917 918 /*ARGSUSED*/ 919 int 920 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 921 pci_msi_state_t msi_state) 922 { 923 uint64_t ret; 924 925 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 926 "msi_state 0x%x\n", dip, msi_num, msi_state); 927 928 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 929 msi_num, msi_state)) != H_EOK) { 930 DBG(DBG_LIB_MSI, dip, 931 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 932 return (DDI_FAILURE); 933 } 934 935 return (DDI_SUCCESS); 936 } 937 938 /* 939 * MSG Functions: 940 */ 941 942 /*ARGSUSED*/ 943 int 944 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 945 msiqid_t *msiq_id) 946 { 947 uint64_t ret; 948 949 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 950 dip, msg_type); 951 952 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 953 msg_type, msiq_id)) != H_EOK) { 954 DBG(DBG_LIB_MSG, dip, 955 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 956 return (DDI_FAILURE); 957 } 958 959 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 960 *msiq_id); 961 962 return (DDI_SUCCESS); 963 } 964 965 /*ARGSUSED*/ 966 int 967 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 968 msiqid_t msiq_id) 969 { 970 uint64_t ret; 971 972 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setmsiq: dip 0x%p msg_type 0x%x " 973 "msq_id 0x%x\n", dip, msg_type, msiq_id); 974 975 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 976 msg_type, msiq_id)) != H_EOK) { 977 DBG(DBG_LIB_MSG, dip, 978 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 979 return (DDI_FAILURE); 980 } 981 982 return (DDI_SUCCESS); 983 } 984 985 /*ARGSUSED*/ 986 int 987 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 988 pcie_msg_valid_state_t *msg_valid_state) 989 { 990 uint64_t ret; 991 992 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 993 dip, msg_type); 994 995 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 996 msg_valid_state)) != H_EOK) { 997 DBG(DBG_LIB_MSG, dip, 998 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 999 return (DDI_FAILURE); 1000 } 1001 1002 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1003 *msg_valid_state); 1004 1005 return (DDI_SUCCESS); 1006 } 1007 1008 /*ARGSUSED*/ 1009 int 1010 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1011 pcie_msg_valid_state_t msg_valid_state) 1012 { 1013 uint64_t ret; 1014 1015 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1016 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1017 1018 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1019 msg_valid_state)) != H_EOK) { 1020 DBG(DBG_LIB_MSG, dip, 1021 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1022 return (DDI_FAILURE); 1023 } 1024 1025 return (DDI_SUCCESS); 1026 } 1027 1028 /* 1029 * Suspend/Resume Functions: 1030 * Currently unsupported by hypervisor and all functions are noops. 1031 */ 1032 /*ARGSUSED*/ 1033 int 1034 px_lib_suspend(dev_info_t *dip) 1035 { 1036 DBG(DBG_ATTACH, dip, "px_lib_suspend: Not supported\n"); 1037 1038 /* Not supported */ 1039 return (DDI_FAILURE); 1040 } 1041 1042 /*ARGSUSED*/ 1043 void 1044 px_lib_resume(dev_info_t *dip) 1045 { 1046 DBG(DBG_ATTACH, dip, "px_lib_resume: Not supported\n"); 1047 1048 /* Noop */ 1049 } 1050 1051 /* 1052 * Misc Functions: 1053 * Currently unsupported by hypervisor and all functions are noops. 1054 */ 1055 /*ARGSUSED*/ 1056 static int 1057 px_lib_config_get(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1058 uint8_t size, pci_cfg_data_t *data_p) 1059 { 1060 uint64_t ret; 1061 1062 DBG(DBG_LIB_CFG, dip, "px_lib_config_get: dip 0x%p, bdf 0x%llx " 1063 "off 0x%x size 0x%x\n", dip, bdf, off, size); 1064 1065 if ((ret = hvio_config_get(DIP_TO_HANDLE(dip), bdf, off, 1066 size, data_p)) != H_EOK) { 1067 DBG(DBG_LIB_CFG, dip, 1068 "hvio_config_get failed, ret 0x%lx\n", ret); 1069 return (DDI_FAILURE); 1070 } 1071 DBG(DBG_LIB_CFG, dip, "px_config_get: data 0x%x\n", data_p->dw); 1072 1073 return (DDI_SUCCESS); 1074 } 1075 1076 /*ARGSUSED*/ 1077 static int 1078 px_lib_config_put(dev_info_t *dip, pci_device_t bdf, pci_config_offset_t off, 1079 uint8_t size, pci_cfg_data_t data) 1080 { 1081 uint64_t ret; 1082 1083 DBG(DBG_LIB_CFG, dip, "px_lib_config_put: dip 0x%p, bdf 0x%llx " 1084 "off 0x%x size 0x%x data 0x%llx\n", dip, bdf, off, size, data.qw); 1085 1086 if ((ret = hvio_config_put(DIP_TO_HANDLE(dip), bdf, off, 1087 size, data)) != H_EOK) { 1088 DBG(DBG_LIB_CFG, dip, 1089 "hvio_config_put failed, ret 0x%lx\n", ret); 1090 return (DDI_FAILURE); 1091 } 1092 1093 return (DDI_SUCCESS); 1094 } 1095 1096 static uint32_t 1097 px_pci_config_get(ddi_acc_impl_t *handle, uint32_t *addr, int size) 1098 { 1099 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1100 handle->ahi_common.ah_bus_private; 1101 uint32_t pci_dev_addr = px_pvt->raddr; 1102 uint32_t vaddr = px_pvt->vaddr; 1103 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1104 uint32_t rdata = 0; 1105 1106 if (px_lib_config_get(px_pvt->dip, pci_dev_addr, off, 1107 size, (pci_cfg_data_t *)&rdata) != DDI_SUCCESS) 1108 /* XXX update error kstats */ 1109 return (0xffffffff); 1110 return (rdata); 1111 } 1112 1113 static void 1114 px_pci_config_put(ddi_acc_impl_t *handle, uint32_t *addr, 1115 int size, pci_cfg_data_t wdata) 1116 { 1117 px_config_acc_pvt_t *px_pvt = (px_config_acc_pvt_t *) 1118 handle->ahi_common.ah_bus_private; 1119 uint32_t pci_dev_addr = px_pvt->raddr; 1120 uint32_t vaddr = px_pvt->vaddr; 1121 uint16_t off = (uint16_t)(uintptr_t)(addr - vaddr) & 0xfff; 1122 1123 if (px_lib_config_put(px_pvt->dip, pci_dev_addr, off, 1124 size, wdata) != DDI_SUCCESS) { 1125 /*EMPTY*/ 1126 /* XXX update error kstats */ 1127 } 1128 } 1129 1130 static uint8_t 1131 px_pci_config_get8(ddi_acc_impl_t *handle, uint8_t *addr) 1132 { 1133 return ((uint8_t)px_pci_config_get(handle, (uint32_t *)addr, 1)); 1134 } 1135 1136 static uint16_t 1137 px_pci_config_get16(ddi_acc_impl_t *handle, uint16_t *addr) 1138 { 1139 return ((uint16_t)px_pci_config_get(handle, (uint32_t *)addr, 2)); 1140 } 1141 1142 static uint32_t 1143 px_pci_config_get32(ddi_acc_impl_t *handle, uint32_t *addr) 1144 { 1145 return ((uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4)); 1146 } 1147 1148 static uint64_t 1149 px_pci_config_get64(ddi_acc_impl_t *handle, uint64_t *addr) 1150 { 1151 uint32_t rdatah, rdatal; 1152 1153 rdatal = (uint32_t)px_pci_config_get(handle, (uint32_t *)addr, 4); 1154 rdatah = (uint32_t)px_pci_config_get(handle, 1155 (uint32_t *)((char *)addr+4), 4); 1156 return (((uint64_t)rdatah << 32) | rdatal); 1157 } 1158 1159 static void 1160 px_pci_config_put8(ddi_acc_impl_t *handle, uint8_t *addr, uint8_t data) 1161 { 1162 pci_cfg_data_t wdata = { 0 }; 1163 1164 wdata.qw = (uint8_t)data; 1165 px_pci_config_put(handle, (uint32_t *)addr, 1, wdata); 1166 } 1167 1168 static void 1169 px_pci_config_put16(ddi_acc_impl_t *handle, uint16_t *addr, uint16_t data) 1170 { 1171 pci_cfg_data_t wdata = { 0 }; 1172 1173 wdata.qw = (uint16_t)data; 1174 px_pci_config_put(handle, (uint32_t *)addr, 2, wdata); 1175 } 1176 1177 static void 1178 px_pci_config_put32(ddi_acc_impl_t *handle, uint32_t *addr, uint32_t data) 1179 { 1180 pci_cfg_data_t wdata = { 0 }; 1181 1182 wdata.qw = (uint32_t)data; 1183 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1184 } 1185 1186 static void 1187 px_pci_config_put64(ddi_acc_impl_t *handle, uint64_t *addr, uint64_t data) 1188 { 1189 pci_cfg_data_t wdata = { 0 }; 1190 1191 wdata.qw = (uint32_t)(data & 0xffffffff); 1192 px_pci_config_put(handle, (uint32_t *)addr, 4, wdata); 1193 wdata.qw = (uint32_t)((data >> 32) & 0xffffffff); 1194 px_pci_config_put(handle, (uint32_t *)((char *)addr+4), 4, wdata); 1195 } 1196 1197 static void 1198 px_pci_config_rep_get8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1199 uint8_t *dev_addr, size_t repcount, uint_t flags) 1200 { 1201 if (flags == DDI_DEV_AUTOINCR) 1202 for (; repcount; repcount--) 1203 *host_addr++ = px_pci_config_get8(handle, dev_addr++); 1204 else 1205 for (; repcount; repcount--) 1206 *host_addr++ = px_pci_config_get8(handle, dev_addr); 1207 } 1208 1209 /* 1210 * Function to rep read 16 bit data off the PCI configuration space behind 1211 * the 21554's host interface. 1212 */ 1213 static void 1214 px_pci_config_rep_get16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1215 uint16_t *dev_addr, size_t repcount, uint_t flags) 1216 { 1217 if (flags == DDI_DEV_AUTOINCR) 1218 for (; repcount; repcount--) 1219 *host_addr++ = px_pci_config_get16(handle, dev_addr++); 1220 else 1221 for (; repcount; repcount--) 1222 *host_addr++ = px_pci_config_get16(handle, dev_addr); 1223 } 1224 1225 /* 1226 * Function to rep read 32 bit data off the PCI configuration space behind 1227 * the 21554's host interface. 1228 */ 1229 static void 1230 px_pci_config_rep_get32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1231 uint32_t *dev_addr, size_t repcount, uint_t flags) 1232 { 1233 if (flags == DDI_DEV_AUTOINCR) 1234 for (; repcount; repcount--) 1235 *host_addr++ = px_pci_config_get32(handle, dev_addr++); 1236 else 1237 for (; repcount; repcount--) 1238 *host_addr++ = px_pci_config_get32(handle, dev_addr); 1239 } 1240 1241 /* 1242 * Function to rep read 64 bit data off the PCI configuration space behind 1243 * the 21554's host interface. 1244 */ 1245 static void 1246 px_pci_config_rep_get64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1247 uint64_t *dev_addr, size_t repcount, uint_t flags) 1248 { 1249 if (flags == DDI_DEV_AUTOINCR) 1250 for (; repcount; repcount--) 1251 *host_addr++ = px_pci_config_get64(handle, dev_addr++); 1252 else 1253 for (; repcount; repcount--) 1254 *host_addr++ = px_pci_config_get64(handle, dev_addr); 1255 } 1256 1257 /* 1258 * Function to rep write 8 bit data into the PCI configuration space behind 1259 * the 21554's host interface. 1260 */ 1261 static void 1262 px_pci_config_rep_put8(ddi_acc_impl_t *handle, uint8_t *host_addr, 1263 uint8_t *dev_addr, size_t repcount, uint_t flags) 1264 { 1265 if (flags == DDI_DEV_AUTOINCR) 1266 for (; repcount; repcount--) 1267 px_pci_config_put8(handle, dev_addr++, *host_addr++); 1268 else 1269 for (; repcount; repcount--) 1270 px_pci_config_put8(handle, dev_addr, *host_addr++); 1271 } 1272 1273 /* 1274 * Function to rep write 16 bit data into the PCI configuration space behind 1275 * the 21554's host interface. 1276 */ 1277 static void 1278 px_pci_config_rep_put16(ddi_acc_impl_t *handle, uint16_t *host_addr, 1279 uint16_t *dev_addr, size_t repcount, uint_t flags) 1280 { 1281 if (flags == DDI_DEV_AUTOINCR) 1282 for (; repcount; repcount--) 1283 px_pci_config_put16(handle, dev_addr++, *host_addr++); 1284 else 1285 for (; repcount; repcount--) 1286 px_pci_config_put16(handle, dev_addr, *host_addr++); 1287 } 1288 1289 /* 1290 * Function to rep write 32 bit data into the PCI configuration space behind 1291 * the 21554's host interface. 1292 */ 1293 static void 1294 px_pci_config_rep_put32(ddi_acc_impl_t *handle, uint32_t *host_addr, 1295 uint32_t *dev_addr, size_t repcount, uint_t flags) 1296 { 1297 if (flags == DDI_DEV_AUTOINCR) 1298 for (; repcount; repcount--) 1299 px_pci_config_put32(handle, dev_addr++, *host_addr++); 1300 else 1301 for (; repcount; repcount--) 1302 px_pci_config_put32(handle, dev_addr, *host_addr++); 1303 } 1304 1305 /* 1306 * Function to rep write 64 bit data into the PCI configuration space behind 1307 * the 21554's host interface. 1308 */ 1309 static void 1310 px_pci_config_rep_put64(ddi_acc_impl_t *handle, uint64_t *host_addr, 1311 uint64_t *dev_addr, size_t repcount, uint_t flags) 1312 { 1313 if (flags == DDI_DEV_AUTOINCR) 1314 for (; repcount; repcount--) 1315 px_pci_config_put64(handle, dev_addr++, *host_addr++); 1316 else 1317 for (; repcount; repcount--) 1318 px_pci_config_put64(handle, dev_addr, *host_addr++); 1319 } 1320 1321 /* 1322 * Provide a private access handle to route config access calls to Hypervisor. 1323 * Beware: Do all error checking for config space accesses before calling 1324 * this function. ie. do error checking from the calling function. 1325 * Due to a lack of meaningful error code in DDI, the gauranteed return of 1326 * DDI_SUCCESS from here makes the code organization readable/easier from 1327 * the generic code. 1328 */ 1329 /*ARGSUSED*/ 1330 int 1331 px_lib_map_vconfig(dev_info_t *dip, 1332 ddi_map_req_t *mp, pci_config_offset_t off, 1333 pci_regspec_t *rp, caddr_t *addrp) 1334 { 1335 ddi_acc_hdl_t *hp; 1336 ddi_acc_impl_t *ap; 1337 uchar_t busnum; /* bus number */ 1338 uchar_t devnum; /* device number */ 1339 uchar_t funcnum; /* function number */ 1340 px_config_acc_pvt_t *px_pvt; 1341 1342 hp = (ddi_acc_hdl_t *)mp->map_handlep; 1343 ap = (ddi_acc_impl_t *)hp->ah_platform_private; 1344 1345 /* Check for mapping teardown operation */ 1346 if ((mp->map_op == DDI_MO_UNMAP) || 1347 (mp->map_op == DDI_MO_UNLOCK)) { 1348 /* free up memory allocated for the private access handle. */ 1349 px_pvt = (px_config_acc_pvt_t *)hp->ah_bus_private; 1350 kmem_free((void *)px_pvt, sizeof (px_config_acc_pvt_t)); 1351 1352 /* unmap operation of PCI IO/config space. */ 1353 return (DDI_SUCCESS); 1354 } 1355 1356 ap->ahi_get8 = px_pci_config_get8; 1357 ap->ahi_get16 = px_pci_config_get16; 1358 ap->ahi_get32 = px_pci_config_get32; 1359 ap->ahi_get64 = px_pci_config_get64; 1360 ap->ahi_put8 = px_pci_config_put8; 1361 ap->ahi_put16 = px_pci_config_put16; 1362 ap->ahi_put32 = px_pci_config_put32; 1363 ap->ahi_put64 = px_pci_config_put64; 1364 ap->ahi_rep_get8 = px_pci_config_rep_get8; 1365 ap->ahi_rep_get16 = px_pci_config_rep_get16; 1366 ap->ahi_rep_get32 = px_pci_config_rep_get32; 1367 ap->ahi_rep_get64 = px_pci_config_rep_get64; 1368 ap->ahi_rep_put8 = px_pci_config_rep_put8; 1369 ap->ahi_rep_put16 = px_pci_config_rep_put16; 1370 ap->ahi_rep_put32 = px_pci_config_rep_put32; 1371 ap->ahi_rep_put64 = px_pci_config_rep_put64; 1372 1373 /* Initialize to default check/notify functions */ 1374 ap->ahi_fault = 0; 1375 ap->ahi_fault_check = i_ddi_acc_fault_check; 1376 ap->ahi_fault_notify = i_ddi_acc_fault_notify; 1377 1378 /* allocate memory for our private handle */ 1379 px_pvt = (px_config_acc_pvt_t *) 1380 kmem_zalloc(sizeof (px_config_acc_pvt_t), KM_SLEEP); 1381 hp->ah_bus_private = (void *)px_pvt; 1382 1383 busnum = PCI_REG_BUS_G(rp->pci_phys_hi); 1384 devnum = PCI_REG_DEV_G(rp->pci_phys_hi); 1385 funcnum = PCI_REG_FUNC_G(rp->pci_phys_hi); 1386 1387 /* set up private data for use during IO routines */ 1388 1389 /* addr needed by the HV APIs */ 1390 px_pvt->raddr = busnum << 16 | devnum << 11 | funcnum << 8; 1391 /* 1392 * Address that specifies the actual offset into the 256MB 1393 * memory mapped configuration space, 4K per device. 1394 * First 12bits form the offset into 4K config space. 1395 * This address is only used during the IO routines to calculate 1396 * the offset at which the transaction must be performed. 1397 * Drivers bypassing DDI functions to access PCI config space will 1398 * panic the system since the following is a bogus virtual address. 1399 */ 1400 px_pvt->vaddr = busnum << 20 | devnum << 15 | funcnum << 12 | off; 1401 px_pvt->dip = dip; 1402 1403 DBG(DBG_LIB_CFG, dip, "px_config_setup: raddr 0x%x, vaddr 0x%x\n", 1404 px_pvt->raddr, px_pvt->vaddr); 1405 *addrp = (caddr_t)(uintptr_t)px_pvt->vaddr; 1406 return (DDI_SUCCESS); 1407 } 1408 1409 /*ARGSUSED*/ 1410 void 1411 px_lib_map_attr_check(ddi_map_req_t *mp) 1412 { 1413 } 1414 1415 /* 1416 * px_lib_log_safeacc_err: 1417 * Imitate a cpu/mem trap call when a peek/poke fails. 1418 * This will initiate something similar to px_fm_callback. 1419 */ 1420 static void 1421 px_lib_log_safeacc_err(px_t *px_p, ddi_acc_handle_t handle, int fme_flag) 1422 { 1423 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)handle; 1424 ddi_fm_error_t derr; 1425 1426 derr.fme_status = DDI_FM_NONFATAL; 1427 derr.fme_version = DDI_FME_VERSION; 1428 derr.fme_flag = fme_flag; 1429 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1430 derr.fme_acc_handle = handle; 1431 if (hp) 1432 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1433 1434 mutex_enter(&px_p->px_fm_mutex); 1435 1436 (void) ndi_fm_handler_dispatch(px_p->px_dip, NULL, &derr); 1437 1438 mutex_exit(&px_p->px_fm_mutex); 1439 } 1440 1441 1442 #ifdef DEBUG 1443 int px_peekfault_cnt = 0; 1444 int px_pokefault_cnt = 0; 1445 #endif /* DEBUG */ 1446 1447 static int 1448 px_lib_bdf_from_dip(dev_info_t *rdip, uint32_t *bdf) 1449 { 1450 /* Start with an array of 8 reg spaces for now to cover most devices. */ 1451 pci_regspec_t regspec_array[8]; 1452 pci_regspec_t *regspec = regspec_array; 1453 int buflen = sizeof (regspec_array); 1454 boolean_t kmalloced = B_FALSE; 1455 int status; 1456 1457 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1458 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1459 1460 /* If need more space, fallback to kmem_alloc. */ 1461 if (status == DDI_PROP_BUF_TOO_SMALL) { 1462 regspec = kmem_alloc(buflen, KM_SLEEP); 1463 1464 status = ddi_getlongprop_buf(DDI_DEV_T_ANY, rdip, 1465 DDI_PROP_DONTPASS, "reg", (caddr_t)regspec, &buflen); 1466 1467 kmalloced = B_TRUE; 1468 } 1469 1470 /* Get phys_hi from first element. All have same bdf. */ 1471 if (status == DDI_PROP_SUCCESS) 1472 *bdf = regspec->pci_phys_hi & (PCI_REG_BDFR_M ^ PCI_REG_REG_M); 1473 1474 if (kmalloced) 1475 kmem_free(regspec, buflen); 1476 1477 return ((status == DDI_PROP_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 1478 } 1479 1480 /* 1481 * Do a safe write to a device. 1482 * 1483 * When this function is given a handle (cautious access), all errors are 1484 * suppressed. 1485 * 1486 * When this function is not given a handle (poke), only Unsupported Request 1487 * and Completer Abort errors are suppressed. 1488 * 1489 * In all cases, all errors are returned in the function return status. 1490 */ 1491 1492 int 1493 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1494 peekpoke_ctlops_t *in_args) 1495 { 1496 px_t *px_p = DIP_TO_STATE(dip); 1497 px_pec_t *pec_p = px_p->px_pec_p; 1498 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1499 1500 size_t repcount = in_args->repcount; 1501 size_t size = in_args->size; 1502 uintptr_t dev_addr = in_args->dev_addr; 1503 uintptr_t host_addr = in_args->host_addr; 1504 1505 int err = DDI_SUCCESS; 1506 uint64_t hvio_poke_status; 1507 uint32_t bdf; 1508 uint32_t wrt_stat; 1509 1510 r_addr_t ra; 1511 uint64_t pokeval; 1512 1513 /* 1514 * Used only to notify error handling peek/poke is occuring 1515 * One scenario is when a fabric err as a result of peek/poke. 1516 * However there is no way to guarantee that the fabric error 1517 * handler will occur in the window where otd is set. 1518 */ 1519 on_trap_data_t otd; 1520 1521 if (px_lib_bdf_from_dip(rdip, &bdf) != DDI_SUCCESS) { 1522 DBG(DBG_LIB_DMA, px_p->px_dip, 1523 "poke: px_lib_bdf_from_dip failed\n"); 1524 err = DDI_FAILURE; 1525 goto done; 1526 } 1527 1528 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1529 for (; repcount; repcount--) { 1530 1531 switch (size) { 1532 case sizeof (uint8_t): 1533 pokeval = *(uint8_t *)host_addr; 1534 break; 1535 case sizeof (uint16_t): 1536 pokeval = *(uint16_t *)host_addr; 1537 break; 1538 case sizeof (uint32_t): 1539 pokeval = *(uint32_t *)host_addr; 1540 break; 1541 case sizeof (uint64_t): 1542 pokeval = *(uint64_t *)host_addr; 1543 break; 1544 default: 1545 DBG(DBG_MAP, px_p->px_dip, 1546 "poke: invalid size %d passed\n", size); 1547 err = DDI_FAILURE; 1548 goto done; 1549 } 1550 1551 /* 1552 * Grab pokefault mutex since hypervisor does not guarantee 1553 * poke serialization. 1554 */ 1555 if (hp) { 1556 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1557 (ddi_acc_handle_t)hp); 1558 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1559 } else { 1560 mutex_enter(&pec_p->pec_pokefault_mutex); 1561 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1562 } 1563 pec_p->pec_ontrap_data = &otd; 1564 1565 hvio_poke_status = hvio_poke(px_p->px_dev_hdl, ra, size, 1566 pokeval, bdf, &wrt_stat); 1567 1568 if (otd.ot_trap & OT_DATA_ACCESS) 1569 err = DDI_FAILURE; 1570 1571 if ((hvio_poke_status != H_EOK) || (wrt_stat != H_EOK)) { 1572 err = DDI_FAILURE; 1573 #ifdef DEBUG 1574 px_pokefault_cnt++; 1575 #endif 1576 /* 1577 * For CAUTIOUS and POKE access, notify FMA to 1578 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1579 */ 1580 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1581 (hp ? DDI_FM_ERR_EXPECTED : 1582 DDI_FM_ERR_POKE)); 1583 1584 pec_p->pec_ontrap_data = NULL; 1585 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1586 if (hp) { 1587 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1588 (ddi_acc_handle_t)hp); 1589 } else { 1590 mutex_exit(&pec_p->pec_pokefault_mutex); 1591 } 1592 goto done; 1593 } 1594 1595 pec_p->pec_ontrap_data = NULL; 1596 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1597 if (hp) { 1598 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1599 (ddi_acc_handle_t)hp); 1600 } else { 1601 mutex_exit(&pec_p->pec_pokefault_mutex); 1602 } 1603 1604 host_addr += size; 1605 1606 if (in_args->flags == DDI_DEV_AUTOINCR) { 1607 dev_addr += size; 1608 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1609 } 1610 } 1611 1612 done: 1613 return (err); 1614 } 1615 1616 1617 /*ARGSUSED*/ 1618 int 1619 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1620 peekpoke_ctlops_t *in_args, void *result) 1621 { 1622 px_t *px_p = DIP_TO_STATE(dip); 1623 px_pec_t *pec_p = px_p->px_pec_p; 1624 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)in_args->handle; 1625 1626 size_t repcount = in_args->repcount; 1627 uintptr_t dev_addr = in_args->dev_addr; 1628 uintptr_t host_addr = in_args->host_addr; 1629 1630 r_addr_t ra; 1631 uint32_t read_status; 1632 uint64_t hvio_peek_status; 1633 uint64_t peekval; 1634 int err = DDI_SUCCESS; 1635 1636 /* 1637 * Used only to notify error handling peek/poke is occuring 1638 * One scenario is when a fabric err as a result of peek/poke. 1639 * However there is no way to guarantee that the fabric error 1640 * handler will occur in the window where otd is set. 1641 */ 1642 on_trap_data_t otd; 1643 1644 result = (void *)in_args->host_addr; 1645 1646 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1647 for (; repcount; repcount--) { 1648 1649 /* Lock pokefault mutex so read doesn't mask a poke fault. */ 1650 if (hp) { 1651 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, 1652 (ddi_acc_handle_t)hp); 1653 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1654 } else { 1655 mutex_enter(&pec_p->pec_pokefault_mutex); 1656 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1657 } 1658 pec_p->pec_ontrap_data = &otd; 1659 1660 hvio_peek_status = hvio_peek(px_p->px_dev_hdl, ra, 1661 in_args->size, &read_status, &peekval); 1662 1663 if ((hvio_peek_status != H_EOK) || (read_status != H_EOK)) { 1664 err = DDI_FAILURE; 1665 1666 /* 1667 * For CAUTIOUS and PEEK access, notify FMA to 1668 * cleanup. Imitate a cpu/mem trap call like in sun4u. 1669 */ 1670 px_lib_log_safeacc_err(px_p, (ddi_acc_handle_t)hp, 1671 (hp ? DDI_FM_ERR_EXPECTED : 1672 DDI_FM_ERR_PEEK)); 1673 1674 /* Stuff FFs in host addr if peek. */ 1675 if (hp == NULL) { 1676 int i; 1677 uint8_t *ff_addr = (uint8_t *)host_addr; 1678 for (i = 0; i < in_args->size; i++) 1679 *ff_addr++ = 0xff; 1680 } 1681 #ifdef DEBUG 1682 px_peekfault_cnt++; 1683 #endif 1684 pec_p->pec_ontrap_data = NULL; 1685 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1686 if (hp) { 1687 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1688 (ddi_acc_handle_t)hp); 1689 } else { 1690 mutex_exit(&pec_p->pec_pokefault_mutex); 1691 } 1692 goto done; 1693 1694 } 1695 pec_p->pec_ontrap_data = NULL; 1696 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1697 if (hp) { 1698 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, 1699 (ddi_acc_handle_t)hp); 1700 } else { 1701 mutex_exit(&pec_p->pec_pokefault_mutex); 1702 } 1703 1704 switch (in_args->size) { 1705 case sizeof (uint8_t): 1706 *(uint8_t *)host_addr = (uint8_t)peekval; 1707 break; 1708 case sizeof (uint16_t): 1709 *(uint16_t *)host_addr = (uint16_t)peekval; 1710 break; 1711 case sizeof (uint32_t): 1712 *(uint32_t *)host_addr = (uint32_t)peekval; 1713 break; 1714 case sizeof (uint64_t): 1715 *(uint64_t *)host_addr = (uint64_t)peekval; 1716 break; 1717 default: 1718 DBG(DBG_MAP, px_p->px_dip, 1719 "peek: invalid size %d passed\n", 1720 in_args->size); 1721 err = DDI_FAILURE; 1722 goto done; 1723 } 1724 1725 host_addr += in_args->size; 1726 1727 if (in_args->flags == DDI_DEV_AUTOINCR) { 1728 dev_addr += in_args->size; 1729 ra = (r_addr_t)va_to_pa((void *)dev_addr); 1730 } 1731 } 1732 done: 1733 return (err); 1734 } 1735 1736 1737 /* add interrupt vector */ 1738 int 1739 px_err_add_intr(px_fault_t *px_fault_p) 1740 { 1741 int ret; 1742 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1743 1744 DBG(DBG_LIB_INT, px_p->px_dip, 1745 "px_err_add_intr: calling add_ivintr"); 1746 ret = add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1747 px_fault_p->px_err_func, (caddr_t)px_fault_p, 1748 (caddr_t)&px_fault_p->px_intr_payload[0]); 1749 1750 if (ret != DDI_SUCCESS) { 1751 DBG(DBG_LIB_INT, px_p->px_dip, 1752 "add_ivintr returns %d, faultp: %p", ret, px_fault_p); 1753 1754 return (ret); 1755 } 1756 DBG(DBG_LIB_INT, px_p->px_dip, 1757 "px_err_add_intr: ib_intr_enable "); 1758 1759 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1760 1761 return (ret); 1762 } 1763 1764 /* remove interrupt vector */ 1765 void 1766 px_err_rem_intr(px_fault_t *px_fault_p) 1767 { 1768 px_t *px_p = DIP_TO_STATE(px_fault_p->px_fh_dip); 1769 1770 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 1771 IB_INTR_WAIT); 1772 1773 rem_ivintr(px_fault_p->px_fh_sysino, NULL); 1774 } 1775 1776 int 1777 px_cb_add_intr(px_fault_t *f_p) 1778 { 1779 return (px_err_add_intr(f_p)); 1780 } 1781 1782 void 1783 px_cb_rem_intr(px_fault_t *f_p) 1784 { 1785 px_err_rem_intr(f_p); 1786 } 1787 1788 void 1789 px_cb_intr_redist(px_t *px_p) 1790 { 1791 px_ib_intr_dist_en(px_p->px_dip, intr_dist_cpuid(), 1792 px_p->px_inos[PX_INTR_XBC], B_FALSE); 1793 } 1794 1795 #ifdef FMA 1796 void 1797 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 1798 { 1799 px_pec_err_t *err_pkt; 1800 1801 err_pkt = (px_pec_err_t *)px_fault_p->px_intr_payload; 1802 1803 /* initialise all the structure members */ 1804 rc_status->status_valid = 0; 1805 1806 if (err_pkt->pec_descr.P) { 1807 /* PCI Status Register */ 1808 rc_status->pci_err_status = err_pkt->pci_err_status; 1809 rc_status->status_valid |= PCI_ERR_STATUS_VALID; 1810 } 1811 1812 if (err_pkt->pec_descr.E) { 1813 /* PCIe Status Register */ 1814 rc_status->pcie_err_status = err_pkt->pcie_err_status; 1815 rc_status->status_valid |= PCIE_ERR_STATUS_VALID; 1816 } 1817 1818 if (err_pkt->pec_descr.U) { 1819 rc_status->ue_status = err_pkt->ue_reg_status; 1820 rc_status->status_valid |= UE_STATUS_VALID; 1821 } 1822 1823 if (err_pkt->pec_descr.H) { 1824 rc_status->ue_hdr1 = err_pkt->hdr[0]; 1825 rc_status->status_valid |= UE_HDR1_VALID; 1826 } 1827 1828 if (err_pkt->pec_descr.I) { 1829 rc_status->ue_hdr2 = err_pkt->hdr[1]; 1830 rc_status->status_valid |= UE_HDR2_VALID; 1831 } 1832 1833 /* ue_fst_err_ptr - not available for sun4v?? */ 1834 1835 1836 if (err_pkt->pec_descr.S) { 1837 rc_status->source_id = err_pkt->err_src_reg; 1838 rc_status->status_valid |= SOURCE_ID_VALID; 1839 } 1840 1841 if (err_pkt->pec_descr.R) { 1842 rc_status->root_err_status = err_pkt->root_err_status; 1843 rc_status->status_valid |= CE_STATUS_VALID; 1844 } 1845 } 1846 #endif 1847 1848 /*ARGSUSED*/ 1849 int 1850 px_lib_pmctl(int cmd, px_t *px_p) 1851 { 1852 return (DDI_FAILURE); 1853 } 1854 1855 /*ARGSUSED*/ 1856 uint_t 1857 px_pmeq_intr(caddr_t arg) 1858 { 1859 return (DDI_INTR_CLAIMED); 1860 } 1861 1862 /* 1863 * Unprotected raw reads/writes of fabric device's config space. 1864 * Only used for temporary PCI-E Fabric Error Handling. 1865 */ 1866 uint32_t 1867 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) { 1868 uint32_t data = 0; 1869 1870 (void) hvio_config_get(px_p->px_dev_hdl, 1871 (bdf << PX_RA_BDF_SHIFT), offset, 4, 1872 (pci_cfg_data_t *)&data); 1873 1874 return (data); 1875 } 1876 1877 void 1878 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 1879 uint32_t val) { 1880 pci_cfg_data_t wdata = { 0 }; 1881 1882 wdata.qw = (uint32_t)val; 1883 (void) hvio_config_put(px_p->px_dev_hdl, 1884 (bdf << PX_RA_BDF_SHIFT), offset, 4, wdata); 1885 } 1886 1887 /*ARGSUSED*/ 1888 int 1889 px_lib_hotplug_init(dev_info_t *dip, void *arg) 1890 { 1891 return (DDI_ENOTSUP); 1892 } 1893 1894 /*ARGSUSED*/ 1895 void 1896 px_lib_hotplug_uninit(dev_info_t *dip) 1897 { 1898 } 1899 1900 /* Dummy cpr add callback */ 1901 /*ARGSUSED*/ 1902 void 1903 px_cpr_add_callb(px_t *px_p) 1904 { 1905 } 1906 1907 /* Dummy cpr rem callback */ 1908 /*ARGSUSED*/ 1909 void 1910 px_cpr_rem_callb(px_t *px_p) 1911 { 1912 } 1913 1914 /*ARGSUSED*/ 1915 boolean_t 1916 px_lib_is_in_drain_state(px_t *px_p) 1917 { 1918 return (B_FALSE); 1919 } 1920