1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27/* 28 * Hypervisor calls called by px nexus driver. 29*/ 30 31#include <sys/asm_linkage.h> 32#include <sys/hypervisor_api.h> 33#include <sys/dditypes.h> 34#include <px_ioapi.h> 35#include "px_lib4v.h" 36 37#if defined(lint) || defined(__lint) 38 39/*ARGSUSED*/ 40uint64_t 41hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 42 pci_config_size_t size, pci_cfg_data_t *data_p) 43{ return (0); } 44 45/*ARGSUSED*/ 46uint64_t 47hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 48 pci_config_size_t size, pci_cfg_data_t data) 49{ return (0); } 50 51/*ARGSUSED*/ 52uint64_t 53hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 54 io_attributes_t attr, io_page_list_t *io_page_list_p, 55 pages_t *pages_mapped) 56{ return (0); } 57 58/*ARGSUSED*/ 59uint64_t 60hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 61 pages_t *pages_demapped) 62{ return (0); } 63 64/*ARGSUSED*/ 65uint64_t 66hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p, 67 r_addr_t *r_addr_p) 68{ return (0); } 69 70/*ARGSUSED*/ 71uint64_t 72hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr, 73 io_addr_t *io_addr_p) 74{ return (0); } 75 76/*ARGSUSED*/ 77uint64_t 78hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, 79 uint64_t *data_p) 80{ return (0); } 81 82/*ARGSUSED*/ 83uint64_t 84hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, 85 r_addr_t ra2, uint32_t *rdbk_status) 86{ return (0); } 87 88/*ARGSUSED*/ 89uint64_t 90hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, 91 io_sync_direction_t io_sync_direction, size_t *bytes_synched) 92{ return (0); } 93 94/*ARGSUSED*/ 95uint64_t 96hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, 97 uint_t msiq_rec_cnt) 98{ return (0); } 99 100/*ARGSUSED*/ 101uint64_t 102hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, 103 uint_t *msiq_rec_cnt_p) 104{ return (0); } 105 106/*ARGSUSED*/ 107uint64_t 108hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 109 pci_msiq_valid_state_t *msiq_valid_state) 110{ return (0); } 111 112/*ARGSUSED*/ 113uint64_t 114hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 115 pci_msiq_valid_state_t msiq_valid_state) 116{ return (0); } 117 118/*ARGSUSED*/ 119uint64_t 120hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 121 pci_msiq_state_t *msiq_state) 122{ return (0); } 123 124/*ARGSUSED*/ 125uint64_t 126hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 127 pci_msiq_state_t msiq_state) 128{ return (0); } 129 130/*ARGSUSED*/ 131uint64_t 132hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 133 msiqhead_t *msiq_head) 134{ return (0); } 135 136/*ARGSUSED*/ 137uint64_t 138hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 139 msiqhead_t msiq_head) 140{ return (0); } 141 142/*ARGSUSED*/ 143uint64_t 144hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 145 msiqtail_t *msiq_tail) 146{ return (0); } 147 148/*ARGSUSED*/ 149uint64_t 150hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 151 msiqid_t *msiq_id) 152{ return (0); } 153 154/*ARGSUSED*/ 155uint64_t 156hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 157 msiqid_t msiq_id, msi_type_t msitype) 158{ return (0); } 159 160/*ARGSUSED*/ 161uint64_t 162hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 163 pci_msi_valid_state_t *msi_valid_state) 164{ return (0); } 165 166/*ARGSUSED*/ 167uint64_t 168hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 169 pci_msi_valid_state_t msi_valid_state) 170{ return (0); } 171 172/*ARGSUSED*/ 173uint64_t 174hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 175 pci_msi_state_t *msi_state) 176{ return (0); } 177 178/*ARGSUSED*/ 179uint64_t 180hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 181 pci_msi_state_t msi_state) 182{ return (0); } 183 184/*ARGSUSED*/ 185uint64_t 186hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 187 msiqid_t *msiq_id) 188{ return (0); } 189 190/*ARGSUSED*/ 191uint64_t 192hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 193 msiqid_t msiq_id) 194{ return (0); } 195 196/*ARGSUSED*/ 197uint64_t 198hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 199 pcie_msg_valid_state_t *msg_valid_state) 200{ return (0); } 201 202/*ARGSUSED*/ 203uint64_t 204hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 205 pcie_msg_valid_state_t msg_valid_state) 206{ return (0); } 207 208/* 209 * First arg to both of these functions is a dummy, to accomodate how 210 * hv_hpriv() works. 211 */ 212/*ARGSUSED*/ 213int 214px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr) 215{ return (0); } 216 217#else /* lint || __lint */ 218 219 /* 220 * arg0 - devhandle 221 * arg1 - pci_device 222 * arg2 - pci_config_offset 223 * arg3 - pci_config_size 224 * 225 * ret0 - status 226 * ret1 - error_flag 227 * ret2 - pci_cfg_data 228 */ 229 ENTRY(hvio_config_get) 230 mov HVIO_CONFIG_GET, %o5 231 ta FAST_TRAP 232 brnz %o0, 1f 233 movrnz %o1, -1, %o2 234 brz,a %o1, 1f 235 stuw %o2, [%o4] 2361: retl 237 nop 238 SET_SIZE(hvio_config_get) 239 240 /* 241 * arg0 - devhandle 242 * arg1 - pci_device 243 * arg2 - pci_config_offset 244 * arg3 - pci_config_size 245 * arg4 - pci_cfg_data 246 * 247 * ret0 - status 248 * ret1 - error_flag 249 */ 250 ENTRY(hvio_config_put) 251 mov HVIO_CONFIG_PUT, %o5 252 ta FAST_TRAP 253 retl 254 nop 255 SET_SIZE(hvio_config_put) 256 257 /* 258 * arg0 - devhandle 259 * arg1 - tsbid 260 * arg2 - pages 261 * arg3 - io_attributes 262 * arg4 - io_page_list_p 263 * 264 * ret1 - pages_mapped 265 */ 266 ENTRY(hvio_iommu_map) 267 save %sp, -SA(MINFRAME64), %sp 268 mov %i0, %o0 269 mov %i1, %o1 270 mov %i2, %o2 271 mov %i3, %o3 272 mov %i4, %o4 273 mov HVIO_IOMMU_MAP, %o5 274 ta FAST_TRAP 275 brnz %o0, 1f 276 mov %o0, %i0 277 stuw %o1, [%i5] 2781: 279 ret 280 restore 281 SET_SIZE(hvio_iommu_map) 282 283 /* 284 * arg0 - devhandle 285 * arg1 - tsbid 286 * arg2 - pages 287 * 288 * ret1 - pages_demapped 289 */ 290 ENTRY(hvio_iommu_demap) 291 mov HVIO_IOMMU_DEMAP, %o5 292 ta FAST_TRAP 293 brz,a %o0, 1f 294 stuw %o1, [%o3] 2951: retl 296 nop 297 SET_SIZE(hvio_iommu_demap) 298 299 /* 300 * arg0 - devhandle 301 * arg1 - tsbid 302 * 303 * 304 * ret0 - status 305 * ret1 - io_attributes 306 * ret2 - r_addr 307 */ 308 ENTRY(hvio_iommu_getmap) 309 mov %o2, %o4 310 mov HVIO_IOMMU_GETMAP, %o5 311 ta FAST_TRAP 312 brnz %o0, 1f 313 nop 314 stx %o2, [%o3] 315 st %o1, [%o4] 3161: 317 retl 318 nop 319 SET_SIZE(hvio_iommu_getmap) 320 321 /* 322 * arg0 - devhandle 323 * arg1 - r_addr 324 * arg2 - io_attributes 325 * 326 * 327 * ret0 - status 328 * ret1 - io_addr 329 */ 330 ENTRY(hvio_iommu_getbypass) 331 mov HVIO_IOMMU_GETBYPASS, %o5 332 ta FAST_TRAP 333 brz,a %o0, 1f 334 stx %o1, [%o3] 3351: retl 336 nop 337 SET_SIZE(hvio_iommu_getbypass) 338 339 /* 340 * arg0 - devhandle 341 * arg1 - r_addr 342 * arg2 - size 343 * 344 * ret1 - error_flag 345 * ret2 - data 346 */ 347 ENTRY(hvio_peek) 348 mov HVIO_PEEK, %o5 349 ta FAST_TRAP 350 brnz %o0, 1f 351 nop 352 stx %o2, [%o4] 353 st %o1, [%o3] 3541: 355 retl 356 nop 357 SET_SIZE(hvio_peek) 358 359 /* 360 * arg0 - devhandle 361 * arg1 - r_addr 362 * arg2 - sizes 363 * arg3 - data 364 * arg4 - r_addr2 365 * 366 * ret1 - error_flag 367 */ 368 ENTRY(hvio_poke) 369 save %sp, -SA(MINFRAME64), %sp 370 mov %i0, %o0 371 mov %i1, %o1 372 mov %i2, %o2 373 mov %i3, %o3 374 mov %i4, %o4 375 mov HVIO_POKE, %o5 376 ta FAST_TRAP 377 brnz %o0, 1f 378 mov %o0, %i0 379 stuw %o1, [%i5] 3801: 381 ret 382 restore 383 SET_SIZE(hvio_poke) 384 385 /* 386 * arg0 - devhandle 387 * arg1 - r_addr 388 * arg2 - num_bytes 389 * arg3 - io_sync_direction 390 * 391 * ret0 - status 392 * ret1 - bytes_synched 393 */ 394 ENTRY(hvio_dma_sync) 395 mov HVIO_DMA_SYNC, %o5 396 ta FAST_TRAP 397 brz,a %o0, 1f 398 stx %o1, [%o4] 3991: retl 400 nop 401 SET_SIZE(hvio_dma_sync) 402 403 /* 404 * arg0 - devhandle 405 * arg1 - msiq_id 406 * arg2 - r_addr 407 * arg3 - nentries 408 * 409 * ret0 - status 410 */ 411 ENTRY(hvio_msiq_conf) 412 mov HVIO_MSIQ_CONF, %o5 413 ta FAST_TRAP 414 retl 415 nop 416 SET_SIZE(hvio_msiq_conf) 417 418 /* 419 * arg0 - devhandle 420 * arg1 - msiq_id 421 * 422 * ret0 - status 423 * ret1 - r_addr 424 * ret1 - nentries 425 */ 426 ENTRY(hvio_msiq_info) 427 mov %o2, %o4 428 mov HVIO_MSIQ_INFO, %o5 429 ta FAST_TRAP 430 brnz %o0, 1f 431 nop 432 stx %o1, [%o4] 433 stuw %o2, [%o3] 4341: retl 435 nop 436 SET_SIZE(hvio_msiq_info) 437 438 /* 439 * arg0 - devhandle 440 * arg1 - msiq_id 441 * 442 * ret0 - status 443 * ret1 - msiq_valid_state 444 */ 445 ENTRY(hvio_msiq_getvalid) 446 mov HVIO_MSIQ_GETVALID, %o5 447 ta FAST_TRAP 448 brz,a %o0, 1f 449 stuw %o1, [%o2] 4501: retl 451 nop 452 SET_SIZE(hvio_msiq_getvalid) 453 454 /* 455 * arg0 - devhandle 456 * arg1 - msiq_id 457 * arg2 - msiq_valid_state 458 * 459 * ret0 - status 460 */ 461 ENTRY(hvio_msiq_setvalid) 462 mov HVIO_MSIQ_SETVALID, %o5 463 ta FAST_TRAP 464 retl 465 nop 466 SET_SIZE(hvio_msiq_setvalid) 467 468 /* 469 * arg0 - devhandle 470 * arg1 - msiq_id 471 * 472 * ret0 - status 473 * ret1 - msiq_state 474 */ 475 ENTRY(hvio_msiq_getstate) 476 mov HVIO_MSIQ_GETSTATE, %o5 477 ta FAST_TRAP 478 brz,a %o0, 1f 479 stuw %o1, [%o2] 4801: retl 481 nop 482 SET_SIZE(hvio_msiq_getstate) 483 484 /* 485 * arg0 - devhandle 486 * arg1 - msiq_id 487 * arg2 - msiq_state 488 * 489 * ret0 - status 490 */ 491 ENTRY(hvio_msiq_setstate) 492 mov HVIO_MSIQ_SETSTATE, %o5 493 ta FAST_TRAP 494 retl 495 nop 496 SET_SIZE(hvio_msiq_setstate) 497 498 /* 499 * arg0 - devhandle 500 * arg1 - msiq_id 501 * 502 * ret0 - status 503 * ret1 - msiq_head 504 */ 505 ENTRY(hvio_msiq_gethead) 506 mov HVIO_MSIQ_GETHEAD, %o5 507 ta FAST_TRAP 508 brz,a %o0, 1f 509 stx %o1, [%o2] 5101: retl 511 nop 512 SET_SIZE(hvio_msiq_gethead) 513 514 /* 515 * arg0 - devhandle 516 * arg1 - msiq_id 517 * arg2 - msiq_head 518 * 519 * ret0 - status 520 */ 521 ENTRY(hvio_msiq_sethead) 522 mov HVIO_MSIQ_SETHEAD, %o5 523 ta FAST_TRAP 524 retl 525 nop 526 SET_SIZE(hvio_msiq_sethead) 527 528 /* 529 * arg0 - devhandle 530 * arg1 - msiq_id 531 * 532 * ret0 - status 533 * ret1 - msiq_tail 534 */ 535 ENTRY(hvio_msiq_gettail) 536 mov HVIO_MSIQ_GETTAIL, %o5 537 ta FAST_TRAP 538 brz,a %o0, 1f 539 stx %o1, [%o2] 5401: retl 541 nop 542 SET_SIZE(hvio_msiq_gettail) 543 544 /* 545 * arg0 - devhandle 546 * arg1 - msi_num 547 * 548 * ret0 - status 549 * ret1 - msiq_id 550 */ 551 ENTRY(hvio_msi_getmsiq) 552 mov HVIO_MSI_GETMSIQ, %o5 553 ta FAST_TRAP 554 brz,a %o0, 1f 555 stuw %o1, [%o2] 5561: retl 557 nop 558 SET_SIZE(hvio_msi_getmsiq) 559 560 /* 561 * arg0 - devhandle 562 * arg1 - msi_num 563 * arg2 - msiq_id 564 * arg2 - msitype 565 * 566 * ret0 - status 567 */ 568 ENTRY(hvio_msi_setmsiq) 569 mov HVIO_MSI_SETMSIQ, %o5 570 ta FAST_TRAP 571 retl 572 nop 573 SET_SIZE(hvio_msi_setmsiq) 574 575 /* 576 * arg0 - devhandle 577 * arg1 - msi_num 578 * 579 * ret0 - status 580 * ret1 - msi_valid_state 581 */ 582 ENTRY(hvio_msi_getvalid) 583 mov HVIO_MSI_GETVALID, %o5 584 ta FAST_TRAP 585 brz,a %o0, 1f 586 stuw %o1, [%o2] 5871: retl 588 nop 589 SET_SIZE(hvio_msi_getvalid) 590 591 /* 592 * arg0 - devhandle 593 * arg1 - msi_num 594 * arg2 - msi_valid_state 595 * 596 * ret0 - status 597 */ 598 ENTRY(hvio_msi_setvalid) 599 mov HVIO_MSI_SETVALID, %o5 600 ta FAST_TRAP 601 retl 602 nop 603 SET_SIZE(hvio_msi_setvalid) 604 605 /* 606 * arg0 - devhandle 607 * arg1 - msi_num 608 * 609 * ret0 - status 610 * ret1 - msi_state 611 */ 612 ENTRY(hvio_msi_getstate) 613 mov HVIO_MSI_GETSTATE, %o5 614 ta FAST_TRAP 615 brz,a %o0, 1f 616 stuw %o1, [%o2] 6171: retl 618 nop 619 SET_SIZE(hvio_msi_getstate) 620 621 /* 622 * arg0 - devhandle 623 * arg1 - msi_num 624 * arg2 - msi_state 625 * 626 * ret0 - status 627 */ 628 ENTRY(hvio_msi_setstate) 629 mov HVIO_MSI_SETSTATE, %o5 630 ta FAST_TRAP 631 retl 632 nop 633 SET_SIZE(hvio_msi_setstate) 634 635 /* 636 * arg0 - devhandle 637 * arg1 - msg_type 638 * 639 * ret0 - status 640 * ret1 - msiq_id 641 */ 642 ENTRY(hvio_msg_getmsiq) 643 mov HVIO_MSG_GETMSIQ, %o5 644 ta FAST_TRAP 645 brz,a %o0, 1f 646 stuw %o1, [%o2] 6471: retl 648 nop 649 SET_SIZE(hvio_msg_getmsiq) 650 651 /* 652 * arg0 - devhandle 653 * arg1 - msg_type 654 * arg2 - msiq_id 655 * 656 * ret0 - status 657 */ 658 ENTRY(hvio_msg_setmsiq) 659 mov HVIO_MSG_SETMSIQ, %o5 660 ta FAST_TRAP 661 retl 662 nop 663 SET_SIZE(hvio_msg_setmsiq) 664 665 /* 666 * arg0 - devhandle 667 * arg1 - msg_type 668 * 669 * ret0 - status 670 * ret1 - msg_valid_state 671 */ 672 ENTRY(hvio_msg_getvalid) 673 mov HVIO_MSG_GETVALID, %o5 674 ta FAST_TRAP 675 brz,a %o0, 1f 676 stuw %o1, [%o2] 6771: retl 678 nop 679 SET_SIZE(hvio_msg_getvalid) 680 681 /* 682 * arg0 - devhandle 683 * arg1 - msg_type 684 * arg2 - msg_valid_state 685 * 686 * ret0 - status 687 */ 688 ENTRY(hvio_msg_setvalid) 689 mov HVIO_MSG_SETVALID, %o5 690 ta FAST_TRAP 691 retl 692 nop 693 SET_SIZE(hvio_msg_setvalid) 694 695#define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3 696 697! px_phys_acc_4v: Do physical address read. 698! 699! After SHIFT_REGS: 700! %o0 is "from" address 701! %o1 is "to" address 702! 703! Assumes 8 byte data and that alignment is correct. 704! 705! Always returns success (0) in %o0 706 707 ! px_phys_acc_4v must not be split across pages. 708 ! 709 ! ATTN: Be sure that the alignment value is larger than the size of 710 ! the px_phys_acc_4v function. 711 ! 712 .align 0x40 713 714 ENTRY(px_phys_acc_4v) 715 716 SHIFT_REGS 717 ldx [%o0], %g1 718 stx %g1, [%o1] 719 membar #Sync ! Make sure the loads take 720 mov %g0, %o0 721 done 722 SET_SIZE(px_phys_acc_4v) 723 724#endif /* lint || __lint */ 725