1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27/* 28 * Hypervisor calls called by px nexus driver. 29*/ 30 31#include <sys/asm_linkage.h> 32#include <sys/hypervisor_api.h> 33#include <sys/dditypes.h> 34#include <px_ioapi.h> 35#include "px_lib4v.h" 36 37#if defined(lint) || defined(__lint) 38 39/*ARGSUSED*/ 40uint64_t 41hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 42 io_attributes_t attr, io_page_list_t *io_page_list_p, 43 pages_t *pages_mapped) 44{ return (0); } 45 46/*ARGSUSED*/ 47uint64_t 48hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 49 pages_t *pages_demapped) 50{ return (0); } 51 52/*ARGSUSED*/ 53uint64_t 54hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p, 55 r_addr_t *r_addr_p) 56{ return (0); } 57 58/*ARGSUSED*/ 59uint64_t 60hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr, 61 io_addr_t *io_addr_p) 62{ return (0); } 63 64/*ARGSUSED*/ 65uint64_t 66hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, 67 uint64_t *data_p) 68{ return (0); } 69 70/*ARGSUSED*/ 71uint64_t 72hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, 73 r_addr_t ra2, uint32_t *rdbk_status) 74{ return (0); } 75 76/*ARGSUSED*/ 77uint64_t 78hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, 79 io_sync_direction_t io_sync_direction, size_t *bytes_synched) 80{ return (0); } 81 82/*ARGSUSED*/ 83uint64_t 84hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, 85 uint_t msiq_rec_cnt) 86{ return (0); } 87 88/*ARGSUSED*/ 89uint64_t 90hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, 91 uint_t *msiq_rec_cnt_p) 92{ return (0); } 93 94/*ARGSUSED*/ 95uint64_t 96hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 97 pci_msiq_valid_state_t *msiq_valid_state) 98{ return (0); } 99 100/*ARGSUSED*/ 101uint64_t 102hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 103 pci_msiq_valid_state_t msiq_valid_state) 104{ return (0); } 105 106/*ARGSUSED*/ 107uint64_t 108hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 109 pci_msiq_state_t *msiq_state) 110{ return (0); } 111 112/*ARGSUSED*/ 113uint64_t 114hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 115 pci_msiq_state_t msiq_state) 116{ return (0); } 117 118/*ARGSUSED*/ 119uint64_t 120hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 121 msiqhead_t *msiq_head) 122{ return (0); } 123 124/*ARGSUSED*/ 125uint64_t 126hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 127 msiqhead_t msiq_head) 128{ return (0); } 129 130/*ARGSUSED*/ 131uint64_t 132hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 133 msiqtail_t *msiq_tail) 134{ return (0); } 135 136/*ARGSUSED*/ 137uint64_t 138hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 139 msiqid_t *msiq_id) 140{ return (0); } 141 142/*ARGSUSED*/ 143uint64_t 144hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 145 msiqid_t msiq_id, msi_type_t msitype) 146{ return (0); } 147 148/*ARGSUSED*/ 149uint64_t 150hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 151 pci_msi_valid_state_t *msi_valid_state) 152{ return (0); } 153 154/*ARGSUSED*/ 155uint64_t 156hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 157 pci_msi_valid_state_t msi_valid_state) 158{ return (0); } 159 160/*ARGSUSED*/ 161uint64_t 162hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 163 pci_msi_state_t *msi_state) 164{ return (0); } 165 166/*ARGSUSED*/ 167uint64_t 168hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 169 pci_msi_state_t msi_state) 170{ return (0); } 171 172/*ARGSUSED*/ 173uint64_t 174hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 175 msiqid_t *msiq_id) 176{ return (0); } 177 178/*ARGSUSED*/ 179uint64_t 180hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 181 msiqid_t msiq_id) 182{ return (0); } 183 184/*ARGSUSED*/ 185uint64_t 186hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 187 pcie_msg_valid_state_t *msg_valid_state) 188{ return (0); } 189 190/*ARGSUSED*/ 191uint64_t 192hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 193 pcie_msg_valid_state_t msg_valid_state) 194{ return (0); } 195 196/* 197 * First arg to both of these functions is a dummy, to accomodate how 198 * hv_hpriv() works. 199 */ 200/*ARGSUSED*/ 201int 202px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr) 203{ return (0); } 204 205#else /* lint || __lint */ 206 207 /* 208 * arg0 - devhandle 209 * arg1 - tsbid 210 * arg2 - pages 211 * arg3 - io_attributes 212 * arg4 - io_page_list_p 213 * 214 * ret1 - pages_mapped 215 */ 216 ENTRY(hvio_iommu_map) 217 save %sp, -SA(MINFRAME64), %sp 218 mov %i0, %o0 219 mov %i1, %o1 220 mov %i2, %o2 221 mov %i3, %o3 222 mov %i4, %o4 223 mov HVIO_IOMMU_MAP, %o5 224 ta FAST_TRAP 225 brnz %o0, 1f 226 mov %o0, %i0 227 stuw %o1, [%i5] 2281: 229 ret 230 restore 231 SET_SIZE(hvio_iommu_map) 232 233 /* 234 * arg0 - devhandle 235 * arg1 - tsbid 236 * arg2 - pages 237 * 238 * ret1 - pages_demapped 239 */ 240 ENTRY(hvio_iommu_demap) 241 mov HVIO_IOMMU_DEMAP, %o5 242 ta FAST_TRAP 243 brz,a %o0, 1f 244 stuw %o1, [%o3] 2451: retl 246 nop 247 SET_SIZE(hvio_iommu_demap) 248 249 /* 250 * arg0 - devhandle 251 * arg1 - tsbid 252 * 253 * 254 * ret0 - status 255 * ret1 - io_attributes 256 * ret2 - r_addr 257 */ 258 ENTRY(hvio_iommu_getmap) 259 mov %o2, %o4 260 mov HVIO_IOMMU_GETMAP, %o5 261 ta FAST_TRAP 262 brnz %o0, 1f 263 nop 264 stx %o2, [%o3] 265 st %o1, [%o4] 2661: 267 retl 268 nop 269 SET_SIZE(hvio_iommu_getmap) 270 271 /* 272 * arg0 - devhandle 273 * arg1 - r_addr 274 * arg2 - io_attributes 275 * 276 * 277 * ret0 - status 278 * ret1 - io_addr 279 */ 280 ENTRY(hvio_iommu_getbypass) 281 mov HVIO_IOMMU_GETBYPASS, %o5 282 ta FAST_TRAP 283 brz,a %o0, 1f 284 stx %o1, [%o3] 2851: retl 286 nop 287 SET_SIZE(hvio_iommu_getbypass) 288 289 /* 290 * arg0 - devhandle 291 * arg1 - r_addr 292 * arg2 - size 293 * 294 * ret1 - error_flag 295 * ret2 - data 296 */ 297 ENTRY(hvio_peek) 298 mov HVIO_PEEK, %o5 299 ta FAST_TRAP 300 brnz %o0, 1f 301 nop 302 stx %o2, [%o4] 303 st %o1, [%o3] 3041: 305 retl 306 nop 307 SET_SIZE(hvio_peek) 308 309 /* 310 * arg0 - devhandle 311 * arg1 - r_addr 312 * arg2 - sizes 313 * arg3 - data 314 * arg4 - r_addr2 315 * 316 * ret1 - error_flag 317 */ 318 ENTRY(hvio_poke) 319 save %sp, -SA(MINFRAME64), %sp 320 mov %i0, %o0 321 mov %i1, %o1 322 mov %i2, %o2 323 mov %i3, %o3 324 mov %i4, %o4 325 mov HVIO_POKE, %o5 326 ta FAST_TRAP 327 brnz %o0, 1f 328 mov %o0, %i0 329 stuw %o1, [%i5] 3301: 331 ret 332 restore 333 SET_SIZE(hvio_poke) 334 335 /* 336 * arg0 - devhandle 337 * arg1 - r_addr 338 * arg2 - num_bytes 339 * arg3 - io_sync_direction 340 * 341 * ret0 - status 342 * ret1 - bytes_synched 343 */ 344 ENTRY(hvio_dma_sync) 345 mov HVIO_DMA_SYNC, %o5 346 ta FAST_TRAP 347 brz,a %o0, 1f 348 stx %o1, [%o4] 3491: retl 350 nop 351 SET_SIZE(hvio_dma_sync) 352 353 /* 354 * arg0 - devhandle 355 * arg1 - msiq_id 356 * arg2 - r_addr 357 * arg3 - nentries 358 * 359 * ret0 - status 360 */ 361 ENTRY(hvio_msiq_conf) 362 mov HVIO_MSIQ_CONF, %o5 363 ta FAST_TRAP 364 retl 365 nop 366 SET_SIZE(hvio_msiq_conf) 367 368 /* 369 * arg0 - devhandle 370 * arg1 - msiq_id 371 * 372 * ret0 - status 373 * ret1 - r_addr 374 * ret1 - nentries 375 */ 376 ENTRY(hvio_msiq_info) 377 mov %o2, %o4 378 mov HVIO_MSIQ_INFO, %o5 379 ta FAST_TRAP 380 brnz %o0, 1f 381 nop 382 stx %o1, [%o4] 383 stuw %o2, [%o3] 3841: retl 385 nop 386 SET_SIZE(hvio_msiq_info) 387 388 /* 389 * arg0 - devhandle 390 * arg1 - msiq_id 391 * 392 * ret0 - status 393 * ret1 - msiq_valid_state 394 */ 395 ENTRY(hvio_msiq_getvalid) 396 mov HVIO_MSIQ_GETVALID, %o5 397 ta FAST_TRAP 398 brz,a %o0, 1f 399 stuw %o1, [%o2] 4001: retl 401 nop 402 SET_SIZE(hvio_msiq_getvalid) 403 404 /* 405 * arg0 - devhandle 406 * arg1 - msiq_id 407 * arg2 - msiq_valid_state 408 * 409 * ret0 - status 410 */ 411 ENTRY(hvio_msiq_setvalid) 412 mov HVIO_MSIQ_SETVALID, %o5 413 ta FAST_TRAP 414 retl 415 nop 416 SET_SIZE(hvio_msiq_setvalid) 417 418 /* 419 * arg0 - devhandle 420 * arg1 - msiq_id 421 * 422 * ret0 - status 423 * ret1 - msiq_state 424 */ 425 ENTRY(hvio_msiq_getstate) 426 mov HVIO_MSIQ_GETSTATE, %o5 427 ta FAST_TRAP 428 brz,a %o0, 1f 429 stuw %o1, [%o2] 4301: retl 431 nop 432 SET_SIZE(hvio_msiq_getstate) 433 434 /* 435 * arg0 - devhandle 436 * arg1 - msiq_id 437 * arg2 - msiq_state 438 * 439 * ret0 - status 440 */ 441 ENTRY(hvio_msiq_setstate) 442 mov HVIO_MSIQ_SETSTATE, %o5 443 ta FAST_TRAP 444 retl 445 nop 446 SET_SIZE(hvio_msiq_setstate) 447 448 /* 449 * arg0 - devhandle 450 * arg1 - msiq_id 451 * 452 * ret0 - status 453 * ret1 - msiq_head 454 */ 455 ENTRY(hvio_msiq_gethead) 456 mov HVIO_MSIQ_GETHEAD, %o5 457 ta FAST_TRAP 458 brz,a %o0, 1f 459 stx %o1, [%o2] 4601: retl 461 nop 462 SET_SIZE(hvio_msiq_gethead) 463 464 /* 465 * arg0 - devhandle 466 * arg1 - msiq_id 467 * arg2 - msiq_head 468 * 469 * ret0 - status 470 */ 471 ENTRY(hvio_msiq_sethead) 472 mov HVIO_MSIQ_SETHEAD, %o5 473 ta FAST_TRAP 474 retl 475 nop 476 SET_SIZE(hvio_msiq_sethead) 477 478 /* 479 * arg0 - devhandle 480 * arg1 - msiq_id 481 * 482 * ret0 - status 483 * ret1 - msiq_tail 484 */ 485 ENTRY(hvio_msiq_gettail) 486 mov HVIO_MSIQ_GETTAIL, %o5 487 ta FAST_TRAP 488 brz,a %o0, 1f 489 stx %o1, [%o2] 4901: retl 491 nop 492 SET_SIZE(hvio_msiq_gettail) 493 494 /* 495 * arg0 - devhandle 496 * arg1 - msi_num 497 * 498 * ret0 - status 499 * ret1 - msiq_id 500 */ 501 ENTRY(hvio_msi_getmsiq) 502 mov HVIO_MSI_GETMSIQ, %o5 503 ta FAST_TRAP 504 brz,a %o0, 1f 505 stuw %o1, [%o2] 5061: retl 507 nop 508 SET_SIZE(hvio_msi_getmsiq) 509 510 /* 511 * arg0 - devhandle 512 * arg1 - msi_num 513 * arg2 - msiq_id 514 * arg2 - msitype 515 * 516 * ret0 - status 517 */ 518 ENTRY(hvio_msi_setmsiq) 519 mov HVIO_MSI_SETMSIQ, %o5 520 ta FAST_TRAP 521 retl 522 nop 523 SET_SIZE(hvio_msi_setmsiq) 524 525 /* 526 * arg0 - devhandle 527 * arg1 - msi_num 528 * 529 * ret0 - status 530 * ret1 - msi_valid_state 531 */ 532 ENTRY(hvio_msi_getvalid) 533 mov HVIO_MSI_GETVALID, %o5 534 ta FAST_TRAP 535 brz,a %o0, 1f 536 stuw %o1, [%o2] 5371: retl 538 nop 539 SET_SIZE(hvio_msi_getvalid) 540 541 /* 542 * arg0 - devhandle 543 * arg1 - msi_num 544 * arg2 - msi_valid_state 545 * 546 * ret0 - status 547 */ 548 ENTRY(hvio_msi_setvalid) 549 mov HVIO_MSI_SETVALID, %o5 550 ta FAST_TRAP 551 retl 552 nop 553 SET_SIZE(hvio_msi_setvalid) 554 555 /* 556 * arg0 - devhandle 557 * arg1 - msi_num 558 * 559 * ret0 - status 560 * ret1 - msi_state 561 */ 562 ENTRY(hvio_msi_getstate) 563 mov HVIO_MSI_GETSTATE, %o5 564 ta FAST_TRAP 565 brz,a %o0, 1f 566 stuw %o1, [%o2] 5671: retl 568 nop 569 SET_SIZE(hvio_msi_getstate) 570 571 /* 572 * arg0 - devhandle 573 * arg1 - msi_num 574 * arg2 - msi_state 575 * 576 * ret0 - status 577 */ 578 ENTRY(hvio_msi_setstate) 579 mov HVIO_MSI_SETSTATE, %o5 580 ta FAST_TRAP 581 retl 582 nop 583 SET_SIZE(hvio_msi_setstate) 584 585 /* 586 * arg0 - devhandle 587 * arg1 - msg_type 588 * 589 * ret0 - status 590 * ret1 - msiq_id 591 */ 592 ENTRY(hvio_msg_getmsiq) 593 mov HVIO_MSG_GETMSIQ, %o5 594 ta FAST_TRAP 595 brz,a %o0, 1f 596 stuw %o1, [%o2] 5971: retl 598 nop 599 SET_SIZE(hvio_msg_getmsiq) 600 601 /* 602 * arg0 - devhandle 603 * arg1 - msg_type 604 * arg2 - msiq_id 605 * 606 * ret0 - status 607 */ 608 ENTRY(hvio_msg_setmsiq) 609 mov HVIO_MSG_SETMSIQ, %o5 610 ta FAST_TRAP 611 retl 612 nop 613 SET_SIZE(hvio_msg_setmsiq) 614 615 /* 616 * arg0 - devhandle 617 * arg1 - msg_type 618 * 619 * ret0 - status 620 * ret1 - msg_valid_state 621 */ 622 ENTRY(hvio_msg_getvalid) 623 mov HVIO_MSG_GETVALID, %o5 624 ta FAST_TRAP 625 brz,a %o0, 1f 626 stuw %o1, [%o2] 6271: retl 628 nop 629 SET_SIZE(hvio_msg_getvalid) 630 631 /* 632 * arg0 - devhandle 633 * arg1 - msg_type 634 * arg2 - msg_valid_state 635 * 636 * ret0 - status 637 */ 638 ENTRY(hvio_msg_setvalid) 639 mov HVIO_MSG_SETVALID, %o5 640 ta FAST_TRAP 641 retl 642 nop 643 SET_SIZE(hvio_msg_setvalid) 644 645#define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3 646 647! px_phys_acc_4v: Do physical address read. 648! 649! After SHIFT_REGS: 650! %o0 is "from" address 651! %o1 is "to" address 652! 653! Assumes 8 byte data and that alignment is correct. 654! 655! Always returns success (0) in %o0 656 657 ! px_phys_acc_4v must not be split across pages. 658 ! 659 ! ATTN: Be sure that the alignment value is larger than the size of 660 ! the px_phys_acc_4v function. 661 ! 662 .align 0x40 663 664 ENTRY(px_phys_acc_4v) 665 666 SHIFT_REGS 667 ldx [%o0], %g1 668 stx %g1, [%o1] 669 membar #Sync ! Make sure the loads take 670 mov %g0, %o0 671 done 672 SET_SIZE(px_phys_acc_4v) 673 674#endif /* lint || __lint */ 675