1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27/* 28 * Hypervisor calls called by px nexus driver. 29*/ 30 31#include <sys/asm_linkage.h> 32#include <sys/hypervisor_api.h> 33#include <sys/dditypes.h> 34#include <px_ioapi.h> 35#include "px_lib4v.h" 36 37#if defined(lint) || defined(__lint) 38 39/*ARGSUSED*/ 40uint64_t 41hvio_config_get(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 42 pci_config_size_t size, pci_cfg_data_t *data_p) 43{ return (0); } 44 45/*ARGSUSED*/ 46uint64_t 47hvio_config_put(devhandle_t dev_hdl, pci_device_t bdf, pci_config_offset_t off, 48 pci_config_size_t size, pci_cfg_data_t data) 49{ return (0); } 50 51/*ARGSUSED*/ 52uint64_t 53hvio_iommu_map(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 54 io_attributes_t attr, io_page_list_t *io_page_list_p, 55 pages_t *pages_mapped) 56{ return (0); } 57 58/*ARGSUSED*/ 59uint64_t 60hvio_iommu_demap(devhandle_t dev_hdl, tsbid_t tsbid, pages_t pages, 61 pages_t *pages_demapped) 62{ return (0); } 63 64/*ARGSUSED*/ 65uint64_t 66hvio_iommu_getmap(devhandle_t dev_hdl, tsbid_t tsbid, io_attributes_t *attr_p, 67 r_addr_t *r_addr_p) 68{ return (0); } 69 70/*ARGSUSED*/ 71uint64_t 72hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, io_attributes_t attr, 73 io_addr_t *io_addr_p) 74{ return (0); } 75 76/*ARGSUSED*/ 77uint64_t 78hvio_peek(devhandle_t dev_hdl, r_addr_t ra, size_t size, uint32_t *status, 79 uint64_t *data_p) 80{ return (0); } 81 82/*ARGSUSED*/ 83uint64_t 84hvio_poke(devhandle_t dev_hdl, r_addr_t ra, uint64_t sizes, uint64_t data, 85 r_addr_t ra2, uint32_t *rdbk_status) 86{ return (0); } 87 88/*ARGSUSED*/ 89uint64_t 90hvio_dma_sync(devhandle_t dev_hdl, r_addr_t ra, size_t num_bytes, 91 io_sync_direction_t io_sync_direction, size_t *bytes_synched) 92{ return (0); } 93 94/*ARGSUSED*/ 95uint64_t 96hvio_msiq_conf(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t ra, 97 uint_t msiq_rec_cnt) 98{ return (0); } 99 100/*ARGSUSED*/ 101uint64_t 102hvio_msiq_info(devhandle_t dev_hdl, msiqid_t msiq_id, r_addr_t *r_addr_p, 103 uint_t *msiq_rec_cnt_p) 104{ return (0); } 105 106/*ARGSUSED*/ 107uint64_t 108hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 109 pci_msiq_valid_state_t *msiq_valid_state) 110{ return (0); } 111 112/*ARGSUSED*/ 113uint64_t 114hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 115 pci_msiq_valid_state_t msiq_valid_state) 116{ return (0); } 117 118/*ARGSUSED*/ 119uint64_t 120hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 121 pci_msiq_state_t *msiq_state) 122{ return (0); } 123 124/*ARGSUSED*/ 125uint64_t 126hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 127 pci_msiq_state_t msiq_state) 128{ return (0); } 129 130/*ARGSUSED*/ 131uint64_t 132hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 133 msiqhead_t *msiq_head) 134{ return (0); } 135 136/*ARGSUSED*/ 137uint64_t 138hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 139 msiqhead_t msiq_head) 140{ return (0); } 141 142/*ARGSUSED*/ 143uint64_t 144hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 145 msiqtail_t *msiq_tail) 146{ return (0); } 147 148/*ARGSUSED*/ 149uint64_t 150hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 151 msiqid_t *msiq_id) 152{ return (0); } 153 154/*ARGSUSED*/ 155uint64_t 156hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 157 msiqid_t msiq_id, msi_type_t msitype) 158{ return (0); } 159 160/*ARGSUSED*/ 161uint64_t 162hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 163 pci_msi_valid_state_t *msi_valid_state) 164{ return (0); } 165 166/*ARGSUSED*/ 167uint64_t 168hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 169 pci_msi_valid_state_t msi_valid_state) 170{ return (0); } 171 172/*ARGSUSED*/ 173uint64_t 174hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 175 pci_msi_state_t *msi_state) 176{ return (0); } 177 178/*ARGSUSED*/ 179uint64_t 180hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 181 pci_msi_state_t msi_state) 182{ return (0); } 183 184/*ARGSUSED*/ 185uint64_t 186hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 187 msiqid_t *msiq_id) 188{ return (0); } 189 190/*ARGSUSED*/ 191uint64_t 192hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 193 msiqid_t msiq_id) 194{ return (0); } 195 196/*ARGSUSED*/ 197uint64_t 198hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 199 pcie_msg_valid_state_t *msg_valid_state) 200{ return (0); } 201 202/*ARGSUSED*/ 203uint64_t 204hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 205 pcie_msg_valid_state_t msg_valid_state) 206{ return (0); } 207 208/* 209 * First arg to both of these functions is a dummy, to accomodate how 210 * hv_hpriv() works. 211 */ 212/*ARGSUSED*/ 213int 214px_phys_acc_4v(uint64_t dummy, uint64_t from_addr, uint64_t to_addr) 215{ return (0); } 216 217#else /* lint || __lint */ 218 219 /* 220 * arg0 - devhandle 221 * arg1 - pci_device 222 * arg2 - pci_config_offset 223 * arg3 - pci_config_size 224 * 225 * ret0 - status 226 * ret1 - error_flag 227 * ret2 - pci_cfg_data 228 */ 229 ENTRY(hvio_config_get) 230 mov HVIO_CONFIG_GET, %o5 231 ta FAST_TRAP 232 movrnz %o1, -1, %o2 233 stuw %o2, [%o4] 234 retl 235 nop 236 SET_SIZE(hvio_config_get) 237 238 /* 239 * arg0 - devhandle 240 * arg1 - pci_device 241 * arg2 - pci_config_offset 242 * arg3 - pci_config_size 243 * arg4 - pci_cfg_data 244 * 245 * ret0 - status 246 * ret1 - error_flag 247 */ 248 ENTRY(hvio_config_put) 249 mov HVIO_CONFIG_PUT, %o5 250 ta FAST_TRAP 251 retl 252 nop 253 SET_SIZE(hvio_config_put) 254 255 /* 256 * arg0 - devhandle 257 * arg1 - tsbid 258 * arg2 - pages 259 * arg3 - io_attributes 260 * arg4 - io_page_list_p 261 * 262 * ret1 - pages_mapped 263 */ 264 ENTRY(hvio_iommu_map) 265 save %sp, -SA(MINFRAME64), %sp 266 mov %i0, %o0 267 mov %i1, %o1 268 mov %i2, %o2 269 mov %i3, %o3 270 mov %i4, %o4 271 mov HVIO_IOMMU_MAP, %o5 272 ta FAST_TRAP 273 brnz %o0, 1f 274 mov %o0, %i0 275 stuw %o1, [%i5] 2761: 277 ret 278 restore 279 SET_SIZE(hvio_iommu_map) 280 281 /* 282 * arg0 - devhandle 283 * arg1 - tsbid 284 * arg2 - pages 285 * 286 * ret1 - pages_demapped 287 */ 288 ENTRY(hvio_iommu_demap) 289 mov HVIO_IOMMU_DEMAP, %o5 290 ta FAST_TRAP 291 brz,a %o0, 1f 292 stuw %o1, [%o3] 2931: retl 294 nop 295 SET_SIZE(hvio_iommu_demap) 296 297 /* 298 * arg0 - devhandle 299 * arg1 - tsbid 300 * 301 * 302 * ret0 - status 303 * ret1 - io_attributes 304 * ret2 - r_addr 305 */ 306 ENTRY(hvio_iommu_getmap) 307 mov %o2, %o4 308 mov HVIO_IOMMU_GETMAP, %o5 309 ta FAST_TRAP 310 brnz %o0, 1f 311 nop 312 stx %o2, [%o3] 313 st %o1, [%o4] 3141: 315 retl 316 nop 317 SET_SIZE(hvio_iommu_getmap) 318 319 /* 320 * arg0 - devhandle 321 * arg1 - r_addr 322 * arg2 - io_attributes 323 * 324 * 325 * ret0 - status 326 * ret1 - io_addr 327 */ 328 ENTRY(hvio_iommu_getbypass) 329 mov HVIO_IOMMU_GETBYPASS, %o5 330 ta FAST_TRAP 331 brz,a %o0, 1f 332 stx %o1, [%o3] 3331: retl 334 nop 335 SET_SIZE(hvio_iommu_getbypass) 336 337 /* 338 * arg0 - devhandle 339 * arg1 - r_addr 340 * arg2 - size 341 * 342 * ret1 - error_flag 343 * ret2 - data 344 */ 345 ENTRY(hvio_peek) 346 mov HVIO_PEEK, %o5 347 ta FAST_TRAP 348 brnz %o0, 1f 349 nop 350 stx %o2, [%o4] 351 st %o1, [%o3] 3521: 353 retl 354 nop 355 SET_SIZE(hvio_peek) 356 357 /* 358 * arg0 - devhandle 359 * arg1 - r_addr 360 * arg2 - sizes 361 * arg3 - data 362 * arg4 - r_addr2 363 * 364 * ret1 - error_flag 365 */ 366 ENTRY(hvio_poke) 367 save %sp, -SA(MINFRAME64), %sp 368 mov %i0, %o0 369 mov %i1, %o1 370 mov %i2, %o2 371 mov %i3, %o3 372 mov %i4, %o4 373 mov HVIO_POKE, %o5 374 ta FAST_TRAP 375 brnz %o0, 1f 376 mov %o0, %i0 377 stuw %o1, [%i5] 3781: 379 ret 380 restore 381 SET_SIZE(hvio_poke) 382 383 /* 384 * arg0 - devhandle 385 * arg1 - r_addr 386 * arg2 - num_bytes 387 * arg3 - io_sync_direction 388 * 389 * ret0 - status 390 * ret1 - bytes_synched 391 */ 392 ENTRY(hvio_dma_sync) 393 mov HVIO_DMA_SYNC, %o5 394 ta FAST_TRAP 395 brz,a %o0, 1f 396 stx %o1, [%o4] 3971: retl 398 nop 399 SET_SIZE(hvio_dma_sync) 400 401 /* 402 * arg0 - devhandle 403 * arg1 - msiq_id 404 * arg2 - r_addr 405 * arg3 - nentries 406 * 407 * ret0 - status 408 */ 409 ENTRY(hvio_msiq_conf) 410 mov HVIO_MSIQ_CONF, %o5 411 ta FAST_TRAP 412 retl 413 nop 414 SET_SIZE(hvio_msiq_conf) 415 416 /* 417 * arg0 - devhandle 418 * arg1 - msiq_id 419 * 420 * ret0 - status 421 * ret1 - r_addr 422 * ret1 - nentries 423 */ 424 ENTRY(hvio_msiq_info) 425 mov %o2, %o4 426 mov HVIO_MSIQ_INFO, %o5 427 ta FAST_TRAP 428 brnz %o0, 1f 429 nop 430 stx %o1, [%o4] 431 stuw %o2, [%o3] 4321: retl 433 nop 434 SET_SIZE(hvio_msiq_info) 435 436 /* 437 * arg0 - devhandle 438 * arg1 - msiq_id 439 * 440 * ret0 - status 441 * ret1 - msiq_valid_state 442 */ 443 ENTRY(hvio_msiq_getvalid) 444 mov HVIO_MSIQ_GETVALID, %o5 445 ta FAST_TRAP 446 brz,a %o0, 1f 447 stuw %o1, [%o2] 4481: retl 449 nop 450 SET_SIZE(hvio_msiq_getvalid) 451 452 /* 453 * arg0 - devhandle 454 * arg1 - msiq_id 455 * arg2 - msiq_valid_state 456 * 457 * ret0 - status 458 */ 459 ENTRY(hvio_msiq_setvalid) 460 mov HVIO_MSIQ_SETVALID, %o5 461 ta FAST_TRAP 462 retl 463 nop 464 SET_SIZE(hvio_msiq_setvalid) 465 466 /* 467 * arg0 - devhandle 468 * arg1 - msiq_id 469 * 470 * ret0 - status 471 * ret1 - msiq_state 472 */ 473 ENTRY(hvio_msiq_getstate) 474 mov HVIO_MSIQ_GETSTATE, %o5 475 ta FAST_TRAP 476 brz,a %o0, 1f 477 stuw %o1, [%o2] 4781: retl 479 nop 480 SET_SIZE(hvio_msiq_getstate) 481 482 /* 483 * arg0 - devhandle 484 * arg1 - msiq_id 485 * arg2 - msiq_state 486 * 487 * ret0 - status 488 */ 489 ENTRY(hvio_msiq_setstate) 490 mov HVIO_MSIQ_SETSTATE, %o5 491 ta FAST_TRAP 492 retl 493 nop 494 SET_SIZE(hvio_msiq_setstate) 495 496 /* 497 * arg0 - devhandle 498 * arg1 - msiq_id 499 * 500 * ret0 - status 501 * ret1 - msiq_head 502 */ 503 ENTRY(hvio_msiq_gethead) 504 mov HVIO_MSIQ_GETHEAD, %o5 505 ta FAST_TRAP 506 brz,a %o0, 1f 507 stx %o1, [%o2] 5081: retl 509 nop 510 SET_SIZE(hvio_msiq_gethead) 511 512 /* 513 * arg0 - devhandle 514 * arg1 - msiq_id 515 * arg2 - msiq_head 516 * 517 * ret0 - status 518 */ 519 ENTRY(hvio_msiq_sethead) 520 mov HVIO_MSIQ_SETHEAD, %o5 521 ta FAST_TRAP 522 retl 523 nop 524 SET_SIZE(hvio_msiq_sethead) 525 526 /* 527 * arg0 - devhandle 528 * arg1 - msiq_id 529 * 530 * ret0 - status 531 * ret1 - msiq_tail 532 */ 533 ENTRY(hvio_msiq_gettail) 534 mov HVIO_MSIQ_GETTAIL, %o5 535 ta FAST_TRAP 536 brz,a %o0, 1f 537 stx %o1, [%o2] 5381: retl 539 nop 540 SET_SIZE(hvio_msiq_gettail) 541 542 /* 543 * arg0 - devhandle 544 * arg1 - msi_num 545 * 546 * ret0 - status 547 * ret1 - msiq_id 548 */ 549 ENTRY(hvio_msi_getmsiq) 550 mov HVIO_MSI_GETMSIQ, %o5 551 ta FAST_TRAP 552 brz,a %o0, 1f 553 stuw %o1, [%o2] 5541: retl 555 nop 556 SET_SIZE(hvio_msi_getmsiq) 557 558 /* 559 * arg0 - devhandle 560 * arg1 - msi_num 561 * arg2 - msiq_id 562 * arg2 - msitype 563 * 564 * ret0 - status 565 */ 566 ENTRY(hvio_msi_setmsiq) 567 mov HVIO_MSI_SETMSIQ, %o5 568 ta FAST_TRAP 569 retl 570 nop 571 SET_SIZE(hvio_msi_setmsiq) 572 573 /* 574 * arg0 - devhandle 575 * arg1 - msi_num 576 * 577 * ret0 - status 578 * ret1 - msi_valid_state 579 */ 580 ENTRY(hvio_msi_getvalid) 581 mov HVIO_MSI_GETVALID, %o5 582 ta FAST_TRAP 583 brz,a %o0, 1f 584 stuw %o1, [%o2] 5851: retl 586 nop 587 SET_SIZE(hvio_msi_getvalid) 588 589 /* 590 * arg0 - devhandle 591 * arg1 - msi_num 592 * arg2 - msi_valid_state 593 * 594 * ret0 - status 595 */ 596 ENTRY(hvio_msi_setvalid) 597 mov HVIO_MSI_SETVALID, %o5 598 ta FAST_TRAP 599 retl 600 nop 601 SET_SIZE(hvio_msi_setvalid) 602 603 /* 604 * arg0 - devhandle 605 * arg1 - msi_num 606 * 607 * ret0 - status 608 * ret1 - msi_state 609 */ 610 ENTRY(hvio_msi_getstate) 611 mov HVIO_MSI_GETSTATE, %o5 612 ta FAST_TRAP 613 brz,a %o0, 1f 614 stuw %o1, [%o2] 6151: retl 616 nop 617 SET_SIZE(hvio_msi_getstate) 618 619 /* 620 * arg0 - devhandle 621 * arg1 - msi_num 622 * arg2 - msi_state 623 * 624 * ret0 - status 625 */ 626 ENTRY(hvio_msi_setstate) 627 mov HVIO_MSI_SETSTATE, %o5 628 ta FAST_TRAP 629 retl 630 nop 631 SET_SIZE(hvio_msi_setstate) 632 633 /* 634 * arg0 - devhandle 635 * arg1 - msg_type 636 * 637 * ret0 - status 638 * ret1 - msiq_id 639 */ 640 ENTRY(hvio_msg_getmsiq) 641 mov HVIO_MSG_GETMSIQ, %o5 642 ta FAST_TRAP 643 brz,a %o0, 1f 644 stuw %o1, [%o2] 6451: retl 646 nop 647 SET_SIZE(hvio_msg_getmsiq) 648 649 /* 650 * arg0 - devhandle 651 * arg1 - msg_type 652 * arg2 - msiq_id 653 * 654 * ret0 - status 655 */ 656 ENTRY(hvio_msg_setmsiq) 657 mov HVIO_MSG_SETMSIQ, %o5 658 ta FAST_TRAP 659 retl 660 nop 661 SET_SIZE(hvio_msg_setmsiq) 662 663 /* 664 * arg0 - devhandle 665 * arg1 - msg_type 666 * 667 * ret0 - status 668 * ret1 - msg_valid_state 669 */ 670 ENTRY(hvio_msg_getvalid) 671 mov HVIO_MSG_GETVALID, %o5 672 ta FAST_TRAP 673 brz,a %o0, 1f 674 stuw %o1, [%o2] 6751: retl 676 nop 677 SET_SIZE(hvio_msg_getvalid) 678 679 /* 680 * arg0 - devhandle 681 * arg1 - msg_type 682 * arg2 - msg_valid_state 683 * 684 * ret0 - status 685 */ 686 ENTRY(hvio_msg_setvalid) 687 mov HVIO_MSG_SETVALID, %o5 688 ta FAST_TRAP 689 retl 690 nop 691 SET_SIZE(hvio_msg_setvalid) 692 693#define SHIFT_REGS mov %o1,%o0; mov %o2,%o1; mov %o3,%o2; mov %o4,%o3 694 695! px_phys_acc_4v: Do physical address read. 696! 697! After SHIFT_REGS: 698! %o0 is "from" address 699! %o1 is "to" address 700! 701! Assumes 8 byte data and that alignment is correct. 702! 703! Always returns success (0) in %o0 704 705 ! px_phys_acc_4v must not be split across pages. 706 ! 707 ! ATTN: Be sure that the alignment value is larger than the size of 708 ! the px_phys_acc_4v function. 709 ! 710 .align 0x40 711 712 ENTRY(px_phys_acc_4v) 713 714 SHIFT_REGS 715 ldx [%o0], %g1 716 stx %g1, [%o1] 717 membar #Sync ! Make sure the loads take 718 mov %g0, %o0 719 done 720 SET_SIZE(px_phys_acc_4v) 721 722#endif /* lint || __lint */ 723