xref: /titanic_41/usr/src/uts/sun4v/io/px/px_err.h (revision 74e20cfe817b82802b16fac8690dadcda76f54f5)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_PX_ERR_H
27 #define	_SYS_PX_ERR_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 /* error packet definitions */
36 
37 /* Block Definitions */
38 #define	BLOCK_RSVD		0x0
39 #define	BLOCK_HOSTBUS		0x1
40 #define	BLOCK_MMU		0x2
41 #define	BLOCK_INTR		0x3
42 #define	BLOCK_PCIE		0x4
43 #define	BLOCK_UNKNOWN		0xe
44 
45 /* Op definitions for HOSTBUS */
46 #define	OP_RESERVED		0x0
47 #define	OP_PIO			0x1
48 #define	OP_DMA			0x2
49 #define	OP_UNKNOWN		0xe
50 
51 
52 /* Op definitions for MMU */
53 #define	OP_RESERVED		0x0
54 #define	OP_XLAT			0x1
55 #define	OP_BYPASS		0x2
56 #define	OP_TBW			0x3
57 #define	OP_UNKNOWN		0xe
58 
59 /* Op definitions for INTR */
60 #define	OP_RESERVED		0x0
61 #define	OP_MSI32		0x1
62 #define	OP_MSI64		0x2
63 #define	OP_MSIQ			0x3
64 #define	OP_PCIEMSG		0x4
65 #define	OP_UNKNOWN		0xe
66 
67 /* Phase definitons */
68 #define	PH_RESERVED		0x0
69 #define	PH_ADDR			0x1
70 #define	PH_DATA			0x2
71 #define	PH_UNKNOWN		0xe
72 #define	PH_IRR			0xf
73 
74 /* Condition definitions for ADDR Phase */
75 #define	CND_RESERVED		0x0
76 #define	CND_ILL			0x1
77 #define	CND_UNMAP		0x2
78 #define	CND_UNKNOWN		0xe
79 #define	CND_IRR			0xf
80 
81 /* Condition definitions for DATA Phase */
82 #define	CND_RESERVED		0x0
83 #define	CND_ILL			0x1
84 #define	CND_INT			0x3
85 #define	CND_UE			0x4
86 #define	CND_UNKNOWN		0xe
87 #define	CND_IRR			0xf
88 
89 /* Condition definitions for MMU Block ADDR phase */
90 #define	CND_PROT		0x5
91 #define	CND_INV			0x6
92 
93 /* Condition definitions for INTR Block MSIQ  Op Data phase */
94 #define	CND_OV			0x5
95 
96 /* Condition definitions for Unkown phase */
97 #define	CND_RESERVED		0x0
98 #define	CND_ILL			0x1
99 #define	CND_TO			0x5
100 #define	CND_UNKNOWN		0xe
101 #define	CND_IRR			0xf
102 
103 /* Dir definitions for HOSTBUS & MMU */
104 #define	DIR_RESERVED		0x0
105 #define	DIR_READ		0x1
106 #define	DIR_WRITE		0x2
107 #define	DIR_RDWR		0x3
108 #define	DIR_INGRESS		0x4
109 #define	DIR_EGRESS		0x5
110 #define	DIR_LINK		0x6
111 #define	DIR_UNKNOWN		0xe
112 #define	DIR_IRR			0xf
113 
114 #define	PX_FM_RC_UNRECOG	"fire.epkt"
115 #define	EPKT_SYSINO		"sysino"
116 #define	EPKT_EHDL		"ehdl"
117 #define	EPKT_STICK		"stick"
118 #define	EPKT_RC_DESCR		"rc_descr"
119 #define	EPKT_PEC_DESCR		"pec_descr"
120 
121 typedef struct root_complex {
122 	uint64_t  sysino;
123 	uint64_t  ehdl;
124 	uint64_t  stick;
125 	struct  {
126 		uint32_t block	: 4,
127 			op	: 4,
128 			phase	: 4,
129 			cond	: 4,
130 			dir	: 4,
131 			STOP	: 1,
132 				: 6,
133 			H	: 1,
134 			R	: 1,
135 			D	: 1,
136 			M	: 1,
137 			S	: 1;
138 	} rc_descr;
139 	uint32_t  size;
140 	uint64_t  addr;
141 	uint64_t  hdr[2];
142 	uint64_t  reserved;
143 } px_rc_err_t;
144 
145 typedef struct pec_block_err {
146 	uint64_t  sysino;
147 	uint64_t  ehdl;
148 	uint64_t  stick;
149 	struct  {
150 		uint32_t block	: 4,
151 			rsvd1	: 12,
152 			dir	: 4,
153 				: 3,
154 			Z	: 1,
155 			S	: 1,
156 			R	: 1,
157 			I	: 1,
158 			H	: 1,
159 			C	: 1,
160 			U	: 1,
161 			E	: 1,
162 			P	: 1;
163 	} pec_descr;
164 	uint16_t  pci_err_status;
165 	uint16_t  pcie_err_status;
166 	uint32_t  ce_reg_status;
167 	uint32_t  ue_reg_status;
168 	uint64_t  hdr[2];
169 	uint32_t  err_src_reg;
170 	uint32_t  root_err_status;
171 } px_pec_err_t;
172 
173 #ifdef	__cplusplus
174 }
175 #endif
176 
177 #endif	/* _SYS_PX_ERR_H */
178