1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_ERR_H 28 #define _SYS_PX_ERR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* error packet definitions */ 37 38 /* Block Definitions */ 39 #define BLOCK_RSVD 0x0 40 #define BLOCK_HOSTBUS 0x1 41 #define BLOCK_MMU 0x2 42 #define BLOCK_INTR 0x3 43 #define BLOCK_PCIE 0x4 44 #define BLOCK_UNKNOWN 0xe 45 46 /* Op definitions for HOSTBUS */ 47 #define OP_RESERVED 0x0 48 #define OP_PIO 0x1 49 #define OP_DMA 0x2 50 #define OP_UNKNOWN 0xe 51 52 53 /* Op definitions for MMU */ 54 #define OP_RESERVED 0x0 55 #define OP_XLAT 0x1 56 #define OP_BYPASS 0x2 57 #define OP_TBW 0x3 58 #define OP_UNKNOWN 0xe 59 60 /* Op definitions for INTR */ 61 #define OP_RESERVED 0x0 62 #define OP_MSI32 0x1 63 #define OP_MSI64 0x2 64 #define OP_MSIQ 0x3 65 #define OP_PCIEMSG 0x4 66 #define OP_UNKNOWN 0xe 67 68 /* Phase definitons */ 69 #define PH_RESERVED 0x0 70 #define PH_ADDR 0x1 71 #define PH_DATA 0x2 72 #define PH_UNKNOWN 0xe 73 #define PH_IRR 0xf 74 75 /* Condition definitions for ADDR Phase */ 76 #define CND_RESERVED 0x0 77 #define CND_ILL 0x1 78 #define CND_UNMAP 0x2 79 #define CND_UNKNOWN 0xe 80 #define CND_IRR 0xf 81 82 /* Condition definitions for DATA Phase */ 83 #define CND_RESERVED 0x0 84 #define CND_ILL 0x1 85 #define CND_INT 0x3 86 #define CND_UE 0x4 87 #define CND_UNKNOWN 0xe 88 #define CND_IRR 0xf 89 90 /* Condition definitions for MMU Block ADDR phase */ 91 #define CND_PROT 0x5 92 #define CND_INV 0x6 93 94 /* Condition definitions for INTR Block MSIQ Op Data phase */ 95 #define CND_OV 0x5 96 97 /* Condition definitions for Unkown phase */ 98 #define CND_RESERVED 0x0 99 #define CND_ILL 0x1 100 #define CND_TO 0x5 101 #define CND_UNKNOWN 0xe 102 #define CND_IRR 0xf 103 104 /* Dir definitions for HOSTBUS & MMU */ 105 #define DIR_RESERVED 0x0 106 #define DIR_READ 0x1 107 #define DIR_WRITE 0x2 108 #define DIR_RDWR 0x3 109 #define DIR_INGRESS 0x4 110 #define DIR_EGRESS 0x5 111 #define DIR_LINK 0x6 112 #define DIR_UNKNOWN 0xe 113 #define DIR_IRR 0xf 114 115 typedef struct root_complex { 116 uint64_t sysino; 117 uint64_t ehdl; 118 uint64_t stick; 119 struct { 120 uint32_t block : 4, 121 op : 4, 122 phase : 4, 123 cond : 4, 124 dir : 4, 125 : 7, 126 H : 1, 127 R : 1, 128 D : 1, 129 M : 1, 130 S : 1; 131 } rc_descr; 132 uint32_t size; 133 uint64_t addr; 134 uint64_t hdr[2]; 135 uint64_t reserved; 136 } px_rc_err_t; 137 138 typedef struct pec_block_err { 139 uint64_t sysino; 140 uint64_t ehdl; 141 uint64_t stick; 142 struct { 143 uint32_t block : 4, 144 rsvd1 : 12, 145 dir : 4, 146 : 3, 147 Z : 1, 148 S : 1, 149 R : 1, 150 I : 1, 151 H : 1, 152 C : 1, 153 U : 1, 154 E : 1, 155 P : 1; 156 } pec_descr; 157 uint16_t pci_err_status; 158 uint16_t pcie_err_status; 159 uint32_t ce_reg_status; 160 uint32_t ue_reg_status; 161 uint64_t hdr[2]; 162 uint32_t err_src_reg; 163 uint32_t root_err_status; 164 } px_pec_err_t; 165 166 #ifdef __cplusplus 167 } 168 #endif 169 170 #endif /* _SYS_PX_ERR_H */ 171