1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/systm.h> 31 #include <sys/archsystm.h> 32 #include <sys/machparam.h> 33 #include <sys/machsystm.h> 34 #include <sys/cpu.h> 35 #include <sys/elf_SPARC.h> 36 #include <vm/hat_sfmmu.h> 37 #include <vm/page.h> 38 #include <vm/vm_dep.h> 39 #include <sys/cpuvar.h> 40 #include <sys/async.h> 41 #include <sys/cmn_err.h> 42 #include <sys/debug.h> 43 #include <sys/dditypes.h> 44 #include <sys/sunddi.h> 45 #include <sys/cpu_module.h> 46 #include <sys/prom_debug.h> 47 #include <sys/vmsystm.h> 48 #include <sys/prom_plat.h> 49 #include <sys/sysmacros.h> 50 #include <sys/intreg.h> 51 #include <sys/machtrap.h> 52 #include <sys/ontrap.h> 53 #include <sys/ivintr.h> 54 #include <sys/atomic.h> 55 #include <sys/panic.h> 56 #include <sys/dtrace.h> 57 #include <sys/simulate.h> 58 #include <sys/fault.h> 59 #include <sys/niagara2regs.h> 60 #include <sys/hsvc.h> 61 #include <sys/trapstat.h> 62 63 uint_t root_phys_addr_lo_mask = 0xffffffffU; 64 #if defined(NIAGARA2_IMPL) 65 char cpu_module_name[] = "SUNW,UltraSPARC-T2"; 66 #elif defined(VFALLS_IMPL) 67 char cpu_module_name[] = "SUNW,UltraSPARC-T2+"; 68 #endif 69 70 /* 71 * Hypervisor services information for the NIAGARA2 and Victoria Falls 72 * CPU module 73 */ 74 static boolean_t cpu_hsvc_available = B_TRUE; 75 static uint64_t cpu_sup_minor; /* Supported minor number */ 76 #if defined(NIAGARA2_IMPL) 77 static hsvc_info_t cpu_hsvc = { 78 HSVC_REV_1, NULL, HSVC_GROUP_NIAGARA2_CPU, NIAGARA2_HSVC_MAJOR, 79 NIAGARA2_HSVC_MINOR, cpu_module_name 80 }; 81 #elif defined(VFALLS_IMPL) 82 static hsvc_info_t cpu_hsvc = { 83 HSVC_REV_1, NULL, HSVC_GROUP_VFALLS_CPU, VFALLS_HSVC_MAJOR, 84 VFALLS_HSVC_MINOR, cpu_module_name 85 }; 86 #endif 87 88 void 89 cpu_setup(void) 90 { 91 extern int mmu_exported_pagesize_mask; 92 extern int cpc_has_overflow_intr; 93 extern size_t contig_mem_prealloc_base; 94 int status; 95 96 /* 97 * Negotiate the API version for Niagara2 specific hypervisor 98 * services. 99 */ 100 status = hsvc_register(&cpu_hsvc, &cpu_sup_minor); 101 if (status != 0) { 102 cmn_err(CE_WARN, "%s: cannot negotiate hypervisor services " 103 "group: 0x%lx major: 0x%lx minor: 0x%lx errno: %d", 104 cpu_hsvc.hsvc_modname, cpu_hsvc.hsvc_group, 105 cpu_hsvc.hsvc_major, cpu_hsvc.hsvc_minor, status); 106 cpu_hsvc_available = B_FALSE; 107 } 108 109 /* 110 * The setup common to all CPU modules is done in cpu_setup_common 111 * routine. 112 */ 113 cpu_setup_common(NULL); 114 115 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 116 117 if ((mmu_exported_pagesize_mask & 118 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 119 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 120 cmn_err(CE_PANIC, "machine description" 121 " does not have required sun4v page sizes" 122 " 8K, 64K and 4M: MD mask is 0x%x", 123 mmu_exported_pagesize_mask); 124 125 cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | AV_SPARC_ASI_BLK_INIT; 126 127 /* 128 * Niagara2 supports a 48-bit subset of the full 64-bit virtual 129 * address space. Virtual addresses between 0x0000800000000000 130 * and 0xffff.7fff.ffff.ffff inclusive lie within a "VA Hole" 131 * and must never be mapped. In addition, software must not use 132 * pages within 4GB of the VA hole as instruction pages to 133 * avoid problems with prefetching into the VA hole. 134 */ 135 hole_start = (caddr_t)((1ull << (va_bits - 1)) - (1ull << 32)); 136 hole_end = (caddr_t)((0ull - (1ull << (va_bits - 1))) + (1ull << 32)); 137 138 /* 139 * Niagara2 has a performance counter overflow interrupt 140 */ 141 cpc_has_overflow_intr = 1; 142 143 /* 144 * Enable 4M pages for OOB. 145 */ 146 max_uheap_lpsize = MMU_PAGESIZE4M; 147 max_ustack_lpsize = MMU_PAGESIZE4M; 148 max_privmap_lpsize = MMU_PAGESIZE4M; 149 150 contig_mem_prealloc_base = NIAGARA2_PREALLOC_BASE; 151 } 152 153 /* 154 * Set the magic constants of the implementation. 155 */ 156 void 157 cpu_fiximp(struct cpu_node *cpunode) 158 { 159 /* 160 * The Cache node is optional in MD. Therefore in case "Cache" 161 * node does not exists in MD, set the default L2 cache associativity, 162 * size, linesize. 163 */ 164 if (cpunode->ecache_size == 0) 165 cpunode->ecache_size = L2CACHE_SIZE; 166 if (cpunode->ecache_linesize == 0) 167 cpunode->ecache_linesize = L2CACHE_LINESIZE; 168 if (cpunode->ecache_associativity == 0) 169 cpunode->ecache_associativity = L2CACHE_ASSOCIATIVITY; 170 } 171 172 void 173 cpu_map_exec_units(struct cpu *cp) 174 { 175 ASSERT(MUTEX_HELD(&cpu_lock)); 176 177 /* 178 * The cpu_ipipe and cpu_fpu fields are initialized based on 179 * the execution unit sharing information from the MD. They 180 * default to the CPU id in the absence of such information. 181 */ 182 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 183 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 184 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 185 186 cp->cpu_m.cpu_fpu = cpunodes[cp->cpu_id].fpu_mapping; 187 if (cp->cpu_m.cpu_fpu == NO_EU_MAPPING_FOUND) 188 cp->cpu_m.cpu_fpu = (id_t)(cp->cpu_id); 189 190 /* 191 * Niagara 2 defines the core to be at the FPU level 192 */ 193 cp->cpu_m.cpu_core = cp->cpu_m.cpu_fpu; 194 195 /* 196 * The cpu_chip field is initialized based on the information 197 * in the MD and assume that all cpus within a chip 198 * share the same L2 cache. If no such info is available, we 199 * set the cpu to belong to the defacto chip 0. 200 */ 201 cp->cpu_m.cpu_mpipe = cpunodes[cp->cpu_id].l2_cache_mapping; 202 if (cp->cpu_m.cpu_mpipe == NO_L2_CACHE_MAPPING_FOUND) 203 cp->cpu_m.cpu_mpipe = CPU_L2_CACHEID_INVALID; 204 } 205 206 static int cpucnt; 207 208 void 209 cpu_init_private(struct cpu *cp) 210 { 211 extern void niagara_kstat_init(void); 212 213 ASSERT(MUTEX_HELD(&cpu_lock)); 214 215 cpu_map_exec_units(cp); 216 217 if ((cpucnt++ == 0) && (cpu_hsvc_available == B_TRUE)) 218 (void) niagara_kstat_init(); 219 } 220 221 /*ARGSUSED*/ 222 void 223 cpu_uninit_private(struct cpu *cp) 224 { 225 extern void niagara_kstat_fini(void); 226 227 ASSERT(MUTEX_HELD(&cpu_lock)); 228 if ((--cpucnt == 0) && (cpu_hsvc_available == B_TRUE)) 229 (void) niagara_kstat_fini(); 230 } 231 232 /* 233 * On Niagara2, any flush will cause all preceding stores to be 234 * synchronized wrt the i$, regardless of address or ASI. In fact, 235 * the address is ignored, so we always flush address 0. 236 */ 237 /*ARGSUSED*/ 238 void 239 dtrace_flush_sec(uintptr_t addr) 240 { 241 doflush(0); 242 } 243 244 /* 245 * Trapstat support for Niagara2 processor 246 * The Niagara2 provides HWTW support for TSB lookup and with HWTW 247 * enabled no TSB hit information will be available. Therefore setting 248 * the time spent in TLB miss handler for TSB hits to 0. 249 */ 250 int 251 cpu_trapstat_conf(int cmd) 252 { 253 int status = 0; 254 255 switch (cmd) { 256 case CPU_TSTATCONF_INIT: 257 case CPU_TSTATCONF_FINI: 258 case CPU_TSTATCONF_ENABLE: 259 case CPU_TSTATCONF_DISABLE: 260 break; 261 default: 262 status = EINVAL; 263 break; 264 } 265 return (status); 266 } 267 268 void 269 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 270 { 271 tstat_pgszdata_t *tstatp = (tstat_pgszdata_t *)buf; 272 int i; 273 274 for (i = 0; i < tstat_pgszs; i++, tstatp++) { 275 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_count = 0; 276 tstatp->tpgsz_kernel.tmode_itlb.ttlb_tlb.tmiss_time = 0; 277 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_count = 0; 278 tstatp->tpgsz_user.tmode_itlb.ttlb_tlb.tmiss_time = 0; 279 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 280 tstatp->tpgsz_kernel.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 281 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_count = 0; 282 tstatp->tpgsz_user.tmode_dtlb.ttlb_tlb.tmiss_time = 0; 283 } 284 } 285 286 /* 287 * Page coloring support for hashed cache index mode 288 */ 289 290 /* 291 * Node id bits from machine description (MD). Node id distinguishes 292 * local versus remote memory. Because of MPO, page allocation does 293 * not cross node boundaries. Therefore, remove the node id bits from 294 * the color, since they are fixed. Either bit 30, or 31:30 in 295 * Victoria Falls processors. 296 * The number of node id bits is always 0 in Niagara2. 297 */ 298 typedef struct n2color { 299 uchar_t nnbits; /* number of node id bits */ 300 uchar_t nnmask; /* mask for node id bits */ 301 uchar_t lomask; /* mask for bits below node id */ 302 uchar_t lobits; /* number of bits below node id */ 303 } n2color_t; 304 305 n2color_t n2color[MMU_PAGE_SIZES]; 306 static uchar_t nhbits[] = {7, 7, 6, 5, 5, 5}; 307 308 /* 309 * Remove node id bits from color bits 32:28. 310 * This will reduce the number of colors. 311 * No change if number of node bits is zero. 312 */ 313 static inline uint_t 314 n2_hash2color(uint_t color, uchar_t szc) 315 { 316 n2color_t m = n2color[szc]; 317 318 if (m.nnbits > 0) { 319 color = ((color >> m.nnbits) & ~m.lomask) | (color & m.lomask); 320 ASSERT((color & ~(hw_page_array[szc].hp_colors - 1)) == 0); 321 } 322 323 return (color); 324 } 325 326 /* 327 * Restore node id bits into page color. 328 * This will increase the number of colors to match N2. 329 * No change if number of node bits is zero. 330 */ 331 static inline uint_t 332 n2_color2hash(uint_t color, uchar_t szc, uint_t node) 333 { 334 n2color_t m = n2color[szc]; 335 336 if (m.nnbits > 0) { 337 color = ((color & ~m.lomask) << m.nnbits) | (color & m.lomask); 338 color |= (node & m.nnmask) << m.lobits; 339 } 340 341 return (color); 342 } 343 344 /* NI2 L2$ index is pa[32:28]^pa[17:13].pa[19:18]^pa[12:11].pa[10:6] */ 345 346 /* 347 * iterator NULL means pfn is VA, do not adjust ra_to_pa 348 * iterator (-1) means pfn is RA, need to convert to PA 349 * iterator non-null means pfn is RA, use ra_to_pa 350 */ 351 uint_t 352 page_pfn_2_color_cpu(pfn_t pfn, uchar_t szc, void *cookie) 353 { 354 mem_node_iterator_t *it = cookie; 355 uint_t color; 356 357 ASSERT(szc <= TTE256M); 358 359 if (it == ((mem_node_iterator_t *)(-1))) { 360 pfn = plat_rapfn_to_papfn(pfn); 361 } else if (it != NULL) { 362 ASSERT(pfn >= it->mi_mblock_base && pfn <= it->mi_mblock_end); 363 pfn = pfn + it->mi_ra_to_pa; 364 } 365 pfn = PFN_BASE(pfn, szc); 366 color = ((pfn >> 15) ^ pfn) & 0x1f; 367 if (szc < TTE4M) { 368 /* 19:18 */ 369 color = (color << 2) | ((pfn >> 5) & 0x3); 370 if (szc > TTE64K) 371 color >>= 1; /* 19 */ 372 } 373 return (n2_hash2color(color, szc)); 374 } 375 376 static uint_t 377 page_papfn_2_color_cpu(pfn_t papfn, uchar_t szc) 378 { 379 uint_t color; 380 381 ASSERT(szc <= TTE256M); 382 383 papfn = PFN_BASE(papfn, szc); 384 color = ((papfn >> 15) ^ papfn) & 0x1f; 385 if (szc < TTE4M) { 386 /* 19:18 */ 387 color = (color << 2) | ((papfn >> 5) & 0x3); 388 if (szc > TTE64K) 389 color >>= 1; /* 19 */ 390 } 391 return (color); 392 } 393 394 #if TTE256M != 5 395 #error TTE256M is not 5 396 #endif 397 398 uint_t 399 page_get_nsz_color_mask_cpu(uchar_t szc, uint_t mask) 400 { 401 static uint_t ni2_color_masks[5] = {0x63, 0x1e, 0x3e, 0x1f, 0x1f}; 402 ASSERT(szc < TTE256M); 403 mask = n2_color2hash(mask, szc, 0); 404 mask &= ni2_color_masks[szc]; 405 if (szc == TTE64K || szc == TTE512K) 406 mask >>= 1; 407 return (n2_hash2color(mask, szc + 1)); 408 } 409 410 uint_t 411 page_get_nsz_color_cpu(uchar_t szc, uint_t color) 412 { 413 ASSERT(szc < TTE256M); 414 color = n2_color2hash(color, szc, 0); 415 if (szc == TTE64K || szc == TTE512K) 416 color >>= 1; 417 return (n2_hash2color(color, szc + 1)); 418 } 419 420 uint_t 421 page_get_color_shift_cpu(uchar_t szc, uchar_t nszc) 422 { 423 uint_t s; 424 ASSERT(nszc >= szc); 425 ASSERT(nszc <= TTE256M); 426 427 s = nhbits[szc] - n2color[szc].nnbits; 428 s -= nhbits[nszc] - n2color[nszc].nnbits; 429 430 return (s); 431 } 432 433 uint_t 434 page_convert_color_cpu(uint_t ncolor, uchar_t szc, uchar_t nszc) 435 { 436 uint_t color; 437 438 ASSERT(nszc > szc); 439 ASSERT(nszc <= TTE256M); 440 ncolor = n2_color2hash(ncolor, nszc, 0); 441 color = ncolor << (nhbits[szc] - nhbits[nszc]); 442 color = n2_hash2color(color, szc); 443 return (color); 444 } 445 446 #define PAPFN_2_MNODE(pfn) \ 447 (((pfn) & it->mi_mnode_pfn_mask) >> it->mi_mnode_pfn_shift) 448 449 /*ARGSUSED*/ 450 pfn_t 451 page_next_pfn_for_color_cpu(pfn_t pfn, uchar_t szc, uint_t color, 452 uint_t ceq_mask, uint_t color_mask, void *cookie) 453 { 454 mem_node_iterator_t *it = cookie; 455 pfn_t pstep = PNUM_SIZE(szc); 456 pfn_t npfn, pfn_ceq_mask, pfn_color; 457 pfn_t tmpmask, mask = (pfn_t)-1; 458 uint_t pfnmn; 459 460 ASSERT((color & ~ceq_mask) == 0); 461 ASSERT(pfn >= it->mi_mblock_base && pfn <= it->mi_mblock_end); 462 463 /* convert RA to PA for accurate color calculation */ 464 if (it->mi_init) { 465 /* first call after it, so cache these values */ 466 it->mi_hash_ceq_mask = 467 n2_color2hash(ceq_mask, szc, it->mi_mnode_mask); 468 it->mi_hash_color = 469 n2_color2hash(color, szc, it->mi_mnode); 470 it->mi_init = 0; 471 } else { 472 ASSERT(it->mi_hash_ceq_mask == 473 n2_color2hash(ceq_mask, szc, it->mi_mnode_mask)); 474 ASSERT(it->mi_hash_color == 475 n2_color2hash(color, szc, it->mi_mnode)); 476 } 477 ceq_mask = it->mi_hash_ceq_mask; 478 color = it->mi_hash_color; 479 pfn += it->mi_ra_to_pa; 480 481 /* restart here when we switch memblocks */ 482 next_mem_block: 483 if (szc <= TTE64K) { 484 pfnmn = PAPFN_2_MNODE(pfn); 485 } 486 if (((page_papfn_2_color_cpu(pfn, szc) ^ color) & ceq_mask) == 0 && 487 (szc > TTE64K || pfnmn == it->mi_mnode)) { 488 489 /* we start from the page with correct color */ 490 if (szc >= TTE512K) { 491 if (szc >= TTE4M) { 492 /* page color is PA[32:28] */ 493 pfn_ceq_mask = ceq_mask << 15; 494 } else { 495 /* page color is PA[32:28].PA[19:19] */ 496 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 497 ((ceq_mask >> 1) << 15); 498 } 499 npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 500 goto done; 501 } else { 502 /* 503 * We deal 64K or 8K page. Check if we could the 504 * satisfy the request without changing PA[32:28] 505 */ 506 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 507 pfn_ceq_mask |= it->mi_mnode_pfn_mask; 508 npfn = ADD_MASKED(pfn, pstep, pfn_ceq_mask, mask); 509 510 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 511 goto done; 512 513 /* 514 * for next pfn we have to change bits PA[32:28] 515 * set PA[63:28] and PA[19:18] of the next pfn 516 */ 517 npfn = (pfn >> 15) << 15; 518 npfn |= (ceq_mask & color & 3) << 5; 519 pfn_ceq_mask = (szc == TTE8K) ? 0 : 520 (ceq_mask & 0x1c) << 13; 521 pfn_ceq_mask |= it->mi_mnode_pfn_mask; 522 npfn = ADD_MASKED(npfn, (1 << 15), pfn_ceq_mask, mask); 523 524 /* 525 * set bits PA[17:13] to match the color 526 */ 527 npfn |= ((npfn >> 15) ^ (color >> 2)) & (ceq_mask >> 2); 528 goto done; 529 } 530 } 531 532 /* 533 * we start from the page with incorrect color - rare case 534 */ 535 if (szc >= TTE512K) { 536 if (szc >= TTE4M) { 537 /* page color is in bits PA[32:28] */ 538 npfn = ((pfn >> 20) << 20) | (color << 15); 539 pfn_ceq_mask = (ceq_mask << 15) | 0x7fff; 540 } else { 541 /* try get the right color by changing bit PA[19:19] */ 542 npfn = pfn + pstep; 543 if (((page_papfn_2_color_cpu(npfn, szc) ^ color) & 544 ceq_mask) == 0) 545 goto done; 546 547 /* page color is PA[32:28].PA[19:19] */ 548 pfn_ceq_mask = ((ceq_mask & 1) << 6) | 549 ((ceq_mask >> 1) << 15) | (0xff << 7); 550 pfn_color = ((color & 1) << 6) | ((color >> 1) << 15); 551 npfn = ((pfn >> 20) << 20) | pfn_color; 552 } 553 554 while (npfn <= pfn) { 555 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, mask); 556 } 557 goto done; 558 } 559 560 /* 561 * We deal 64K or 8K page of incorrect color. 562 * Try correcting color without changing PA[32:28] 563 */ 564 pfn_ceq_mask = ((ceq_mask & 3) << 5) | (ceq_mask >> 2); 565 pfn_color = ((color & 3) << 5) | (color >> 2); 566 if (pfnmn == it->mi_mnode) { 567 npfn = (pfn & ~(pfn_t)0x7f); 568 npfn |= (((pfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 569 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 570 571 if (((page_papfn_2_color_cpu(npfn, szc) ^ color) & 572 ceq_mask) == 0) { 573 /* the color is fixed - find the next page */ 574 pfn_ceq_mask |= it->mi_mnode_pfn_mask; 575 while (npfn <= pfn) { 576 npfn = ADD_MASKED(npfn, pstep, pfn_ceq_mask, 577 mask); 578 } 579 if ((((npfn ^ pfn) >> 15) & 0x1f) == 0) 580 goto done; 581 } 582 } 583 584 /* to fix the color need to touch PA[32:28] */ 585 npfn = (szc == TTE8K) ? ((pfn >> 15) << 15) : 586 (((pfn >> 18) << 18) | ((color & 0x1c) << 13)); 587 588 /* fix mnode if input pfn is in the wrong mnode. */ 589 if ((pfnmn = PAPFN_2_MNODE(npfn)) != it->mi_mnode) { 590 npfn += ((it->mi_mnode - pfnmn) & it->mi_mnode_mask) << 591 it->mi_mnode_pfn_shift; 592 } 593 594 tmpmask = (szc == TTE8K) ? 0 : (ceq_mask & 0x1c) << 13; 595 tmpmask |= it->mi_mnode_pfn_mask; 596 597 while (npfn <= pfn) { 598 npfn = ADD_MASKED(npfn, (1 << 15), tmpmask, mask); 599 } 600 601 /* set bits PA[19:13] to match the color */ 602 npfn |= (((npfn >> 15) & 0x1f) ^ pfn_color) & pfn_ceq_mask; 603 npfn = (szc == TTE64K) ? (npfn & ~(pfn_t)0x7) : npfn; 604 605 done: 606 ASSERT(((page_papfn_2_color_cpu(npfn, szc) ^ color) & ceq_mask) == 0); 607 ASSERT(PAPFN_2_MNODE(npfn) == it->mi_mnode); 608 609 /* PA to RA */ 610 npfn -= it->mi_ra_to_pa; 611 612 /* check for possible memblock switch */ 613 if (npfn > it->mi_mblock_end) { 614 pfn = plat_mem_node_iterator_init(npfn, it->mi_mnode, it, 0); 615 if (pfn == (pfn_t)-1) 616 return (pfn); 617 ASSERT(pfn >= it->mi_mblock_base && pfn <= it->mi_mblock_end); 618 pfn += it->mi_ra_to_pa; 619 goto next_mem_block; 620 } 621 622 return (npfn); 623 } 624 625 /* 626 * init page coloring 627 * VF encodes node_id for an L-group in either bit 30 or 31:30, 628 * which effectively reduces the number of colors available per mnode. 629 */ 630 void 631 page_coloring_init_cpu() 632 { 633 int i; 634 uchar_t id; 635 uchar_t lo; 636 uchar_t hi; 637 n2color_t m; 638 mem_node_iterator_t it; 639 static uchar_t idmask[] = {0, 0x7, 0x1f, 0x1f, 0x1f, 0x1f}; 640 641 (void) plat_mem_node_iterator_init(0, 0, &it, 1); 642 for (i = 0; i < mmu_page_sizes; i++) { 643 memset(&m, 0, sizeof (m)); 644 id = it.mi_mnode_pfn_mask >> 15; /* node id mask */ 645 id &= idmask[i]; 646 lo = lowbit(id); 647 if (lo > 0) { 648 hi = highbit(id); 649 m.nnbits = hi - lo + 1; 650 m.nnmask = (1 << m.nnbits) - 1; 651 lo += nhbits[i] - 5; 652 m.lomask = (1 << (lo - 1)) - 1; 653 m.lobits = lo - 1; 654 } 655 hw_page_array[i].hp_colors = 1 << (nhbits[i] - m.nnbits); 656 n2color[i] = m; 657 } 658 } 659 660 /* 661 * group colorequiv colors on N2 by low order bits of the color first 662 */ 663 void 664 page_set_colorequiv_arr_cpu(void) 665 { 666 static uint_t nequiv_shades_log2[MMU_PAGE_SIZES] = {2, 5, 0, 0, 0, 0}; 667 668 nequiv_shades_log2[1] -= n2color[1].nnbits; 669 if (colorequiv > 1) { 670 int i; 671 uint_t sv_a = lowbit(colorequiv) - 1; 672 673 if (sv_a > 15) 674 sv_a = 15; 675 676 for (i = 0; i < MMU_PAGE_SIZES; i++) { 677 uint_t colors; 678 uint_t a = sv_a; 679 680 if ((colors = hw_page_array[i].hp_colors) <= 1) 681 continue; 682 while ((colors >> a) == 0) 683 a--; 684 if (a > (colorequivszc[i] & 0xf) + 685 (colorequivszc[i] >> 4)) { 686 if (a <= nequiv_shades_log2[i]) { 687 colorequivszc[i] = (uchar_t)a; 688 } else { 689 colorequivszc[i] = 690 ((a - nequiv_shades_log2[i]) << 4) | 691 nequiv_shades_log2[i]; 692 } 693 } 694 } 695 } 696 } 697