1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/archsystm.h> 31 #include <sys/machparam.h> 32 #include <sys/machsystm.h> 33 #include <sys/cpu.h> 34 #include <sys/elf_SPARC.h> 35 #include <vm/hat_sfmmu.h> 36 #include <vm/page.h> 37 #include <sys/cpuvar.h> 38 #include <sys/async.h> 39 #include <sys/cmn_err.h> 40 #include <sys/debug.h> 41 #include <sys/dditypes.h> 42 #include <sys/sunddi.h> 43 #include <sys/cpu_module.h> 44 #include <sys/prom_debug.h> 45 #include <sys/vmsystm.h> 46 #include <sys/prom_plat.h> 47 #include <sys/sysmacros.h> 48 #include <sys/intreg.h> 49 #include <sys/machtrap.h> 50 #include <sys/ontrap.h> 51 #include <sys/ivintr.h> 52 #include <sys/atomic.h> 53 #include <sys/panic.h> 54 #include <sys/dtrace.h> 55 #include <vm/seg_spt.h> 56 #include <sys/simulate.h> 57 #include <sys/fault.h> 58 59 60 uint_t root_phys_addr_lo_mask = 0xffffffffU; 61 62 void 63 cpu_setup(void) 64 { 65 extern int mmu_exported_pagesize_mask; 66 char *generic_isa_set[] = { 67 "sparcv9+vis", 68 "sparcv8plus+vis", 69 NULL 70 }; 71 72 /* 73 * The setup common to all CPU modules is done in cpu_setup_common 74 * routine. 75 */ 76 cpu_setup_common(generic_isa_set); 77 78 cache |= (CACHE_PTAG | CACHE_IOCOHERENT); 79 80 if (broken_md_flag) { 81 /* 82 * Turn on the missing bits supported by sun4v architecture in 83 * MMU pagesize mask returned by MD. 84 */ 85 mmu_exported_pagesize_mask |= DEFAULT_SUN4V_MMU_PAGESIZE_MASK; 86 } else { 87 /* 88 * According to sun4v architecture each processor must 89 * support 8K, 64K and 4M page sizes. If any of the page 90 * size is missing from page size mask, then panic. 91 */ 92 if ((mmu_exported_pagesize_mask & 93 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) != 94 DEFAULT_SUN4V_MMU_PAGESIZE_MASK) 95 cmn_err(CE_PANIC, "machine description" 96 " does not have required sun4v page sizes" 97 " 8K, 64K and 4M: MD mask is 0x%x", 98 mmu_exported_pagesize_mask); 99 } 100 101 /* 102 * If processor supports the subset of full 64-bit virtual 103 * address space, then set VA hole accordingly. 104 */ 105 if (va_bits < VA_ADDRESS_SPACE_BITS) { 106 hole_start = (caddr_t)(1ull << (va_bits - 1)); 107 hole_end = (caddr_t)(0ull - (1ull << (va_bits - 1))); 108 } else { 109 hole_start = hole_end = 0; 110 } 111 } 112 113 void 114 cpu_fiximp(struct cpu_node *cpunode) 115 { 116 /* 117 * The Cache node is optional in MD. Therefore in case "Cache" 118 * does not exists in MD, set the default L2 cache associativity, 119 * size, linesize for generic CPU module. 120 */ 121 if (cpunode->ecache_size == 0) 122 cpunode->ecache_size = 0x100000; 123 if (cpunode->ecache_linesize == 0) 124 cpunode->ecache_linesize = 64; 125 if (cpunode->ecache_associativity == 0) 126 cpunode->ecache_associativity = 1; 127 } 128 129 void 130 dtrace_flush_sec(uintptr_t addr) 131 { 132 pfn_t pfn; 133 proc_t *procp = ttoproc(curthread); 134 page_t *pp; 135 caddr_t va; 136 137 pfn = hat_getpfnum(procp->p_as->a_hat, (void *)addr); 138 if (pfn != -1) { 139 ASSERT(pf_is_memory(pfn)); 140 pp = page_numtopp_noreclaim(pfn, SE_SHARED); 141 if (pp != NULL) { 142 va = ppmapin(pp, PROT_READ | PROT_WRITE, (void *)addr); 143 /* sparc needs 8-byte align */ 144 doflush((caddr_t)((uintptr_t)va & -8l)); 145 ppmapout(va); 146 page_unlock(pp); 147 } 148 } 149 } 150 151 void 152 cpu_init_private(struct cpu *cp) 153 { 154 /* 155 * The cpu_ipipe field is initialized based on the execution 156 * unit sharing information from the Machine Description table. 157 * It defaults to the CPU id in the absence of such information. 158 */ 159 cp->cpu_m.cpu_ipipe = cpunodes[cp->cpu_id].exec_unit_mapping; 160 if (cp->cpu_m.cpu_ipipe == NO_EU_MAPPING_FOUND) 161 cp->cpu_m.cpu_ipipe = (id_t)(cp->cpu_id); 162 } 163 164 void 165 cpu_uninit_private(struct cpu *cp) 166 { 167 } 168 169 /* 170 * Invalidate a TSB. Since this needs to work on all sun4v 171 * architecture compliant processors, we use the old method of 172 * walking the TSB, setting each tag to TSBTAG_INVALID. 173 */ 174 void 175 cpu_inv_tsb(caddr_t tsb_base, uint_t tsb_bytes) 176 { 177 struct tsbe *tsbaddr; 178 179 for (tsbaddr = (struct tsbe *)tsb_base; 180 (uintptr_t)tsbaddr < (uintptr_t)(tsb_base + tsb_bytes); 181 tsbaddr++) { 182 tsbaddr->tte_tag.tag_inthi = TSBTAG_INVALID; 183 } 184 } 185 186 /* 187 * Sun4v kernel must emulate code a generic sun4v processor may not support 188 * i.e. VIS1 and VIS2. 189 */ 190 #define IS_FLOAT(i) (((i) & 0x1000000) != 0) 191 #define IS_IBIT_SET(x) (x & 0x2000) 192 #define IS_VIS1(op, op3)(op == 2 && op3 == 0x36) 193 #define IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi) \ 194 (op == 3 && (op3 == IOP_V8_LDDFA || \ 195 op3 == IOP_V8_STDFA) && asi > ASI_SNFL) 196 int 197 vis1_partial_support(struct regs *rp, k_siginfo_t *siginfo, uint_t *fault) 198 { 199 char *badaddr; 200 int instr; 201 uint_t optype, op3, asi; 202 uint_t rd, ignor; 203 204 if (!USERMODE(rp->r_tstate)) 205 return (-1); 206 207 instr = fetch_user_instr((caddr_t)rp->r_pc); 208 209 rd = (instr >> 25) & 0x1f; 210 optype = (instr >> 30) & 0x3; 211 op3 = (instr >> 19) & 0x3f; 212 ignor = (instr >> 5) & 0xff; 213 if (IS_IBIT_SET(instr)) { 214 asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 215 TSTATE_ASI_MASK); 216 } else { 217 asi = ignor; 218 } 219 220 if (!IS_VIS1(optype, op3) && 221 !IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) { 222 return (-1); 223 } 224 switch (simulate_unimp(rp, &badaddr)) { 225 case SIMU_RETRY: 226 break; /* regs are already set up */ 227 /*NOTREACHED*/ 228 229 case SIMU_SUCCESS: 230 /* 231 * skip the successfully 232 * simulated instruction 233 */ 234 rp->r_pc = rp->r_npc; 235 rp->r_npc += 4; 236 break; 237 /*NOTREACHED*/ 238 239 case SIMU_FAULT: 240 siginfo->si_signo = SIGSEGV; 241 siginfo->si_code = SEGV_MAPERR; 242 siginfo->si_addr = badaddr; 243 *fault = FLTBOUNDS; 244 break; 245 246 case SIMU_DZERO: 247 siginfo->si_signo = SIGFPE; 248 siginfo->si_code = FPE_INTDIV; 249 siginfo->si_addr = (caddr_t)rp->r_pc; 250 *fault = FLTIZDIV; 251 break; 252 253 case SIMU_UNALIGN: 254 siginfo->si_signo = SIGBUS; 255 siginfo->si_code = BUS_ADRALN; 256 siginfo->si_addr = badaddr; 257 *fault = FLTACCESS; 258 break; 259 260 case SIMU_ILLEGAL: 261 default: 262 siginfo->si_signo = SIGILL; 263 op3 = (instr >> 19) & 0x3F; 264 if ((IS_FLOAT(instr) && (op3 == IOP_V8_STQFA) || 265 (op3 == IOP_V8_STDFA))) 266 siginfo->si_code = ILL_ILLADR; 267 else 268 siginfo->si_code = ILL_ILLOPC; 269 siginfo->si_addr = (caddr_t)rp->r_pc; 270 *fault = FLTILL; 271 break; 272 } 273 return (0); 274 } 275 276 /* 277 * Trapstat support for generic sun4v processor 278 */ 279 int 280 cpu_trapstat_conf(int cmd) 281 { 282 int status; 283 284 switch (cmd) { 285 case CPU_TSTATCONF_INIT: 286 case CPU_TSTATCONF_FINI: 287 case CPU_TSTATCONF_ENABLE: 288 case CPU_TSTATCONF_DISABLE: 289 status = ENOTSUP; 290 break; 291 292 default: 293 status = EINVAL; 294 break; 295 } 296 return (status); 297 } 298 299 /*ARGSUSED*/ 300 void 301 cpu_trapstat_data(void *buf, uint_t tstat_pgszs) 302 { 303 } 304