1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 27 /* All Rights Reserved */ 28 29 /* 30 * Portions of this source code were derived from Berkeley 4.3 BSD 31 * under license from the Regents of the University of California. 32 */ 33 34 #pragma ident "%Z%%M% %I% %E% SMI" 35 36 /* 37 * UNIX machine dependent virtual memory support. 38 */ 39 40 #include <sys/vm.h> 41 #include <sys/exec.h> 42 #include <sys/cmn_err.h> 43 #include <sys/cpu_module.h> 44 #include <sys/cpu.h> 45 #include <sys/elf_SPARC.h> 46 #include <sys/archsystm.h> 47 #include <vm/hat_sfmmu.h> 48 #include <sys/memnode.h> 49 #include <sys/mem_cage.h> 50 #include <vm/vm_dep.h> 51 52 #if defined(__sparcv9) && defined(SF_ERRATA_57) 53 caddr_t errata57_limit; 54 #endif 55 56 uint_t page_colors = 0; 57 uint_t page_colors_mask = 0; 58 uint_t page_coloring_shift = 0; 59 int consistent_coloring; 60 int update_proc_pgcolorbase_after_fork = 0; 61 62 uint_t mmu_page_sizes = DEFAULT_MMU_PAGE_SIZES; 63 uint_t max_mmu_page_sizes = MMU_PAGE_SIZES; 64 uint_t mmu_hashcnt = DEFAULT_MAX_HASHCNT; 65 uint_t max_mmu_hashcnt = MAX_HASHCNT; 66 size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 67 68 /* 69 * The sun4u hardware mapping sizes which will always be supported are 70 * 8K, 64K, 512K and 4M. If sun4u based machines need to support other 71 * page sizes, platform or cpu specific routines need to modify the value. 72 * The base pagesize (p_szc == 0) must always be supported by the hardware. 73 */ 74 int mmu_exported_pagesize_mask = (1 << TTE8K) | (1 << TTE64K) | 75 (1 << TTE512K) | (1 << TTE4M); 76 uint_t mmu_exported_page_sizes; 77 78 uint_t szc_2_userszc[MMU_PAGE_SIZES]; 79 uint_t userszc_2_szc[MMU_PAGE_SIZES]; 80 81 extern uint_t vac_colors_mask; 82 extern int vac_shift; 83 84 hw_pagesize_t hw_page_array[] = { 85 {MMU_PAGESIZE, MMU_PAGESHIFT, 0, MMU_PAGESIZE >> MMU_PAGESHIFT}, 86 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, 0, 87 MMU_PAGESIZE64K >> MMU_PAGESHIFT}, 88 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 0, 89 MMU_PAGESIZE512K >> MMU_PAGESHIFT}, 90 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, 0, MMU_PAGESIZE4M >> MMU_PAGESHIFT}, 91 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, 0, 92 MMU_PAGESIZE32M >> MMU_PAGESHIFT}, 93 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 0, 94 MMU_PAGESIZE256M >> MMU_PAGESHIFT}, 95 {0, 0, 0, 0} 96 }; 97 98 /* 99 * Maximum page size used to map 64-bit memory segment kmem64_base..kmem64_end 100 */ 101 int max_bootlp_tteszc = TTE4M; 102 103 /* 104 * use_text_pgsz64k and use_text_pgsz512k allow the user to turn on these 105 * additional text page sizes for USIII-IV+ and OPL by changing the default 106 * values via /etc/system. 107 */ 108 int use_text_pgsz64K = 0; 109 int use_text_pgsz512K = 0; 110 111 /* 112 * Maximum and default segment size tunables for user heap, stack, private 113 * and shared anonymous memory, and user text and initialized data. 114 */ 115 size_t max_uheap_lpsize = MMU_PAGESIZE4M; 116 size_t default_uheap_lpsize = MMU_PAGESIZE; 117 size_t max_ustack_lpsize = MMU_PAGESIZE4M; 118 size_t default_ustack_lpsize = MMU_PAGESIZE; 119 size_t max_privmap_lpsize = MMU_PAGESIZE4M; 120 size_t max_uidata_lpsize = MMU_PAGESIZE; 121 size_t max_utext_lpsize = MMU_PAGESIZE4M; 122 size_t max_shm_lpsize = MMU_PAGESIZE4M; 123 124 void 125 adjust_data_maxlpsize(size_t ismpagesize) 126 { 127 if (max_uheap_lpsize == MMU_PAGESIZE4M) { 128 max_uheap_lpsize = ismpagesize; 129 } 130 if (max_ustack_lpsize == MMU_PAGESIZE4M) { 131 max_ustack_lpsize = ismpagesize; 132 } 133 if (max_privmap_lpsize == MMU_PAGESIZE4M) { 134 max_privmap_lpsize = ismpagesize; 135 } 136 if (max_shm_lpsize == MMU_PAGESIZE4M) { 137 max_shm_lpsize = ismpagesize; 138 } 139 } 140 141 /* 142 * map_addr_proc() is the routine called when the system is to 143 * choose an address for the user. We will pick an address 144 * range which is just below the current stack limit. The 145 * algorithm used for cache consistency on machines with virtual 146 * address caches is such that offset 0 in the vnode is always 147 * on a shm_alignment'ed aligned address. Unfortunately, this 148 * means that vnodes which are demand paged will not be mapped 149 * cache consistently with the executable images. When the 150 * cache alignment for a given object is inconsistent, the 151 * lower level code must manage the translations so that this 152 * is not seen here (at the cost of efficiency, of course). 153 * 154 * Every mapping will have a redzone of a single page on either side of 155 * the request. This is done to leave one page unmapped between segments. 156 * This is not required, but it's useful for the user because if their 157 * program strays across a segment boundary, it will catch a fault 158 * immediately making debugging a little easier. Currently the redzone 159 * is mandatory. 160 * 161 * 162 * addrp is a value/result parameter. 163 * On input it is a hint from the user to be used in a completely 164 * machine dependent fashion. For MAP_ALIGN, addrp contains the 165 * minimal alignment, which must be some "power of two" multiple of 166 * pagesize. 167 * 168 * On output it is NULL if no address can be found in the current 169 * processes address space or else an address that is currently 170 * not mapped for len bytes with a page of red zone on either side. 171 * If vacalign is true, then the selected address will obey the alignment 172 * constraints of a vac machine based on the given off value. 173 */ 174 /*ARGSUSED4*/ 175 void 176 map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign, 177 caddr_t userlimit, struct proc *p, uint_t flags) 178 { 179 struct as *as = p->p_as; 180 caddr_t addr; 181 caddr_t base; 182 size_t slen; 183 uintptr_t align_amount; 184 int allow_largepage_alignment = 1; 185 186 base = p->p_brkbase; 187 if (userlimit < as->a_userlimit) { 188 /* 189 * This happens when a program wants to map something in 190 * a range that's accessible to a program in a smaller 191 * address space. For example, a 64-bit program might 192 * be calling mmap32(2) to guarantee that the returned 193 * address is below 4Gbytes. 194 */ 195 ASSERT(userlimit > base); 196 slen = userlimit - base; 197 } else { 198 slen = p->p_usrstack - base - (((size_t)rctl_enforced_value( 199 rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET) 200 & PAGEMASK); 201 } 202 203 /* Make len be a multiple of PAGESIZE */ 204 len = (len + PAGEOFFSET) & PAGEMASK; 205 206 /* 207 * If the request is larger than the size of a particular 208 * mmu level, then we use that level to map the request. 209 * But this requires that both the virtual and the physical 210 * addresses be aligned with respect to that level, so we 211 * do the virtual bit of nastiness here. 212 * 213 * For 32-bit processes, only those which have specified 214 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise 215 * we can potentially waste up to 256MB of the 4G process address 216 * space just for alignment. 217 */ 218 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 || 219 ((uintptr_t)*addrp) != 0)) { 220 allow_largepage_alignment = 0; 221 } 222 if ((mmu_page_sizes == max_mmu_page_sizes) && 223 allow_largepage_alignment && 224 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */ 225 align_amount = MMU_PAGESIZE256M; 226 } else if ((mmu_page_sizes == max_mmu_page_sizes) && 227 allow_largepage_alignment && 228 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */ 229 align_amount = MMU_PAGESIZE32M; 230 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */ 231 align_amount = MMU_PAGESIZE4M; 232 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */ 233 align_amount = MMU_PAGESIZE512K; 234 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */ 235 align_amount = MMU_PAGESIZE64K; 236 } else { 237 /* 238 * Align virtual addresses on a 64K boundary to ensure 239 * that ELF shared libraries are mapped with the appropriate 240 * alignment constraints by the run-time linker. 241 */ 242 align_amount = ELF_SPARC_MAXPGSZ; 243 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) && 244 ((uintptr_t)*addrp < align_amount)) 245 align_amount = (uintptr_t)*addrp; 246 } 247 248 /* 249 * 64-bit processes require 1024K alignment of ELF shared libraries. 250 */ 251 if (p->p_model == DATAMODEL_LP64) 252 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ); 253 #ifdef VAC 254 if (vac && vacalign && (align_amount < shm_alignment)) 255 align_amount = shm_alignment; 256 #endif 257 258 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) { 259 align_amount = (uintptr_t)*addrp; 260 } 261 262 ASSERT(ISP2(align_amount)); 263 ASSERT(align_amount == 0 || align_amount >= PAGESIZE); 264 265 /* 266 * Look for a large enough hole starting below the stack limit. 267 * After finding it, use the upper part. 268 */ 269 as_purge(as); 270 off = off & (align_amount - 1); 271 if (as_gap_aligned(as, len, &base, &slen, AH_HI, NULL, align_amount, 272 PAGESIZE, off) == 0) { 273 caddr_t as_addr; 274 275 /* 276 * addr is the highest possible address to use since we have 277 * a PAGESIZE redzone at the beginning and end. 278 */ 279 addr = base + slen - (PAGESIZE + len); 280 as_addr = addr; 281 /* 282 * Round address DOWN to the alignment amount and 283 * add the offset in. 284 * If addr is greater than as_addr, len would not be large 285 * enough to include the redzone, so we must adjust down 286 * by the alignment amount. 287 */ 288 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l))); 289 addr += (long)off; 290 if (addr > as_addr) { 291 addr -= align_amount; 292 } 293 294 ASSERT(addr > base); 295 ASSERT(addr + len < base + slen); 296 ASSERT(((uintptr_t)addr & (align_amount - 1l)) == 297 ((uintptr_t)(off))); 298 *addrp = addr; 299 300 #if defined(SF_ERRATA_57) 301 if (AS_TYPE_64BIT(as) && addr < errata57_limit) { 302 *addrp = NULL; 303 } 304 #endif 305 } else { 306 *addrp = NULL; /* no more virtual space */ 307 } 308 } 309 310 /* 311 * Platform-dependent page scrub call. 312 */ 313 void 314 pagescrub(page_t *pp, uint_t off, uint_t len) 315 { 316 /* 317 * For now, we rely on the fact that pagezero() will 318 * always clear UEs. 319 */ 320 pagezero(pp, off, len); 321 } 322 323 /*ARGSUSED*/ 324 void 325 sync_data_memory(caddr_t va, size_t len) 326 { 327 cpu_flush_ecache(); 328 } 329 330 /* 331 * platform specific large pages for kernel heap support 332 */ 333 void 334 mmu_init_kcontext() 335 { 336 extern void set_kcontextreg(); 337 338 if (kcontextreg) 339 set_kcontextreg(); 340 } 341 342 void 343 contig_mem_init(void) 344 { 345 /* not applicable to sun4u */ 346 } 347 348 /*ARGSUSED*/ 349 caddr_t 350 contig_mem_prealloc(caddr_t alloc_base, pgcnt_t npages) 351 { 352 /* not applicable to sun4u */ 353 return (alloc_base); 354 } 355 356 size_t 357 exec_get_spslew(void) 358 { 359 return (0); 360 } 361