1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* Copyright (c) 1984, 1986, 1987, 1988, 1989 AT&T */ 27 /* All Rights Reserved */ 28 29 /* 30 * Portions of this source code were derived from Berkeley 4.3 BSD 31 * under license from the Regents of the University of California. 32 */ 33 34 #pragma ident "%Z%%M% %I% %E% SMI" 35 36 /* 37 * UNIX machine dependent virtual memory support. 38 */ 39 40 #include <sys/vm.h> 41 #include <sys/exec.h> 42 #include <sys/cmn_err.h> 43 #include <sys/cpu_module.h> 44 #include <sys/cpu.h> 45 #include <sys/elf_SPARC.h> 46 #include <sys/archsystm.h> 47 #include <vm/hat_sfmmu.h> 48 #include <sys/memnode.h> 49 #include <sys/mem_cage.h> 50 #include <vm/vm_dep.h> 51 52 #if defined(__sparcv9) && defined(SF_ERRATA_57) 53 caddr_t errata57_limit; 54 #endif 55 56 uint_t page_colors = 0; 57 uint_t page_colors_mask = 0; 58 uint_t page_coloring_shift = 0; 59 int consistent_coloring; 60 61 uint_t mmu_page_sizes = DEFAULT_MMU_PAGE_SIZES; 62 uint_t max_mmu_page_sizes = MMU_PAGE_SIZES; 63 uint_t mmu_hashcnt = DEFAULT_MAX_HASHCNT; 64 uint_t max_mmu_hashcnt = MAX_HASHCNT; 65 size_t mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 66 67 /* 68 * The sun4u hardware mapping sizes which will always be supported are 69 * 8K, 64K, 512K and 4M. If sun4u based machines need to support other 70 * page sizes, platform or cpu specific routines need to modify the value. 71 * The base pagesize (p_szc == 0) must always be supported by the hardware. 72 */ 73 int mmu_exported_pagesize_mask = (1 << TTE8K) | (1 << TTE64K) | 74 (1 << TTE512K) | (1 << TTE4M); 75 uint_t mmu_exported_page_sizes; 76 77 uint_t szc_2_userszc[MMU_PAGE_SIZES]; 78 uint_t userszc_2_szc[MMU_PAGE_SIZES]; 79 80 extern uint_t vac_colors_mask; 81 extern int vac_shift; 82 83 hw_pagesize_t hw_page_array[] = { 84 {MMU_PAGESIZE, MMU_PAGESHIFT, MMU_PAGESIZE >> MMU_PAGESHIFT}, 85 {MMU_PAGESIZE64K, MMU_PAGESHIFT64K, MMU_PAGESIZE64K >> MMU_PAGESHIFT}, 86 {MMU_PAGESIZE512K, MMU_PAGESHIFT512K, 87 MMU_PAGESIZE512K >> MMU_PAGESHIFT}, 88 {MMU_PAGESIZE4M, MMU_PAGESHIFT4M, MMU_PAGESIZE4M >> MMU_PAGESHIFT}, 89 {MMU_PAGESIZE32M, MMU_PAGESHIFT32M, MMU_PAGESIZE32M >> MMU_PAGESHIFT}, 90 {MMU_PAGESIZE256M, MMU_PAGESHIFT256M, 91 MMU_PAGESIZE256M >> MMU_PAGESHIFT}, 92 {0, 0, 0} 93 }; 94 95 /* 96 * use_text_pgsz64k, use_initdata_pgsz64k and use_text_pgsz4m 97 * can be set in platform or CPU specific code but user can change the 98 * default values via /etc/system. 99 */ 100 101 int use_text_pgsz64k = 0; 102 int use_text_pgsz4m = 0; 103 int use_initdata_pgsz64k = 0; 104 105 /* 106 * disable_text_largepages and disable_initdata_largepages bitmaks are set in 107 * platform or CPU specific code to disable page sizes that should not be 108 * used. These variables normally shouldn't be changed via /etc/system. A 109 * particular page size for text or inititialized data will be used by default 110 * if both one of use_* variables is set to 1 AND this page size is not 111 * disabled in the corresponding disable_* bitmask variable. 112 */ 113 114 int disable_text_largepages = (1 << TTE4M) | (1 << TTE64K); 115 int disable_initdata_largepages = (1 << TTE64K); 116 117 /* 118 * Minimum segment size tunables before 64K or 4M large pages 119 * should be used to map it. 120 */ 121 size_t text_pgsz64k_minsize = MMU_PAGESIZE64K; 122 size_t text_pgsz4m_minsize = MMU_PAGESIZE4M; 123 size_t initdata_pgsz64k_minsize = MMU_PAGESIZE64K; 124 125 size_t max_shm_lpsize = ULONG_MAX; 126 127 /* 128 * Platforms with smaller or larger TLBs may wish to change this. Most 129 * sun4u platforms can hold 1024 8K entries by default and most processes 130 * are observed to be < 6MB on these machines, so we decide to move up 131 * here to give ourselves some wiggle room for other, smaller segments. 132 */ 133 int auto_lpg_tlb_threshold = 768; 134 int auto_lpg_minszc = TTE4M; 135 int auto_lpg_maxszc = TTE4M; 136 size_t auto_lpg_heap_default = MMU_PAGESIZE; 137 size_t auto_lpg_stack_default = MMU_PAGESIZE; 138 size_t auto_lpg_va_default = MMU_PAGESIZE; 139 size_t auto_lpg_remap_threshold = 0; 140 /* 141 * Number of pages in 1 GB. Don't enable automatic large pages if we have 142 * fewer than this many pages. 143 */ 144 pgcnt_t auto_lpg_min_physmem = 1 << (30 - MMU_PAGESHIFT); 145 146 /* 147 * map_addr_proc() is the routine called when the system is to 148 * choose an address for the user. We will pick an address 149 * range which is just below the current stack limit. The 150 * algorithm used for cache consistency on machines with virtual 151 * address caches is such that offset 0 in the vnode is always 152 * on a shm_alignment'ed aligned address. Unfortunately, this 153 * means that vnodes which are demand paged will not be mapped 154 * cache consistently with the executable images. When the 155 * cache alignment for a given object is inconsistent, the 156 * lower level code must manage the translations so that this 157 * is not seen here (at the cost of efficiency, of course). 158 * 159 * addrp is a value/result parameter. 160 * On input it is a hint from the user to be used in a completely 161 * machine dependent fashion. For MAP_ALIGN, addrp contains the 162 * minimal alignment. 163 * 164 * On output it is NULL if no address can be found in the current 165 * processes address space or else an address that is currently 166 * not mapped for len bytes with a page of red zone on either side. 167 * If vacalign is true, then the selected address will obey the alignment 168 * constraints of a vac machine based on the given off value. 169 */ 170 /*ARGSUSED4*/ 171 void 172 map_addr_proc(caddr_t *addrp, size_t len, offset_t off, int vacalign, 173 caddr_t userlimit, struct proc *p, uint_t flags) 174 { 175 struct as *as = p->p_as; 176 caddr_t addr; 177 caddr_t base; 178 size_t slen; 179 uintptr_t align_amount; 180 int allow_largepage_alignment = 1; 181 182 base = p->p_brkbase; 183 if (userlimit < as->a_userlimit) { 184 /* 185 * This happens when a program wants to map something in 186 * a range that's accessible to a program in a smaller 187 * address space. For example, a 64-bit program might 188 * be calling mmap32(2) to guarantee that the returned 189 * address is below 4Gbytes. 190 */ 191 ASSERT(userlimit > base); 192 slen = userlimit - base; 193 } else { 194 slen = p->p_usrstack - base - (((size_t)rctl_enforced_value( 195 rctlproc_legacy[RLIMIT_STACK], p->p_rctls, p) + PAGEOFFSET) 196 & PAGEMASK); 197 } 198 len = (len + PAGEOFFSET) & PAGEMASK; 199 200 /* 201 * Redzone for each side of the request. This is done to leave 202 * one page unmapped between segments. This is not required, but 203 * it's useful for the user because if their program strays across 204 * a segment boundary, it will catch a fault immediately making 205 * debugging a little easier. 206 */ 207 len += (2 * PAGESIZE); 208 209 /* 210 * If the request is larger than the size of a particular 211 * mmu level, then we use that level to map the request. 212 * But this requires that both the virtual and the physical 213 * addresses be aligned with respect to that level, so we 214 * do the virtual bit of nastiness here. 215 * 216 * For 32-bit processes, only those which have specified 217 * MAP_ALIGN or an addr will be aligned on a page size > 4MB. Otherwise 218 * we can potentially waste up to 256MB of the 4G process address 219 * space just for alignment. 220 */ 221 if (p->p_model == DATAMODEL_ILP32 && ((flags & MAP_ALIGN) == 0 || 222 ((uintptr_t)*addrp) != 0)) { 223 allow_largepage_alignment = 0; 224 } 225 if ((mmu_page_sizes == max_mmu_page_sizes) && 226 allow_largepage_alignment && 227 (len >= MMU_PAGESIZE256M)) { /* 256MB mappings */ 228 align_amount = MMU_PAGESIZE256M; 229 } else if ((mmu_page_sizes == max_mmu_page_sizes) && 230 allow_largepage_alignment && 231 (len >= MMU_PAGESIZE32M)) { /* 32MB mappings */ 232 align_amount = MMU_PAGESIZE32M; 233 } else if (len >= MMU_PAGESIZE4M) { /* 4MB mappings */ 234 align_amount = MMU_PAGESIZE4M; 235 } else if (len >= MMU_PAGESIZE512K) { /* 512KB mappings */ 236 align_amount = MMU_PAGESIZE512K; 237 } else if (len >= MMU_PAGESIZE64K) { /* 64KB mappings */ 238 align_amount = MMU_PAGESIZE64K; 239 } else { 240 /* 241 * Align virtual addresses on a 64K boundary to ensure 242 * that ELF shared libraries are mapped with the appropriate 243 * alignment constraints by the run-time linker. 244 */ 245 align_amount = ELF_SPARC_MAXPGSZ; 246 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp != 0) && 247 ((uintptr_t)*addrp < align_amount)) 248 align_amount = (uintptr_t)*addrp; 249 } 250 251 /* 252 * 64-bit processes require 1024K alignment of ELF shared libraries. 253 */ 254 if (p->p_model == DATAMODEL_LP64) 255 align_amount = MAX(align_amount, ELF_SPARCV9_MAXPGSZ); 256 #ifdef VAC 257 if (vac && vacalign && (align_amount < shm_alignment)) 258 align_amount = shm_alignment; 259 #endif 260 261 if ((flags & MAP_ALIGN) && ((uintptr_t)*addrp > align_amount)) { 262 align_amount = (uintptr_t)*addrp; 263 } 264 len += align_amount; 265 266 /* 267 * Look for a large enough hole starting below the stack limit. 268 * After finding it, use the upper part. Addition of PAGESIZE is 269 * for the redzone as described above. 270 */ 271 as_purge(as); 272 if (as_gap(as, len, &base, &slen, AH_HI, NULL) == 0) { 273 caddr_t as_addr; 274 275 addr = base + slen - len + PAGESIZE; 276 as_addr = addr; 277 /* 278 * Round address DOWN to the alignment amount, 279 * add the offset, and if this address is less 280 * than the original address, add alignment amount. 281 */ 282 addr = (caddr_t)((uintptr_t)addr & (~(align_amount - 1l))); 283 addr += (long)(off & (align_amount - 1l)); 284 if (addr < as_addr) { 285 addr += align_amount; 286 } 287 288 ASSERT(addr <= (as_addr + align_amount)); 289 ASSERT(((uintptr_t)addr & (align_amount - 1l)) == 290 ((uintptr_t)(off & (align_amount - 1l)))); 291 *addrp = addr; 292 293 #if defined(SF_ERRATA_57) 294 if (AS_TYPE_64BIT(as) && addr < errata57_limit) { 295 *addrp = NULL; 296 } 297 #endif 298 } else { 299 *addrp = NULL; /* no more virtual space */ 300 } 301 } 302 303 /* 304 * Platform-dependent page scrub call. 305 */ 306 void 307 pagescrub(page_t *pp, uint_t off, uint_t len) 308 { 309 /* 310 * For now, we rely on the fact that pagezero() will 311 * always clear UEs. 312 */ 313 pagezero(pp, off, len); 314 } 315 316 /*ARGSUSED*/ 317 void 318 sync_data_memory(caddr_t va, size_t len) 319 { 320 cpu_flush_ecache(); 321 } 322 323 /* 324 * platform specific large pages for kernel heap support 325 */ 326 void 327 mmu_init_kcontext() 328 { 329 extern void set_kcontextreg(); 330 331 if (kcontextreg) 332 set_kcontextreg(); 333 } 334 335 void 336 contig_mem_init(void) 337 { 338 /* not applicable to sun4u */ 339 } 340