1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * VM - Hardware Address Translation management. 28 * 29 * This file describes the contents of the sun reference mmu (sfmmu) 30 * specific hat data structures and the sfmmu specific hat procedures. 31 * The machine independent interface is described in <vm/hat.h>. 32 */ 33 34 #ifndef _VM_MACH_SFMMU_H 35 #define _VM_MACH_SFMMU_H 36 37 #include <sys/x_call.h> 38 #include <sys/cheetahregs.h> 39 #include <sys/spitregs.h> 40 #include <sys/opl_olympus_regs.h> 41 #include <sys/mmu.h> 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 /* 48 * On sun4u platforms, user TSBs are accessed via virtual address by default. 49 * Platforms that support ASI_SCRATCHPAD registers can define UTSB_PHYS in the 50 * platform Makefile to access user TSBs via physical address but must also 51 * designate one ASI_SCRATCHPAD register to hold the second user TSB. To 52 * designate the user TSB scratchpad register, platforms must provide a 53 * definition for SCRATCHPAD_UTSBREG2 below. 54 * 55 * Platforms that use UTSB_PHYS do not allocate 2 locked TLB entries to access 56 * the user TSBs. 57 */ 58 #if defined(UTSB_PHYS) 59 60 #if defined(_OPL) 61 #define SCRATCHPAD_UTSBREG2 OPL_SCRATCHPAD_UTSBREG4 /* 4M-256M pages */ 62 #define SCRATCHPAD_UTSBREG3 OPL_SCRATCHPAD_UTSBREG5 /* 8K-512K pages */ 63 #define SCRATCHPAD_UTSBREG4 OPL_SCRATCHPAD_UTSBREG6 /* 4M-256M pages */ 64 #else 65 #error "Compiling UTSB_PHYS but no SCRATCHPAD_UTSBREG2 specified" 66 #endif /* _OPL */ 67 68 #endif /* UTSB_PHYS */ 69 70 71 #ifdef _ASM 72 73 /* 74 * This macro is used to set private/shared secondary context register in 75 * sfmmu_alloc_ctx(). 76 * if is_shctx = 0 then we set the SCONTEXT to cnum and invalidate the 77 * SHARED_CONTEXT register. If is_shctx = 1 then only the SHARED_CONTEXT 78 * register is set. 79 * (See additional comments in sfmmu_alloc_ctx) 80 * Input: 81 * cnum = cnum 82 * is_shctx = sfmmu private/shared flag (0: private, 1: shared) 83 * tmp1 : %o4 scratch 84 * tmp2 : %o5 scratch 85 * label: used as local branch targets 86 */ 87 #define SET_SECCTX(cnum, is_shctx, tmp1, tmp2, label) \ 88 /* BEGIN CSTYLED */ \ 89 brnz,pn is_shctx, label/**/1 ;\ 90 sethi %hi(FLUSH_ADDR), tmp2 ;\ 91 mov MMU_SCONTEXT, tmp1 ;\ 92 stxa cnum, [tmp1]ASI_MMU_CTX ;\ 93 flush tmp2 ;\ 94 sethi %hi(shctx_on), tmp1 ;\ 95 ld [tmp1 + %lo(shctx_on)], tmp1 ;\ 96 brz,pt tmp1, label/**/3 ;\ 97 mov %g0, cnum ;\ 98 ba,pt %xcc, label/**/2 ;\ 99 label/**/1: ;\ 100 set SHCTXREG_VALID_BIT, tmp1 ;\ 101 sllx cnum, CTXREG_CTX_SHIFT, cnum ;\ 102 srlx cnum, CTXREG_CTX_SHIFT, cnum ;\ 103 or cnum, tmp1, cnum ;\ 104 mov cnum, tmp1 ;\ 105 sllx cnum, 32, cnum ;\ 106 or cnum, tmp1, cnum ;\ 107 label/**/2: ;\ 108 mov MMU_SHARED_CONTEXT, tmp1 ;\ 109 stxa cnum, [tmp1]ASI_MMU_CTX ;\ 110 flush tmp2 ;\ 111 label/**/3: 112 /* END CSTYLED */ 113 114 /* 115 * This macro is to control the pagesizes used for shared context on 116 * Rock systems. 117 */ 118 #define CHECK_SHARED_PGSZ(tsbarea, tte, tmp, use_shctx, label) 119 120 /* 121 * This macro is used in the MMU code to check if TL should be lowered from 122 * 2 to 1 to pop trapstat's state. See the block comment in trapstat.c 123 * for details. 124 */ 125 126 #define TSTAT_CHECK_TL1(label, scr1, scr2) \ 127 rdpr %tpc, scr1; \ 128 sethi %hi(KERNELBASE), scr2; \ 129 or scr2, %lo(KERNELBASE), scr2; \ 130 cmp scr1, scr2; \ 131 bgeu %xcc, 9f; \ 132 nop; \ 133 ba label; \ 134 wrpr %g0, 1, %tl; \ 135 9: 136 137 138 /* 139 * The following macros allow us to share majority of the 140 * SFMMU code between sun4u and sun4v platforms. 141 */ 142 143 #define SETUP_TSB_ASI(qlp, tmp) \ 144 movrz qlp, ASI_N, tmp; \ 145 movrnz qlp, ASI_MEM, tmp; \ 146 mov tmp, %asi 147 148 /* 149 * Macro to swtich to alternate global register on sun4u platforms 150 * (not applicable to sun4v platforms) 151 */ 152 #define USE_ALTERNATE_GLOBALS(scr) \ 153 rdpr %pstate, scr; \ 154 wrpr scr, PSTATE_MG | PSTATE_AG, %pstate 155 156 /* 157 * Macro to set %gl register value on sun4v platforms 158 * (not applicable to sun4u platforms) 159 */ 160 #define SET_GL_REG(val) 161 162 /* 163 * Get MMU data tag access register value 164 * 165 * In: 166 * tagacc, scr1 = scratch registers 167 * Out: 168 * tagacc = MMU data tag access register value 169 */ 170 #define GET_MMU_D_TAGACC(tagacc, scr1) \ 171 mov MMU_TAG_ACCESS, scr1; \ 172 ldxa [scr1]ASI_DMMU, tagacc 173 174 /* 175 * Get MMU data tag target register 176 * 177 * In: 178 * ttarget, scr1 = scratch registers 179 * Out: 180 * ttarget = MMU data tag target register value 181 */ 182 #define GET_MMU_D_TTARGET(ttarget, scr1) \ 183 ldxa [%g0]ASI_DMMU, ttarget 184 185 /* 186 * Get MMU data/instruction tag access register values 187 * 188 * In: 189 * dtagacc, itagacc, scr1, scr2 = scratch registers 190 * Out: 191 * dtagacc = MMU data tag access register value 192 * itagacc = MMU instruction tag access register value 193 */ 194 #define GET_MMU_BOTH_TAGACC(dtagacc, itagacc, scr1, scr2) \ 195 mov MMU_TAG_ACCESS, scr1; \ 196 ldxa [scr1]ASI_DMMU, dtagacc; \ 197 ldxa [scr1]ASI_IMMU, itagacc 198 199 /* 200 * Get MMU data fault address from the tag access register 201 * 202 * In: 203 * daddr, scr1 = scratch registers 204 * Out: 205 * daddr = MMU data fault address 206 */ 207 #define GET_MMU_D_ADDR(daddr, scr1) \ 208 mov MMU_TAG_ACCESS, scr1; \ 209 ldxa [scr1]ASI_DMMU, daddr; \ 210 set TAGACC_CTX_MASK, scr1; \ 211 andn daddr, scr1, daddr 212 213 214 /* 215 * Load ITLB entry 216 * 217 * In: 218 * tte = reg containing tte 219 * scr1, scr2, scr3, scr4 = scratch registers (not used) 220 */ 221 #define ITLB_STUFF(tte, scr1, scr2, scr3, scr4) \ 222 stxa tte, [%g0]ASI_ITLB_IN 223 224 /* 225 * Load DTLB entry 226 * 227 * In: 228 * tte = reg containing tte 229 * scr1, scr2, scr3, scr4 = scratch register (not used) 230 */ 231 #define DTLB_STUFF(tte, scr1, scr2, scr3, scr4) \ 232 stxa tte, [%g0]ASI_DTLB_IN 233 234 235 /* 236 * Returns PFN given the TTE and vaddr 237 * 238 * In: 239 * tte = reg containing tte 240 * vaddr = reg containing vaddr 241 * scr1, scr2, scr3 = scratch registers 242 * Out: 243 * tte = PFN value 244 */ 245 #define TTETOPFN(tte, vaddr, label, scr1, scr2, scr3) \ 246 srlx tte, TTE_SZ_SHFT, scr1; \ 247 and scr1, TTE_SZ_BITS, scr1; /* scr1 = tte_size */ \ 248 srlx tte, TTE_SZ2_SHFT, scr3; \ 249 and scr3, TTE_SZ2_BITS, scr3; /* scr3 = tte_size2 */ \ 250 or scr1, scr3, scr1; \ 251 sllx scr1, 1, scr2; \ 252 add scr2, scr1, scr2; /* mulx 3 */ \ 253 sllx tte, TTE_PA_LSHIFT, tte; \ 254 add scr2, MMU_PAGESHIFT + TTE_PA_LSHIFT, scr3; \ 255 /* BEGIN CSTYLED */ \ 256 brz,pt scr2, label/**/1; \ 257 srlx tte, scr3, tte; \ 258 /* END CSTYLED */ \ 259 sllx tte, scr2, tte; \ 260 set 1, scr1; \ 261 add scr2, MMU_PAGESHIFT, scr3; \ 262 sllx scr1, scr3, scr1; \ 263 sub scr1, 1, scr1; /* g2=TTE_PAGE_OFFSET(ttesz) */ \ 264 and vaddr, scr1, scr2; \ 265 srln scr2, MMU_PAGESHIFT, scr2; \ 266 or tte, scr2, tte; \ 267 /* CSTYLED */ \ 268 label/**/1: 269 270 /* 271 * No support for non-coherent I-cache in sun4u 272 */ 273 #define TTE_SET_EXEC_ML(tte, ttepa, tmp1, label) 274 #define TTE_CLR_SOFTEXEC_ML(tte) 275 #define TTE_CHK_SOFTEXEC_ML(tte) andcc tte, 0, %g0 276 277 /* 278 * TTE_SET_REF_ML is a macro that updates the reference bit if it is 279 * not already set. 280 * 281 * Parameters: 282 * tte = reg containing tte 283 * ttepa = physical pointer to tte 284 * tteva = virtual ptr to tte 285 * tsbarea = tsb miss area 286 * tmp1 = tmp reg 287 * label = temporary label 288 */ 289 290 #define TTE_SET_REF_ML(tte, ttepa, tteva, tsbarea, tmp1, label) \ 291 /* BEGIN CSTYLED */ \ 292 /* check reference bit */ \ 293 andcc tte, TTE_REF_INT, %g0; \ 294 bnz,pt %xcc, label/**/4; /* if ref bit set-skip ahead */ \ 295 nop; \ 296 GET_CPU_IMPL(tmp1); \ 297 cmp tmp1, SPITFIRE_IMPL; \ 298 blt %icc, label/**/2; /* skip flush if FJ-OPL cpus */ \ 299 cmp tmp1, CHEETAH_IMPL; \ 300 bl,a %icc, label/**/1; \ 301 /* update reference bit */ \ 302 lduh [tsbarea + TSBMISS_DMASK], tmp1; \ 303 stxa %g0, [ttepa]ASI_DC_INVAL; /* flush line from dcache */ \ 304 membar #Sync; \ 305 ba label/**/2; \ 306 label/**/1: \ 307 and tteva, tmp1, tmp1; \ 308 stxa %g0, [tmp1]ASI_DC_TAG; /* flush line from dcache */ \ 309 membar #Sync; \ 310 label/**/2: \ 311 or tte, TTE_REF_INT, tmp1; \ 312 casxa [ttepa]ASI_MEM, tte, tmp1; /* update ref bit */ \ 313 cmp tte, tmp1; \ 314 bne,a,pn %xcc, label/**/2; \ 315 ldxa [ttepa]ASI_MEM, tte; /* MMU_READTTE through pa */ \ 316 or tte, TTE_REF_INT, tte; \ 317 label/**/4: \ 318 /* END CSTYLED */ 319 320 321 /* 322 * TTE_SET_REFMOD_ML is a macro that updates the reference and modify bits 323 * if not already set. 324 * 325 * Parameters: 326 * tte = reg containing tte 327 * ttepa = physical pointer to tte 328 * tteva = virtual ptr to tte 329 * tsbarea = tsb miss area 330 * tmp1 = tmp reg 331 * label = temporary label 332 * exitlabel = label where to jump to if write perm bit not set. 333 */ 334 335 #define TTE_SET_REFMOD_ML(tte, ttepa, tteva, tsbarea, tmp1, label, \ 336 exitlabel) \ 337 /* BEGIN CSTYLED */ \ 338 /* check reference bit */ \ 339 andcc tte, TTE_WRPRM_INT, %g0; \ 340 bz,pn %xcc, exitlabel; /* exit if wr_perm not set */ \ 341 nop; \ 342 andcc tte, TTE_HWWR_INT, %g0; \ 343 bnz,pn %xcc, label/**/4; /* nothing to do */ \ 344 nop; \ 345 GET_CPU_IMPL(tmp1); \ 346 cmp tmp1, SPITFIRE_IMPL; \ 347 blt %icc, label/**/2; /* skip flush if FJ-OPL cpus */ \ 348 cmp tmp1, CHEETAH_IMPL; \ 349 bl,a %icc, label/**/1; \ 350 /* update reference bit */ \ 351 lduh [tsbarea + TSBMISS_DMASK], tmp1; \ 352 stxa %g0, [ttepa]ASI_DC_INVAL; /* flush line from dcache */ \ 353 membar #Sync; \ 354 ba label/**/2; \ 355 label/**/1: \ 356 and tteva, tmp1, tmp1; \ 357 stxa %g0, [tmp1]ASI_DC_TAG; /* flush line from dcache */ \ 358 membar #Sync; \ 359 label/**/2: \ 360 or tte, TTE_HWWR_INT | TTE_REF_INT, tmp1; \ 361 casxa [ttepa]ASI_MEM, tte, tmp1; /* update ref/mod bit */ \ 362 cmp tte, tmp1; \ 363 bne,a,pn %xcc, label/**/2; \ 364 ldxa [ttepa]ASI_MEM, tte; /* MMU_READTTE through pa */ \ 365 or tte, TTE_HWWR_INT | TTE_REF_INT, tte; \ 366 label/**/4: \ 367 /* END CSTYLED */ 368 369 370 #ifndef UTSB_PHYS 371 372 /* 373 * Synthesize TSB base register contents for a process with 374 * a single TSB. 375 * 376 * We patch the virtual address mask in at runtime since the 377 * number of significant virtual address bits in the TSB VA 378 * can vary depending upon the TSB slab size being used on the 379 * machine. 380 * 381 * In: 382 * tsbinfo = TSB info pointer (ro) 383 * vabase = value of utsb_vabase (ro) 384 * Out: 385 * tsbreg = value to program into TSB base register 386 */ 387 388 #define MAKE_TSBREG(tsbreg, tsbinfo, vabase, tmp1, tmp2, label) \ 389 /* BEGIN CSTYLED */ \ 390 ldx [tsbinfo + TSBINFO_VADDR], tmp1; \ 391 .global label/**/_tsbreg_vamask ;\ 392 label/**/_tsbreg_vamask: \ 393 or %g0, RUNTIME_PATCH, tsbreg; \ 394 lduh [tsbinfo + TSBINFO_SZCODE], tmp2; \ 395 sllx tsbreg, TSBREG_VAMASK_SHIFT, tsbreg; \ 396 or vabase, tmp2, tmp2; \ 397 and tmp1, tsbreg, tsbreg; \ 398 or tsbreg, tmp2, tsbreg; \ 399 /* END CSTYLED */ 400 401 402 /* 403 * Synthesize TSB base register contents for a process with 404 * two TSBs. See hat_sfmmu.h for the layout of the TSB base 405 * register in this case. 406 * 407 * In: 408 * tsb1 = pointer to first TSB info (ro) 409 * tsb2 = pointer to second TSB info (ro) 410 * Out: 411 * tsbreg = value to program into TSB base register 412 */ 413 #define MAKE_TSBREG_SECTSB(tsbreg, tsb1, tsb2, tmp1, tmp2, tmp3, label) \ 414 /* BEGIN CSTYLED */ \ 415 set TSBREG_MSB_CONST, tmp3 ;\ 416 sllx tmp3, TSBREG_MSB_SHIFT, tsbreg ;\ 417 .global label/**/_tsbreg_vamask ;\ 418 label/**/_tsbreg_vamask: ;\ 419 or %g0, RUNTIME_PATCH, tmp3 ;\ 420 sll tmp3, TSBREG_VAMASK_SHIFT, tmp3 ;\ 421 ldx [tsb1 + TSBINFO_VADDR], tmp1 ;\ 422 ldx [tsb2 + TSBINFO_VADDR], tmp2 ;\ 423 and tmp1, tmp3, tmp1 ;\ 424 and tmp2, tmp3, tmp2 ;\ 425 sllx tmp2, TSBREG_SECTSB_MKSHIFT, tmp2 ;\ 426 or tmp1, tmp2, tmp3 ;\ 427 or tsbreg, tmp3, tsbreg ;\ 428 lduh [tsb1 + TSBINFO_SZCODE], tmp1 ;\ 429 lduh [tsb2 + TSBINFO_SZCODE], tmp2 ;\ 430 and tmp1, TSB_SOFTSZ_MASK, tmp1 ;\ 431 and tmp2, TSB_SOFTSZ_MASK, tmp2 ;\ 432 sllx tmp2, TSBREG_SECSZ_SHIFT, tmp2 ;\ 433 or tmp1, tmp2, tmp3 ;\ 434 or tsbreg, tmp3, tsbreg ;\ 435 /* END CSTYLED */ 436 437 438 /* 439 * Load the locked TSB TLB entry. 440 * 441 * In: 442 * tsbinfo = tsb_info pointer as va (ro) 443 * tteidx = shifted index into TLB to load the locked entry (ro) 444 * va = virtual address at which to load the locked TSB entry (ro) 445 * Out: 446 * Scratch: 447 * tmp 448 */ 449 #define LOAD_TSBTTE(tsbinfo, tteidx, va, tmp) \ 450 mov MMU_TAG_ACCESS, tmp; \ 451 stxa va, [tmp]ASI_DMMU; /* set tag access */ \ 452 membar #Sync; \ 453 ldx [tsbinfo + TSBINFO_TTE], tmp; /* fetch locked tte */ \ 454 stxa tmp, [tteidx]ASI_DTLB_ACCESS; /* load locked tte */ \ 455 membar #Sync 456 457 458 /* 459 * In the current implementation, TSBs usually come from physically 460 * contiguous chunks of memory up to 4MB in size, but 8K TSBs may be 461 * allocated from 8K chunks of memory under certain conditions. To 462 * prevent aliasing in the virtual address cache when the TSB slab is 463 * 8K in size we must align the reserved (TL>0) TSB virtual address to 464 * have the same low-order bits as the kernel (TL=0) TSB virtual address, 465 * and map 8K TSBs with an 8K TTE. In cases where the TSB reserved VA 466 * range is smaller than the assumed 4M we will patch the shift at 467 * runtime; otherwise we leave it alone (which is why RUNTIME_PATCH 468 * constant doesn't appear below). 469 * 470 * In: 471 * tsbinfo (ro) 472 * resva: reserved VA base for this TSB 473 * Out: 474 * resva: corrected VA for this TSB 475 */ 476 #define RESV_OFFSET(tsbinfo, resva, tmp1, label) \ 477 /* BEGIN CSTYLED */ \ 478 lduh [tsbinfo + TSBINFO_SZCODE], tmp1 ;\ 479 brgz,pn tmp1, label/**/9 ;\ 480 nop ;\ 481 ldx [tsbinfo + TSBINFO_VADDR], tmp1 ;\ 482 .global label/**/_resv_offset ;\ 483 label/**/_resv_offset: ;\ 484 sllx tmp1, (64 - MMU_PAGESHIFT4M), tmp1 ;\ 485 srlx tmp1, (64 - MMU_PAGESHIFT4M), tmp1 ;\ 486 or tmp1, resva, resva ;\ 487 label/**/9: \ 488 /* END CSTYLED */ 489 490 /* 491 * Determine the pointer of the entry in the first TSB to probe given 492 * the 8K TSB pointer register contents. 493 * 494 * In: 495 * tsbp8k = 8K TSB pointer register (ro) 496 * tmp = scratch register 497 * label = label for hot patching of utsb_vabase 498 * 499 * Out: tsbe_ptr = TSB entry address 500 * 501 * Note: This function is patched at runtime for performance reasons. 502 * Any changes here require sfmmu_patch_utsb fixed. 503 */ 504 505 #define GET_1ST_TSBE_PTR(tsbp8k, tsbe_ptr, tmp, label) \ 506 /* BEGIN CSTYLED */ \ 507 label/**/_get_1st_tsbe_ptr: ;\ 508 RUNTIME_PATCH_SETX(tsbe_ptr, tmp) ;\ 509 /* tsbeptr = contents of utsb_vabase */ ;\ 510 /* clear upper bits leaving just bits 21:0 of TSB ptr. */ ;\ 511 sllx tsbp8k, TSBREG_FIRTSB_SHIFT, tmp ;\ 512 /* finish clear */ ;\ 513 srlx tmp, TSBREG_FIRTSB_SHIFT, tmp ;\ 514 /* or-in bits 41:22 of the VA to form the real pointer. */ ;\ 515 or tsbe_ptr, tmp, tsbe_ptr \ 516 /* END CSTYLED */ 517 518 /* 519 * Determine the base address of the second TSB given the 8K TSB 520 * pointer register contents. 521 * 522 * In: 523 * tsbp8k = 8K TSB pointer register (ro) 524 * tmp = scratch register 525 * label = label for hot patching of utsb_vabase 526 * 527 * Out: 528 * tsbbase = TSB base address 529 * 530 * Note: This function is patched at runtime for performance reasons. 531 * Any changes here require sfmmu_patch_utsb fixed. 532 */ 533 534 #define GET_2ND_TSB_BASE(tsbp8k, tsbbase, tmp, label) \ 535 /* BEGIN CSTYLED */ \ 536 label/**/_get_2nd_tsb_base: ;\ 537 RUNTIME_PATCH_SETX(tsbbase, tmp) ;\ 538 /* tsbbase = contents of utsb4m_vabase */ ;\ 539 /* clear upper bits leaving just bits 21:xx of TSB addr. */ ;\ 540 sllx tsbp8k, TSBREG_SECTSB_LSHIFT, tmp ;\ 541 /* clear lower bits leaving just 21:13 in 8:0 */ ;\ 542 srlx tmp, (TSBREG_SECTSB_RSHIFT + MMU_PAGESHIFT), tmp ;\ 543 /* adjust TSB offset to bits 21:13 */ ;\ 544 sllx tmp, MMU_PAGESHIFT, tmp ;\ 545 or tsbbase, tmp, tsbbase ;\ 546 /* END CSTYLED */ 547 548 /* 549 * Determine the size code of the second TSB given the 8K TSB 550 * pointer register contents. 551 * 552 * In: 553 * tsbp8k = 8K TSB pointer register (ro) 554 * Out: 555 * size = TSB size code 556 */ 557 558 #define GET_2ND_TSB_SIZE(tsbp8k, size) \ 559 srlx tsbp8k, TSBREG_SECSZ_SHIFT, size; \ 560 and size, TSB_SOFTSZ_MASK, size 561 562 /* 563 * Get the location in the 2nd TSB of the tsbe for this fault. 564 * Assumes that the second TSB only contains 4M mappings. 565 * 566 * In: 567 * tagacc = tag access register (clobbered) 568 * tsbp8k = contents of TSB8K pointer register (ro) 569 * tmp1, tmp2 = scratch registers 570 * label = label at which to patch in reserved TSB 4M VA range 571 * Out: 572 * tsbe_ptr = pointer to the tsbe in the 2nd TSB 573 */ 574 #define GET_2ND_TSBE_PTR(tagacc, tsbp8k, tsbe_ptr, tmp1, tmp2, label) \ 575 GET_2ND_TSB_BASE(tsbp8k, tsbe_ptr, tmp2, label); \ 576 /* tsbe_ptr = TSB base address, tmp2 = junk */ \ 577 GET_2ND_TSB_SIZE(tsbp8k, tmp1); \ 578 /* tmp1 = TSB size code */ \ 579 GET_TSBE_POINTER(MMU_PAGESHIFT4M, tsbe_ptr, tagacc, tmp1, tmp2) 580 581 582 #else /* !UTSB_PHYS */ 583 584 585 /* 586 * Determine the pointer of the entry in the first TSB to probe given 587 * the 8K TSB pointer register contents. 588 * 589 * In: 590 * tagacc = tag access register 591 * tsbe_ptr = 8K TSB pointer register 592 * tmp = scratch registers 593 * 594 * Out: tsbe_ptr = TSB entry address 595 * 596 * Note: This macro is a nop since the 8K TSB pointer register 597 * is the entry pointer and does not need to be decoded. 598 * It is defined to allow for code sharing with sun4v. 599 */ 600 601 #define GET_1ST_TSBE_PTR(tagacc, tsbe_ptr, tmp1, tmp2) 602 603 #endif /* !UTSB_PHYS */ 604 605 606 /* 607 * Load TSB base register. In the single TSB case this register 608 * contains utsb_vabase, bits 21:13 of tsbinfo->tsb_va, and the 609 * TSB size code in bits 2:0. See hat_sfmmu.h for the layout in 610 * the case where we have multiple TSBs per process. 611 * 612 * In: 613 * tsbreg = value to load (ro) 614 */ 615 #define LOAD_TSBREG(tsbreg, tmp1, tmp2) \ 616 mov MMU_TSB, tmp1; \ 617 sethi %hi(FLUSH_ADDR), tmp2; \ 618 stxa tsbreg, [tmp1]ASI_DMMU; /* dtsb reg */ \ 619 stxa tsbreg, [tmp1]ASI_IMMU; /* itsb reg */ \ 620 flush tmp2 621 622 #ifdef UTSB_PHYS 623 #define UTSB_PROBE_ASI ASI_QUAD_LDD_PHYS 624 #else 625 #define UTSB_PROBE_ASI ASI_NQUAD_LD 626 #endif 627 #define PROBE_TSB(tsbe_ptr, tag, tsbtag, label) \ 628 /* BEGIN CSTYLED */ \ 629 ldda [tsbe_ptr]UTSB_PROBE_ASI, tsbtag ;\ 630 cmp tsbtag, tag /* compare tag w/ TSB */ ;\ 631 bne,pn %xcc, label/**/1 /* branch if !match */ ;\ 632 nop \ 633 /* END CSTYLED */ 634 /* 635 * Probe a TSB. If miss continue from the end of the macro for most probes 636 * except jump to TSB miss for 3rd ITSB probe. If hit retry faulted 637 * instruction for DTSB probes. For ITSB probes in case of TSB hit check 638 * execute bit and branch to exec_fault if the bit is not set otherwise retry 639 * faulted instruction. Do ITLB synthesis in case of hit in second ITSB if 640 * synthesis bit is set. 641 * 642 * tsbe_ptr = precomputed TSB entry pointer (in, ro) 643 * vpg_4m = 4M virtual page number for tag matching (in, ro) 644 * label = where to branch to if this is a miss (text) 645 * 646 * For trapstat, we have to explicily use these registers. 647 * g4 = location tag will be retrieved into from TSB (out) 648 * g5 = location data(tte) will be retrieved into from TSB (out) 649 * 650 * In case of first tsb probe tsbe_ptr is %g1. For other tsb probes 651 * move tsbe_ptr into %g1 in case of hit for traptrace. 652 * 653 * If the probe fails and we continue from call site %g4-%g5 are clobbered. 654 * 2nd ITSB probe macro will also clobber %g6 in this case. 655 */ 656 #define PROBE_1ST_DTSB(tsbe_ptr, vpg_4m, label) \ 657 /* BEGIN CSTYLED */ \ 658 PROBE_TSB(tsbe_ptr, vpg_4m, %g4, label) ;\ 659 TT_TRACE(trace_tsbhit) ;\ 660 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4) ;\ 661 retry /* retry faulted instruction */ ;\ 662 label/**/1: \ 663 /* END CSTYLED */ 664 665 #define PROBE_2ND_DTSB(tsbe_ptr, vpg_4m, label) \ 666 /* BEGIN CSTYLED */ \ 667 PROBE_TSB(tsbe_ptr, vpg_4m, %g4, label) ;\ 668 mov tsbe_ptr, %g1 /* trace_tsbhit wants ptr in %g1 */ ;\ 669 TT_TRACE(trace_tsbhit) ;\ 670 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4) ;\ 671 retry /* retry faulted instruction */ ;\ 672 label/**/1: \ 673 /* END CSTYLED */ 674 675 #define PROBE_1ST_ITSB(tsbe_ptr, vpg_4m, label) \ 676 /* BEGIN CSTYLED */ \ 677 PROBE_TSB(tsbe_ptr, vpg_4m, %g4, label) ;\ 678 andcc %g5, TTE_EXECPRM_INT, %g0 /* check execute bit */ ;\ 679 bz,pn %icc, exec_fault ;\ 680 nop ;\ 681 TT_TRACE(trace_tsbhit) ;\ 682 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4) ;\ 683 retry /* retry faulted instruction */ ;\ 684 label/**/1: \ 685 /* END CSTYLED */ 686 687 #define PROBE_2ND_ITSB(tsbe_ptr, vpg_4m, label) \ 688 /* BEGIN CSTYLED */ \ 689 ldda [tsbe_ptr]UTSB_PROBE_ASI, %g4 /* g4 = tag, g5 = data */ ;\ 690 cmp %g4, vpg_4m /* compare tag w/ TSB */ ;\ 691 bne,pn %xcc, label/**/2 /* branch if !match */ ;\ 692 or %g0, TTE4M, %g6 ;\ 693 andcc %g5, TTE_EXECPRM_INT, %g0 /* check execute bit */ ;\ 694 bz,a,pn %icc, label/**/1 ;\ 695 sllx %g6, TTE_SZ_SHFT, %g6 ;\ 696 mov tsbe_ptr, %g1 /* trap trace wants ptr in %g1 */ ;\ 697 TT_TRACE(trace_tsbhit) ;\ 698 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4) ;\ 699 retry /* retry faulted instruction */ ;\ 700 label/**/1: ;\ 701 andcc %g5, TTE_E_SYNTH_INT, %g0 ;\ 702 bz,pn %icc, exec_fault ;\ 703 mov tsbe_ptr, %g1 /* trap trace wants ptr in %g1 */ ;\ 704 or %g5, %g6, %g5 ;\ 705 TT_TRACE(trace_tsbhit) ;\ 706 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4) ;\ 707 retry /* retry faulted instruction */ ;\ 708 label/**/2: 709 /* END CSTYLED */ 710 711 #ifdef UTSB_PHYS 712 713 /* 714 * Updates the context filed in the tagaccess register with the shared 715 * context to force the next i/DTLB_STUFF() to load this mapping into 716 * the TLB with the shared context. 717 */ 718 #define SET_SHCTX_TAGACC(tmp1, tmp2, asi) \ 719 /* BEGIN CSTYLED */ \ 720 mov MMU_TAG_ACCESS, tmp2 ;\ 721 ldxa [tmp2]asi, tmp2 /* tmp2 = VA|CTX */ ;\ 722 srlx tmp2, TAGACC_SHIFT, tmp2 ;\ 723 sllx tmp2, TAGACC_SHIFT, tmp2 /* tmp2 = VA */ ;\ 724 mov MMU_SHARED_CONTEXT, tmp1 /* clobber tsbe_ptr */ ;\ 725 ldxa [tmp1]ASI_MMU_CTX, tmp1 /* tmp2 = shctx reg */ ;\ 726 sllx tmp1, SHCTXREG_CTX_LSHIFT, tmp1 ;\ 727 srlx tmp1, SHCTXREG_CTX_LSHIFT, tmp1 /* tmp1 = SHCTX */ ;\ 728 or tmp1, tmp2, tmp1 /* tmp1 = VA|SHCTX */ ;\ 729 mov MMU_TAG_ACCESS, tmp2 ;\ 730 stxa tmp1, [tmp2]asi /* asi = VA|SHCTX */ 731 /* END CSTYLED */ 732 733 #define PROBE_SHCTX_DTSB(tsbe_ptr, vpg_4m, label) \ 734 /* BEGIN CSTYLED */ \ 735 PROBE_TSB(tsbe_ptr, vpg_4m, %g4, label) ;\ 736 mov tsbe_ptr, %g1 /* trace_tsbhit wants ptr in %g1 */ ;\ 737 TT_TRACE(trace_tsbhit) ;\ 738 SET_SHCTX_TAGACC(%g3, %g4, ASI_DMMU) ;\ 739 DTLB_STUFF(%g5, %g1, %g2, %g3, %g4) ;\ 740 retry /* retry faulted instruction */ ;\ 741 label/**/1: \ 742 /* END CSTYLED */ 743 744 #define PROBE_3RD_DTSB(tsbe_ptr, vpg_4m, label) \ 745 /* BEGIN CSTYLED */ \ 746 PROBE_SHCTX_DTSB(tsbe_ptr, vpg_4m, label) ;\ 747 /* END CSTYLED */ 748 749 #define PROBE_4TH_DTSB(tsbe_ptr, vpg_4m, label) \ 750 /* BEGIN CSTYLED */ \ 751 PROBE_SHCTX_DTSB(tsbe_ptr, vpg_4m, label) ;\ 752 /* END CSTYLED */ 753 754 #define PROBE_SHCTX_ITSB(tsbe_ptr, vpg_4m, label) \ 755 /* BEGIN CSTYLED */ \ 756 PROBE_TSB(tsbe_ptr, vpg_4m, %g4, label) ;\ 757 andcc %g5, TTE_EXECPRM_INT, %g0 /* check execute bit */ ;\ 758 bz,pn %icc, exec_fault ;\ 759 mov tsbe_ptr, %g1 /* for traptrace sake */ ;\ 760 TT_TRACE(trace_tsbhit) ;\ 761 SET_SHCTX_TAGACC(%g3, %g4, ASI_IMMU) ;\ 762 ITLB_STUFF(%g5, %g1, %g2, %g3, %g4) ;\ 763 retry /* retry faulted instruction */ ;\ 764 label/**/1: 765 /* END CSTYLED */ 766 767 #define PROBE_3RD_ITSB(tsbe_ptr, vpg_4m, label) \ 768 /* BEGIN CSTYLED */ \ 769 PROBE_SHCTX_ITSB(tsbe_ptr, vpg_4m, sfmmu_tsb_miss_tt) ;\ 770 /* END CSTYLED */ 771 772 #define PROBE_4TH_ITSB(tsbe_ptr, vpg_4m, label) \ 773 /* BEGIN CSTYLED */ \ 774 PROBE_SHCTX_ITSB(tsbe_ptr, vpg_4m, label) ;\ 775 /* END CSTYLED */ 776 777 /* 778 * The traptype is supplied by caller. 779 * 780 * If iTSB miss, store shctx into IMMU TAG ACCESS REG 781 * If dTSB miss, store shctx into DMMU TAG ACCESS REG 782 * Thus the [D|I]TLB_STUFF will work as expected. 783 */ 784 #define SAVE_CTX1(traptype, tmp1, tmp2, label) \ 785 /* BEGIN CSTYLED */ \ 786 cmp traptype, FAST_IMMU_MISS_TT ;\ 787 be,pn %icc, label/**/1 ;\ 788 nop ;\ 789 SET_SHCTX_TAGACC(tmp1, tmp2, ASI_DMMU) ;\ 790 membar #Sync ;\ 791 ba,a label/**/2 ;\ 792 label/**/1: ;\ 793 SET_SHCTX_TAGACC(tmp1, tmp2, ASI_IMMU) ;\ 794 sethi %hi(FLUSH_ADDR), tmp1 ;\ 795 flush tmp1 ;\ 796 label/**/2: 797 /* END CSTYLED */ 798 799 #endif /* UTSB_PHYS */ 800 801 #endif /* _ASM */ 802 803 #ifdef __cplusplus 804 } 805 #endif 806 807 #endif /* _VM_MACH_SFMMU_H */ 808