1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_US3_MODULE_H 28 #define _SYS_US3_MODULE_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/async.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #ifdef _KERNEL 39 40 /* 41 * Macros to access the "cheetah cpu private" data structure. 42 */ 43 #define CPU_PRIVATE_PTR(cp, x) (&(((cheetah_private_t *)CPU_PRIVATE(cp))->x)) 44 #define CPU_PRIVATE_VAL(cp, x) (((cheetah_private_t *)CPU_PRIVATE(cp))->x) 45 46 #define CHP_WORD_TO_OFF(word, off) (((word) * 8) == off) 47 48 #if defined(JALAPENO) || defined(SERRANO) 49 /* JP J_REQ errors */ 50 #define C_AFSR_JREQ_ERRS (C_AFSR_RUE | C_AFSR_BP | C_AFSR_WBP | \ 51 C_AFSR_RCE | C_AFSR_TO | C_AFSR_BERR | C_AFSR_UMS) 52 /* JP AID errors */ 53 #define C_AFSR_AID_ERRS (C_AFSR_CPU | C_AFSR_FRU | C_AFSR_CPC | \ 54 C_AFSR_FRC) 55 56 #if defined(SERRANO) 57 /* SERRANO AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 58 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \ 59 C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \ 60 C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \ 61 C_AFSR_FRU | C_AFSR_EDU | C_AFSR_ETI | C_AFSR_ETC) 62 63 #else /* SERRANO */ 64 /* JP AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 65 #define C_AFSR_CECC_ERRS (C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_CPC | \ 66 C_AFSR_CPU | C_AFSR_WDC | C_AFSR_WDU | C_AFSR_EDC | \ 67 C_AFSR_CE | C_AFSR_RCE | C_AFSR_WBP | C_AFSR_FRC | \ 68 C_AFSR_FRU | C_AFSR_EDU) 69 #endif /* SERRANO */ 70 71 #if defined(SERRANO) 72 /* 73 * SERRANO AFSR bits from {Instruction,Data}_access_error traps 74 * (Traps 0xa, 0x32) 75 */ 76 #define C_AFSR_ASYNC_ERRS (C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \ 77 C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP | \ 78 C_AFSR_ETU | C_AFSR_ETS) 79 #else /* SERRANO */ 80 /* JP AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 81 #define C_AFSR_ASYNC_ERRS (C_AFSR_OM | C_AFSR_TO | C_AFSR_BERR | \ 82 C_AFSR_UE | C_AFSR_RUE | C_AFSR_EDU | C_AFSR_BP) 83 #endif /* SERRANO */ 84 85 #if defined(SERRANO) 86 /* SERRANO AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 87 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_ETI | \ 88 C_AFSR_ETC) 89 90 #else /* SERRANO */ 91 /* JP AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 92 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC) 93 #endif /* SERRANO */ 94 95 #if defined(SERRANO) 96 /* SERRANO AFSR bits from Fatal errors (processor asserts ERROR pin) */ 97 #define C_AFSR_FATAL_ERRS (C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \ 98 C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \ 99 C_AFSR_ISAP | C_AFSR_EFES | C_AFSR_ETS | C_AFSR_ETU) 100 101 #else /* SERRANO */ 102 /* JP AFSR bits from Fatal errors (processor asserts ERROR pin) */ 103 #define C_AFSR_FATAL_ERRS (C_AFSR_JETO | C_AFSR_SCE | C_AFSR_JEIC | \ 104 C_AFSR_JEIT | C_AFSR_JEIS | C_AFSR_IERR | \ 105 C_AFSR_ISAP | C_AFSR_ETP) 106 #endif /* SERRANO */ 107 108 /* JP AFSR all valid error status bits */ 109 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 110 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 111 112 #if defined(SERRANO) 113 /* SERRANO AFSR all ME status bits */ 114 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \ 115 C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \ 116 C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETU | C_AFSR_OM | \ 117 C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \ 118 C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \ 119 C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS | \ 120 C_AFSR_ETC | C_AFSR_ETI) 121 122 #else /* SERRANO */ 123 /* JP AFSR all ME status bits */ 124 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_UCU | \ 125 C_AFSR_EDU | C_AFSR_WDU | C_AFSR_CPU | C_AFSR_UCC | \ 126 C_AFSR_BERR | C_AFSR_TO | C_AFSR_ETP | C_AFSR_OM | \ 127 C_AFSR_UMS | C_AFSR_IVPE | C_AFSR_RUE | C_AFSR_BP | \ 128 C_AFSR_WBP | C_AFSR_FRU | C_AFSR_JETO | C_AFSR_SCE | \ 129 C_AFSR_JEIC | C_AFSR_JEIT | C_AFSR_JEIS) 130 #endif /* SERRANO */ 131 132 #if defined(SERRANO) 133 /* SERRANO AFSR bits due to an Ecache error */ 134 #define C_AFSR_ECACHE (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 135 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 136 C_AFSR_ETU | C_AFSR_ETS | C_AFSR_ETI | C_AFSR_ETC) 137 138 #else /* SERRANO */ 139 /* JP AFSR bits due to an Ecache error */ 140 #define C_AFSR_ECACHE (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 141 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 142 C_AFSR_ETP) 143 #endif /* SERRANO */ 144 145 /* JP AFSR bits due to a Memory error */ 146 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_FRC | C_AFSR_FRU |\ 147 C_AFSR_RCE | C_AFSR_RUE) 148 149 /* JP AFSR bits due to parity errors and have a valid BSYND */ 150 #define C_AFSR_MSYND_ERRS (C_AFSR_IVPE | C_AFSR_BP | C_AFSR_WBP) 151 152 /* JP AFSR bits with a valid ESYND field */ 153 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 154 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 155 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 156 C_AFSR_FRC | C_AFSR_FRU) 157 158 /* JP AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 159 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_RUE | C_AFSR_UCU | C_AFSR_EDU | \ 160 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVPE | C_AFSR_TO | \ 161 C_AFSR_BERR | C_AFSR_UMS | C_AFSR_OM | C_AFSR_WBP | \ 162 C_AFSR_FRU | C_AFSR_BP) 163 164 #elif defined(CHEETAH_PLUS) 165 166 /* Ch+ AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 167 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \ 168 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 169 C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE | \ 170 C_AFSR_THCE | C_AFSR_DBERR | C_AFSR_DTO | C_AFSR_IMU | \ 171 C_AFSR_IMC) 172 173 /* Ch+ AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 174 #define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \ 175 C_AFSR_TO | C_AFSR_BERR) 176 177 /* Ch+ AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 178 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_TSCE) 179 180 /* Ch+ AFSR bits from Fatal errors (processor asserts ERROR pin) */ 181 #define C_AFSR_FATAL_ERRS (C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \ 182 C_AFSR_TUE | C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_EMU) 183 184 /* Ch+ AFSR all valid error status bits */ 185 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 186 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 187 188 /* Ch+ AFSR all errors that set ME bit, in both AFSR and AFSR_EXT */ 189 #define C_AFSR_ALL_ME_ERRS (C_AFSR_TUE_SH | C_AFSR_IMU | C_AFSR_DTO | \ 190 C_AFSR_DBERR | C_AFSR_TSCE | C_AFSR_TUE | C_AFSR_DUE | \ 191 C_AFSR_ISAP | C_AFSR_EMU | C_AFSR_IVU | C_AFSR_TO | \ 192 C_AFSR_BERR | C_AFSR_UCC | C_AFSR_UCU | C_AFSR_CPU | \ 193 C_AFSR_WDU | C_AFSR_EDU | C_AFSR_UE | \ 194 C_AFSR_L3_TUE_SH | C_AFSR_L3_TUE | C_AFSR_L3_EDU | \ 195 C_AFSR_L3_UCC | C_AFSR_L3_UCU | C_AFSR_L3_CPU | \ 196 C_AFSR_L3_WDU) 197 198 /* Ch+ AFSR bits due to an Ecache error */ 199 #define C_AFSR_ECACHE (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 200 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 201 C_AFSR_TUE | C_AFSR_TSCE | C_AFSR_THCE | C_AFSR_TUE_SH) 202 203 /* Ch+ AFSR bits due to a Memory error */ 204 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC | \ 205 C_AFSR_DUE) 206 207 /* Ch+ AFSR bits due to an Mtag error and have a valid MSYND */ 208 #define C_AFSR_MSYND_ERRS (C_AFSR_EMU | C_AFSR_EMC | C_AFSR_IMU | \ 209 C_AFSR_IMC) 210 211 /* Ch+ AFSR bits with a valid ESYND field */ 212 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 213 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 214 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 215 C_AFSR_IVU | C_AFSR_IVC | C_AFSR_DUE) 216 217 /* Ch+ AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 218 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \ 219 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \ 220 C_AFSR_BERR | C_AFSR_DUE | C_AFSR_TUE | C_AFSR_DTO | \ 221 C_AFSR_DBERR | C_AFSR_TUE_SH | C_AFSR_IMU) 222 223 #else /* CHEETAH_PLUS */ 224 225 /* AFSR bits from Disrupting (Corrected) ECC error Trap (Trap 0x63) */ 226 #define C_AFSR_CECC_ERRS (C_AFSR_CE | C_AFSR_EMC | C_AFSR_EDU | \ 227 C_AFSR_EDC | C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | \ 228 C_AFSR_CPC | C_AFSR_IVU | C_AFSR_IVC) 229 230 /* AFSR bits from {Instruction,Data}_access_error traps (Traps 0xa, 0x32) */ 231 #define C_AFSR_ASYNC_ERRS (C_AFSR_UE | C_AFSR_EMU | C_AFSR_EDU | \ 232 C_AFSR_TO | C_AFSR_BERR) 233 234 /* AFSR bits from Fast_ECC_error trap (Trap 0x70) */ 235 #define C_AFSR_FECC_ERRS (C_AFSR_UCU | C_AFSR_UCC) 236 237 /* AFSR bits from Fatal errors (processor asserts ERROR pin) */ 238 #define C_AFSR_FATAL_ERRS (C_AFSR_PERR | C_AFSR_IERR | C_AFSR_ISAP | \ 239 C_AFSR_EMU) 240 241 /* AFSR all valid error status bits */ 242 #define C_AFSR_ALL_ERRS (C_AFSR_FATAL_ERRS | C_AFSR_FECC_ERRS | \ 243 C_AFSR_CECC_ERRS | C_AFSR_ASYNC_ERRS | C_AFSR_ME) 244 245 /* AFSR all ME status bits */ 246 #define C_AFSR_ALL_ME_ERRS (C_AFSR_ISAP | C_AFSR_UE | C_AFSR_IVU | \ 247 C_AFSR_EMU | C_AFSR_UCU | C_AFSR_EDU | C_AFSR_WDU | \ 248 C_AFSR_CPU | C_AFSR_UCC | C_AFSR_BERR | C_AFSR_TO) 249 250 /* AFSR bits due to an Ecache error */ 251 #define C_AFSR_ECACHE (C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 252 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC) 253 254 /* AFSR bits due to a Memory error */ 255 #define C_AFSR_MEMORY (C_AFSR_UE | C_AFSR_CE | C_AFSR_EMU | C_AFSR_EMC) 256 257 /* AFSR bits due to an Mtag error and have a valid MSYND */ 258 #define C_AFSR_MSYND_ERRS (C_AFSR_EMU | C_AFSR_EMC) 259 260 /* AFSR bits with a valid ESYND field */ 261 #define C_AFSR_ESYND_ERRS (C_AFSR_UE | C_AFSR_CE | \ 262 C_AFSR_UCU | C_AFSR_UCC | C_AFSR_EDU | C_AFSR_EDC | \ 263 C_AFSR_WDU | C_AFSR_WDC | C_AFSR_CPU | C_AFSR_CPC | \ 264 C_AFSR_IVU | C_AFSR_IVC) 265 266 /* AFSR error bits for AFT Level 1 messages (uncorrected + TO + BERR) */ 267 #define C_AFSR_LEVEL1 (C_AFSR_UE | C_AFSR_UCU | C_AFSR_EMU | C_AFSR_EDU | \ 268 C_AFSR_WDU | C_AFSR_CPU | C_AFSR_IVU | C_AFSR_TO | \ 269 C_AFSR_BERR) 270 271 #endif /* CHEETAH_PLUS */ 272 273 #if defined(JALAPENO) || defined(SERRANO) 274 /* AFSR all valid bits (except for ETW) */ 275 #define C_AFSR_MASK (C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_B_SYND | \ 276 C_AFSR_E_SYND | C_AFSR_AID | C_AFSR_JREQ) 277 #else /* JALAPENO || SERRANO */ 278 /* AFSR all valid bits */ 279 #define C_AFSR_MASK (C_AFSR_ALL_ERRS | C_AFSR_PRIV | C_AFSR_M_SYND | \ 280 C_AFSR_E_SYND) 281 #endif /* JALAPENO || SERRANO */ 282 283 /* 284 * Panther AFSR_EXT bits from Disrupting (Corrected) ECC error Trap 285 * (Trap 0x63) 286 */ 287 #define C_AFSR_EXT_CECC_ERRS (C_AFSR_L3_EDU | C_AFSR_L3_EDC | \ 288 C_AFSR_L3_WDU | C_AFSR_L3_WDC | C_AFSR_L3_CPU | \ 289 C_AFSR_L3_CPC | C_AFSR_L3_THCE) 290 291 /* 292 * Panther AFSR_EXT bits from {Instruction,Data}_access_error traps 293 * (Traps 0xa, 0x32) 294 */ 295 #define C_AFSR_EXT_ASYNC_ERRS (C_AFSR_L3_EDU) 296 297 /* Panther AFSR_EXT bits from Fast_ECC_error trap (Trap 0x70) */ 298 #define C_AFSR_EXT_FECC_ERRS (C_AFSR_L3_UCU | C_AFSR_L3_UCC) 299 300 /* Panther AFSR_EXT bits from Fatal errors (processor asserts ERROR pin) */ 301 #define C_AFSR_EXT_FATAL_ERRS (C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH | \ 302 C_AFSR_RED_ERR | C_AFSR_EFA_PAR_ERR) 303 304 /* Panther AFSR_EXT all valid error status bits */ 305 #define C_AFSR_EXT_ALL_ERRS (C_AFSR_EXT_FATAL_ERRS | \ 306 C_AFSR_EXT_FECC_ERRS | C_AFSR_EXT_CECC_ERRS | \ 307 C_AFSR_EXT_ASYNC_ERRS | C_AFSR_L3_MECC) 308 309 /* Panther AFSR_EXT bits due to L3 cache errors */ 310 #define C_AFSR_EXT_L3_ERRS (C_AFSR_L3_WDU | C_AFSR_L3_WDC | \ 311 C_AFSR_L3_CPU | C_AFSR_L3_CPC | C_AFSR_L3_UCU | \ 312 C_AFSR_L3_UCC | C_AFSR_L3_EDU | C_AFSR_L3_EDC | \ 313 C_AFSR_L3_TUE | C_AFSR_L3_TUE_SH | C_AFSR_L3_THCE) 314 315 /* Panther AFSR_EXT bits with a valid ESYND field */ 316 #define C_AFSR_EXT_ESYND_ERRS (C_AFSR_L3_UCU | C_AFSR_L3_UCC | \ 317 C_AFSR_L3_EDU | C_AFSR_L3_EDC | C_AFSR_L3_WDU | \ 318 C_AFSR_L3_WDC | C_AFSR_L3_CPU | C_AFSR_L3_CPC) 319 320 /* PANTHER AFSR_EXT error bits for AFT Level 1 messages (uncorrected) */ 321 #define C_AFSR_EXT_LEVEL1 (C_AFSR_L3_UCU | C_AFSR_L3_EDU | \ 322 C_AFSR_L3_WDU | C_AFSR_L3_CPU | C_AFSR_L3_TUE | \ 323 C_AFSR_L3_TUE_SH) 324 325 /* 326 * AFSR / AFSR_EXT bits for which we need to panic the system. 327 */ 328 #define C_AFSR_PANIC(errs) (((errs) & (C_AFSR_FATAL_ERRS | \ 329 C_AFSR_EXT_FATAL_ERRS)) != 0) 330 331 /* 332 * For the Fast ECC TL1 handler, we are limited in how many registers 333 * we can use, so we need to store the AFSR_EXT bits within the AFSR 334 * register using some of the AFSR reserved bits. 335 */ 336 #define AFSR_EXT_IN_AFSR_MASK C_AFSR_EXT_ALL_ERRS 337 #define AFSR_EXT_IN_AFSR_SHIFT 20 338 339 /* 340 * Defines for the flag field in the CPU logout structure. See the 341 * definition of ch_cpu_logout_t for further description. 342 */ 343 #define CLO_FLAGS_TT_MASK 0xff000 344 #define CLO_FLAGS_TT_SHIFT 12 345 #define CLO_FLAGS_TL_MASK 0xf00 346 #define CLO_FLAGS_TL_SHIFT 8 347 #define CLO_NESTING_MAX 20 /* Arbitrary maximum value */ 348 349 #define C_M_SYND_SHIFT 16 350 #define GET_M_SYND(afsr) (((afsr) & C_AFSR_M_SYND) >> C_M_SYND_SHIFT) 351 #define GET_E_SYND(afsr) ((afsr) & C_AFSR_E_SYND) 352 353 /* 354 * Bits of Cheetah Asynchronous Fault Address Register 355 */ 356 #define C_AFAR_PA INT64_C(0x000007fffffffff0) /* PA<42:4> physical address */ 357 358 /* 359 * Defines for the different types of dcache_flush 360 * it is stored in dflush_type 361 */ 362 #define FLUSHALL_TYPE 0x0 /* blasts all cache lines */ 363 #define FLUSHMATCH_TYPE 0x1 /* flush entire cache but check each */ 364 /* each line for a match */ 365 #define FLUSHPAGE_TYPE 0x2 /* flush only one page and check */ 366 /* each line for a match */ 367 368 /* 369 * D-Cache Tag Data Register 370 * 371 * +----------+--------+----------+ 372 * | Reserved | DC_Tag | DC_Valid | 373 * +----------+--------+----------+ 374 * 63 31 30 1 0 375 * 376 */ 377 #define ICACHE_FLUSHSZ 0x20 /* one line in i$ */ 378 #define CHEETAH_DC_VBIT_SHIFT 1 379 #define CHEETAH_DC_VBIT_MASK 0x1 380 381 /* 382 * Define for max size of "reason" string in panic flows. Since this is on 383 * the stack, we want to keep it as small as is reasonable. 384 */ 385 #define MAX_REASON_STRING 40 386 387 /* 388 * These error types are specific to Cheetah and are used internally for the 389 * Cheetah fault structure flt_type field. 390 */ 391 #define CPU_TO 1 /* Timeout */ 392 #define CPU_BERR 2 /* Bus Error */ 393 #define CPU_CE 3 /* Correctable Memory Error */ 394 #define CPU_UE 4 /* Uncorrectable Memory Error */ 395 #define CPU_CE_ECACHE 5 /* Correctable Ecache Error */ 396 #define CPU_UE_ECACHE 6 /* Uncorrectable Ecache Error */ 397 #define CPU_EMC 7 /* Correctable Mtag Error */ 398 #define CPU_FATAL 8 /* Fatal Error */ 399 #define CPU_ORPH 9 /* Orphaned UCC/UCU error */ 400 #define CPU_IV 10 /* IVU or IVC */ 401 #define CPU_INV_AFSR 11 /* Invalid AFSR */ 402 #define CPU_UE_ECACHE_RETIRE 12 /* Uncorrectable Ecache, retire page */ 403 #define CPU_IC_PARITY 13 /* Icache parity error trap */ 404 #define CPU_DC_PARITY 14 /* Dcache parity error trap */ 405 #define CPU_DUE 15 /* Disrupting UE */ 406 #define CPU_FPUERR 16 /* FPU Error */ 407 /* 408 * These next six error types (17-22) are only used in Jalapeno code 409 */ 410 #define CPU_RCE 17 /* Correctable remote memory error */ 411 #define CPU_RUE 18 /* Uncorrectable remote memory error */ 412 #define CPU_FRC 19 /* Correctable foreign memory error */ 413 #define CPU_FRU 20 /* Uncorrectable foreign memory error */ 414 #define CPU_BPAR 21 /* Bus parity (BP or WBP) errorrs */ 415 #define CPU_UMS 22 /* Unsupported memory store */ 416 /* 417 * These next four error types (23-26) are only used in Panther code 418 */ 419 #define CPU_PC_PARITY 23 /* Pcache parity error */ 420 #define CPU_ITLB_PARITY 24 /* Panther ITLB parity error */ 421 #define CPU_DTLB_PARITY 25 /* Panther DTLB parity error */ 422 #define CPU_L3_ADDR_PE 26 /* Panther L3$ address parity error */ 423 424 /* 425 * Sets trap table entry ttentry by overwriting eight instructions from ttlabel 426 */ 427 #define CH_SET_TRAP(ttentry, ttlabel) \ 428 bcopy((const void *)&ttlabel, &ttentry, 32); \ 429 flush_instr_mem((caddr_t)&ttentry, 32); 430 431 /* 432 * Return values for implementation specific error logging in the routine 433 * cpu_impl_async_log_err() 434 */ 435 #define CH_ASYNC_LOG_DONE 0 /* finished logging the error */ 436 #define CH_ASYNC_LOG_CONTINUE 1 /* continue onto handle panicker */ 437 #define CH_ASYNC_LOG_UNKNOWN 2 /* unknown error type */ 438 #define CH_ASYNC_LOG_RECIRC 3 /* suppress logging of error */ 439 440 #ifndef _ASM 441 442 /* 443 * Define Cheetah family (UltraSPARC-III) specific asynchronous error structure 444 */ 445 typedef struct cheetah_async_flt { 446 struct async_flt cmn_asyncflt; /* common - see sun4u/sys/async.h */ 447 ushort_t flt_type; /* types of faults - cpu specific */ 448 uint64_t flt_bit; /* fault bit for this log msg */ 449 uint64_t afsr_ext; /* Panther has an AFSR_EXT register */ 450 uint64_t afsr_errs; /* Store all AFSR error bits together */ 451 uint64_t afar2; /* Serrano has an AFAR2 for FRC/FRU */ 452 ch_diag_data_t flt_diag_data; /* Diagnostic data */ 453 int flt_data_incomplete; /* Diagnostic data is incomplete */ 454 int flt_trapped_ce; /* CEEN fault caught by trap handler */ 455 #if defined(CPU_IMP_L1_CACHE_PARITY) 456 ch_l1_parity_log_t parity_data; /* L1$ Parity error logging info */ 457 #endif /* CPU_IMP_L1_CACHE_PARITY */ 458 pn_tlb_logout_t tlb_diag_data; /* TLB parity error Diagnostic data */ 459 uint32_t flt_fpdata[16]; /* Data from fpras failure */ 460 uint64_t flt_sdw_afar; /* Shadow AFAR */ 461 uint64_t flt_sdw_afsr; /* Shadow AFSR */ 462 uint64_t flt_sdw_afsr_ext; /* Shadow Extended AFSR */ 463 } ch_async_flt_t; 464 465 #define ECC_ALL_TRAPS (ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP | ECC_F_TRAP) 466 #define ECC_ORPH_TRAPS (ECC_D_TRAP | ECC_I_TRAP | ECC_C_TRAP) 467 #define ECC_ASYNC_TRAPS (ECC_D_TRAP | ECC_I_TRAP) 468 #define ECC_MECC_TRAPS (ECC_D_TRAP | ECC_C_TRAP | ECC_F_TRAP) 469 470 /* 471 * Error type table struct. 472 */ 473 typedef struct ecc_type_to_info { 474 uint64_t ec_afsr_bit; /* AFSR bit of error */ 475 char *ec_reason; /* Short error description */ 476 uint_t ec_flags; /* Trap type error should be seen at */ 477 int ec_flt_type; /* Used by cpu_async_log_err */ 478 char *ec_desc; /* Long error description */ 479 uint64_t ec_err_payload; /* FM ereport payload information */ 480 char *ec_err_class; /* FM ereport class */ 481 } ecc_type_to_info_t; 482 483 typedef struct bus_config_eclk { 484 uint_t divisor; 485 uint64_t mask; 486 } bus_config_eclk_t; 487 488 #endif /* _ASM */ 489 490 #endif /* _KERNEL */ 491 492 #ifndef _ASM 493 494 #include <sys/cpuvar.h> 495 496 /* 497 * Since all the US3_* files share a bunch of routines between each other 498 * we will put all the "extern" definitions in this header file so that we 499 * don't have to repeat it all in every file. 500 */ 501 502 /* 503 * functions that are defined in the US3 cpu module: 504 * ------------------------------------------------- 505 */ 506 extern uint64_t get_safari_config(void); 507 extern void set_safari_config(uint64_t safari_config); 508 extern void shipit(int, int); 509 extern void cpu_aflt_log(int ce_code, int tagnum, ch_async_flt_t *aflt, 510 uint_t logflags, const char *endstr, const char *fmt, ...); 511 extern uint8_t flt_to_trap_type(struct async_flt *aflt); 512 extern char *tag_state_to_desc(uint64_t tagstate); 513 extern void cpu_log_err(struct async_flt *aflt); 514 extern void cpu_page_retire(ch_async_flt_t *ch_flt); 515 extern int clear_errors(ch_async_flt_t *ch_flt); 516 extern void cpu_init_ecache_scrub_dr(struct cpu *cp); 517 extern void get_cpu_error_state(ch_cpu_errors_t *); 518 extern void set_cpu_error_state(ch_cpu_errors_t *); 519 extern int cpu_flt_in_memory(ch_async_flt_t *ch_flt, uint64_t t_afsr_bit); 520 extern int cpu_queue_events(ch_async_flt_t *ch_flt, char *reason, 521 uint64_t t_afsr, ch_cpu_logout_t *clop); 522 extern void cpu_error_ecache_flush(ch_async_flt_t *); 523 extern void cpu_clearphys(struct async_flt *aflt); 524 extern void cpu_async_log_ic_parity_err(ch_async_flt_t *); 525 extern void cpu_async_log_dc_parity_err(ch_async_flt_t *); 526 extern uint64_t get_ecache_ctrl(void); 527 extern uint64_t get_jbus_config(void); 528 extern void set_jbus_config(uint64_t jbus_config); 529 extern uint64_t get_mcu_ctl_reg1(void); 530 extern void set_mcu_ctl_reg1(uint64_t mcu_ctl); 531 extern void cpu_init_trap(void); 532 extern int cpu_ecache_nway(void); 533 extern void cpu_delayed_logout(size_t, ch_cpu_logout_t *); 534 extern void cpu_payload_add_pcache(struct async_flt *, nvlist_t *); 535 extern void cpu_payload_add_tlb(struct async_flt *, nvlist_t *); 536 extern int cpu_scrub_cpu_setup(cpu_setup_t, int, void *); 537 #if defined(JALAPENO) || defined(SERRANO) 538 extern int afsr_to_jaid_status(uint64_t afsr, uint64_t afsr_bit); 539 #endif /* JALAPENO || SERRANO */ 540 /* 541 * Address of the level 15 interrupt handler preamble, used to log Fast ECC 542 * at TL>0 errors, which will be moved to the trap table address above. 543 */ 544 extern void ch_pil15_interrupt_instr(); 545 #ifdef CHEETAHPLUS_ERRATUM_25 546 extern int mondo_recover(uint16_t, int); 547 #endif /* CHEETAHPLUS_ERRATUM_25 */ 548 /* 549 * Adddresses of the Fast ECC Error trap handler preambles which will be 550 * moved to the appropriate trap table addresses. 551 */ 552 extern void fecc_err_instr(void); 553 extern void fecc_err_tl1_instr(void); 554 extern void fecc_err_tl1_cont_instr(void); 555 556 extern int afsr_to_overw_status(uint64_t afsr, uint64_t afsr_bit, 557 uint64_t *ow_bits); 558 #if defined(CHEETAH_PLUS) 559 extern int afsr_to_pn_esynd_status(uint64_t afsr, uint64_t afsr_bit); 560 #endif /* CHEETAH_PLUS */ 561 extern void flush_ecache(uint64_t physaddr, size_t ecachesize, size_t linesize); 562 extern void flush_dcache(void); 563 extern void flush_icache(void); 564 extern void flush_pcache(void); 565 extern void flush_ipb(void); 566 extern uint64_t get_dcu(void); 567 extern void set_dcu(uint64_t ncc); 568 extern void scrubphys(uint64_t paddr, int ecache_set_size); 569 extern void clearphys(uint64_t paddr, int ecache_set_size, int ecache_linesize); 570 extern void stick_adj(int64_t skew); 571 extern void stick_timestamp(int64_t *ts); 572 extern void icache_inval_all(void); 573 extern void dcache_inval_line(int index); 574 extern void ecache_flush_line(uint64_t flushaddr, int ec_size); 575 extern int ecache_get_lineinfo(uint32_t ecache_index, uint64_t *tag, 576 uint64_t *data); 577 #if defined(CPU_IMP_L1_CACHE_PARITY) 578 extern void get_dcache_dtag(uint32_t dcache_idx, uint64_t *data); 579 extern void get_icache_dtag(uint32_t icache_idx, uint64_t *data); 580 extern void get_pcache_dtag(uint32_t pcache_idx, uint64_t *data); 581 extern void correct_dcache_parity(size_t dcache_size, size_t dcache_linesize); 582 #endif /* CPU_IMP_L1_CACHE_PARITY */ 583 extern void cpu_check_block(caddr_t, uint_t); 584 extern uint32_t us3_gen_ecc(uint64_t data_low, uint64_t data_high); 585 extern int cpu_impl_async_log_err(void *, errorq_elem_t *); 586 extern void cpu_fast_ecc_error(struct regs *rp, ulong_t p_clo_flags); 587 extern void cpu_tl1_error(struct regs *rp, int panic); 588 extern void cpu_tl1_err_panic(struct regs *rp, ulong_t flags); 589 extern void cpu_disrupting_error(struct regs *rp, ulong_t p_clo_flags); 590 extern void cpu_deferred_error(struct regs *rp, ulong_t p_clo_flags); 591 #if defined(CPU_IMP_L1_CACHE_PARITY) 592 extern void cpu_parity_error(struct regs *rp, uint_t flags, caddr_t tpc); 593 #endif /* CPU_IMP_L1_CACHE_PARITY */ 594 extern void claimlines(uint64_t startpa, size_t len, int stride); 595 extern void copy_tsb_entry(uintptr_t src, uintptr_t dest); 596 extern void hwblkpagecopy(const void *src, void *dst); 597 #if defined(CHEETAH_PLUS) 598 extern void pn_cpu_log_diag_l2_info(ch_async_flt_t *ch_flt); 599 extern void set_afsr_ext(uint64_t afsr_ext); 600 #endif 601 extern void cpu_tlb_parity_error(struct regs *rp, ulong_t trap_va, 602 ulong_t tlb_info); 603 extern void log_flt_func(struct async_flt *aflt, char *unum); 604 extern uint64_t pn_get_tlb_index(uint64_t va, uint64_t pg_sz); 605 extern int popc64(uint64_t val); 606 607 /* 608 * variables and structures that are defined in the US3 cpu module: 609 * ---------------------------------------------------------------- 610 */ 611 extern bus_config_eclk_t bus_config_eclk[]; 612 extern ecc_type_to_info_t ecc_type_to_info[]; 613 extern uint64_t ch_err_tl1_paddrs[]; 614 extern uchar_t ch_err_tl1_pending[]; 615 #ifdef CHEETAHPLUS_ERRATUM_25 616 /* 617 * Tunable defined in us3_common.c 618 */ 619 extern int cheetah_sendmondo_recover; 620 #endif /* CHEETAHPLUS_ERRATUM_25 */ 621 /* 622 * The following allows for a one time calculation of the number of dcache 623 * lines vs. calculating the number every time through the scrub routine. 624 */ 625 int dcache_nlines; /* max number of D$ lines */ 626 627 extern uint64_t afar_overwrite[]; 628 extern uint64_t esynd_overwrite[]; 629 extern uint64_t msynd_overwrite[]; 630 631 #if defined(JALAPENO) || defined(SERRANO) 632 extern uint64_t jreq_overwrite[]; 633 #if defined(SERRANO) 634 extern uint64_t afar2_overwrite[]; 635 #endif /* SERRANO */ 636 #endif /* JALAPENO || SERRANO */ 637 638 /* 639 * variables and structures that are defined outside the US3 cpu module: 640 * --------------------------------------------------------------------- 641 */ 642 extern uint64_t xc_tick_limit; 643 extern uint64_t xc_tick_jump_limit; 644 extern struct kmem_cache *ch_private_cache; 645 646 #if defined(CPU_IMP_L1_CACHE_PARITY) 647 /* 648 * Addresses of the Dcache and Icache parity error trap table entries. 649 * If L1 cache parity protection is implemented, need to replace Dcache and 650 * Icache parity error handlers. 651 */ 652 extern void *tt0_dperr; 653 extern void *tt1_dperr; 654 extern void *tt1_swtrap1; 655 extern void *tt0_iperr; 656 extern void *tt1_iperr; 657 extern void *tt1_swtrap2; 658 /* 659 * Addresses of the Dcache and Icache parity error trap preambles, which will 660 * be moved to the appropriate trap table addresses. 661 */ 662 extern void dcache_parity_instr(); 663 extern void dcache_parity_tl1_instr(); 664 extern void dcache_parity_tl1_cont_instr(); 665 extern void icache_parity_instr(); 666 extern void icache_parity_tl1_instr(); 667 extern void icache_parity_tl1_cont_instr(); 668 #endif /* CPU_IMP_L1_CACHE_PARITY */ 669 670 /* 671 * Addresses of the Fast ECC error trap table entries. 672 */ 673 extern void *tt0_fecc; 674 extern void *tt1_fecc; 675 extern void *tt1_swtrap0; 676 /* 677 * Address of trap table level 15 interrupt handler in the trap table. 678 */ 679 extern void *tt_pil15; 680 /* 681 * D$ and I$ global parameters. 682 */ 683 extern int dcache_size; 684 extern int dcache_linesize; 685 extern int icache_size; 686 extern int icache_linesize; 687 688 /* 689 * Set of all offline cpus 690 */ 691 extern cpuset_t cpu_offline_set; 692 693 #endif /* _ASM */ 694 695 #ifdef __cplusplus 696 } 697 #endif 698 699 #endif /* _SYS_US3_MODULE_H */ 700