1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27 #ifndef _SYS_SBBCREG_H 28 #define _SYS_SBBCREG_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Register definitions for SBBC, a PCI device. 38 */ 39 #define SBBC_SC_MODE 0x00000020 40 41 typedef struct pad12 { 42 uint32_t pad[3]; 43 }pad12_t; 44 45 /* 46 * SBBC registers. 47 */ 48 struct sbbc_regs_map { 49 uint32_t devid; /* 0x0.0000 All, device ID */ 50 pad12_t pada; 51 uint32_t devtemp; /* 0x0.0010 All */ 52 pad12_t padb; 53 uint32_t incon_scratch; /* 0x0.0020 All */ 54 pad12_t padc; 55 uint32_t incon_tstl1; /* 0x0.0030 AR and SDC */ 56 pad12_t padd; 57 uint32_t incon_tsterr; /* 0x0.0040 AR and SDC */ 58 pad12_t pade; 59 uint32_t device_conf; /* 0x0.0050 All, device configuration */ 60 pad12_t padf; 61 uint32_t device_rstcntl; /* 0x0.0060 SBBC,AR,dev reset control */ 62 pad12_t padg; 63 uint32_t device_rststat; /* 0x0.0070 All, device reset status */ 64 pad12_t padh; 65 uint32_t device_errstat; /* 0x0.0080 SBBC, device reset */ 66 pad12_t padi; 67 uint32_t device_errcntl; /* 0x0.0090 SBBC,device error control */ 68 pad12_t padj; 69 uint32_t jtag_cntl; /* 0x0.00a0 SBBC and SDC,JTAG control */ 70 pad12_t padk; 71 uint32_t jtag_cmd; /* 0x0.00b0 SBBC and SDC,JTAG command */ 72 pad12_t padl; 73 uint32_t i2c_addrcmd; /* 0x0.00c0 SBBC,I2C addr and command */ 74 pad12_t padm; 75 uint32_t i2c_data; /* 0x0.00d0 SBBC, I2C data */ 76 pad12_t padn; 77 uint32_t pci_errstat; /* 0x0.00e0 SBBC, PCI error status */ 78 pad12_t pad2[45]; 79 uint32_t consbus_conf; /* 0x0.0300 All */ 80 pad12_t pado; 81 uint32_t consbus_erraddr; /* 0x0.0310 SBBC */ 82 pad12_t padp; 83 uint32_t consbus_errack; /* 0x0.0320 SBBC */ 84 pad12_t pad4[18]; 85 uint32_t pad5; 86 uint32_t consbus_port0_err; /* 0x0.0400 All */ 87 pad12_t pad6[19]; 88 uint32_t pad7[2]; 89 uint32_t consbus_part_dom_err; /* 0x0.04f0 SBBC and CBH */ 90 pad12_t pad8[235]; 91 uint32_t pad8a[2]; 92 uint32_t sbbc_synch; /* 0x0.1000 SBBC */ 93 pad12_t padq[20]; 94 uint32_t padqa[3]; 95 uint32_t dev_access_tim0; /* 0x0.1100 SBBC */ 96 pad12_t padr; 97 uint32_t dev_access_tim1; /* 0x0.1110 SBBC */ 98 pad12_t pads; 99 uint32_t dev_access_tim2; /* 0x0.1120 SBBC */ 100 pad12_t padt; 101 uint32_t dev_access_tim3; /* 0x0.1130 SBBC */ 102 pad12_t padu; 103 uint32_t dev_access_tim4; /* 0x0.1140 SBBC */ 104 pad12_t padv; 105 uint32_t dev_access_tim5; /* 0x0.1150 SBBC */ 106 pad12_t pad9[14]; 107 uint32_t pad9a[1]; 108 uint32_t spare_in_out; /* 0x0.1200 SBBC */ 109 pad12_t pad10[127]; 110 uint32_t pad10a[2]; 111 uint32_t monitor_cntl; /* 0x0.1800 SBBC */ 112 pad12_t pad11[170]; 113 uint32_t pad11a[1]; 114 uint32_t port_intr_gen0; /* 0x0.2000 SBBC */ 115 pad12_t padw; 116 uint32_t port_intr_gen1; /* 0x0.2010 SBBC */ 117 pad12_t padx; 118 uint32_t syscntlr_intr_gen; /* 0x0.2020 SBBC */ 119 pad12_t pad12[61]; 120 uint32_t sys_intr_status; /* 0x0.2300 SBBC */ 121 pad12_t pady; 122 uint32_t sys_intr_enable; /* 0x0.2310 SBBC */ 123 pad12_t padz; 124 uint32_t pci_intr_status; /* 0x0.2320 SBBC */ 125 pad12_t padaa; 126 uint32_t pci_intr_enable; /* 0x0.2330 SBBC */ 127 pad12_t pad13[614]; 128 uint32_t pad13a[1]; 129 uint32_t pci_to_consbus_map; /* 0x0.4000 SBBC */ 130 pad12_t padab; 131 uint32_t consbus_to_pci_map; /* 0x0.4010 SBBC */ 132 }; 133 134 135 /* 136 * SSC DEV presence registers 137 */ 138 struct ssc_devpresence_regs_map { 139 uint8_t devpres_reg0; 140 uint8_t devpres_reg1; 141 uint8_t devpres_reg2; 142 uint8_t devpres_reg3; 143 uint8_t devpres_reg4; 144 uint8_t devpres_reg5; 145 uint8_t devpres_reg6; 146 uint8_t devpres_reg7; 147 uint8_t devpres_reg8; 148 uint8_t devpres_reg9; 149 uint8_t devpres_rega; 150 uint8_t devpres_regb; 151 }; 152 153 /* 154 * EChip 155 * 0088.0000 - 0089.FFFF 156 */ 157 struct ssc_echip_regs { 158 uint8_t offset[0x20000]; 159 }; 160 161 /* 162 * Device Presence 163 * 008A.0000 - 008B.FFFF 164 */ 165 struct ssc_devpresence_regs { 166 uint8_t offset[0x20000]; 167 }; 168 169 /* 170 * I2C Mux 171 * 008C.0000 - 008D.FFFF 172 */ 173 struct ssc_i2cmux_regs { 174 uint8_t offset[0x20000]; 175 }; 176 177 /* 178 * Error Interrupts Status and Control 179 * 008E.0000 - 008F.FFFF 180 */ 181 struct ssc_errintr_statcntl_regs { 182 uint8_t offset[0x20000]; 183 }; 184 185 /* 186 * Console Bus Window 187 * 0400.0000 - 07FF.FFFF 188 */ 189 struct ssc_console_bus { 190 uint8_t offset[0x4000000]; 191 }; 192 193 /* 194 * SSC EILD registers 195 */ 196 struct ssc_eild_reg_map { 197 uint8_t darb_intr; 198 uint8_t darb_intr_mask; 199 uint8_t sbbc_cons_err; 200 uint8_t sbbc_cons_err_mask; 201 uint8_t pwr_supply; 202 }; 203 204 /* 205 * PCI SBBC slave mapping 206 */ 207 struct pci_sbbc { 208 uint8_t fprom[0x800000]; /* FPROM */ 209 struct sbbc_regs_map sbbc_internal_regs; /* sbbc registers */ 210 uint8_t dontcare[0x7BFEC]; /* non-sbbc registers */ 211 struct ssc_echip_regs echip_regs; 212 struct ssc_devpresence_regs devpres_regs; 213 struct ssc_i2cmux_regs i2cmux_regs; 214 struct ssc_errintr_statcntl_regs errintr_scntl_regs; 215 uint8_t sram[0x100000]; 216 uint8_t reserved[0x3600000]; 217 struct ssc_console_bus consbus; 218 }; 219 220 221 /* 222 * SBBC registers. 223 */ 224 struct sbbc_common_devregs { 225 uint32_t devid; /* All, device ID */ 226 uint32_t devtemp; /* All */ 227 uint32_t incon_scratch; /* All */ 228 uint32_t incon_tstl1; /* AR and SDC */ 229 uint32_t incon_tsterr; /* AR and SDC */ 230 uint32_t device_conf; /* All, device configuration */ 231 uint32_t device_rstcntl; /* SBBC and AR, dev reset control */ 232 uint32_t device_rststat; /* All, device reset status */ 233 uint32_t device_errstat; /* SBBC, device reset */ 234 uint32_t device_errcntl; /* SBBC, device error control */ 235 uint32_t jtag_cntl; /* SBBC and SDC, JTAG control */ 236 uint32_t jtag_cmd; /* SBBC and SDC, JTAG command */ 237 uint32_t i2c_addrcmd; /* SBBC, I2C address and command */ 238 uint32_t i2c_data; /* SBBC, I2C data */ 239 uint32_t pci_errstat; /* SBBC, PCI error status */ 240 uint32_t domain_conf; /* CBH */ 241 uint32_t safari_port0_conf; /* AR and SDC */ 242 uint32_t safari_port1_conf; /* AR and SDC */ 243 uint32_t safari_port2_conf; /* AR and SDC */ 244 uint32_t safari_port3_conf; /* AR and SDC */ 245 uint32_t safari_port4_conf; /* AR and SDC */ 246 uint32_t safari_port5_conf; /* AR and SDC */ 247 uint32_t safari_port6_conf; /* AR and SDC */ 248 uint32_t safari_port7_conf; /* AR and SDC */ 249 uint32_t safari_port8_conf; /* AR and SDC */ 250 uint32_t safari_port9_conf; /* AR and SDC */ 251 uint32_t safari_port0_err; /* AR and SDC */ 252 uint32_t safari_port1_err; /* AR and SDC */ 253 uint32_t safari_port2_err; /* AR and SDC */ 254 uint32_t safari_port3_err; /* AR and SDC */ 255 uint32_t safari_port4_err; /* AR and SDC */ 256 uint32_t safari_port5_err; /* AR and SDC */ 257 uint32_t safari_port6_err; /* AR and SDC */ 258 uint32_t safari_port7_err; /* AR and SDC */ 259 uint32_t safari_port8_err; /* AR and SDC */ 260 uint32_t safari_port9_err; /* AR and SDC */ 261 uint32_t consbus_conf; /* All */ 262 uint32_t consbus_erraddr; /* SBBC */ 263 uint32_t consbus_errack; /* SBBC */ 264 uint32_t consbus_errinj0; /* CBH */ 265 uint32_t consbus_errinj1; /* CBH */ 266 uint32_t consbus_port0_err; /* All */ 267 uint32_t consbus_port1_err; /* SDC and CBH */ 268 uint32_t consbus_port2_err; /* SDC and CBH */ 269 uint32_t consbus_port3_err; /* SDC and CBH */ 270 uint32_t consbus_port4_err; /* SDC and CBH */ 271 uint32_t consbus_port5_err; /* CBH */ 272 uint32_t consbus_port6_err; /* CBH */ 273 uint32_t consbus_port7_err; /* CBH */ 274 uint32_t consbus_port8_err; /* CBH */ 275 uint32_t consbus_port9_err; /* CBH */ 276 uint32_t consbus_porta_err; /* CBH */ 277 uint32_t consbus_portb_err; /* CBH */ 278 uint32_t consbus_portc_err; /* CBH */ 279 uint32_t consbus_portd_err; /* CBH */ 280 uint32_t consbus_porte_err; /* CBH */ 281 uint32_t consbus_part_dom_err; /* SBBC and CBH */ 282 uint32_t sbbc_synch; /* SBBC */ 283 uint32_t dev_access_tim0; /* SBBC */ 284 uint32_t dev_access_tim1; /* SBBC */ 285 uint32_t dev_access_tim2; /* SBBC */ 286 uint32_t dev_access_tim3; /* SBBC */ 287 uint32_t dev_access_tim4; /* SBBC */ 288 uint32_t dev_access_tim5; /* SBBC */ 289 uint32_t spare_in_out; /* SBBC */ 290 uint32_t monitor_cntl; /* SBBC */ 291 uint32_t port_intr_gen0; /* SBBC */ 292 uint32_t port_intr_gen1; /* SBBC */ 293 uint32_t syscntlr_intr_gen; /* SBBC */ 294 uint32_t sys_intr_status; /* SBBC */ 295 uint32_t sys_intr_enable; /* SBBC */ 296 uint32_t pci_intr_status; /* SBBC */ 297 uint32_t pci_intr_enable; /* SBBC */ 298 uint32_t pci_to_consbus_map; /* SBBC */ 299 uint32_t consbus_to_pci_map; /* SBBC */ 300 uint32_t scm_consbus_addrmap; /* CBH */ 301 uint32_t ar_slot0_trans_cnt; /* AR */ 302 uint32_t ar_slot1_trans_cnt; /* AR */ 303 uint32_t ar_slot2_trans_cnt; /* AR */ 304 uint32_t ar_slot3_trans_cnt; /* AR */ 305 uint32_t ar_slot4_trans_cnt; /* AR */ 306 uint32_t ar_slot5_trans_cnt; /* AR */ 307 uint32_t ar_slot6_trans_cnt; /* AR */ 308 uint32_t ar_slot7_trans_cnt; /* AR */ 309 uint32_t ar_slot8_trans_cnt; /* AR */ 310 uint32_t ar_slot9_trans_cnt; /* AR */ 311 uint32_t ar_trans_cnt_oflow; /* AR */ 312 uint32_t ar_trans_cnt_uflow; /* AR */ 313 uint32_t ar_l1l1_conf; /* AR */ 314 uint32_t lock_step_err; /* AR and SDC */ 315 uint32_t l2_check_err; /* AR and SDC */ 316 uint32_t incon_tstl1_slave; /* AR */ 317 uint32_t incon_tstl2_slave; /* AR and SDC */ 318 uint32_t ecc_status; /* SDC */ 319 uint32_t event_counter0; /* SDC */ 320 uint32_t event_counter1; /* SDC */ 321 uint32_t event_counter2; /* SDC */ 322 uint32_t monitor_counter_cntl; /* AR and SDC */ 323 uint32_t ar_transid_match; /* AR */ 324 }; 325 326 327 #ifdef __cplusplus 328 } 329 #endif 330 331 #endif /* _SYS_SBBCREG_H */ 332